./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/config/AutomizerReach.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 01a21536345230b7194ff5017879c469eb8be909ba72352bb81feb2f101a934f ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 09:50:49,273 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 09:50:49,277 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 09:50:49,352 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 09:50:49,353 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 09:50:49,358 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 09:50:49,361 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 09:50:49,365 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 09:50:49,369 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 09:50:49,375 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 09:50:49,377 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 09:50:49,379 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 09:50:49,380 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 09:50:49,383 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 09:50:49,386 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 09:50:49,394 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 09:50:49,396 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 09:50:49,398 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 09:50:49,404 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 09:50:49,407 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 09:50:49,409 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 09:50:49,411 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 09:50:49,415 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 09:50:49,417 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 09:50:49,431 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 09:50:49,431 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 09:50:49,432 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 09:50:49,434 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 09:50:49,435 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 09:50:49,437 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 09:50:49,438 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 09:50:49,439 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 09:50:49,441 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 09:50:49,443 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 09:50:49,446 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 09:50:49,446 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 09:50:49,447 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 09:50:49,447 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 09:50:49,448 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 09:50:49,449 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 09:50:49,450 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 09:50:49,451 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/config/svcomp-Reach-32bit-Automizer_Default.epf [2021-10-28 09:50:49,512 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 09:50:49,512 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 09:50:49,513 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 09:50:49,514 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 09:50:49,522 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 09:50:49,523 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 09:50:49,524 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 09:50:49,524 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 09:50:49,524 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 09:50:49,525 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 09:50:49,526 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 09:50:49,526 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 09:50:49,526 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-10-28 09:50:49,527 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-10-28 09:50:49,527 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-10-28 09:50:49,527 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 09:50:49,528 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 09:50:49,528 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 09:50:49,528 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-10-28 09:50:49,529 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 09:50:49,529 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 09:50:49,529 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-10-28 09:50:49,530 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-10-28 09:50:49,530 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 09:50:49,530 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-10-28 09:50:49,530 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-10-28 09:50:49,531 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 09:50:49,531 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-10-28 09:50:49,531 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-10-28 09:50:49,533 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2021-10-28 09:50:49,534 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-10-28 09:50:49,534 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 09:50:49,534 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 01a21536345230b7194ff5017879c469eb8be909ba72352bb81feb2f101a934f [2021-10-28 09:50:49,931 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 09:50:49,962 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 09:50:49,965 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 09:50:49,966 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 09:50:49,967 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 09:50:49,969 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/../../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2021-10-28 09:50:50,051 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/data/6387bb98a/263ab428ecba47bfb0139b2f92b7a0cb/FLAG9c4989d26 [2021-10-28 09:50:50,685 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 09:50:50,686 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2021-10-28 09:50:50,714 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/data/6387bb98a/263ab428ecba47bfb0139b2f92b7a0cb/FLAG9c4989d26 [2021-10-28 09:50:50,940 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/data/6387bb98a/263ab428ecba47bfb0139b2f92b7a0cb [2021-10-28 09:50:50,943 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 09:50:50,945 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 09:50:50,951 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 09:50:50,952 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 09:50:50,956 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 09:50:50,956 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:50:50" (1/1) ... [2021-10-28 09:50:50,959 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@522ccb8a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:50, skipping insertion in model container [2021-10-28 09:50:50,959 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 09:50:50" (1/1) ... [2021-10-28 09:50:50,968 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 09:50:51,025 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 09:50:51,367 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c[14684,14697] [2021-10-28 09:50:51,375 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:50:51,387 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 09:50:51,490 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c[14684,14697] [2021-10-28 09:50:51,491 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 09:50:51,530 INFO L208 MainTranslator]: Completed translation [2021-10-28 09:50:51,531 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51 WrapperNode [2021-10-28 09:50:51,531 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 09:50:51,532 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 09:50:51,532 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 09:50:51,532 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 09:50:51,541 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,556 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,661 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 09:50:51,662 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 09:50:51,662 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 09:50:51,663 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 09:50:51,673 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,673 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,682 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,683 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,707 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,722 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,727 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,738 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 09:50:51,739 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 09:50:51,740 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 09:50:51,740 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 09:50:51,741 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (1/1) ... [2021-10-28 09:50:51,769 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-10-28 09:50:51,794 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:50:51,816 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-10-28 09:50:51,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-10-28 09:50:51,881 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 09:50:51,881 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 09:50:51,881 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 09:50:51,882 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 09:50:53,174 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 09:50:53,174 INFO L299 CfgBuilder]: Removed 123 assume(true) statements. [2021-10-28 09:50:53,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:50:53 BoogieIcfgContainer [2021-10-28 09:50:53,178 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 09:50:53,180 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-10-28 09:50:53,181 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-10-28 09:50:53,185 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-10-28 09:50:53,185 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.10 09:50:50" (1/3) ... [2021-10-28 09:50:53,186 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d5c7e5c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.10 09:50:53, skipping insertion in model container [2021-10-28 09:50:53,186 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 09:50:51" (2/3) ... [2021-10-28 09:50:53,187 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d5c7e5c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.10 09:50:53, skipping insertion in model container [2021-10-28 09:50:53,187 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:50:53" (3/3) ... [2021-10-28 09:50:53,189 INFO L111 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2021-10-28 09:50:53,195 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-10-28 09:50:53,196 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 23 error locations. [2021-10-28 09:50:53,275 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-10-28 09:50:53,282 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-10-28 09:50:53,282 INFO L340 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2021-10-28 09:50:53,315 INFO L276 IsEmpty]: Start isEmpty. Operand has 296 states, 272 states have (on average 1.7058823529411764) internal successors, (464), 295 states have internal predecessors, (464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:53,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2021-10-28 09:50:53,324 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:53,325 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:53,326 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:53,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:53,333 INFO L85 PathProgramCache]: Analyzing trace with hash 349506240, now seen corresponding path program 1 times [2021-10-28 09:50:53,345 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:53,346 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134575437] [2021-10-28 09:50:53,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:53,347 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:53,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:53,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:53,627 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134575437] [2021-10-28 09:50:53,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134575437] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:53,628 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:53,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 09:50:53,631 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705645156] [2021-10-28 09:50:53,638 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-10-28 09:50:53,639 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:53,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-10-28 09:50:53,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-10-28 09:50:53,667 INFO L87 Difference]: Start difference. First operand has 296 states, 272 states have (on average 1.7058823529411764) internal successors, (464), 295 states have internal predecessors, (464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 16.5) internal successors, (33), 2 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:53,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:53,727 INFO L93 Difference]: Finished difference Result 572 states and 896 transitions. [2021-10-28 09:50:53,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-10-28 09:50:53,729 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 16.5) internal successors, (33), 2 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2021-10-28 09:50:53,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:53,749 INFO L225 Difference]: With dead ends: 572 [2021-10-28 09:50:53,749 INFO L226 Difference]: Without dead ends: 292 [2021-10-28 09:50:53,753 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-10-28 09:50:53,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2021-10-28 09:50:53,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 292. [2021-10-28 09:50:53,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292 states, 269 states have (on average 1.5910780669144982) internal successors, (428), 291 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:53,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292 states to 292 states and 428 transitions. [2021-10-28 09:50:53,906 INFO L78 Accepts]: Start accepts. Automaton has 292 states and 428 transitions. Word has length 33 [2021-10-28 09:50:53,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:53,907 INFO L470 AbstractCegarLoop]: Abstraction has 292 states and 428 transitions. [2021-10-28 09:50:53,907 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 16.5) internal successors, (33), 2 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:53,909 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 428 transitions. [2021-10-28 09:50:53,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2021-10-28 09:50:53,913 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:53,913 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:53,913 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-10-28 09:50:53,914 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:53,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:53,919 INFO L85 PathProgramCache]: Analyzing trace with hash -1047215368, now seen corresponding path program 1 times [2021-10-28 09:50:53,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:53,920 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405874730] [2021-10-28 09:50:53,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:53,921 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:53,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:54,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:54,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:54,087 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405874730] [2021-10-28 09:50:54,088 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405874730] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:54,088 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:54,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:50:54,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4671125] [2021-10-28 09:50:54,090 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:50:54,091 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:54,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:50:54,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:50:54,096 INFO L87 Difference]: Start difference. First operand 292 states and 428 transitions. Second operand has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:54,223 INFO L93 Difference]: Finished difference Result 570 states and 830 transitions. [2021-10-28 09:50:54,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:50:54,224 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2021-10-28 09:50:54,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:54,228 INFO L225 Difference]: With dead ends: 570 [2021-10-28 09:50:54,231 INFO L226 Difference]: Without dead ends: 292 [2021-10-28 09:50:54,233 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:50:54,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2021-10-28 09:50:54,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 292. [2021-10-28 09:50:54,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292 states, 269 states have (on average 1.546468401486989) internal successors, (416), 291 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292 states to 292 states and 416 transitions. [2021-10-28 09:50:54,276 INFO L78 Accepts]: Start accepts. Automaton has 292 states and 416 transitions. Word has length 33 [2021-10-28 09:50:54,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:54,277 INFO L470 AbstractCegarLoop]: Abstraction has 292 states and 416 transitions. [2021-10-28 09:50:54,277 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,277 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 416 transitions. [2021-10-28 09:50:54,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2021-10-28 09:50:54,286 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:54,286 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:54,287 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-10-28 09:50:54,287 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:54,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:54,289 INFO L85 PathProgramCache]: Analyzing trace with hash -600938825, now seen corresponding path program 1 times [2021-10-28 09:50:54,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:54,290 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726792529] [2021-10-28 09:50:54,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:54,292 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:54,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:54,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:54,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:54,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726792529] [2021-10-28 09:50:54,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726792529] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:54,529 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:54,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:54,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589165396] [2021-10-28 09:50:54,530 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:54,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:54,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:54,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:54,532 INFO L87 Difference]: Start difference. First operand 292 states and 416 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:54,599 INFO L93 Difference]: Finished difference Result 600 states and 864 transitions. [2021-10-28 09:50:54,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:54,600 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 44 [2021-10-28 09:50:54,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:54,604 INFO L225 Difference]: With dead ends: 600 [2021-10-28 09:50:54,604 INFO L226 Difference]: Without dead ends: 325 [2021-10-28 09:50:54,605 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:54,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2021-10-28 09:50:54,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 268. [2021-10-28 09:50:54,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 249 states have (on average 1.5261044176706828) internal successors, (380), 267 states have internal predecessors, (380), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 380 transitions. [2021-10-28 09:50:54,623 INFO L78 Accepts]: Start accepts. Automaton has 268 states and 380 transitions. Word has length 44 [2021-10-28 09:50:54,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:54,624 INFO L470 AbstractCegarLoop]: Abstraction has 268 states and 380 transitions. [2021-10-28 09:50:54,624 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,625 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 380 transitions. [2021-10-28 09:50:54,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2021-10-28 09:50:54,626 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:54,627 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:54,627 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-10-28 09:50:54,627 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:54,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:54,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1585020226, now seen corresponding path program 1 times [2021-10-28 09:50:54,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:54,628 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514832716] [2021-10-28 09:50:54,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:54,629 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:54,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:54,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:54,748 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:54,748 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514832716] [2021-10-28 09:50:54,748 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514832716] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:54,749 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:54,749 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:54,749 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100641499] [2021-10-28 09:50:54,750 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:54,750 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:54,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:54,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:54,751 INFO L87 Difference]: Start difference. First operand 268 states and 380 transitions. Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:54,807 INFO L93 Difference]: Finished difference Result 747 states and 1071 transitions. [2021-10-28 09:50:54,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:54,808 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 53 [2021-10-28 09:50:54,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:54,814 INFO L225 Difference]: With dead ends: 747 [2021-10-28 09:50:54,814 INFO L226 Difference]: Without dead ends: 496 [2021-10-28 09:50:54,816 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:54,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2021-10-28 09:50:54,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 303. [2021-10-28 09:50:54,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 284 states have (on average 1.5211267605633803) internal successors, (432), 302 states have internal predecessors, (432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 432 transitions. [2021-10-28 09:50:54,859 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 432 transitions. Word has length 53 [2021-10-28 09:50:54,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:54,862 INFO L470 AbstractCegarLoop]: Abstraction has 303 states and 432 transitions. [2021-10-28 09:50:54,862 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:54,862 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 432 transitions. [2021-10-28 09:50:54,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2021-10-28 09:50:54,866 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:54,866 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:54,866 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-10-28 09:50:54,868 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:54,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:54,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1396202520, now seen corresponding path program 1 times [2021-10-28 09:50:54,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:54,872 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334253899] [2021-10-28 09:50:54,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:54,872 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:54,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:55,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:55,039 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:55,039 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334253899] [2021-10-28 09:50:55,040 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334253899] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:55,040 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:55,040 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:55,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425145239] [2021-10-28 09:50:55,042 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:55,042 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:55,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:55,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:55,043 INFO L87 Difference]: Start difference. First operand 303 states and 432 transitions. Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:55,111 INFO L93 Difference]: Finished difference Result 831 states and 1196 transitions. [2021-10-28 09:50:55,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:55,112 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2021-10-28 09:50:55,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:55,120 INFO L225 Difference]: With dead ends: 831 [2021-10-28 09:50:55,120 INFO L226 Difference]: Without dead ends: 545 [2021-10-28 09:50:55,121 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:55,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2021-10-28 09:50:55,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 328. [2021-10-28 09:50:55,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 328 states, 309 states have (on average 1.5210355987055015) internal successors, (470), 327 states have internal predecessors, (470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 470 transitions. [2021-10-28 09:50:55,143 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 470 transitions. Word has length 54 [2021-10-28 09:50:55,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:55,145 INFO L470 AbstractCegarLoop]: Abstraction has 328 states and 470 transitions. [2021-10-28 09:50:55,145 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,145 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 470 transitions. [2021-10-28 09:50:55,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2021-10-28 09:50:55,148 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:55,148 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:55,148 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-10-28 09:50:55,149 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:55,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:55,150 INFO L85 PathProgramCache]: Analyzing trace with hash -716144150, now seen corresponding path program 1 times [2021-10-28 09:50:55,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:55,150 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832870629] [2021-10-28 09:50:55,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:55,151 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:55,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:55,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:55,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:55,306 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832870629] [2021-10-28 09:50:55,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832870629] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:55,307 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:55,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:50:55,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450075757] [2021-10-28 09:50:55,308 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-10-28 09:50:55,308 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:55,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:50:55,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:50:55,309 INFO L87 Difference]: Start difference. First operand 328 states and 470 transitions. Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:55,596 INFO L93 Difference]: Finished difference Result 1020 states and 1473 transitions. [2021-10-28 09:50:55,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 09:50:55,597 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 10.8) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2021-10-28 09:50:55,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:55,612 INFO L225 Difference]: With dead ends: 1020 [2021-10-28 09:50:55,613 INFO L226 Difference]: Without dead ends: 709 [2021-10-28 09:50:55,614 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2021-10-28 09:50:55,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709 states. [2021-10-28 09:50:55,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709 to 426. [2021-10-28 09:50:55,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 426 states, 407 states have (on average 1.4914004914004915) internal successors, (607), 425 states have internal predecessors, (607), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 426 states to 426 states and 607 transitions. [2021-10-28 09:50:55,648 INFO L78 Accepts]: Start accepts. Automaton has 426 states and 607 transitions. Word has length 54 [2021-10-28 09:50:55,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:55,648 INFO L470 AbstractCegarLoop]: Abstraction has 426 states and 607 transitions. [2021-10-28 09:50:55,649 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 10.8) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:55,649 INFO L276 IsEmpty]: Start isEmpty. Operand 426 states and 607 transitions. [2021-10-28 09:50:55,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2021-10-28 09:50:55,651 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:55,651 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:55,651 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-10-28 09:50:55,652 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:55,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:55,652 INFO L85 PathProgramCache]: Analyzing trace with hash 153208358, now seen corresponding path program 1 times [2021-10-28 09:50:55,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:55,658 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687495672] [2021-10-28 09:50:55,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:55,659 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:55,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:55,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:55,769 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:55,770 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687495672] [2021-10-28 09:50:55,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687495672] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:55,770 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:55,770 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:50:55,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507126156] [2021-10-28 09:50:55,771 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-10-28 09:50:55,771 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:55,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:50:55,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:50:55,773 INFO L87 Difference]: Start difference. First operand 426 states and 607 transitions. Second operand has 5 states, 5 states have (on average 11.0) internal successors, (55), 4 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:56,038 INFO L93 Difference]: Finished difference Result 1024 states and 1473 transitions. [2021-10-28 09:50:56,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 09:50:56,039 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.0) internal successors, (55), 4 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 55 [2021-10-28 09:50:56,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:56,044 INFO L225 Difference]: With dead ends: 1024 [2021-10-28 09:50:56,044 INFO L226 Difference]: Without dead ends: 713 [2021-10-28 09:50:56,046 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2021-10-28 09:50:56,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2021-10-28 09:50:56,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 434. [2021-10-28 09:50:56,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 434 states, 415 states have (on average 1.4819277108433735) internal successors, (615), 433 states have internal predecessors, (615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 615 transitions. [2021-10-28 09:50:56,075 INFO L78 Accepts]: Start accepts. Automaton has 434 states and 615 transitions. Word has length 55 [2021-10-28 09:50:56,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:56,075 INFO L470 AbstractCegarLoop]: Abstraction has 434 states and 615 transitions. [2021-10-28 09:50:56,076 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.0) internal successors, (55), 4 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,076 INFO L276 IsEmpty]: Start isEmpty. Operand 434 states and 615 transitions. [2021-10-28 09:50:56,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2021-10-28 09:50:56,077 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:56,077 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:56,077 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-10-28 09:50:56,077 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:56,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:56,078 INFO L85 PathProgramCache]: Analyzing trace with hash -748848364, now seen corresponding path program 1 times [2021-10-28 09:50:56,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:56,078 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899850419] [2021-10-28 09:50:56,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:56,079 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:56,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:56,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:56,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:56,212 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899850419] [2021-10-28 09:50:56,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899850419] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:56,212 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:56,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:50:56,213 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53253896] [2021-10-28 09:50:56,213 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:50:56,213 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:56,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:50:56,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:50:56,214 INFO L87 Difference]: Start difference. First operand 434 states and 615 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:56,476 INFO L93 Difference]: Finished difference Result 1024 states and 1465 transitions. [2021-10-28 09:50:56,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:50:56,477 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 57 [2021-10-28 09:50:56,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:56,483 INFO L225 Difference]: With dead ends: 1024 [2021-10-28 09:50:56,483 INFO L226 Difference]: Without dead ends: 713 [2021-10-28 09:50:56,485 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:50:56,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2021-10-28 09:50:56,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 434. [2021-10-28 09:50:56,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 434 states, 415 states have (on average 1.472289156626506) internal successors, (611), 433 states have internal predecessors, (611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 611 transitions. [2021-10-28 09:50:56,519 INFO L78 Accepts]: Start accepts. Automaton has 434 states and 611 transitions. Word has length 57 [2021-10-28 09:50:56,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:56,521 INFO L470 AbstractCegarLoop]: Abstraction has 434 states and 611 transitions. [2021-10-28 09:50:56,521 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,521 INFO L276 IsEmpty]: Start isEmpty. Operand 434 states and 611 transitions. [2021-10-28 09:50:56,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-10-28 09:50:56,522 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:56,522 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:56,522 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-10-28 09:50:56,523 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:56,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:56,523 INFO L85 PathProgramCache]: Analyzing trace with hash 2035065116, now seen corresponding path program 1 times [2021-10-28 09:50:56,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:56,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57570326] [2021-10-28 09:50:56,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:56,524 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:56,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:56,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:56,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:56,658 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57570326] [2021-10-28 09:50:56,659 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57570326] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:56,659 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:56,659 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:56,659 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819074431] [2021-10-28 09:50:56,661 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:56,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:56,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:56,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:56,667 INFO L87 Difference]: Start difference. First operand 434 states and 611 transitions. Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:56,720 INFO L93 Difference]: Finished difference Result 872 states and 1252 transitions. [2021-10-28 09:50:56,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:56,721 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 58 [2021-10-28 09:50:56,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:56,726 INFO L225 Difference]: With dead ends: 872 [2021-10-28 09:50:56,726 INFO L226 Difference]: Without dead ends: 561 [2021-10-28 09:50:56,727 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:56,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states. [2021-10-28 09:50:56,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 429. [2021-10-28 09:50:56,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 429 states, 411 states have (on average 1.467153284671533) internal successors, (603), 428 states have internal predecessors, (603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 603 transitions. [2021-10-28 09:50:56,755 INFO L78 Accepts]: Start accepts. Automaton has 429 states and 603 transitions. Word has length 58 [2021-10-28 09:50:56,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:56,755 INFO L470 AbstractCegarLoop]: Abstraction has 429 states and 603 transitions. [2021-10-28 09:50:56,755 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,756 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 603 transitions. [2021-10-28 09:50:56,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-10-28 09:50:56,756 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:56,757 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:56,757 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-10-28 09:50:56,757 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:56,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:56,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1833641356, now seen corresponding path program 1 times [2021-10-28 09:50:56,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:56,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127287492] [2021-10-28 09:50:56,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:56,760 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:56,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:56,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:56,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:56,887 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127287492] [2021-10-28 09:50:56,887 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127287492] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:56,888 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:56,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:56,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048463375] [2021-10-28 09:50:56,890 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:56,890 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:56,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:56,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:56,892 INFO L87 Difference]: Start difference. First operand 429 states and 603 transitions. Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:56,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:56,981 INFO L93 Difference]: Finished difference Result 871 states and 1251 transitions. [2021-10-28 09:50:56,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:56,981 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 62 [2021-10-28 09:50:56,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:56,985 INFO L225 Difference]: With dead ends: 871 [2021-10-28 09:50:56,986 INFO L226 Difference]: Without dead ends: 565 [2021-10-28 09:50:56,986 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:56,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 565 states. [2021-10-28 09:50:57,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 565 to 409. [2021-10-28 09:50:57,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 409 states, 395 states have (on average 1.4455696202531645) internal successors, (571), 408 states have internal predecessors, (571), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 409 states and 571 transitions. [2021-10-28 09:50:57,015 INFO L78 Accepts]: Start accepts. Automaton has 409 states and 571 transitions. Word has length 62 [2021-10-28 09:50:57,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:57,016 INFO L470 AbstractCegarLoop]: Abstraction has 409 states and 571 transitions. [2021-10-28 09:50:57,016 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,016 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 571 transitions. [2021-10-28 09:50:57,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-28 09:50:57,017 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:57,017 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:57,018 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2021-10-28 09:50:57,018 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:57,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:57,019 INFO L85 PathProgramCache]: Analyzing trace with hash -532758708, now seen corresponding path program 1 times [2021-10-28 09:50:57,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:57,022 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760799246] [2021-10-28 09:50:57,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:57,022 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:57,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:57,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:57,103 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:57,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760799246] [2021-10-28 09:50:57,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760799246] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:57,104 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:57,104 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:57,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449562837] [2021-10-28 09:50:57,106 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:57,106 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:57,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:57,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:57,108 INFO L87 Difference]: Start difference. First operand 409 states and 571 transitions. Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:57,175 INFO L93 Difference]: Finished difference Result 839 states and 1195 transitions. [2021-10-28 09:50:57,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:57,176 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 66 [2021-10-28 09:50:57,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:57,180 INFO L225 Difference]: With dead ends: 839 [2021-10-28 09:50:57,180 INFO L226 Difference]: Without dead ends: 553 [2021-10-28 09:50:57,181 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:57,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2021-10-28 09:50:57,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 397. [2021-10-28 09:50:57,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 397 states, 385 states have (on average 1.4363636363636363) internal successors, (553), 396 states have internal predecessors, (553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 397 states and 553 transitions. [2021-10-28 09:50:57,208 INFO L78 Accepts]: Start accepts. Automaton has 397 states and 553 transitions. Word has length 66 [2021-10-28 09:50:57,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:57,208 INFO L470 AbstractCegarLoop]: Abstraction has 397 states and 553 transitions. [2021-10-28 09:50:57,208 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,209 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 553 transitions. [2021-10-28 09:50:57,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-10-28 09:50:57,216 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:57,216 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:57,217 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-10-28 09:50:57,217 INFO L402 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:57,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:57,217 INFO L85 PathProgramCache]: Analyzing trace with hash 949999250, now seen corresponding path program 1 times [2021-10-28 09:50:57,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:57,218 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738936404] [2021-10-28 09:50:57,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:57,218 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:57,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:57,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:57,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:57,322 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738936404] [2021-10-28 09:50:57,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738936404] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:57,323 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:57,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:57,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526308044] [2021-10-28 09:50:57,324 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:57,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:57,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:57,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:57,326 INFO L87 Difference]: Start difference. First operand 397 states and 553 transitions. Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:57,419 INFO L93 Difference]: Finished difference Result 835 states and 1187 transitions. [2021-10-28 09:50:57,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:57,420 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 67 [2021-10-28 09:50:57,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:57,424 INFO L225 Difference]: With dead ends: 835 [2021-10-28 09:50:57,425 INFO L226 Difference]: Without dead ends: 561 [2021-10-28 09:50:57,426 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:57,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states. [2021-10-28 09:50:57,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 377. [2021-10-28 09:50:57,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 369 states have (on average 1.4119241192411924) internal successors, (521), 376 states have internal predecessors, (521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 521 transitions. [2021-10-28 09:50:57,454 INFO L78 Accepts]: Start accepts. Automaton has 377 states and 521 transitions. Word has length 67 [2021-10-28 09:50:57,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:57,454 INFO L470 AbstractCegarLoop]: Abstraction has 377 states and 521 transitions. [2021-10-28 09:50:57,455 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,455 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 521 transitions. [2021-10-28 09:50:57,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-10-28 09:50:57,456 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:57,457 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:57,457 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2021-10-28 09:50:57,457 INFO L402 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:57,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:57,458 INFO L85 PathProgramCache]: Analyzing trace with hash -448644128, now seen corresponding path program 1 times [2021-10-28 09:50:57,458 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:57,458 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170799904] [2021-10-28 09:50:57,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:57,459 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:57,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:57,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:57,653 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:57,653 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170799904] [2021-10-28 09:50:57,653 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170799904] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:57,653 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:57,654 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:50:57,654 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754659926] [2021-10-28 09:50:57,654 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:50:57,655 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:57,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:50:57,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:50:57,656 INFO L87 Difference]: Start difference. First operand 377 states and 521 transitions. Second operand has 6 states, 6 states have (on average 12.0) internal successors, (72), 6 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:57,886 INFO L93 Difference]: Finished difference Result 1127 states and 1582 transitions. [2021-10-28 09:50:57,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:50:57,888 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.0) internal successors, (72), 6 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 72 [2021-10-28 09:50:57,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:57,894 INFO L225 Difference]: With dead ends: 1127 [2021-10-28 09:50:57,894 INFO L226 Difference]: Without dead ends: 873 [2021-10-28 09:50:57,895 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2021-10-28 09:50:57,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 873 states. [2021-10-28 09:50:57,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 873 to 427. [2021-10-28 09:50:57,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 427 states, 419 states have (on average 1.405727923627685) internal successors, (589), 426 states have internal predecessors, (589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 589 transitions. [2021-10-28 09:50:57,938 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 589 transitions. Word has length 72 [2021-10-28 09:50:57,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:57,938 INFO L470 AbstractCegarLoop]: Abstraction has 427 states and 589 transitions. [2021-10-28 09:50:57,939 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 12.0) internal successors, (72), 6 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:57,939 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 589 transitions. [2021-10-28 09:50:57,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-28 09:50:57,940 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:57,940 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:57,940 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2021-10-28 09:50:57,941 INFO L402 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:57,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:57,941 INFO L85 PathProgramCache]: Analyzing trace with hash 534764451, now seen corresponding path program 1 times [2021-10-28 09:50:57,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:57,942 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152076701] [2021-10-28 09:50:57,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:57,942 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:57,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:58,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:58,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:58,052 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152076701] [2021-10-28 09:50:58,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152076701] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:58,052 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:58,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:58,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534555439] [2021-10-28 09:50:58,053 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:58,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:58,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:58,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:58,055 INFO L87 Difference]: Start difference. First operand 427 states and 589 transitions. Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:58,131 INFO L93 Difference]: Finished difference Result 760 states and 1066 transitions. [2021-10-28 09:50:58,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:58,132 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 73 [2021-10-28 09:50:58,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:58,136 INFO L225 Difference]: With dead ends: 760 [2021-10-28 09:50:58,136 INFO L226 Difference]: Without dead ends: 506 [2021-10-28 09:50:58,138 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:58,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2021-10-28 09:50:58,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 423. [2021-10-28 09:50:58,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 423 states, 416 states have (on average 1.3990384615384615) internal successors, (582), 422 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 582 transitions. [2021-10-28 09:50:58,178 INFO L78 Accepts]: Start accepts. Automaton has 423 states and 582 transitions. Word has length 73 [2021-10-28 09:50:58,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:58,178 INFO L470 AbstractCegarLoop]: Abstraction has 423 states and 582 transitions. [2021-10-28 09:50:58,179 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,179 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 582 transitions. [2021-10-28 09:50:58,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-28 09:50:58,180 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:58,180 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:58,181 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2021-10-28 09:50:58,181 INFO L402 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:58,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:58,182 INFO L85 PathProgramCache]: Analyzing trace with hash -344815767, now seen corresponding path program 1 times [2021-10-28 09:50:58,182 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:58,182 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497914276] [2021-10-28 09:50:58,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:58,182 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:58,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:58,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:58,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:58,270 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497914276] [2021-10-28 09:50:58,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1497914276] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:58,271 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:58,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:50:58,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39168742] [2021-10-28 09:50:58,272 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:50:58,272 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:58,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:50:58,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:58,273 INFO L87 Difference]: Start difference. First operand 423 states and 582 transitions. Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:58,378 INFO L93 Difference]: Finished difference Result 859 states and 1203 transitions. [2021-10-28 09:50:58,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:50:58,379 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 73 [2021-10-28 09:50:58,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:58,383 INFO L225 Difference]: With dead ends: 859 [2021-10-28 09:50:58,384 INFO L226 Difference]: Without dead ends: 592 [2021-10-28 09:50:58,387 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:50:58,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2021-10-28 09:50:58,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 407. [2021-10-28 09:50:58,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 402 states have (on average 1.3830845771144278) internal successors, (556), 406 states have internal predecessors, (556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 556 transitions. [2021-10-28 09:50:58,434 INFO L78 Accepts]: Start accepts. Automaton has 407 states and 556 transitions. Word has length 73 [2021-10-28 09:50:58,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:58,435 INFO L470 AbstractCegarLoop]: Abstraction has 407 states and 556 transitions. [2021-10-28 09:50:58,435 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:58,436 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 556 transitions. [2021-10-28 09:50:58,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-10-28 09:50:58,437 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:58,437 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:58,438 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2021-10-28 09:50:58,438 INFO L402 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:58,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:58,441 INFO L85 PathProgramCache]: Analyzing trace with hash 317146558, now seen corresponding path program 1 times [2021-10-28 09:50:58,441 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:58,443 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819708153] [2021-10-28 09:50:58,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:58,444 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:58,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:58,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:58,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:58,610 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819708153] [2021-10-28 09:50:58,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819708153] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:58,613 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:58,613 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-10-28 09:50:58,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160908842] [2021-10-28 09:50:58,614 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2021-10-28 09:50:58,614 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:58,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-28 09:50:58,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2021-10-28 09:50:58,616 INFO L87 Difference]: Start difference. First operand 407 states and 556 transitions. Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:59,051 INFO L93 Difference]: Finished difference Result 1397 states and 1937 transitions. [2021-10-28 09:50:59,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:50:59,052 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 76 [2021-10-28 09:50:59,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:59,060 INFO L225 Difference]: With dead ends: 1397 [2021-10-28 09:50:59,060 INFO L226 Difference]: Without dead ends: 1141 [2021-10-28 09:50:59,062 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2021-10-28 09:50:59,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1141 states. [2021-10-28 09:50:59,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1141 to 435. [2021-10-28 09:50:59,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 430 states have (on average 1.3674418604651162) internal successors, (588), 434 states have internal predecessors, (588), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 588 transitions. [2021-10-28 09:50:59,112 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 588 transitions. Word has length 76 [2021-10-28 09:50:59,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:59,113 INFO L470 AbstractCegarLoop]: Abstraction has 435 states and 588 transitions. [2021-10-28 09:50:59,113 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,113 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 588 transitions. [2021-10-28 09:50:59,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-10-28 09:50:59,114 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:59,115 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:59,115 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2021-10-28 09:50:59,115 INFO L402 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:59,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:59,116 INFO L85 PathProgramCache]: Analyzing trace with hash 917353494, now seen corresponding path program 1 times [2021-10-28 09:50:59,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:59,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766434821] [2021-10-28 09:50:59,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:59,118 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:59,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:59,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:59,198 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:59,199 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766434821] [2021-10-28 09:50:59,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [766434821] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:59,199 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:59,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:50:59,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721074759] [2021-10-28 09:50:59,200 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:50:59,200 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:59,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:50:59,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:50:59,202 INFO L87 Difference]: Start difference. First operand 435 states and 588 transitions. Second operand has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:59,374 INFO L93 Difference]: Finished difference Result 1111 states and 1515 transitions. [2021-10-28 09:50:59,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:50:59,374 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 76 [2021-10-28 09:50:59,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:59,380 INFO L225 Difference]: With dead ends: 1111 [2021-10-28 09:50:59,380 INFO L226 Difference]: Without dead ends: 849 [2021-10-28 09:50:59,382 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:50:59,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 849 states. [2021-10-28 09:50:59,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 849 to 656. [2021-10-28 09:50:59,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 656 states, 651 states have (on average 1.348694316436252) internal successors, (878), 655 states have internal predecessors, (878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 656 states to 656 states and 878 transitions. [2021-10-28 09:50:59,449 INFO L78 Accepts]: Start accepts. Automaton has 656 states and 878 transitions. Word has length 76 [2021-10-28 09:50:59,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:59,450 INFO L470 AbstractCegarLoop]: Abstraction has 656 states and 878 transitions. [2021-10-28 09:50:59,450 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,450 INFO L276 IsEmpty]: Start isEmpty. Operand 656 states and 878 transitions. [2021-10-28 09:50:59,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2021-10-28 09:50:59,452 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:59,452 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:59,452 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2021-10-28 09:50:59,453 INFO L402 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:59,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:59,454 INFO L85 PathProgramCache]: Analyzing trace with hash -480894404, now seen corresponding path program 1 times [2021-10-28 09:50:59,454 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:59,455 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642042325] [2021-10-28 09:50:59,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:59,455 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:59,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:50:59,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:50:59,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:50:59,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642042325] [2021-10-28 09:50:59,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642042325] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:50:59,558 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:50:59,559 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:50:59,559 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402941246] [2021-10-28 09:50:59,561 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:50:59,561 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:50:59,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:50:59,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:50:59,563 INFO L87 Difference]: Start difference. First operand 656 states and 878 transitions. Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:50:59,776 INFO L93 Difference]: Finished difference Result 1019 states and 1388 transitions. [2021-10-28 09:50:59,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 09:50:59,777 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 77 [2021-10-28 09:50:59,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:50:59,784 INFO L225 Difference]: With dead ends: 1019 [2021-10-28 09:50:59,785 INFO L226 Difference]: Without dead ends: 1017 [2021-10-28 09:50:59,786 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2021-10-28 09:50:59,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states. [2021-10-28 09:50:59,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 658. [2021-10-28 09:50:59,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 658 states, 653 states have (on average 1.3476263399693722) internal successors, (880), 657 states have internal predecessors, (880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 880 transitions. [2021-10-28 09:50:59,872 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 880 transitions. Word has length 77 [2021-10-28 09:50:59,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:50:59,872 INFO L470 AbstractCegarLoop]: Abstraction has 658 states and 880 transitions. [2021-10-28 09:50:59,873 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:50:59,873 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 880 transitions. [2021-10-28 09:50:59,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2021-10-28 09:50:59,874 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:50:59,875 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:50:59,875 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2021-10-28 09:50:59,876 INFO L402 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:50:59,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:50:59,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1699767669, now seen corresponding path program 1 times [2021-10-28 09:50:59,877 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:50:59,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147399847] [2021-10-28 09:50:59,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:50:59,878 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:50:59,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:00,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:00,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:00,051 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147399847] [2021-10-28 09:51:00,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147399847] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:00,052 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:00,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:51:00,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2104732041] [2021-10-28 09:51:00,054 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:00,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:00,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:00,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:51:00,055 INFO L87 Difference]: Start difference. First operand 658 states and 880 transitions. Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:00,440 INFO L93 Difference]: Finished difference Result 1981 states and 2732 transitions. [2021-10-28 09:51:00,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:51:00,441 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 77 [2021-10-28 09:51:00,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:00,451 INFO L225 Difference]: With dead ends: 1981 [2021-10-28 09:51:00,451 INFO L226 Difference]: Without dead ends: 1602 [2021-10-28 09:51:00,453 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2021-10-28 09:51:00,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1602 states. [2021-10-28 09:51:00,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1602 to 646. [2021-10-28 09:51:00,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 646 states, 641 states have (on average 1.3510140405616224) internal successors, (866), 645 states have internal predecessors, (866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 646 states to 646 states and 866 transitions. [2021-10-28 09:51:00,542 INFO L78 Accepts]: Start accepts. Automaton has 646 states and 866 transitions. Word has length 77 [2021-10-28 09:51:00,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:00,543 INFO L470 AbstractCegarLoop]: Abstraction has 646 states and 866 transitions. [2021-10-28 09:51:00,543 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,543 INFO L276 IsEmpty]: Start isEmpty. Operand 646 states and 866 transitions. [2021-10-28 09:51:00,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-10-28 09:51:00,544 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:00,545 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:00,545 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2021-10-28 09:51:00,545 INFO L402 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:00,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:00,546 INFO L85 PathProgramCache]: Analyzing trace with hash 239208754, now seen corresponding path program 1 times [2021-10-28 09:51:00,546 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:00,546 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240716710] [2021-10-28 09:51:00,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:00,547 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:00,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:00,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:00,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:00,618 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240716710] [2021-10-28 09:51:00,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240716710] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:00,618 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:00,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:51:00,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515496589] [2021-10-28 09:51:00,619 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:00,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:00,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:00,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:51:00,621 INFO L87 Difference]: Start difference. First operand 646 states and 866 transitions. Second operand has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:00,859 INFO L93 Difference]: Finished difference Result 1537 states and 2160 transitions. [2021-10-28 09:51:00,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:51:00,859 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 78 [2021-10-28 09:51:00,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:00,866 INFO L225 Difference]: With dead ends: 1537 [2021-10-28 09:51:00,867 INFO L226 Difference]: Without dead ends: 1158 [2021-10-28 09:51:00,868 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2021-10-28 09:51:00,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1158 states. [2021-10-28 09:51:00,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1158 to 652. [2021-10-28 09:51:00,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 652 states, 647 states have (on average 1.3477588871715611) internal successors, (872), 651 states have internal predecessors, (872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 652 states to 652 states and 872 transitions. [2021-10-28 09:51:00,961 INFO L78 Accepts]: Start accepts. Automaton has 652 states and 872 transitions. Word has length 78 [2021-10-28 09:51:00,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:00,962 INFO L470 AbstractCegarLoop]: Abstraction has 652 states and 872 transitions. [2021-10-28 09:51:00,962 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:00,962 INFO L276 IsEmpty]: Start isEmpty. Operand 652 states and 872 transitions. [2021-10-28 09:51:00,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-10-28 09:51:00,963 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:00,964 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:00,964 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2021-10-28 09:51:00,964 INFO L402 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:00,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:00,965 INFO L85 PathProgramCache]: Analyzing trace with hash 341178161, now seen corresponding path program 1 times [2021-10-28 09:51:00,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:00,966 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245434363] [2021-10-28 09:51:00,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:00,966 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:00,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:01,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:01,024 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:01,024 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245434363] [2021-10-28 09:51:01,025 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245434363] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:01,025 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:01,025 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:01,025 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426990942] [2021-10-28 09:51:01,025 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:51:01,027 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:01,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:51:01,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:01,028 INFO L87 Difference]: Start difference. First operand 652 states and 872 transitions. Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:01,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:01,226 INFO L93 Difference]: Finished difference Result 1507 states and 2024 transitions. [2021-10-28 09:51:01,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:51:01,227 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 78 [2021-10-28 09:51:01,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:01,234 INFO L225 Difference]: With dead ends: 1507 [2021-10-28 09:51:01,234 INFO L226 Difference]: Without dead ends: 1104 [2021-10-28 09:51:01,235 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:01,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states. [2021-10-28 09:51:01,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 850. [2021-10-28 09:51:01,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 850 states, 845 states have (on average 1.3396449704142013) internal successors, (1132), 849 states have internal predecessors, (1132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:01,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 1132 transitions. [2021-10-28 09:51:01,363 INFO L78 Accepts]: Start accepts. Automaton has 850 states and 1132 transitions. Word has length 78 [2021-10-28 09:51:01,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:01,363 INFO L470 AbstractCegarLoop]: Abstraction has 850 states and 1132 transitions. [2021-10-28 09:51:01,364 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:01,364 INFO L276 IsEmpty]: Start isEmpty. Operand 850 states and 1132 transitions. [2021-10-28 09:51:01,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-10-28 09:51:01,366 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:01,366 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:01,366 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2021-10-28 09:51:01,366 INFO L402 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:01,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:01,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1360037685, now seen corresponding path program 1 times [2021-10-28 09:51:01,367 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:01,368 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197544439] [2021-10-28 09:51:01,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:01,368 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:01,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:01,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:01,499 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:01,499 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197544439] [2021-10-28 09:51:01,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197544439] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:01,499 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:01,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:51:01,500 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631509375] [2021-10-28 09:51:01,500 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:01,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:01,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:01,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:51:01,502 INFO L87 Difference]: Start difference. First operand 850 states and 1132 transitions. Second operand has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:02,132 INFO L93 Difference]: Finished difference Result 3240 states and 4364 transitions. [2021-10-28 09:51:02,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:51:02,133 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 78 [2021-10-28 09:51:02,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:02,148 INFO L225 Difference]: With dead ends: 3240 [2021-10-28 09:51:02,149 INFO L226 Difference]: Without dead ends: 2706 [2021-10-28 09:51:02,151 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2021-10-28 09:51:02,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2706 states. [2021-10-28 09:51:02,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2706 to 900. [2021-10-28 09:51:02,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 900 states, 895 states have (on average 1.336312849162011) internal successors, (1196), 899 states have internal predecessors, (1196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900 states to 900 states and 1196 transitions. [2021-10-28 09:51:02,284 INFO L78 Accepts]: Start accepts. Automaton has 900 states and 1196 transitions. Word has length 78 [2021-10-28 09:51:02,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:02,284 INFO L470 AbstractCegarLoop]: Abstraction has 900 states and 1196 transitions. [2021-10-28 09:51:02,284 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 13.0) internal successors, (78), 6 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,285 INFO L276 IsEmpty]: Start isEmpty. Operand 900 states and 1196 transitions. [2021-10-28 09:51:02,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2021-10-28 09:51:02,286 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:02,286 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:02,287 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2021-10-28 09:51:02,287 INFO L402 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:02,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:02,288 INFO L85 PathProgramCache]: Analyzing trace with hash -504696615, now seen corresponding path program 1 times [2021-10-28 09:51:02,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:02,288 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794574935] [2021-10-28 09:51:02,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:02,288 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:02,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:02,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:02,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:02,352 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794574935] [2021-10-28 09:51:02,352 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [794574935] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:02,352 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:02,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:02,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455797465] [2021-10-28 09:51:02,355 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:51:02,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:02,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:51:02,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:02,357 INFO L87 Difference]: Start difference. First operand 900 states and 1196 transitions. Second operand has 4 states, 4 states have (on average 19.75) internal successors, (79), 4 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:02,630 INFO L93 Difference]: Finished difference Result 2315 states and 3085 transitions. [2021-10-28 09:51:02,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:51:02,631 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.75) internal successors, (79), 4 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 79 [2021-10-28 09:51:02,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:02,641 INFO L225 Difference]: With dead ends: 2315 [2021-10-28 09:51:02,641 INFO L226 Difference]: Without dead ends: 1728 [2021-10-28 09:51:02,643 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:02,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1728 states. [2021-10-28 09:51:02,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1728 to 1255. [2021-10-28 09:51:02,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1255 states, 1250 states have (on average 1.3248) internal successors, (1656), 1254 states have internal predecessors, (1656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1255 states to 1255 states and 1656 transitions. [2021-10-28 09:51:02,811 INFO L78 Accepts]: Start accepts. Automaton has 1255 states and 1656 transitions. Word has length 79 [2021-10-28 09:51:02,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:02,812 INFO L470 AbstractCegarLoop]: Abstraction has 1255 states and 1656 transitions. [2021-10-28 09:51:02,812 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.75) internal successors, (79), 4 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:02,812 INFO L276 IsEmpty]: Start isEmpty. Operand 1255 states and 1656 transitions. [2021-10-28 09:51:02,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2021-10-28 09:51:02,814 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:02,814 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:02,814 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2021-10-28 09:51:02,815 INFO L402 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:02,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:02,815 INFO L85 PathProgramCache]: Analyzing trace with hash -676572605, now seen corresponding path program 1 times [2021-10-28 09:51:02,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:02,816 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433248119] [2021-10-28 09:51:02,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:02,816 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:02,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:02,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:02,868 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:02,868 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433248119] [2021-10-28 09:51:02,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433248119] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:02,868 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:02,868 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:51:02,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578097504] [2021-10-28 09:51:02,869 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:51:02,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:02,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:51:02,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:51:02,870 INFO L87 Difference]: Start difference. First operand 1255 states and 1656 transitions. Second operand has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:03,194 INFO L93 Difference]: Finished difference Result 3061 states and 4041 transitions. [2021-10-28 09:51:03,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:51:03,195 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 80 [2021-10-28 09:51:03,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:03,206 INFO L225 Difference]: With dead ends: 3061 [2021-10-28 09:51:03,206 INFO L226 Difference]: Without dead ends: 2076 [2021-10-28 09:51:03,208 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:51:03,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2021-10-28 09:51:03,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 1257. [2021-10-28 09:51:03,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1257 states, 1252 states have (on average 1.3242811501597445) internal successors, (1658), 1256 states have internal predecessors, (1658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1257 states to 1257 states and 1658 transitions. [2021-10-28 09:51:03,405 INFO L78 Accepts]: Start accepts. Automaton has 1257 states and 1658 transitions. Word has length 80 [2021-10-28 09:51:03,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:03,406 INFO L470 AbstractCegarLoop]: Abstraction has 1257 states and 1658 transitions. [2021-10-28 09:51:03,406 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,407 INFO L276 IsEmpty]: Start isEmpty. Operand 1257 states and 1658 transitions. [2021-10-28 09:51:03,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2021-10-28 09:51:03,409 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:03,409 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:03,409 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2021-10-28 09:51:03,409 INFO L402 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:03,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:03,410 INFO L85 PathProgramCache]: Analyzing trace with hash -659983772, now seen corresponding path program 1 times [2021-10-28 09:51:03,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:03,411 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9928067] [2021-10-28 09:51:03,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:03,411 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:03,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:03,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:03,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:03,494 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9928067] [2021-10-28 09:51:03,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9928067] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:03,495 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:03,495 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:03,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664164380] [2021-10-28 09:51:03,495 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:51:03,496 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:03,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:51:03,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:03,497 INFO L87 Difference]: Start difference. First operand 1257 states and 1658 transitions. Second operand has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:03,742 INFO L93 Difference]: Finished difference Result 2597 states and 3427 transitions. [2021-10-28 09:51:03,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:51:03,742 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 81 [2021-10-28 09:51:03,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:03,750 INFO L225 Difference]: With dead ends: 2597 [2021-10-28 09:51:03,750 INFO L226 Difference]: Without dead ends: 1416 [2021-10-28 09:51:03,752 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:03,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1416 states. [2021-10-28 09:51:03,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1416 to 1054. [2021-10-28 09:51:03,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1054 states, 1049 states have (on average 1.321258341277407) internal successors, (1386), 1053 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1054 states to 1054 states and 1386 transitions. [2021-10-28 09:51:03,905 INFO L78 Accepts]: Start accepts. Automaton has 1054 states and 1386 transitions. Word has length 81 [2021-10-28 09:51:03,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:03,905 INFO L470 AbstractCegarLoop]: Abstraction has 1054 states and 1386 transitions. [2021-10-28 09:51:03,906 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 20.25) internal successors, (81), 4 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:03,906 INFO L276 IsEmpty]: Start isEmpty. Operand 1054 states and 1386 transitions. [2021-10-28 09:51:03,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2021-10-28 09:51:03,908 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:03,908 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:03,908 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2021-10-28 09:51:03,908 INFO L402 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:03,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:03,909 INFO L85 PathProgramCache]: Analyzing trace with hash -63459148, now seen corresponding path program 1 times [2021-10-28 09:51:03,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:03,909 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347838943] [2021-10-28 09:51:03,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:03,909 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:03,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:03,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:03,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:03,961 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347838943] [2021-10-28 09:51:03,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347838943] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:03,962 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:03,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 09:51:03,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388895418] [2021-10-28 09:51:03,963 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-10-28 09:51:03,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:03,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 09:51:03,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:51:03,964 INFO L87 Difference]: Start difference. First operand 1054 states and 1386 transitions. Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:04,261 INFO L93 Difference]: Finished difference Result 2488 states and 3290 transitions. [2021-10-28 09:51:04,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 09:51:04,262 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 82 [2021-10-28 09:51:04,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:04,271 INFO L225 Difference]: With dead ends: 2488 [2021-10-28 09:51:04,271 INFO L226 Difference]: Without dead ends: 1583 [2021-10-28 09:51:04,273 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 09:51:04,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1583 states. [2021-10-28 09:51:04,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1583 to 1060. [2021-10-28 09:51:04,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1060 states, 1055 states have (on average 1.3194312796208532) internal successors, (1392), 1059 states have internal predecessors, (1392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 1060 states and 1392 transitions. [2021-10-28 09:51:04,449 INFO L78 Accepts]: Start accepts. Automaton has 1060 states and 1392 transitions. Word has length 82 [2021-10-28 09:51:04,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:04,449 INFO L470 AbstractCegarLoop]: Abstraction has 1060 states and 1392 transitions. [2021-10-28 09:51:04,449 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,450 INFO L276 IsEmpty]: Start isEmpty. Operand 1060 states and 1392 transitions. [2021-10-28 09:51:04,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2021-10-28 09:51:04,451 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:04,451 INFO L513 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:04,451 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2021-10-28 09:51:04,452 INFO L402 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:04,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:04,452 INFO L85 PathProgramCache]: Analyzing trace with hash -753963456, now seen corresponding path program 1 times [2021-10-28 09:51:04,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:04,453 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359494821] [2021-10-28 09:51:04,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:04,453 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:04,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:04,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:04,522 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:04,522 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359494821] [2021-10-28 09:51:04,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359494821] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:04,524 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:04,525 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:04,525 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061705908] [2021-10-28 09:51:04,525 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:51:04,526 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:04,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:51:04,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:04,527 INFO L87 Difference]: Start difference. First operand 1060 states and 1392 transitions. Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 4 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:04,767 INFO L93 Difference]: Finished difference Result 2437 states and 3211 transitions. [2021-10-28 09:51:04,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:51:04,778 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 20.5) internal successors, (82), 4 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 82 [2021-10-28 09:51:04,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:04,786 INFO L225 Difference]: With dead ends: 2437 [2021-10-28 09:51:04,786 INFO L226 Difference]: Without dead ends: 1476 [2021-10-28 09:51:04,793 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:04,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states. [2021-10-28 09:51:04,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1000. [2021-10-28 09:51:04,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1000 states, 995 states have (on average 1.3145728643216081) internal successors, (1308), 999 states have internal predecessors, (1308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1000 states to 1000 states and 1308 transitions. [2021-10-28 09:51:04,974 INFO L78 Accepts]: Start accepts. Automaton has 1000 states and 1308 transitions. Word has length 82 [2021-10-28 09:51:04,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:04,974 INFO L470 AbstractCegarLoop]: Abstraction has 1000 states and 1308 transitions. [2021-10-28 09:51:04,974 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 20.5) internal successors, (82), 4 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:04,975 INFO L276 IsEmpty]: Start isEmpty. Operand 1000 states and 1308 transitions. [2021-10-28 09:51:04,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2021-10-28 09:51:04,977 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:04,978 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:04,978 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2021-10-28 09:51:04,978 INFO L402 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:04,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:04,979 INFO L85 PathProgramCache]: Analyzing trace with hash 196290815, now seen corresponding path program 1 times [2021-10-28 09:51:04,979 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:04,979 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750124350] [2021-10-28 09:51:04,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:04,980 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:05,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:05,148 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 18 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:05,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:05,149 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [750124350] [2021-10-28 09:51:05,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [750124350] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:05,149 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2094381473] [2021-10-28 09:51:05,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:05,150 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:05,150 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:05,156 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:05,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-10-28 09:51:05,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:05,382 INFO L263 TraceCheckSpWp]: Trace formula consists of 712 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 09:51:05,395 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:05,982 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-10-28 09:51:05,982 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2094381473] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:05,983 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-10-28 09:51:05,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 12 [2021-10-28 09:51:05,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020776579] [2021-10-28 09:51:05,984 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:05,984 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:05,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:05,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2021-10-28 09:51:05,985 INFO L87 Difference]: Start difference. First operand 1000 states and 1308 transitions. Second operand has 6 states, 6 states have (on average 21.0) internal successors, (126), 6 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:06,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:06,533 INFO L93 Difference]: Finished difference Result 2594 states and 3522 transitions. [2021-10-28 09:51:06,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:51:06,534 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 21.0) internal successors, (126), 6 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 127 [2021-10-28 09:51:06,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:06,556 INFO L225 Difference]: With dead ends: 2594 [2021-10-28 09:51:06,563 INFO L226 Difference]: Without dead ends: 1781 [2021-10-28 09:51:06,565 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=199, Unknown=0, NotChecked=0, Total=240 [2021-10-28 09:51:06,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1781 states. [2021-10-28 09:51:06,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1781 to 1000. [2021-10-28 09:51:06,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1000 states, 995 states have (on average 1.31356783919598) internal successors, (1307), 999 states have internal predecessors, (1307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:06,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1000 states to 1000 states and 1307 transitions. [2021-10-28 09:51:06,740 INFO L78 Accepts]: Start accepts. Automaton has 1000 states and 1307 transitions. Word has length 127 [2021-10-28 09:51:06,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:06,741 INFO L470 AbstractCegarLoop]: Abstraction has 1000 states and 1307 transitions. [2021-10-28 09:51:06,741 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 21.0) internal successors, (126), 6 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:06,741 INFO L276 IsEmpty]: Start isEmpty. Operand 1000 states and 1307 transitions. [2021-10-28 09:51:06,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2021-10-28 09:51:06,744 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:06,744 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:06,787 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:06,957 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2021-10-28 09:51:06,958 INFO L402 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:06,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:06,958 INFO L85 PathProgramCache]: Analyzing trace with hash 537443172, now seen corresponding path program 1 times [2021-10-28 09:51:06,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:06,959 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582118055] [2021-10-28 09:51:06,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:06,959 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:07,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:07,125 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 18 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:07,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:07,126 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582118055] [2021-10-28 09:51:07,126 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582118055] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:07,126 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1891383770] [2021-10-28 09:51:07,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:07,126 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:07,127 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:07,128 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:07,157 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-10-28 09:51:07,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:07,403 INFO L263 TraceCheckSpWp]: Trace formula consists of 726 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 09:51:07,417 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:08,083 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 16 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:08,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1891383770] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:08,084 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:08,084 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 13 [2021-10-28 09:51:08,084 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037727537] [2021-10-28 09:51:08,085 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2021-10-28 09:51:08,085 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:08,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-10-28 09:51:08,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2021-10-28 09:51:08,087 INFO L87 Difference]: Start difference. First operand 1000 states and 1307 transitions. Second operand has 13 states, 13 states have (on average 19.692307692307693) internal successors, (256), 13 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:20,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:20,507 INFO L93 Difference]: Finished difference Result 16786 states and 22448 transitions. [2021-10-28 09:51:20,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 242 states. [2021-10-28 09:51:20,508 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 19.692307692307693) internal successors, (256), 13 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 131 [2021-10-28 09:51:20,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:20,554 INFO L225 Difference]: With dead ends: 16786 [2021-10-28 09:51:20,555 INFO L226 Difference]: Without dead ends: 15979 [2021-10-28 09:51:20,583 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 474 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 251 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28995 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=8289, Invalid=55467, Unknown=0, NotChecked=0, Total=63756 [2021-10-28 09:51:20,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15979 states. [2021-10-28 09:51:21,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15979 to 2718. [2021-10-28 09:51:21,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2718 states, 2713 states have (on average 1.3110947290821968) internal successors, (3557), 2717 states have internal predecessors, (3557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:21,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2718 states to 2718 states and 3557 transitions. [2021-10-28 09:51:21,305 INFO L78 Accepts]: Start accepts. Automaton has 2718 states and 3557 transitions. Word has length 131 [2021-10-28 09:51:21,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:21,305 INFO L470 AbstractCegarLoop]: Abstraction has 2718 states and 3557 transitions. [2021-10-28 09:51:21,306 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 19.692307692307693) internal successors, (256), 13 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:21,307 INFO L276 IsEmpty]: Start isEmpty. Operand 2718 states and 3557 transitions. [2021-10-28 09:51:21,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2021-10-28 09:51:21,313 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:21,313 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:21,366 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:21,539 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2021-10-28 09:51:21,540 INFO L402 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:21,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:21,541 INFO L85 PathProgramCache]: Analyzing trace with hash -57966914, now seen corresponding path program 1 times [2021-10-28 09:51:21,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:21,541 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472411516] [2021-10-28 09:51:21,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:21,541 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:21,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:21,761 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 8 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:21,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:21,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472411516] [2021-10-28 09:51:21,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472411516] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:21,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [963650273] [2021-10-28 09:51:21,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:21,763 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:21,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:21,764 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:21,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-10-28 09:51:22,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:22,073 INFO L263 TraceCheckSpWp]: Trace formula consists of 778 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 09:51:22,079 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:22,557 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 8 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:22,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [963650273] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:22,557 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:22,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 8 [2021-10-28 09:51:22,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099731171] [2021-10-28 09:51:22,558 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2021-10-28 09:51:22,558 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:22,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-10-28 09:51:22,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2021-10-28 09:51:22,559 INFO L87 Difference]: Start difference. First operand 2718 states and 3557 transitions. Second operand has 8 states, 8 states have (on average 20.0) internal successors, (160), 8 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:24,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:24,011 INFO L93 Difference]: Finished difference Result 9790 states and 13378 transitions. [2021-10-28 09:51:24,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-10-28 09:51:24,012 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 20.0) internal successors, (160), 8 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 132 [2021-10-28 09:51:24,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:24,028 INFO L225 Difference]: With dead ends: 9790 [2021-10-28 09:51:24,029 INFO L226 Difference]: Without dead ends: 7299 [2021-10-28 09:51:24,034 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 142 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=146, Invalid=360, Unknown=0, NotChecked=0, Total=506 [2021-10-28 09:51:24,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7299 states. [2021-10-28 09:51:24,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7299 to 2324. [2021-10-28 09:51:24,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2324 states, 2319 states have (on average 1.314359637774903) internal successors, (3048), 2323 states have internal predecessors, (3048), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:24,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 3048 transitions. [2021-10-28 09:51:24,456 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 3048 transitions. Word has length 132 [2021-10-28 09:51:24,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:24,457 INFO L470 AbstractCegarLoop]: Abstraction has 2324 states and 3048 transitions. [2021-10-28 09:51:24,457 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 20.0) internal successors, (160), 8 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:24,457 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 3048 transitions. [2021-10-28 09:51:24,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2021-10-28 09:51:24,464 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:24,464 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:24,499 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-10-28 09:51:24,679 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:24,680 INFO L402 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:24,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:24,680 INFO L85 PathProgramCache]: Analyzing trace with hash -812401068, now seen corresponding path program 1 times [2021-10-28 09:51:24,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:24,681 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294209846] [2021-10-28 09:51:24,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:24,681 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:24,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:24,817 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-10-28 09:51:24,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:24,818 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294209846] [2021-10-28 09:51:24,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294209846] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:24,818 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:24,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-10-28 09:51:24,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496802083] [2021-10-28 09:51:24,820 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2021-10-28 09:51:24,820 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:24,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-28 09:51:24,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-10-28 09:51:24,821 INFO L87 Difference]: Start difference. First operand 2324 states and 3048 transitions. Second operand has 7 states, 7 states have (on average 16.428571428571427) internal successors, (115), 7 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:26,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:26,657 INFO L93 Difference]: Finished difference Result 13266 states and 17764 transitions. [2021-10-28 09:51:26,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-10-28 09:51:26,658 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 16.428571428571427) internal successors, (115), 7 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 133 [2021-10-28 09:51:26,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:26,687 INFO L225 Difference]: With dead ends: 13266 [2021-10-28 09:51:26,687 INFO L226 Difference]: Without dead ends: 11189 [2021-10-28 09:51:26,693 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=90, Invalid=252, Unknown=0, NotChecked=0, Total=342 [2021-10-28 09:51:26,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11189 states. [2021-10-28 09:51:27,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11189 to 2744. [2021-10-28 09:51:27,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2744 states, 2739 states have (on average 1.2942679810149689) internal successors, (3545), 2743 states have internal predecessors, (3545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:27,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2744 states to 2744 states and 3545 transitions. [2021-10-28 09:51:27,164 INFO L78 Accepts]: Start accepts. Automaton has 2744 states and 3545 transitions. Word has length 133 [2021-10-28 09:51:27,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:27,165 INFO L470 AbstractCegarLoop]: Abstraction has 2744 states and 3545 transitions. [2021-10-28 09:51:27,165 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 16.428571428571427) internal successors, (115), 7 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:27,165 INFO L276 IsEmpty]: Start isEmpty. Operand 2744 states and 3545 transitions. [2021-10-28 09:51:27,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2021-10-28 09:51:27,172 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:27,172 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:27,173 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2021-10-28 09:51:27,173 INFO L402 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:27,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:27,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1166749575, now seen corresponding path program 1 times [2021-10-28 09:51:27,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:27,174 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018736983] [2021-10-28 09:51:27,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:27,175 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:27,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:27,320 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 18 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:27,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:27,321 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018736983] [2021-10-28 09:51:27,321 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018736983] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:27,321 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [319238232] [2021-10-28 09:51:27,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:27,322 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:27,322 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:27,328 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:27,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-10-28 09:51:27,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:27,712 INFO L263 TraceCheckSpWp]: Trace formula consists of 757 conjuncts, 12 conjunts are in the unsatisfiable core [2021-10-28 09:51:27,715 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:28,089 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2021-10-28 09:51:28,089 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [319238232] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:28,089 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:28,089 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5] total 11 [2021-10-28 09:51:28,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707513248] [2021-10-28 09:51:28,090 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2021-10-28 09:51:28,090 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:28,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-10-28 09:51:28,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2021-10-28 09:51:28,091 INFO L87 Difference]: Start difference. First operand 2744 states and 3545 transitions. Second operand has 11 states, 11 states have (on average 20.90909090909091) internal successors, (230), 11 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:29,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:29,937 INFO L93 Difference]: Finished difference Result 5987 states and 7865 transitions. [2021-10-28 09:51:29,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-10-28 09:51:29,937 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 20.90909090909091) internal successors, (230), 11 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 135 [2021-10-28 09:51:29,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:29,945 INFO L225 Difference]: With dead ends: 5987 [2021-10-28 09:51:29,945 INFO L226 Difference]: Without dead ends: 3338 [2021-10-28 09:51:29,949 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 621 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=525, Invalid=1545, Unknown=0, NotChecked=0, Total=2070 [2021-10-28 09:51:29,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3338 states. [2021-10-28 09:51:30,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3338 to 1878. [2021-10-28 09:51:30,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1878 states, 1873 states have (on average 1.2819006940736786) internal successors, (2401), 1877 states have internal predecessors, (2401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:30,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1878 states to 1878 states and 2401 transitions. [2021-10-28 09:51:30,298 INFO L78 Accepts]: Start accepts. Automaton has 1878 states and 2401 transitions. Word has length 135 [2021-10-28 09:51:30,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:30,298 INFO L470 AbstractCegarLoop]: Abstraction has 1878 states and 2401 transitions. [2021-10-28 09:51:30,298 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 20.90909090909091) internal successors, (230), 11 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:30,299 INFO L276 IsEmpty]: Start isEmpty. Operand 1878 states and 2401 transitions. [2021-10-28 09:51:30,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2021-10-28 09:51:30,302 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:30,302 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:30,323 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:30,502 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:30,503 INFO L402 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:30,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:30,503 INFO L85 PathProgramCache]: Analyzing trace with hash -2040989094, now seen corresponding path program 1 times [2021-10-28 09:51:30,503 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:30,503 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934085273] [2021-10-28 09:51:30,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:30,504 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:30,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:30,704 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 26 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:30,705 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:30,705 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934085273] [2021-10-28 09:51:30,705 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934085273] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:30,705 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [607546987] [2021-10-28 09:51:30,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:30,705 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:30,705 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:30,708 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:30,733 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2021-10-28 09:51:31,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:31,087 INFO L263 TraceCheckSpWp]: Trace formula consists of 781 conjuncts, 9 conjunts are in the unsatisfiable core [2021-10-28 09:51:31,090 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:31,419 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-10-28 09:51:31,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [607546987] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:31,420 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-10-28 09:51:31,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2021-10-28 09:51:31,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115745160] [2021-10-28 09:51:31,421 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:31,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:31,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:31,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2021-10-28 09:51:31,422 INFO L87 Difference]: Start difference. First operand 1878 states and 2401 transitions. Second operand has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:32,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:32,119 INFO L93 Difference]: Finished difference Result 5950 states and 7855 transitions. [2021-10-28 09:51:32,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:51:32,119 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 135 [2021-10-28 09:51:32,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:32,125 INFO L225 Difference]: With dead ends: 5950 [2021-10-28 09:51:32,125 INFO L226 Difference]: Without dead ends: 4227 [2021-10-28 09:51:32,128 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2021-10-28 09:51:32,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4227 states. [2021-10-28 09:51:32,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4227 to 1878. [2021-10-28 09:51:32,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1878 states, 1873 states have (on average 1.2802989855846236) internal successors, (2398), 1877 states have internal predecessors, (2398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:32,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1878 states to 1878 states and 2398 transitions. [2021-10-28 09:51:32,426 INFO L78 Accepts]: Start accepts. Automaton has 1878 states and 2398 transitions. Word has length 135 [2021-10-28 09:51:32,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:32,426 INFO L470 AbstractCegarLoop]: Abstraction has 1878 states and 2398 transitions. [2021-10-28 09:51:32,426 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:32,426 INFO L276 IsEmpty]: Start isEmpty. Operand 1878 states and 2398 transitions. [2021-10-28 09:51:32,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2021-10-28 09:51:32,429 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:32,429 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:32,454 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:32,631 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2021-10-28 09:51:32,632 INFO L402 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:32,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:32,632 INFO L85 PathProgramCache]: Analyzing trace with hash 722347797, now seen corresponding path program 1 times [2021-10-28 09:51:32,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:32,633 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145369755] [2021-10-28 09:51:32,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:32,633 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:32,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:32,812 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 26 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:32,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:32,813 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145369755] [2021-10-28 09:51:32,813 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145369755] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:32,813 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [390233965] [2021-10-28 09:51:32,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:32,814 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:32,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:32,815 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:32,834 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2021-10-28 09:51:33,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:33,228 INFO L263 TraceCheckSpWp]: Trace formula consists of 794 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 09:51:33,231 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:33,657 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-10-28 09:51:33,657 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [390233965] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:33,657 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-10-28 09:51:33,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2021-10-28 09:51:33,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173020796] [2021-10-28 09:51:33,658 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:33,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:33,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:33,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=181, Unknown=0, NotChecked=0, Total=210 [2021-10-28 09:51:33,658 INFO L87 Difference]: Start difference. First operand 1878 states and 2398 transitions. Second operand has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:34,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:34,412 INFO L93 Difference]: Finished difference Result 5394 states and 7030 transitions. [2021-10-28 09:51:34,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:51:34,413 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 139 [2021-10-28 09:51:34,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:34,418 INFO L225 Difference]: With dead ends: 5394 [2021-10-28 09:51:34,418 INFO L226 Difference]: Without dead ends: 3671 [2021-10-28 09:51:34,421 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 136 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2021-10-28 09:51:34,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3671 states. [2021-10-28 09:51:34,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3671 to 1878. [2021-10-28 09:51:34,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1878 states, 1873 states have (on average 1.2786972770955687) internal successors, (2395), 1877 states have internal predecessors, (2395), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:34,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1878 states to 1878 states and 2395 transitions. [2021-10-28 09:51:34,728 INFO L78 Accepts]: Start accepts. Automaton has 1878 states and 2395 transitions. Word has length 139 [2021-10-28 09:51:34,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:34,728 INFO L470 AbstractCegarLoop]: Abstraction has 1878 states and 2395 transitions. [2021-10-28 09:51:34,729 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:34,729 INFO L276 IsEmpty]: Start isEmpty. Operand 1878 states and 2395 transitions. [2021-10-28 09:51:34,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2021-10-28 09:51:34,734 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:34,734 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:34,775 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:34,947 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable33 [2021-10-28 09:51:34,948 INFO L402 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:34,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:34,948 INFO L85 PathProgramCache]: Analyzing trace with hash -1061111299, now seen corresponding path program 1 times [2021-10-28 09:51:34,948 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:34,948 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725485887] [2021-10-28 09:51:34,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:34,949 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:35,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:35,189 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 26 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:35,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:35,189 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725485887] [2021-10-28 09:51:35,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725485887] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:35,189 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1839893710] [2021-10-28 09:51:35,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:35,190 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:35,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:35,196 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:35,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2021-10-28 09:51:35,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:35,600 INFO L263 TraceCheckSpWp]: Trace formula consists of 806 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 09:51:35,603 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:36,823 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 17 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:36,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1839893710] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:36,824 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:36,824 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 6] total 14 [2021-10-28 09:51:36,824 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838012869] [2021-10-28 09:51:36,825 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2021-10-28 09:51:36,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:36,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-10-28 09:51:36,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2021-10-28 09:51:36,826 INFO L87 Difference]: Start difference. First operand 1878 states and 2395 transitions. Second operand has 15 states, 15 states have (on average 16.2) internal successors, (243), 14 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:39,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:39,836 INFO L93 Difference]: Finished difference Result 5843 states and 7527 transitions. [2021-10-28 09:51:39,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2021-10-28 09:51:39,837 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 16.2) internal successors, (243), 14 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 142 [2021-10-28 09:51:39,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:39,842 INFO L225 Difference]: With dead ends: 5843 [2021-10-28 09:51:39,842 INFO L226 Difference]: Without dead ends: 4160 [2021-10-28 09:51:39,846 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 136 SyntacticMatches, 2 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1627 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=942, Invalid=4314, Unknown=0, NotChecked=0, Total=5256 [2021-10-28 09:51:39,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4160 states. [2021-10-28 09:51:40,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4160 to 2115. [2021-10-28 09:51:40,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2115 states, 2110 states have (on average 1.2691943127962084) internal successors, (2678), 2114 states have internal predecessors, (2678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:40,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2115 states to 2115 states and 2678 transitions. [2021-10-28 09:51:40,407 INFO L78 Accepts]: Start accepts. Automaton has 2115 states and 2678 transitions. Word has length 142 [2021-10-28 09:51:40,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:40,408 INFO L470 AbstractCegarLoop]: Abstraction has 2115 states and 2678 transitions. [2021-10-28 09:51:40,408 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 16.2) internal successors, (243), 14 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:40,408 INFO L276 IsEmpty]: Start isEmpty. Operand 2115 states and 2678 transitions. [2021-10-28 09:51:40,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2021-10-28 09:51:40,413 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:40,414 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:40,440 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:40,624 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2021-10-28 09:51:40,625 INFO L402 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:40,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:40,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1545838345, now seen corresponding path program 1 times [2021-10-28 09:51:40,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:40,628 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [821785988] [2021-10-28 09:51:40,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:40,629 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:40,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:40,738 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-10-28 09:51:40,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:40,738 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [821785988] [2021-10-28 09:51:40,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [821785988] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:40,739 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:40,739 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:40,739 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847162147] [2021-10-28 09:51:40,740 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-10-28 09:51:40,740 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:40,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 09:51:40,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:40,741 INFO L87 Difference]: Start difference. First operand 2115 states and 2678 transitions. Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 4 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:41,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:41,209 INFO L93 Difference]: Finished difference Result 3968 states and 5065 transitions. [2021-10-28 09:51:41,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 09:51:41,209 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.4) internal successors, (122), 4 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 143 [2021-10-28 09:51:41,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:41,212 INFO L225 Difference]: With dead ends: 3968 [2021-10-28 09:51:41,212 INFO L226 Difference]: Without dead ends: 1987 [2021-10-28 09:51:41,215 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-10-28 09:51:41,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1987 states. [2021-10-28 09:51:41,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1987 to 1987. [2021-10-28 09:51:41,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1987 states, 1982 states have (on average 1.2734611503531785) internal successors, (2524), 1986 states have internal predecessors, (2524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:41,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1987 states to 1987 states and 2524 transitions. [2021-10-28 09:51:41,566 INFO L78 Accepts]: Start accepts. Automaton has 1987 states and 2524 transitions. Word has length 143 [2021-10-28 09:51:41,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:41,567 INFO L470 AbstractCegarLoop]: Abstraction has 1987 states and 2524 transitions. [2021-10-28 09:51:41,567 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.4) internal successors, (122), 4 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:41,567 INFO L276 IsEmpty]: Start isEmpty. Operand 1987 states and 2524 transitions. [2021-10-28 09:51:41,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2021-10-28 09:51:41,571 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:41,571 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:41,572 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2021-10-28 09:51:41,572 INFO L402 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:41,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:41,572 INFO L85 PathProgramCache]: Analyzing trace with hash 956328512, now seen corresponding path program 1 times [2021-10-28 09:51:41,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:41,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324927632] [2021-10-28 09:51:41,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:41,573 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:41,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:41,653 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-10-28 09:51:41,653 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:41,653 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324927632] [2021-10-28 09:51:41,654 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324927632] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:41,654 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:41,654 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:51:41,654 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302536707] [2021-10-28 09:51:41,655 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:51:41,655 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:41,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:51:41,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:51:41,656 INFO L87 Difference]: Start difference. First operand 1987 states and 2524 transitions. Second operand has 6 states, 6 states have (on average 19.666666666666668) internal successors, (118), 6 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:42,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:42,933 INFO L93 Difference]: Finished difference Result 8551 states and 11174 transitions. [2021-10-28 09:51:42,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-10-28 09:51:42,933 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 19.666666666666668) internal successors, (118), 6 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 143 [2021-10-28 09:51:42,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:42,939 INFO L225 Difference]: With dead ends: 8551 [2021-10-28 09:51:42,939 INFO L226 Difference]: Without dead ends: 6759 [2021-10-28 09:51:42,941 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2021-10-28 09:51:42,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6759 states. [2021-10-28 09:51:43,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6759 to 2340. [2021-10-28 09:51:43,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2340 states, 2335 states have (on average 1.2582441113490364) internal successors, (2938), 2339 states have internal predecessors, (2938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:43,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2340 states to 2340 states and 2938 transitions. [2021-10-28 09:51:43,460 INFO L78 Accepts]: Start accepts. Automaton has 2340 states and 2938 transitions. Word has length 143 [2021-10-28 09:51:43,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:43,461 INFO L470 AbstractCegarLoop]: Abstraction has 2340 states and 2938 transitions. [2021-10-28 09:51:43,461 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 19.666666666666668) internal successors, (118), 6 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:43,461 INFO L276 IsEmpty]: Start isEmpty. Operand 2340 states and 2938 transitions. [2021-10-28 09:51:43,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2021-10-28 09:51:43,465 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:43,466 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:43,466 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable36 [2021-10-28 09:51:43,466 INFO L402 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:43,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:43,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1126731789, now seen corresponding path program 1 times [2021-10-28 09:51:43,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:43,467 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073638528] [2021-10-28 09:51:43,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:43,467 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:43,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:43,658 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 32 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:43,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:43,658 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073638528] [2021-10-28 09:51:43,659 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073638528] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:43,659 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1249968817] [2021-10-28 09:51:43,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:43,660 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:43,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:43,664 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:43,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-10-28 09:51:44,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:44,242 INFO L263 TraceCheckSpWp]: Trace formula consists of 809 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 09:51:44,245 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:44,657 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 34 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:44,658 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1249968817] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:44,658 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:44,658 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 17 [2021-10-28 09:51:44,658 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533646922] [2021-10-28 09:51:44,658 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2021-10-28 09:51:44,659 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:44,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-10-28 09:51:44,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2021-10-28 09:51:44,660 INFO L87 Difference]: Start difference. First operand 2340 states and 2938 transitions. Second operand has 17 states, 17 states have (on average 15.411764705882353) internal successors, (262), 17 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:52,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:52,210 INFO L93 Difference]: Finished difference Result 15605 states and 19700 transitions. [2021-10-28 09:51:52,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2021-10-28 09:51:52,210 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 15.411764705882353) internal successors, (262), 17 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 144 [2021-10-28 09:51:52,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:52,223 INFO L225 Difference]: With dead ends: 15605 [2021-10-28 09:51:52,223 INFO L226 Difference]: Without dead ends: 13460 [2021-10-28 09:51:52,229 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11702 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3629, Invalid=26821, Unknown=0, NotChecked=0, Total=30450 [2021-10-28 09:51:52,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13460 states. [2021-10-28 09:51:53,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13460 to 4490. [2021-10-28 09:51:53,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4490 states, 4485 states have (on average 1.2550724637681159) internal successors, (5629), 4489 states have internal predecessors, (5629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:53,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4490 states to 4490 states and 5629 transitions. [2021-10-28 09:51:53,145 INFO L78 Accepts]: Start accepts. Automaton has 4490 states and 5629 transitions. Word has length 144 [2021-10-28 09:51:53,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:53,146 INFO L470 AbstractCegarLoop]: Abstraction has 4490 states and 5629 transitions. [2021-10-28 09:51:53,146 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 15.411764705882353) internal successors, (262), 17 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:53,146 INFO L276 IsEmpty]: Start isEmpty. Operand 4490 states and 5629 transitions. [2021-10-28 09:51:53,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2021-10-28 09:51:53,156 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:53,156 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:53,196 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:53,383 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2021-10-28 09:51:53,384 INFO L402 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:53,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:53,384 INFO L85 PathProgramCache]: Analyzing trace with hash -2053713263, now seen corresponding path program 1 times [2021-10-28 09:51:53,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:53,384 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997873909] [2021-10-28 09:51:53,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:53,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:53,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:53,443 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2021-10-28 09:51:53,444 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:53,445 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997873909] [2021-10-28 09:51:53,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997873909] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:51:53,445 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:51:53,445 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:51:53,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590941496] [2021-10-28 09:51:53,446 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:51:53,446 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:53,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:51:53,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:53,447 INFO L87 Difference]: Start difference. First operand 4490 states and 5629 transitions. Second operand has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:54,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:54,169 INFO L93 Difference]: Finished difference Result 8234 states and 10375 transitions. [2021-10-28 09:51:54,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:51:54,170 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 144 [2021-10-28 09:51:54,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:54,174 INFO L225 Difference]: With dead ends: 8234 [2021-10-28 09:51:54,174 INFO L226 Difference]: Without dead ends: 3927 [2021-10-28 09:51:54,178 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:51:54,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3927 states. [2021-10-28 09:51:54,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3927 to 3911. [2021-10-28 09:51:54,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3911 states, 3906 states have (on average 1.2521761392729134) internal successors, (4891), 3910 states have internal predecessors, (4891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:54,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3911 states to 3911 states and 4891 transitions. [2021-10-28 09:51:54,812 INFO L78 Accepts]: Start accepts. Automaton has 3911 states and 4891 transitions. Word has length 144 [2021-10-28 09:51:54,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:54,812 INFO L470 AbstractCegarLoop]: Abstraction has 3911 states and 4891 transitions. [2021-10-28 09:51:54,813 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:54,813 INFO L276 IsEmpty]: Start isEmpty. Operand 3911 states and 4891 transitions. [2021-10-28 09:51:54,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2021-10-28 09:51:54,821 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:54,821 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:54,821 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2021-10-28 09:51:54,821 INFO L402 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:54,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:54,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1332568633, now seen corresponding path program 1 times [2021-10-28 09:51:54,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:54,822 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018735947] [2021-10-28 09:51:54,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:54,823 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:54,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:54,949 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:54,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:54,949 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018735947] [2021-10-28 09:51:54,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018735947] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:54,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1163447032] [2021-10-28 09:51:54,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:54,950 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:54,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:54,951 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:54,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-10-28 09:51:55,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:55,508 INFO L263 TraceCheckSpWp]: Trace formula consists of 806 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-28 09:51:55,511 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:51:55,908 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:55,909 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1163447032] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:55,909 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 09:51:55,909 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2021-10-28 09:51:55,909 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396589963] [2021-10-28 09:51:55,910 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2021-10-28 09:51:55,910 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:51:55,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-28 09:51:55,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-10-28 09:51:55,911 INFO L87 Difference]: Start difference. First operand 3911 states and 4891 transitions. Second operand has 7 states, 7 states have (on average 20.571428571428573) internal successors, (144), 7 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:57,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:51:57,916 INFO L93 Difference]: Finished difference Result 14859 states and 18978 transitions. [2021-10-28 09:51:57,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-10-28 09:51:57,916 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 20.571428571428573) internal successors, (144), 7 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 144 [2021-10-28 09:51:57,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:51:57,926 INFO L225 Difference]: With dead ends: 14859 [2021-10-28 09:51:57,926 INFO L226 Difference]: Without dead ends: 11247 [2021-10-28 09:51:57,930 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2021-10-28 09:51:57,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11247 states. [2021-10-28 09:51:59,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11247 to 7251. [2021-10-28 09:51:59,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7251 states, 7246 states have (on average 1.250483025117306) internal successors, (9061), 7250 states have internal predecessors, (9061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:59,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7251 states to 7251 states and 9061 transitions. [2021-10-28 09:51:59,245 INFO L78 Accepts]: Start accepts. Automaton has 7251 states and 9061 transitions. Word has length 144 [2021-10-28 09:51:59,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:51:59,246 INFO L470 AbstractCegarLoop]: Abstraction has 7251 states and 9061 transitions. [2021-10-28 09:51:59,246 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 20.571428571428573) internal successors, (144), 7 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:51:59,246 INFO L276 IsEmpty]: Start isEmpty. Operand 7251 states and 9061 transitions. [2021-10-28 09:51:59,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2021-10-28 09:51:59,251 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:51:59,251 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:51:59,274 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2021-10-28 09:51:59,452 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2021-10-28 09:51:59,452 INFO L402 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:51:59,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:51:59,452 INFO L85 PathProgramCache]: Analyzing trace with hash -372796990, now seen corresponding path program 1 times [2021-10-28 09:51:59,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:51:59,453 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302489283] [2021-10-28 09:51:59,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:59,453 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:51:59,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:51:59,601 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 26 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:51:59,601 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:51:59,601 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302489283] [2021-10-28 09:51:59,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302489283] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:51:59,602 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [98536154] [2021-10-28 09:51:59,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:51:59,602 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:51:59,603 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:51:59,608 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:51:59,619 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-10-28 09:52:00,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:52:00,322 INFO L263 TraceCheckSpWp]: Trace formula consists of 817 conjuncts, 12 conjunts are in the unsatisfiable core [2021-10-28 09:52:00,324 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:52:00,643 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-28 09:52:00,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [98536154] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:52:00,644 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-10-28 09:52:00,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 12 [2021-10-28 09:52:00,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090480458] [2021-10-28 09:52:00,644 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:52:00,644 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:52:00,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:52:00,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2021-10-28 09:52:00,645 INFO L87 Difference]: Start difference. First operand 7251 states and 9061 transitions. Second operand has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:02,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:52:02,609 INFO L93 Difference]: Finished difference Result 16296 states and 20669 transitions. [2021-10-28 09:52:02,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:52:02,610 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 144 [2021-10-28 09:52:02,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:52:02,618 INFO L225 Difference]: With dead ends: 16296 [2021-10-28 09:52:02,618 INFO L226 Difference]: Without dead ends: 10692 [2021-10-28 09:52:02,623 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 144 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2021-10-28 09:52:02,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10692 states. [2021-10-28 09:52:03,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10692 to 7251. [2021-10-28 09:52:03,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7251 states, 7246 states have (on average 1.236820314656362) internal successors, (8962), 7250 states have internal predecessors, (8962), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:03,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7251 states to 7251 states and 8962 transitions. [2021-10-28 09:52:03,758 INFO L78 Accepts]: Start accepts. Automaton has 7251 states and 8962 transitions. Word has length 144 [2021-10-28 09:52:03,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:52:03,759 INFO L470 AbstractCegarLoop]: Abstraction has 7251 states and 8962 transitions. [2021-10-28 09:52:03,759 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 6 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:03,759 INFO L276 IsEmpty]: Start isEmpty. Operand 7251 states and 8962 transitions. [2021-10-28 09:52:03,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2021-10-28 09:52:03,766 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:52:03,767 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:52:03,795 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2021-10-28 09:52:03,980 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:52:03,980 INFO L402 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:52:03,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:52:03,980 INFO L85 PathProgramCache]: Analyzing trace with hash 729040484, now seen corresponding path program 1 times [2021-10-28 09:52:03,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:52:03,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115799566] [2021-10-28 09:52:03,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:52:03,981 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:52:03,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:52:04,044 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-10-28 09:52:04,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:52:04,044 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115799566] [2021-10-28 09:52:04,045 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115799566] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:52:04,045 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:52:04,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 09:52:04,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250402505] [2021-10-28 09:52:04,045 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-10-28 09:52:04,045 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:52:04,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 09:52:04,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:52:04,046 INFO L87 Difference]: Start difference. First operand 7251 states and 8962 transitions. Second operand has 4 states, 4 states have (on average 31.0) internal successors, (124), 4 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:05,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:52:05,105 INFO L93 Difference]: Finished difference Result 11820 states and 14654 transitions. [2021-10-28 09:52:05,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 09:52:05,106 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 31.0) internal successors, (124), 4 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 145 [2021-10-28 09:52:05,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:52:05,110 INFO L225 Difference]: With dead ends: 11820 [2021-10-28 09:52:05,110 INFO L226 Difference]: Without dead ends: 5207 [2021-10-28 09:52:05,116 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 09:52:05,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5207 states. [2021-10-28 09:52:06,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5207 to 5179. [2021-10-28 09:52:06,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5179 states, 5174 states have (on average 1.2377270970235794) internal successors, (6404), 5178 states have internal predecessors, (6404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:06,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5179 states to 5179 states and 6404 transitions. [2021-10-28 09:52:06,055 INFO L78 Accepts]: Start accepts. Automaton has 5179 states and 6404 transitions. Word has length 145 [2021-10-28 09:52:06,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:52:06,055 INFO L470 AbstractCegarLoop]: Abstraction has 5179 states and 6404 transitions. [2021-10-28 09:52:06,055 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 31.0) internal successors, (124), 4 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:06,056 INFO L276 IsEmpty]: Start isEmpty. Operand 5179 states and 6404 transitions. [2021-10-28 09:52:06,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2021-10-28 09:52:06,061 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:52:06,061 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:52:06,062 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41 [2021-10-28 09:52:06,062 INFO L402 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:52:06,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:52:06,063 INFO L85 PathProgramCache]: Analyzing trace with hash -828579161, now seen corresponding path program 1 times [2021-10-28 09:52:06,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:52:06,063 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097606535] [2021-10-28 09:52:06,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:52:06,064 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:52:06,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:52:06,230 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 26 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 09:52:06,230 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:52:06,230 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097606535] [2021-10-28 09:52:06,230 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097606535] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 09:52:06,231 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1277930187] [2021-10-28 09:52:06,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:52:06,231 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:52:06,231 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 [2021-10-28 09:52:06,235 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 09:52:06,243 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-10-28 09:52:07,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:52:07,032 INFO L263 TraceCheckSpWp]: Trace formula consists of 830 conjuncts, 8 conjunts are in the unsatisfiable core [2021-10-28 09:52:07,034 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 09:52:07,423 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-28 09:52:07,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1277930187] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:52:07,423 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-10-28 09:52:07,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 12 [2021-10-28 09:52:07,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103570721] [2021-10-28 09:52:07,424 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:52:07,424 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:52:07,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:52:07,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2021-10-28 09:52:07,425 INFO L87 Difference]: Start difference. First operand 5179 states and 6404 transitions. Second operand has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:09,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:52:09,099 INFO L93 Difference]: Finished difference Result 13279 states and 16533 transitions. [2021-10-28 09:52:09,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 09:52:09,099 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 148 [2021-10-28 09:52:09,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:52:09,107 INFO L225 Difference]: With dead ends: 13279 [2021-10-28 09:52:09,107 INFO L226 Difference]: Without dead ends: 8944 [2021-10-28 09:52:09,111 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 160 GetRequests, 145 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2021-10-28 09:52:09,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8944 states. [2021-10-28 09:52:09,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8944 to 5179. [2021-10-28 09:52:09,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5179 states, 5174 states have (on average 1.2373405488983378) internal successors, (6402), 5178 states have internal predecessors, (6402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:09,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5179 states to 5179 states and 6402 transitions. [2021-10-28 09:52:09,950 INFO L78 Accepts]: Start accepts. Automaton has 5179 states and 6402 transitions. Word has length 148 [2021-10-28 09:52:09,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:52:09,951 INFO L470 AbstractCegarLoop]: Abstraction has 5179 states and 6402 transitions. [2021-10-28 09:52:09,951 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 22.333333333333332) internal successors, (134), 6 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:09,951 INFO L276 IsEmpty]: Start isEmpty. Operand 5179 states and 6402 transitions. [2021-10-28 09:52:09,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2021-10-28 09:52:09,955 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:52:09,956 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:52:09,979 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2021-10-28 09:52:10,159 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 09:52:10,160 INFO L402 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:52:10,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:52:10,160 INFO L85 PathProgramCache]: Analyzing trace with hash -572580853, now seen corresponding path program 1 times [2021-10-28 09:52:10,160 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:52:10,160 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487162296] [2021-10-28 09:52:10,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:52:10,161 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:52:10,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 09:52:10,296 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2021-10-28 09:52:10,296 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 09:52:10,297 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487162296] [2021-10-28 09:52:10,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487162296] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 09:52:10,297 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 09:52:10,297 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-10-28 09:52:10,297 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136129541] [2021-10-28 09:52:10,298 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-10-28 09:52:10,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 09:52:10,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-10-28 09:52:10,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-10-28 09:52:10,299 INFO L87 Difference]: Start difference. First operand 5179 states and 6402 transitions. Second operand has 6 states, 6 states have (on average 23.833333333333332) internal successors, (143), 6 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:12,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 09:52:12,700 INFO L93 Difference]: Finished difference Result 13168 states and 16527 transitions. [2021-10-28 09:52:12,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 09:52:12,701 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 23.833333333333332) internal successors, (143), 6 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 149 [2021-10-28 09:52:12,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-10-28 09:52:12,710 INFO L225 Difference]: With dead ends: 13168 [2021-10-28 09:52:12,710 INFO L226 Difference]: Without dead ends: 10225 [2021-10-28 09:52:12,714 INFO L786 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2021-10-28 09:52:12,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10225 states. [2021-10-28 09:52:13,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10225 to 5305. [2021-10-28 09:52:13,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5305 states, 5300 states have (on average 1.2356603773584907) internal successors, (6549), 5304 states have internal predecessors, (6549), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:13,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5305 states to 5305 states and 6549 transitions. [2021-10-28 09:52:13,646 INFO L78 Accepts]: Start accepts. Automaton has 5305 states and 6549 transitions. Word has length 149 [2021-10-28 09:52:13,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-10-28 09:52:13,647 INFO L470 AbstractCegarLoop]: Abstraction has 5305 states and 6549 transitions. [2021-10-28 09:52:13,647 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 23.833333333333332) internal successors, (143), 6 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 09:52:13,647 INFO L276 IsEmpty]: Start isEmpty. Operand 5305 states and 6549 transitions. [2021-10-28 09:52:13,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2021-10-28 09:52:13,650 INFO L505 BasicCegarLoop]: Found error trace [2021-10-28 09:52:13,650 INFO L513 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:52:13,650 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43 [2021-10-28 09:52:13,651 INFO L402 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION (and 20 more)] === [2021-10-28 09:52:13,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 09:52:13,651 INFO L85 PathProgramCache]: Analyzing trace with hash -146521997, now seen corresponding path program 1 times [2021-10-28 09:52:13,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 09:52:13,651 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295138449] [2021-10-28 09:52:13,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 09:52:13,652 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 09:52:13,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:52:13,717 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 09:52:13,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 09:52:13,873 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 09:52:13,873 INFO L627 BasicCegarLoop]: Counterexample is feasible [2021-10-28 09:52:13,874 INFO L764 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,876 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,876 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,877 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,877 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,877 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,877 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,877 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,878 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,878 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,878 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,878 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,878 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,879 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,879 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,879 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,879 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,879 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,880 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,880 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,880 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,880 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,880 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION [2021-10-28 09:52:13,881 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44 [2021-10-28 09:52:13,884 INFO L731 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 09:52:13,889 INFO L179 ceAbstractionStarter]: Computing trace abstraction results [2021-10-28 09:52:14,092 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.10 09:52:14 BoogieIcfgContainer [2021-10-28 09:52:14,092 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-10-28 09:52:14,092 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 09:52:14,093 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 09:52:14,093 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 09:52:14,093 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 09:50:53" (3/4) ... [2021-10-28 09:52:14,095 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-10-28 09:52:14,304 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/witness.graphml [2021-10-28 09:52:14,304 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 09:52:14,306 INFO L168 Benchmark]: Toolchain (without parser) took 83360.50 ms. Allocated memory was 96.5 MB in the beginning and 1.9 GB in the end (delta: 1.8 GB). Free memory was 61.7 MB in the beginning and 1.3 GB in the end (delta: -1.2 GB). Peak memory consumption was 616.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,306 INFO L168 Benchmark]: CDTParser took 0.33 ms. Allocated memory is still 96.5 MB. Free memory was 68.4 MB in the beginning and 68.4 MB in the end (delta: 21.3 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 09:52:14,307 INFO L168 Benchmark]: CACSL2BoogieTranslator took 579.66 ms. Allocated memory is still 96.5 MB. Free memory was 61.7 MB in the beginning and 64.8 MB in the end (delta: -3.0 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,307 INFO L168 Benchmark]: Boogie Procedure Inliner took 129.79 ms. Allocated memory is still 96.5 MB. Free memory was 64.8 MB in the beginning and 60.0 MB in the end (delta: 4.8 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,307 INFO L168 Benchmark]: Boogie Preprocessor took 76.24 ms. Allocated memory is still 96.5 MB. Free memory was 60.0 MB in the beginning and 56.4 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,308 INFO L168 Benchmark]: RCFGBuilder took 1438.63 ms. Allocated memory was 96.5 MB in the beginning and 127.9 MB in the end (delta: 31.5 MB). Free memory was 56.4 MB in the beginning and 83.1 MB in the end (delta: -26.7 MB). Peak memory consumption was 23.9 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,308 INFO L168 Benchmark]: TraceAbstraction took 80911.55 ms. Allocated memory was 127.9 MB in the beginning and 1.9 GB in the end (delta: 1.8 GB). Free memory was 82.4 MB in the beginning and 1.3 GB in the end (delta: -1.2 GB). Peak memory consumption was 559.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,309 INFO L168 Benchmark]: Witness Printer took 211.98 ms. Allocated memory is still 1.9 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 48.1 MB). Peak memory consumption was 48.2 MB. Max. memory is 16.1 GB. [2021-10-28 09:52:14,311 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.33 ms. Allocated memory is still 96.5 MB. Free memory was 68.4 MB in the beginning and 68.4 MB in the end (delta: 21.3 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 579.66 ms. Allocated memory is still 96.5 MB. Free memory was 61.7 MB in the beginning and 64.8 MB in the end (delta: -3.0 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 129.79 ms. Allocated memory is still 96.5 MB. Free memory was 64.8 MB in the beginning and 60.0 MB in the end (delta: 4.8 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 76.24 ms. Allocated memory is still 96.5 MB. Free memory was 60.0 MB in the beginning and 56.4 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1438.63 ms. Allocated memory was 96.5 MB in the beginning and 127.9 MB in the end (delta: 31.5 MB). Free memory was 56.4 MB in the beginning and 83.1 MB in the end (delta: -26.7 MB). Peak memory consumption was 23.9 MB. Max. memory is 16.1 GB. * TraceAbstraction took 80911.55 ms. Allocated memory was 127.9 MB in the beginning and 1.9 GB in the end (delta: 1.8 GB). Free memory was 82.4 MB in the beginning and 1.3 GB in the end (delta: -1.2 GB). Peak memory consumption was 559.2 MB. Max. memory is 16.1 GB. * Witness Printer took 211.98 ms. Allocated memory is still 1.9 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 48.1 MB). Peak memory consumption was 48.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 618]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L24] msg_t nomsg = (msg_t )-1; [L25] port_t cs1 ; [L26] int8_t cs1_old ; [L27] int8_t cs1_new ; [L28] port_t cs2 ; [L29] int8_t cs2_old ; [L30] int8_t cs2_new ; [L31] port_t s1s2 ; [L32] int8_t s1s2_old ; [L33] int8_t s1s2_new ; [L34] port_t s1s1 ; [L35] int8_t s1s1_old ; [L36] int8_t s1s1_new ; [L37] port_t s2s1 ; [L38] int8_t s2s1_old ; [L39] int8_t s2s1_new ; [L40] port_t s2s2 ; [L41] int8_t s2s2_old ; [L42] int8_t s2s2_new ; [L43] port_t s1p ; [L44] int8_t s1p_old ; [L45] int8_t s1p_new ; [L46] port_t s2p ; [L47] int8_t s2p_old ; [L48] int8_t s2p_new ; [L51] _Bool side1Failed ; [L52] _Bool side2Failed ; [L53] msg_t side1_written ; [L54] msg_t side2_written ; [L60] static _Bool side1Failed_History_0 ; [L61] static _Bool side1Failed_History_1 ; [L62] static _Bool side1Failed_History_2 ; [L63] static _Bool side2Failed_History_0 ; [L64] static _Bool side2Failed_History_1 ; [L65] static _Bool side2Failed_History_2 ; [L66] static int8_t active_side_History_0 ; [L67] static int8_t active_side_History_1 ; [L68] static int8_t active_side_History_2 ; [L69] static msg_t manual_selection_History_0 ; [L70] static msg_t manual_selection_History_1 ; [L71] static msg_t manual_selection_History_2 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L542] int c1 ; [L543] int i2 ; [L546] c1 = 0 [L547] side1Failed = __VERIFIER_nondet_bool() [L548] side2Failed = __VERIFIER_nondet_bool() [L549] side1_written = __VERIFIER_nondet_char() [L550] side2_written = __VERIFIER_nondet_char() [L551] side1Failed_History_0 = __VERIFIER_nondet_bool() [L552] side1Failed_History_1 = __VERIFIER_nondet_bool() [L553] side1Failed_History_2 = __VERIFIER_nondet_bool() [L554] side2Failed_History_0 = __VERIFIER_nondet_bool() [L555] side2Failed_History_1 = __VERIFIER_nondet_bool() [L556] side2Failed_History_2 = __VERIFIER_nondet_bool() [L557] active_side_History_0 = __VERIFIER_nondet_char() [L558] active_side_History_1 = __VERIFIER_nondet_char() [L559] active_side_History_2 = __VERIFIER_nondet_char() [L560] manual_selection_History_0 = __VERIFIER_nondet_char() [L561] manual_selection_History_1 = __VERIFIER_nondet_char() [L562] manual_selection_History_2 = __VERIFIER_nondet_char() [L197] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L200] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L203] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L206] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L209] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L212] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L215] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L218] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L221] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L224] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L227] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L230] COND FALSE !((int )manual_selection_History_2 != 0) [L233] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L563] i2 = init() [L58] COND FALSE !(!cond) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L565] cs1_old = nomsg [L566] cs1_new = nomsg [L567] cs2_old = nomsg [L568] cs2_new = nomsg [L569] s1s2_old = nomsg [L570] s1s2_new = nomsg [L571] s1s1_old = nomsg [L572] s1s1_new = nomsg [L573] s2s1_old = nomsg [L574] s2s1_new = nomsg [L575] s2s2_old = nomsg [L576] s2s2_new = nomsg [L577] s1p_old = nomsg [L578] s1p_new = nomsg [L579] s2p_old = nomsg [L580] s2p_new = nomsg [L581] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L582] COND TRUE 1 [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L258] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=3, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L277] COND TRUE \read(side1Failed) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L278] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=2, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L347] COND TRUE (int )side1 == (int )side2 [L348] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L371] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L400] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L408] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L409] COND FALSE !((int )side2 == 0) [L412] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-3, cs1_old=-1, cs2=0, cs2_new=-3, cs2_old=-1, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L588] cs1_old = cs1_new [L589] cs1_new = nomsg [L590] cs2_old = cs2_new [L591] cs2_new = nomsg [L592] s1s2_old = s1s2_new [L593] s1s2_new = nomsg [L594] s1s1_old = s1s1_new [L595] s1s1_new = nomsg [L596] s2s1_old = s2s1_new [L597] s2s1_new = nomsg [L598] s2s2_old = s2s2_new [L599] s2s2_new = nomsg [L600] s1p_old = s1p_new [L601] s1p_new = nomsg [L602] s2p_old = s2p_new [L603] s2p_new = nomsg [L423] int tmp ; [L424] msg_t tmp___0 ; [L425] _Bool tmp___1 ; [L426] _Bool tmp___2 ; [L427] _Bool tmp___3 ; [L428] _Bool tmp___4 ; [L429] int8_t tmp___5 ; [L430] _Bool tmp___6 ; [L431] _Bool tmp___7 ; [L432] _Bool tmp___8 ; [L433] int8_t tmp___9 ; [L434] _Bool tmp___10 ; [L435] _Bool tmp___11 ; [L436] _Bool tmp___12 ; [L437] msg_t tmp___13 ; [L438] _Bool tmp___14 ; [L439] _Bool tmp___15 ; [L440] _Bool tmp___16 ; [L441] _Bool tmp___17 ; [L442] int8_t tmp___18 ; [L443] int8_t tmp___19 ; [L444] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L447] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE ! side2Failed [L451] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L58] COND FALSE !(!cond) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L178] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L456] tmp___0 = read_manual_selection_history((unsigned char)1) [L457] COND TRUE ! tmp___0 [L88] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L458] tmp___1 = read_side1_failed_history((unsigned char)1) [L459] COND TRUE ! tmp___1 [L88] COND TRUE (int )index == 0 [L89] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L460] tmp___2 = read_side1_failed_history((unsigned char)0) [L461] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L88] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L486] tmp___7 = read_side1_failed_history((unsigned char)1) [L487] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L88] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L502] tmp___11 = read_side1_failed_history((unsigned char)1) [L503] COND TRUE ! tmp___11 [L118] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L504] tmp___12 = read_side2_failed_history((unsigned char)1) [L505] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L148] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L151] COND FALSE !((int )index == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L154] COND TRUE (int )index == 2 [L155] return (active_side_History_2); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L518] tmp___20 = read_active_side_history((unsigned char)2) [L519] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L537] return (1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L604] c1 = check() [L616] COND FALSE !(! arg) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-3, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L582] COND TRUE 1 [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L258] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-1, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L277] COND TRUE \read(side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L278] EXPR nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] EXPR nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] EXPR nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-3, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L347] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L350] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L351] COND TRUE (int )side2 != (int )nomsg [L352] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L371] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L400] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L408] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L409] COND TRUE (int )side2 == 0 [L410] active_side = (int8_t )2 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-2, cs1_old=-3, cs2=0, cs2_new=-2, cs2_old=-1, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L588] cs1_old = cs1_new [L589] cs1_new = nomsg [L590] cs2_old = cs2_new [L591] cs2_new = nomsg [L592] s1s2_old = s1s2_new [L593] s1s2_new = nomsg [L594] s1s1_old = s1s1_new [L595] s1s1_new = nomsg [L596] s2s1_old = s2s1_new [L597] s2s1_new = nomsg [L598] s2s2_old = s2s2_new [L599] s2s2_new = nomsg [L600] s1p_old = s1p_new [L601] s1p_new = nomsg [L602] s2p_old = s2p_new [L603] s2p_new = nomsg [L423] int tmp ; [L424] msg_t tmp___0 ; [L425] _Bool tmp___1 ; [L426] _Bool tmp___2 ; [L427] _Bool tmp___3 ; [L428] _Bool tmp___4 ; [L429] int8_t tmp___5 ; [L430] _Bool tmp___6 ; [L431] _Bool tmp___7 ; [L432] _Bool tmp___8 ; [L433] int8_t tmp___9 ; [L434] _Bool tmp___10 ; [L435] _Bool tmp___11 ; [L436] _Bool tmp___12 ; [L437] msg_t tmp___13 ; [L438] _Bool tmp___14 ; [L439] _Bool tmp___15 ; [L440] _Bool tmp___16 ; [L441] _Bool tmp___17 ; [L442] int8_t tmp___18 ; [L443] int8_t tmp___19 ; [L444] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L447] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE ! side2Failed [L451] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L58] COND FALSE !(!cond) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L178] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L456] tmp___0 = read_manual_selection_history((unsigned char)1) [L457] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L88] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L486] tmp___7 = read_side1_failed_history((unsigned char)1) [L487] COND TRUE \read(tmp___7) [L118] COND FALSE !((int )index == 0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L488] tmp___8 = read_side2_failed_history((unsigned char)1) [L489] COND TRUE ! tmp___8 [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] tmp___5 = read_active_side_history((unsigned char)0) [L491] COND FALSE !(! ((int )tmp___5 == 2)) [L118] COND TRUE (int )index == 0 [L119] return (side2Failed_History_0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L494] tmp___6 = read_side2_failed_history((unsigned char)0) [L495] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L496] COND TRUE ! ((int )side2_written == 1) [L497] return (0); VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L604] c1 = check() [L616] COND TRUE ! arg VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L618] reach_error() VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-2, cs2=0, cs2_new=-1, cs2_old=-2, manual_selection_History_0=-2, manual_selection_History_1=-3, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1_written=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - UnprovableResult [Line: 618]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: Not analyzed. - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 296 locations, 23 error locations. Started 1 CEGAR loops. OverallTime: 80.6s, OverallIterations: 45, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 47.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 21531 SDtfs, 49487 SDslu, 63295 SDs, 0 SdLazy, 12847 SolverSat, 794 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 8.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2582 GetRequests, 1775 SyntacticMatches, 3 SemanticMatches, 804 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43369 ImplicationChecksByTransitivity, 12.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=7251occurred in iteration=40, InterpolantAutomatonStates: 791, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 12.9s AutomataMinimizationTime, 44 MinimizatonAttempts, 74747 StatesRemovedByMinimization, 41 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.7s SsaConstructionTime, 2.7s SatisfiabilityAnalysisTime, 9.3s InterpolantComputationTime, 5847 NumberOfCodeBlocks, 5847 NumberOfCodeBlocksAsserted, 56 NumberOfCheckSat, 5642 ConstructedInterpolants, 0 QuantifiedInterpolants, 19808 SizeOfPredicates, 40 NumberOfNonLiveVariables, 8616 ConjunctsInSsa, 129 ConjunctsInUnsatCore, 55 InterpolantComputations, 38 PerfectInterpolantSequences, 792/1160 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2021-10-28 09:52:14,371 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4fbcdd48-b6b1-40f0-a6fa-74fd410c9acd/bin/uautomizer-UnR33cPsHg/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...