./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5900b6d010f1a05b489d03740eff20354d3bdae3e0a57f452d87a41022d28f81 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 23:18:01,174 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 23:18:01,176 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 23:18:01,214 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 23:18:01,214 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 23:18:01,216 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 23:18:01,218 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 23:18:01,221 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 23:18:01,224 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 23:18:01,225 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 23:18:01,227 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 23:18:01,228 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 23:18:01,229 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 23:18:01,231 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 23:18:01,233 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 23:18:01,235 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 23:18:01,236 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 23:18:01,237 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 23:18:01,240 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 23:18:01,244 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 23:18:01,247 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 23:18:01,249 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 23:18:01,252 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 23:18:01,253 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 23:18:01,259 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 23:18:01,260 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 23:18:01,260 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 23:18:01,262 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 23:18:01,263 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 23:18:01,264 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 23:18:01,265 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 23:18:01,266 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 23:18:01,268 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 23:18:01,269 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 23:18:01,270 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 23:18:01,271 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 23:18:01,272 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 23:18:01,273 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 23:18:01,273 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 23:18:01,275 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 23:18:01,279 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 23:18:01,280 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 23:18:01,329 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 23:18:01,338 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 23:18:01,339 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 23:18:01,339 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 23:18:01,341 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 23:18:01,341 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 23:18:01,341 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 23:18:01,342 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 23:18:01,342 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 23:18:01,342 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 23:18:01,344 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 23:18:01,344 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 23:18:01,344 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 23:18:01,345 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 23:18:01,345 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 23:18:01,345 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 23:18:01,345 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 23:18:01,346 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 23:18:01,346 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 23:18:01,346 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 23:18:01,347 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 23:18:01,347 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 23:18:01,347 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 23:18:01,347 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 23:18:01,348 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 23:18:01,348 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 23:18:01,350 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 23:18:01,351 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 23:18:01,351 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 23:18:01,352 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 23:18:01,352 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 23:18:01,352 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 23:18:01,354 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 23:18:01,355 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5900b6d010f1a05b489d03740eff20354d3bdae3e0a57f452d87a41022d28f81 [2021-10-28 23:18:01,667 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 23:18:01,697 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 23:18:01,701 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 23:18:01,702 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 23:18:01,704 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 23:18:01,705 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-10-28 23:18:01,799 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/data/1095121d7/3d6729886bc4439b9ac2ac7cb4ef8c0e/FLAG83c303dfb [2021-10-28 23:18:02,432 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 23:18:02,433 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-10-28 23:18:02,455 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/data/1095121d7/3d6729886bc4439b9ac2ac7cb4ef8c0e/FLAG83c303dfb [2021-10-28 23:18:02,725 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/data/1095121d7/3d6729886bc4439b9ac2ac7cb4ef8c0e [2021-10-28 23:18:02,729 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 23:18:02,731 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 23:18:02,733 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 23:18:02,733 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 23:18:02,741 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 23:18:02,742 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:18:02" (1/1) ... [2021-10-28 23:18:02,744 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b52f3c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:02, skipping insertion in model container [2021-10-28 23:18:02,744 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:18:02" (1/1) ... [2021-10-28 23:18:02,753 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 23:18:02,798 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 23:18:02,990 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[366,379] [2021-10-28 23:18:03,091 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:18:03,105 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 23:18:03,120 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[366,379] [2021-10-28 23:18:03,223 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:18:03,256 INFO L208 MainTranslator]: Completed translation [2021-10-28 23:18:03,256 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03 WrapperNode [2021-10-28 23:18:03,257 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 23:18:03,258 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 23:18:03,258 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 23:18:03,259 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 23:18:03,270 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,304 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,402 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 23:18:03,403 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 23:18:03,403 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 23:18:03,404 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 23:18:03,415 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,415 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,423 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,424 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,451 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,493 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,511 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,519 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 23:18:03,520 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 23:18:03,520 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 23:18:03,521 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 23:18:03,522 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (1/1) ... [2021-10-28 23:18:03,532 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:18:03,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:18:03,576 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:18:03,597 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 23:18:03,638 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 23:18:03,638 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 23:18:03,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 23:18:03,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 23:18:05,077 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 23:18:05,077 INFO L299 CfgBuilder]: Removed 161 assume(true) statements. [2021-10-28 23:18:05,081 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:18:05 BoogieIcfgContainer [2021-10-28 23:18:05,081 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 23:18:05,090 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 23:18:05,091 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 23:18:05,096 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 23:18:05,097 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:18:05,097 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 11:18:02" (1/3) ... [2021-10-28 23:18:05,100 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@247db2af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:18:05, skipping insertion in model container [2021-10-28 23:18:05,100 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:18:05,100 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:18:03" (2/3) ... [2021-10-28 23:18:05,101 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@247db2af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:18:05, skipping insertion in model container [2021-10-28 23:18:05,101 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:18:05,101 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:18:05" (3/3) ... [2021-10-28 23:18:05,103 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2021-10-28 23:18:05,174 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 23:18:05,174 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 23:18:05,175 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 23:18:05,175 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 23:18:05,175 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 23:18:05,175 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 23:18:05,175 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 23:18:05,176 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 23:18:05,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 413 states, 412 states have (on average 1.5558252427184467) internal successors, (641), 412 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:05,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 346 [2021-10-28 23:18:05,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:05,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:05,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,309 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,309 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 23:18:05,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 413 states, 412 states have (on average 1.5558252427184467) internal successors, (641), 412 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:05,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 346 [2021-10-28 23:18:05,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:05,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:05,352 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,352 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,364 INFO L791 eck$LassoCheckResult]: Stem: 401#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 351#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 299#L758true havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 270#L338true assume !(1 == ~m_i~0);~m_st~0 := 2; 67#L345-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 362#L350-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 219#L355-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 193#L360-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 222#L365-1true assume !(0 == ~M_E~0); 371#L506-1true assume !(0 == ~T1_E~0); 60#L511-1true assume !(0 == ~T2_E~0); 253#L516-1true assume !(0 == ~T3_E~0); 381#L521-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 287#L526-1true assume !(0 == ~E_M~0); 228#L531-1true assume !(0 == ~E_1~0); 177#L536-1true assume !(0 == ~E_2~0); 282#L541-1true assume !(0 == ~E_3~0); 173#L546-1true assume !(0 == ~E_4~0); 235#L551-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 217#L242true assume 1 == ~m_pc~0; 377#L243true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 185#L253true is_master_triggered_#res := is_master_triggered_~__retres1~0; 272#L254true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 259#L629true assume !(0 != activate_threads_~tmp~1); 335#L629-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 321#L261true assume !(1 == ~t1_pc~0); 267#L261-2true is_transmit1_triggered_~__retres1~1 := 0; 36#L272true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 366#L273true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 303#L637true assume !(0 != activate_threads_~tmp___0~0); 35#L637-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 190#L280true assume 1 == ~t2_pc~0; 118#L281true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 176#L291true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 73#L292true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 322#L645true assume !(0 != activate_threads_~tmp___1~0); 155#L645-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 248#L299true assume !(1 == ~t3_pc~0); 291#L299-2true is_transmit3_triggered_~__retres1~3 := 0; 170#L310true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 268#L311true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 261#L653true assume !(0 != activate_threads_~tmp___2~0); 312#L653-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 212#L318true assume 1 == ~t4_pc~0; 415#L319true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 346#L329true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 269#L330true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 309#L661true assume !(0 != activate_threads_~tmp___3~0); 130#L661-2true assume !(1 == ~M_E~0); 169#L564-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 221#L569-1true assume !(1 == ~T2_E~0); 105#L574-1true assume !(1 == ~T3_E~0); 112#L579-1true assume !(1 == ~T4_E~0); 75#L584-1true assume !(1 == ~E_M~0); 85#L589-1true assume !(1 == ~E_1~0); 251#L594-1true assume !(1 == ~E_2~0); 135#L599-1true assume !(1 == ~E_3~0); 16#L604-1true assume 1 == ~E_4~0;~E_4~0 := 2; 233#L795-1true [2021-10-28 23:18:05,367 INFO L793 eck$LassoCheckResult]: Loop: 233#L795-1true assume !false; 292#L796true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 339#L481true assume !true; 181#L496true start_simulation_~kernel_st~0 := 2; 79#L338-1true start_simulation_~kernel_st~0 := 3; 308#L506-2true assume 0 == ~M_E~0;~M_E~0 := 1; 348#L506-4true assume !(0 == ~T1_E~0); 340#L511-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 295#L516-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 405#L521-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 136#L526-3true assume 0 == ~E_M~0;~E_M~0 := 1; 71#L531-3true assume 0 == ~E_1~0;~E_1~0 := 1; 374#L536-3true assume 0 == ~E_2~0;~E_2~0 := 1; 15#L541-3true assume 0 == ~E_3~0;~E_3~0 := 1; 188#L546-3true assume !(0 == ~E_4~0); 407#L551-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 383#L242-18true assume !(1 == ~m_pc~0); 120#L242-20true is_master_triggered_~__retres1~0 := 0; 246#L253-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 249#L254-6true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 205#L629-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 55#L629-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51#L261-18true assume !(1 == ~t1_pc~0); 179#L261-20true is_transmit1_triggered_~__retres1~1 := 0; 355#L272-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 277#L273-6true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 275#L637-18true assume !(0 != activate_threads_~tmp___0~0); 93#L637-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 151#L280-18true assume !(1 == ~t2_pc~0); 289#L280-20true is_transmit2_triggered_~__retres1~2 := 0; 134#L291-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 168#L292-6true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 192#L645-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 296#L645-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 83#L299-18true assume 1 == ~t3_pc~0; 63#L300-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 119#L310-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43#L311-6true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 180#L653-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 97#L653-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12#L318-18true assume 1 == ~t4_pc~0; 122#L319-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 95#L329-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92#L330-6true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 87#L661-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 338#L661-20true assume 1 == ~M_E~0;~M_E~0 := 2; 84#L564-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 162#L569-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 406#L574-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 414#L579-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 128#L584-3true assume 1 == ~E_M~0;~E_M~0 := 2; 29#L589-3true assume !(1 == ~E_1~0); 126#L594-3true assume 1 == ~E_2~0;~E_2~0 := 2; 207#L599-3true assume 1 == ~E_3~0;~E_3~0 := 2; 149#L604-3true assume 1 == ~E_4~0;~E_4~0 := 2; 385#L609-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 114#L378-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 69#L405-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 98#L406-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 294#L814true assume !(0 == start_simulation_~tmp~3); 178#L814-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 183#L378-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 58#L405-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 281#L406-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 260#L769true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 244#L776true stop_simulation_#res := stop_simulation_~__retres2~0; 22#L777true start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 109#L827true assume !(0 != start_simulation_~tmp___0~1); 233#L795-1true [2021-10-28 23:18:05,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:05,375 INFO L85 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2021-10-28 23:18:05,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:05,387 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461951557] [2021-10-28 23:18:05,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:05,388 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:05,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:05,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:05,607 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:05,608 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461951557] [2021-10-28 23:18:05,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461951557] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:05,609 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:05,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:05,612 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328647476] [2021-10-28 23:18:05,620 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:05,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:05,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1152111383, now seen corresponding path program 1 times [2021-10-28 23:18:05,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:05,622 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684015382] [2021-10-28 23:18:05,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:05,623 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:05,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:05,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:05,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:05,660 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684015382] [2021-10-28 23:18:05,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684015382] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:05,661 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:05,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:05,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906777469] [2021-10-28 23:18:05,663 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:05,664 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:05,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:05,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:05,687 INFO L87 Difference]: Start difference. First operand has 413 states, 412 states have (on average 1.5558252427184467) internal successors, (641), 412 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:05,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:05,745 INFO L93 Difference]: Finished difference Result 413 states and 625 transitions. [2021-10-28 23:18:05,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:05,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 625 transitions. [2021-10-28 23:18:05,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:05,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 408 states and 620 transitions. [2021-10-28 23:18:05,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2021-10-28 23:18:05,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2021-10-28 23:18:05,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 620 transitions. [2021-10-28 23:18:05,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:05,790 INFO L681 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2021-10-28 23:18:05,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 620 transitions. [2021-10-28 23:18:05,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2021-10-28 23:18:05,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 408 states have (on average 1.5196078431372548) internal successors, (620), 407 states have internal predecessors, (620), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:05,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 620 transitions. [2021-10-28 23:18:05,865 INFO L704 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2021-10-28 23:18:05,865 INFO L587 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2021-10-28 23:18:05,865 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 23:18:05,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 620 transitions. [2021-10-28 23:18:05,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:05,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:05,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:05,873 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,873 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:05,874 INFO L791 eck$LassoCheckResult]: Stem: 1241#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1235#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1213#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1202#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 966#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 967#L350-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1163#L355-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1136#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1137#L365-1 assume !(0 == ~M_E~0); 1165#L506-1 assume !(0 == ~T1_E~0); 951#L511-1 assume !(0 == ~T2_E~0); 952#L516-1 assume !(0 == ~T3_E~0); 1185#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1210#L526-1 assume !(0 == ~E_M~0); 1171#L531-1 assume !(0 == ~E_1~0); 1123#L536-1 assume !(0 == ~E_2~0); 1124#L541-1 assume !(0 == ~E_3~0); 1119#L546-1 assume !(0 == ~E_4~0); 1120#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1161#L242 assume 1 == ~m_pc~0; 1162#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1091#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1129#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1193#L629 assume !(0 != activate_threads_~tmp~1); 1194#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1227#L261 assume !(1 == ~t1_pc~0); 1100#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 909#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 910#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1217#L637 assume !(0 != activate_threads_~tmp___0~0); 907#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 908#L280 assume 1 == ~t2_pc~0; 1053#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1004#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 975#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 976#L645 assume !(0 != activate_threads_~tmp___1~0); 1094#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1095#L299 assume !(1 == ~t3_pc~0); 1111#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 1110#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1116#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1196#L653 assume !(0 != activate_threads_~tmp___2~0); 1197#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1155#L318 assume 1 == ~t4_pc~0; 1156#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1024#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1200#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1201#L661 assume !(0 != activate_threads_~tmp___3~0); 1064#L661-2 assume !(1 == ~M_E~0); 1065#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1115#L569-1 assume !(1 == ~T2_E~0); 1036#L574-1 assume !(1 == ~T3_E~0); 1037#L579-1 assume !(1 == ~T4_E~0); 978#L584-1 assume !(1 == ~E_M~0); 979#L589-1 assume !(1 == ~E_1~0); 998#L594-1 assume !(1 == ~E_2~0); 1070#L599-1 assume !(1 == ~E_3~0); 868#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 869#L795-1 [2021-10-28 23:18:05,875 INFO L793 eck$LassoCheckResult]: Loop: 869#L795-1 assume !false; 1176#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1080#L481 assume !false; 1174#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1175#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1021#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1077#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1072#L420 assume !(0 != eval_~tmp~0); 1074#L496 start_simulation_~kernel_st~0 := 2; 985#L338-1 start_simulation_~kernel_st~0 := 3; 986#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1222#L506-4 assume !(0 == ~T1_E~0); 1230#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1211#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1212#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1071#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 971#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 972#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 866#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 867#L546-3 assume !(0 == ~E_4~0); 1132#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1239#L242-18 assume 1 == ~m_pc~0; 1041#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1042#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1184#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1147#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 941#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 932#L261-18 assume !(1 == ~t1_pc~0); 933#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 935#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1206#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1205#L637-18 assume !(0 != activate_threads_~tmp___0~0); 1012#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1013#L280-18 assume 1 == ~t2_pc~0; 1028#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1029#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1069#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1114#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1135#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 995#L299-18 assume 1 == ~t3_pc~0; 956#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 958#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 922#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 923#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1018#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 857#L318-18 assume 1 == ~t4_pc~0; 858#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1017#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1011#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1001#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1002#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 996#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 997#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1104#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1242#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1063#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 896#L589-3 assume !(1 == ~E_1~0); 897#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1061#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1086#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1087#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1048#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 883#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 970#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1019#L814 assume !(0 == start_simulation_~tmp~3); 1125#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1126#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 947#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 948#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1195#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1183#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 880#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 881#L827 assume !(0 != start_simulation_~tmp___0~1); 869#L795-1 [2021-10-28 23:18:05,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:05,876 INFO L85 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2021-10-28 23:18:05,876 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:05,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588614871] [2021-10-28 23:18:05,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:05,877 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:05,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:05,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:05,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:05,948 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588614871] [2021-10-28 23:18:05,948 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588614871] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:05,948 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:05,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:05,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823488556] [2021-10-28 23:18:05,950 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:05,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:05,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1043358087, now seen corresponding path program 1 times [2021-10-28 23:18:05,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:05,951 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827770316] [2021-10-28 23:18:05,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:05,952 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:05,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,069 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827770316] [2021-10-28 23:18:06,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827770316] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,082 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072509009] [2021-10-28 23:18:06,083 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:06,083 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:06,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:06,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:06,085 INFO L87 Difference]: Start difference. First operand 408 states and 620 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:06,162 INFO L93 Difference]: Finished difference Result 408 states and 619 transitions. [2021-10-28 23:18:06,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:06,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 619 transitions. [2021-10-28 23:18:06,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 619 transitions. [2021-10-28 23:18:06,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2021-10-28 23:18:06,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2021-10-28 23:18:06,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 619 transitions. [2021-10-28 23:18:06,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:06,182 INFO L681 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2021-10-28 23:18:06,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 619 transitions. [2021-10-28 23:18:06,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2021-10-28 23:18:06,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 408 states have (on average 1.517156862745098) internal successors, (619), 407 states have internal predecessors, (619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 619 transitions. [2021-10-28 23:18:06,206 INFO L704 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2021-10-28 23:18:06,206 INFO L587 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2021-10-28 23:18:06,206 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 23:18:06,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 619 transitions. [2021-10-28 23:18:06,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:06,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:06,227 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,228 INFO L791 eck$LassoCheckResult]: Stem: 2064#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2058#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2036#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2025#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 1789#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1986#L355-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1959#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1960#L365-1 assume !(0 == ~M_E~0); 1988#L506-1 assume !(0 == ~T1_E~0); 1774#L511-1 assume !(0 == ~T2_E~0); 1775#L516-1 assume !(0 == ~T3_E~0); 2008#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2033#L526-1 assume !(0 == ~E_M~0); 1994#L531-1 assume !(0 == ~E_1~0); 1946#L536-1 assume !(0 == ~E_2~0); 1947#L541-1 assume !(0 == ~E_3~0); 1942#L546-1 assume !(0 == ~E_4~0); 1943#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1984#L242 assume 1 == ~m_pc~0; 1985#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1914#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1952#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2016#L629 assume !(0 != activate_threads_~tmp~1); 2017#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2050#L261 assume !(1 == ~t1_pc~0); 1923#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 1732#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1733#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2040#L637 assume !(0 != activate_threads_~tmp___0~0); 1730#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1731#L280 assume 1 == ~t2_pc~0; 1876#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1827#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1798#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1799#L645 assume !(0 != activate_threads_~tmp___1~0); 1917#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1918#L299 assume !(1 == ~t3_pc~0); 1934#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 1933#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1939#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2019#L653 assume !(0 != activate_threads_~tmp___2~0); 2020#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1978#L318 assume 1 == ~t4_pc~0; 1979#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1847#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2023#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2024#L661 assume !(0 != activate_threads_~tmp___3~0); 1887#L661-2 assume !(1 == ~M_E~0); 1888#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1938#L569-1 assume !(1 == ~T2_E~0); 1859#L574-1 assume !(1 == ~T3_E~0); 1860#L579-1 assume !(1 == ~T4_E~0); 1801#L584-1 assume !(1 == ~E_M~0); 1802#L589-1 assume !(1 == ~E_1~0); 1821#L594-1 assume !(1 == ~E_2~0); 1893#L599-1 assume !(1 == ~E_3~0); 1691#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1692#L795-1 [2021-10-28 23:18:06,229 INFO L793 eck$LassoCheckResult]: Loop: 1692#L795-1 assume !false; 1999#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1903#L481 assume !false; 1997#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1998#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1844#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1900#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1895#L420 assume !(0 != eval_~tmp~0); 1897#L496 start_simulation_~kernel_st~0 := 2; 1808#L338-1 start_simulation_~kernel_st~0 := 3; 1809#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2045#L506-4 assume !(0 == ~T1_E~0); 2053#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2034#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2035#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1894#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1794#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1689#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1690#L546-3 assume !(0 == ~E_4~0); 1955#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2062#L242-18 assume 1 == ~m_pc~0; 1864#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1865#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2007#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1970#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1764#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1755#L261-18 assume !(1 == ~t1_pc~0); 1756#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 1758#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2029#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2028#L637-18 assume !(0 != activate_threads_~tmp___0~0); 1835#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1836#L280-18 assume 1 == ~t2_pc~0; 1851#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1852#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1892#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1937#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1958#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1818#L299-18 assume 1 == ~t3_pc~0; 1779#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1781#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1745#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1746#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1841#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1680#L318-18 assume 1 == ~t4_pc~0; 1681#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1840#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1834#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1824#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1825#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1819#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1820#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1927#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2065#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1886#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1719#L589-3 assume !(1 == ~E_1~0); 1720#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1884#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1909#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1910#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1871#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1706#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1793#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1842#L814 assume !(0 == start_simulation_~tmp~3); 1948#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1949#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1770#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1771#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2018#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2006#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 1703#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1704#L827 assume !(0 != start_simulation_~tmp___0~1); 1692#L795-1 [2021-10-28 23:18:06,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,230 INFO L85 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2021-10-28 23:18:06,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634499169] [2021-10-28 23:18:06,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,231 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,329 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634499169] [2021-10-28 23:18:06,329 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634499169] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,330 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,330 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,330 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326661157] [2021-10-28 23:18:06,331 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:06,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1043358087, now seen corresponding path program 2 times [2021-10-28 23:18:06,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,332 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837898670] [2021-10-28 23:18:06,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,333 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,450 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837898670] [2021-10-28 23:18:06,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837898670] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,452 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270640282] [2021-10-28 23:18:06,454 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:06,457 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:06,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:06,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:06,459 INFO L87 Difference]: Start difference. First operand 408 states and 619 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:06,481 INFO L93 Difference]: Finished difference Result 408 states and 618 transitions. [2021-10-28 23:18:06,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:06,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 618 transitions. [2021-10-28 23:18:06,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 618 transitions. [2021-10-28 23:18:06,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2021-10-28 23:18:06,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2021-10-28 23:18:06,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 618 transitions. [2021-10-28 23:18:06,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:06,506 INFO L681 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2021-10-28 23:18:06,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 618 transitions. [2021-10-28 23:18:06,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2021-10-28 23:18:06,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 408 states have (on average 1.5147058823529411) internal successors, (618), 407 states have internal predecessors, (618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 618 transitions. [2021-10-28 23:18:06,546 INFO L704 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2021-10-28 23:18:06,546 INFO L587 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2021-10-28 23:18:06,546 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 23:18:06,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 618 transitions. [2021-10-28 23:18:06,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:06,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:06,558 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,560 INFO L791 eck$LassoCheckResult]: Stem: 2887#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2881#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2859#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2848#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 2612#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2613#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2809#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2782#L360-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2783#L365-1 assume !(0 == ~M_E~0); 2811#L506-1 assume !(0 == ~T1_E~0); 2597#L511-1 assume !(0 == ~T2_E~0); 2598#L516-1 assume !(0 == ~T3_E~0); 2831#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2856#L526-1 assume !(0 == ~E_M~0); 2817#L531-1 assume !(0 == ~E_1~0); 2769#L536-1 assume !(0 == ~E_2~0); 2770#L541-1 assume !(0 == ~E_3~0); 2765#L546-1 assume !(0 == ~E_4~0); 2766#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2807#L242 assume 1 == ~m_pc~0; 2808#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2737#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2775#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2839#L629 assume !(0 != activate_threads_~tmp~1); 2840#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2873#L261 assume !(1 == ~t1_pc~0); 2746#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 2555#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2556#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2863#L637 assume !(0 != activate_threads_~tmp___0~0); 2553#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2554#L280 assume 1 == ~t2_pc~0; 2699#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2650#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2621#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2622#L645 assume !(0 != activate_threads_~tmp___1~0); 2740#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2741#L299 assume !(1 == ~t3_pc~0); 2757#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 2756#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2762#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2842#L653 assume !(0 != activate_threads_~tmp___2~0); 2843#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2801#L318 assume 1 == ~t4_pc~0; 2802#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2670#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2846#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2847#L661 assume !(0 != activate_threads_~tmp___3~0); 2710#L661-2 assume !(1 == ~M_E~0); 2711#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2761#L569-1 assume !(1 == ~T2_E~0); 2682#L574-1 assume !(1 == ~T3_E~0); 2683#L579-1 assume !(1 == ~T4_E~0); 2624#L584-1 assume !(1 == ~E_M~0); 2625#L589-1 assume !(1 == ~E_1~0); 2644#L594-1 assume !(1 == ~E_2~0); 2716#L599-1 assume !(1 == ~E_3~0); 2514#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2515#L795-1 [2021-10-28 23:18:06,564 INFO L793 eck$LassoCheckResult]: Loop: 2515#L795-1 assume !false; 2822#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2726#L481 assume !false; 2820#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2821#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2667#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2723#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2718#L420 assume !(0 != eval_~tmp~0); 2720#L496 start_simulation_~kernel_st~0 := 2; 2631#L338-1 start_simulation_~kernel_st~0 := 3; 2632#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2868#L506-4 assume !(0 == ~T1_E~0); 2876#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2857#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2858#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2717#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2617#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2618#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2512#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2513#L546-3 assume !(0 == ~E_4~0); 2778#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2885#L242-18 assume !(1 == ~m_pc~0); 2689#L242-20 is_master_triggered_~__retres1~0 := 0; 2688#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2830#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2793#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2587#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2578#L261-18 assume !(1 == ~t1_pc~0); 2579#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 2581#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2852#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2851#L637-18 assume !(0 != activate_threads_~tmp___0~0); 2658#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2659#L280-18 assume 1 == ~t2_pc~0; 2674#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2675#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2715#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2760#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2781#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2641#L299-18 assume 1 == ~t3_pc~0; 2602#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2604#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2568#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2569#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2664#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2503#L318-18 assume 1 == ~t4_pc~0; 2504#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2663#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2657#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2647#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2648#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2642#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2643#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2750#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2888#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2709#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2542#L589-3 assume !(1 == ~E_1~0); 2543#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2707#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2732#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2733#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2694#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2529#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2616#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2665#L814 assume !(0 == start_simulation_~tmp~3); 2771#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2772#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2593#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2594#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2841#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2829#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 2526#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2527#L827 assume !(0 != start_simulation_~tmp___0~1); 2515#L795-1 [2021-10-28 23:18:06,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,565 INFO L85 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2021-10-28 23:18:06,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880036218] [2021-10-28 23:18:06,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,568 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,659 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,660 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880036218] [2021-10-28 23:18:06,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880036218] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,660 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302721609] [2021-10-28 23:18:06,662 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:06,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,662 INFO L85 PathProgramCache]: Analyzing trace with hash 341789862, now seen corresponding path program 1 times [2021-10-28 23:18:06,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,663 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751299974] [2021-10-28 23:18:06,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,664 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,713 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751299974] [2021-10-28 23:18:06,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751299974] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,714 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753771138] [2021-10-28 23:18:06,726 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:06,727 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:06,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:06,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:06,728 INFO L87 Difference]: Start difference. First operand 408 states and 618 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:06,751 INFO L93 Difference]: Finished difference Result 408 states and 617 transitions. [2021-10-28 23:18:06,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:06,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 617 transitions. [2021-10-28 23:18:06,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 617 transitions. [2021-10-28 23:18:06,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2021-10-28 23:18:06,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2021-10-28 23:18:06,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 617 transitions. [2021-10-28 23:18:06,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:06,767 INFO L681 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2021-10-28 23:18:06,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 617 transitions. [2021-10-28 23:18:06,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2021-10-28 23:18:06,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 408 states have (on average 1.5122549019607843) internal successors, (617), 407 states have internal predecessors, (617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:06,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 617 transitions. [2021-10-28 23:18:06,781 INFO L704 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2021-10-28 23:18:06,781 INFO L587 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2021-10-28 23:18:06,781 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 23:18:06,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 617 transitions. [2021-10-28 23:18:06,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:06,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:06,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:06,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:06,791 INFO L791 eck$LassoCheckResult]: Stem: 3710#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3704#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3682#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3672#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 3435#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3436#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3632#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3605#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3606#L365-1 assume !(0 == ~M_E~0); 3634#L506-1 assume !(0 == ~T1_E~0); 3420#L511-1 assume !(0 == ~T2_E~0); 3421#L516-1 assume !(0 == ~T3_E~0); 3656#L521-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3679#L526-1 assume !(0 == ~E_M~0); 3640#L531-1 assume !(0 == ~E_1~0); 3592#L536-1 assume !(0 == ~E_2~0); 3593#L541-1 assume !(0 == ~E_3~0); 3588#L546-1 assume !(0 == ~E_4~0); 3589#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3630#L242 assume 1 == ~m_pc~0; 3631#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3560#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3598#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3663#L629 assume !(0 != activate_threads_~tmp~1); 3664#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3696#L261 assume !(1 == ~t1_pc~0); 3569#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 3380#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3381#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3686#L637 assume !(0 != activate_threads_~tmp___0~0); 3376#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3377#L280 assume 1 == ~t2_pc~0; 3522#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3473#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3445#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3446#L645 assume !(0 != activate_threads_~tmp___1~0); 3564#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3565#L299 assume !(1 == ~t3_pc~0); 3580#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 3579#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3585#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3665#L653 assume !(0 != activate_threads_~tmp___2~0); 3666#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3625#L318 assume 1 == ~t4_pc~0; 3626#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3493#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3669#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3670#L661 assume !(0 != activate_threads_~tmp___3~0); 3533#L661-2 assume !(1 == ~M_E~0); 3534#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3584#L569-1 assume !(1 == ~T2_E~0); 3505#L574-1 assume !(1 == ~T3_E~0); 3506#L579-1 assume !(1 == ~T4_E~0); 3447#L584-1 assume !(1 == ~E_M~0); 3448#L589-1 assume !(1 == ~E_1~0); 3467#L594-1 assume !(1 == ~E_2~0); 3539#L599-1 assume !(1 == ~E_3~0); 3337#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3338#L795-1 [2021-10-28 23:18:06,793 INFO L793 eck$LassoCheckResult]: Loop: 3338#L795-1 assume !false; 3645#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3549#L481 assume !false; 3643#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3644#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3490#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3546#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3541#L420 assume !(0 != eval_~tmp~0); 3543#L496 start_simulation_~kernel_st~0 := 2; 3456#L338-1 start_simulation_~kernel_st~0 := 3; 3457#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3691#L506-4 assume !(0 == ~T1_E~0); 3699#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3680#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3681#L521-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3540#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3440#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3441#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3335#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3336#L546-3 assume !(0 == ~E_4~0); 3601#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3708#L242-18 assume 1 == ~m_pc~0; 3510#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3511#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3653#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3616#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3407#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3401#L261-18 assume !(1 == ~t1_pc~0); 3402#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 3404#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3675#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3674#L637-18 assume !(0 != activate_threads_~tmp___0~0); 3481#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3482#L280-18 assume 1 == ~t2_pc~0; 3497#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3498#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3538#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3581#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3604#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3464#L299-18 assume 1 == ~t3_pc~0; 3425#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3427#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3391#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3392#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3487#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3326#L318-18 assume !(1 == ~t4_pc~0); 3328#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 3486#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3480#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3470#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3471#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3465#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3466#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3573#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3711#L579-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3532#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3365#L589-3 assume !(1 == ~E_1~0); 3366#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3530#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3555#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3556#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3515#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3352#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3439#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3488#L814 assume !(0 == start_simulation_~tmp~3); 3594#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3595#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3416#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3417#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 3662#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3652#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 3349#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3350#L827 assume !(0 != start_simulation_~tmp___0~1); 3338#L795-1 [2021-10-28 23:18:06,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,795 INFO L85 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2021-10-28 23:18:06,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,796 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038354676] [2021-10-28 23:18:06,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,796 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,888 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038354676] [2021-10-28 23:18:06,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038354676] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,888 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:06,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143251829] [2021-10-28 23:18:06,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:06,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:06,890 INFO L85 PathProgramCache]: Analyzing trace with hash 734919078, now seen corresponding path program 1 times [2021-10-28 23:18:06,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:06,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000632650] [2021-10-28 23:18:06,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:06,891 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:06,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:06,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:06,987 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:06,988 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000632650] [2021-10-28 23:18:06,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000632650] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:06,988 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:06,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:06,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646268878] [2021-10-28 23:18:06,989 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:06,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:06,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:06,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:06,991 INFO L87 Difference]: Start difference. First operand 408 states and 617 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:07,038 INFO L93 Difference]: Finished difference Result 408 states and 612 transitions. [2021-10-28 23:18:07,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:07,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 612 transitions. [2021-10-28 23:18:07,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:07,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 612 transitions. [2021-10-28 23:18:07,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2021-10-28 23:18:07,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2021-10-28 23:18:07,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 612 transitions. [2021-10-28 23:18:07,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:07,051 INFO L681 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2021-10-28 23:18:07,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 612 transitions. [2021-10-28 23:18:07,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2021-10-28 23:18:07,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 408 states have (on average 1.5) internal successors, (612), 407 states have internal predecessors, (612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 612 transitions. [2021-10-28 23:18:07,065 INFO L704 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2021-10-28 23:18:07,065 INFO L587 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2021-10-28 23:18:07,065 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 23:18:07,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 612 transitions. [2021-10-28 23:18:07,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-10-28 23:18:07,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:07,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:07,080 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,080 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,080 INFO L791 eck$LassoCheckResult]: Stem: 4533#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4527#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4505#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4494#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 4258#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4259#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4455#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4428#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4429#L365-1 assume !(0 == ~M_E~0); 4457#L506-1 assume !(0 == ~T1_E~0); 4243#L511-1 assume !(0 == ~T2_E~0); 4244#L516-1 assume !(0 == ~T3_E~0); 4479#L521-1 assume !(0 == ~T4_E~0); 4502#L526-1 assume !(0 == ~E_M~0); 4463#L531-1 assume !(0 == ~E_1~0); 4415#L536-1 assume !(0 == ~E_2~0); 4416#L541-1 assume !(0 == ~E_3~0); 4411#L546-1 assume !(0 == ~E_4~0); 4412#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4453#L242 assume 1 == ~m_pc~0; 4454#L243 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4383#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4421#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4485#L629 assume !(0 != activate_threads_~tmp~1); 4486#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4519#L261 assume !(1 == ~t1_pc~0); 4392#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 4201#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4202#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4509#L637 assume !(0 != activate_threads_~tmp___0~0); 4199#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4200#L280 assume 1 == ~t2_pc~0; 4345#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4296#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4267#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4268#L645 assume !(0 != activate_threads_~tmp___1~0); 4386#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4387#L299 assume !(1 == ~t3_pc~0); 4403#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 4402#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4408#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4488#L653 assume !(0 != activate_threads_~tmp___2~0); 4489#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4447#L318 assume 1 == ~t4_pc~0; 4448#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4316#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4492#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4493#L661 assume !(0 != activate_threads_~tmp___3~0); 4356#L661-2 assume !(1 == ~M_E~0); 4357#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4407#L569-1 assume !(1 == ~T2_E~0); 4328#L574-1 assume !(1 == ~T3_E~0); 4329#L579-1 assume !(1 == ~T4_E~0); 4270#L584-1 assume !(1 == ~E_M~0); 4271#L589-1 assume !(1 == ~E_1~0); 4290#L594-1 assume !(1 == ~E_2~0); 4362#L599-1 assume !(1 == ~E_3~0); 4160#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4161#L795-1 [2021-10-28 23:18:07,081 INFO L793 eck$LassoCheckResult]: Loop: 4161#L795-1 assume !false; 4468#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4372#L481 assume !false; 4466#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4467#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4313#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4369#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4364#L420 assume !(0 != eval_~tmp~0); 4366#L496 start_simulation_~kernel_st~0 := 2; 4277#L338-1 start_simulation_~kernel_st~0 := 3; 4278#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4514#L506-4 assume !(0 == ~T1_E~0); 4522#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4503#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4504#L521-3 assume !(0 == ~T4_E~0); 4363#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4263#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4264#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4158#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4159#L546-3 assume !(0 == ~E_4~0); 4424#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4531#L242-18 assume 1 == ~m_pc~0; 4333#L243-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4334#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4476#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4439#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4233#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4224#L261-18 assume !(1 == ~t1_pc~0); 4225#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 4227#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4498#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4497#L637-18 assume !(0 != activate_threads_~tmp___0~0); 4304#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4305#L280-18 assume 1 == ~t2_pc~0; 4322#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4323#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4361#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4406#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4427#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4287#L299-18 assume 1 == ~t3_pc~0; 4248#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4250#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4214#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4215#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4310#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4149#L318-18 assume 1 == ~t4_pc~0; 4150#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4309#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4303#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4293#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4294#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4288#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4289#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4396#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4534#L579-3 assume !(1 == ~T4_E~0); 4355#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4188#L589-3 assume !(1 == ~E_1~0); 4189#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4353#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4378#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4379#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4340#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4175#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4262#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4311#L814 assume !(0 == start_simulation_~tmp~3); 4417#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4418#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4239#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4240#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 4487#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4475#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 4172#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4173#L827 assume !(0 != start_simulation_~tmp___0~1); 4161#L795-1 [2021-10-28 23:18:07,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2021-10-28 23:18:07,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171464673] [2021-10-28 23:18:07,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,082 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,152 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,153 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171464673] [2021-10-28 23:18:07,153 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171464673] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,154 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,154 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:07,154 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372018776] [2021-10-28 23:18:07,155 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:07,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,156 INFO L85 PathProgramCache]: Analyzing trace with hash -84885877, now seen corresponding path program 1 times [2021-10-28 23:18:07,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,157 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661762049] [2021-10-28 23:18:07,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,158 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,271 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661762049] [2021-10-28 23:18:07,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661762049] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,272 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:07,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770681653] [2021-10-28 23:18:07,273 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:07,273 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:07,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:07,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:07,274 INFO L87 Difference]: Start difference. First operand 408 states and 612 transitions. cyclomatic complexity: 205 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:07,360 INFO L93 Difference]: Finished difference Result 743 states and 1099 transitions. [2021-10-28 23:18:07,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:07,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 743 states and 1099 transitions. [2021-10-28 23:18:07,370 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 680 [2021-10-28 23:18:07,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 743 states to 743 states and 1099 transitions. [2021-10-28 23:18:07,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 743 [2021-10-28 23:18:07,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 743 [2021-10-28 23:18:07,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 743 states and 1099 transitions. [2021-10-28 23:18:07,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:07,388 INFO L681 BuchiCegarLoop]: Abstraction has 743 states and 1099 transitions. [2021-10-28 23:18:07,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states and 1099 transitions. [2021-10-28 23:18:07,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 710. [2021-10-28 23:18:07,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 710 states, 710 states have (on average 1.4830985915492958) internal successors, (1053), 709 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 710 states to 710 states and 1053 transitions. [2021-10-28 23:18:07,421 INFO L704 BuchiCegarLoop]: Abstraction has 710 states and 1053 transitions. [2021-10-28 23:18:07,421 INFO L587 BuchiCegarLoop]: Abstraction has 710 states and 1053 transitions. [2021-10-28 23:18:07,421 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 23:18:07,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 710 states and 1053 transitions. [2021-10-28 23:18:07,427 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 647 [2021-10-28 23:18:07,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:07,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:07,429 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,429 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,429 INFO L791 eck$LassoCheckResult]: Stem: 5710#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5700#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5672#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5662#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 5414#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5415#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5618#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5590#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5591#L365-1 assume !(0 == ~M_E~0); 5620#L506-1 assume !(0 == ~T1_E~0); 5400#L511-1 assume !(0 == ~T2_E~0); 5401#L516-1 assume !(0 == ~T3_E~0); 5645#L521-1 assume !(0 == ~T4_E~0); 5669#L526-1 assume !(0 == ~E_M~0); 5626#L531-1 assume !(0 == ~E_1~0); 5577#L536-1 assume !(0 == ~E_2~0); 5578#L541-1 assume !(0 == ~E_3~0); 5573#L546-1 assume !(0 == ~E_4~0); 5574#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5617#L242 assume !(1 == ~m_pc~0); 5542#L242-2 is_master_triggered_~__retres1~0 := 0; 5543#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5583#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5652#L629 assume !(0 != activate_threads_~tmp~1); 5653#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5691#L261 assume !(1 == ~t1_pc~0); 5552#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 5360#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5361#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5676#L637 assume !(0 != activate_threads_~tmp___0~0); 5356#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5357#L280 assume 1 == ~t2_pc~0; 5505#L281 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5454#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5426#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5427#L645 assume !(0 != activate_threads_~tmp___1~0); 5547#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5548#L299 assume !(1 == ~t3_pc~0); 5564#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 5563#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5570#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5654#L653 assume !(0 != activate_threads_~tmp___2~0); 5655#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5612#L318 assume 1 == ~t4_pc~0; 5613#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5474#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5659#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5660#L661 assume !(0 != activate_threads_~tmp___3~0); 5517#L661-2 assume !(1 == ~M_E~0); 5518#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5569#L569-1 assume !(1 == ~T2_E~0); 5486#L574-1 assume !(1 == ~T3_E~0); 5487#L579-1 assume !(1 == ~T4_E~0); 5428#L584-1 assume !(1 == ~E_M~0); 5429#L589-1 assume !(1 == ~E_1~0); 5448#L594-1 assume !(1 == ~E_2~0); 5523#L599-1 assume !(1 == ~E_3~0); 5317#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5318#L795-1 [2021-10-28 23:18:07,429 INFO L793 eck$LassoCheckResult]: Loop: 5318#L795-1 assume !false; 5631#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5533#L481 assume !false; 5629#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5630#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5471#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5530#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5525#L420 assume !(0 != eval_~tmp~0); 5527#L496 start_simulation_~kernel_st~0 := 2; 5435#L338-1 start_simulation_~kernel_st~0 := 3; 5436#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5682#L506-4 assume !(0 == ~T1_E~0); 5695#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5670#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5671#L521-3 assume !(0 == ~T4_E~0); 5524#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5421#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5422#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5315#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5316#L546-3 assume !(0 == ~E_4~0); 5586#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5706#L242-18 assume !(1 == ~m_pc~0); 5506#L242-20 is_master_triggered_~__retres1~0 := 0; 5507#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5642#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5603#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5390#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5381#L261-18 assume !(1 == ~t1_pc~0); 5382#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 5384#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5665#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5664#L637-18 assume !(0 != activate_threads_~tmp___0~0); 5462#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5463#L280-18 assume 1 == ~t2_pc~0; 5478#L281-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5479#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5522#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5565#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5589#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5445#L299-18 assume 1 == ~t3_pc~0; 5404#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5406#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5368#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5369#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5468#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5306#L318-18 assume 1 == ~t4_pc~0; 5307#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5464#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5461#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5451#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5452#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5694#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5556#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5557#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5711#L579-3 assume !(1 == ~T4_E~0); 5515#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5343#L589-3 assume !(1 == ~E_1~0); 5344#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5514#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5538#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5539#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5498#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5332#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5418#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5469#L814 assume !(0 == start_simulation_~tmp~3); 5579#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5580#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5396#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5397#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5651#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5638#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 5329#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5330#L827 assume !(0 != start_simulation_~tmp___0~1); 5318#L795-1 [2021-10-28 23:18:07,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2021-10-28 23:18:07,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,431 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418330487] [2021-10-28 23:18:07,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,432 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,483 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418330487] [2021-10-28 23:18:07,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418330487] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,483 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:07,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408352827] [2021-10-28 23:18:07,484 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:07,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,484 INFO L85 PathProgramCache]: Analyzing trace with hash -786454102, now seen corresponding path program 1 times [2021-10-28 23:18:07,485 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,485 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239081922] [2021-10-28 23:18:07,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,485 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,531 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,532 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239081922] [2021-10-28 23:18:07,532 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239081922] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,532 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,532 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:07,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567977100] [2021-10-28 23:18:07,533 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:07,533 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:07,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:18:07,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:18:07,534 INFO L87 Difference]: Start difference. First operand 710 states and 1053 transitions. cyclomatic complexity: 345 Second operand has 4 states, 4 states have (on average 14.5) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:07,735 INFO L93 Difference]: Finished difference Result 1608 states and 2350 transitions. [2021-10-28 23:18:07,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:18:07,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1608 states and 2350 transitions. [2021-10-28 23:18:07,756 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1505 [2021-10-28 23:18:07,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1608 states to 1608 states and 2350 transitions. [2021-10-28 23:18:07,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1608 [2021-10-28 23:18:07,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1608 [2021-10-28 23:18:07,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1608 states and 2350 transitions. [2021-10-28 23:18:07,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:07,782 INFO L681 BuchiCegarLoop]: Abstraction has 1608 states and 2350 transitions. [2021-10-28 23:18:07,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1608 states and 2350 transitions. [2021-10-28 23:18:07,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1608 to 1271. [2021-10-28 23:18:07,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1271 states, 1271 states have (on average 1.4720692368214006) internal successors, (1871), 1270 states have internal predecessors, (1871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:07,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1871 transitions. [2021-10-28 23:18:07,828 INFO L704 BuchiCegarLoop]: Abstraction has 1271 states and 1871 transitions. [2021-10-28 23:18:07,828 INFO L587 BuchiCegarLoop]: Abstraction has 1271 states and 1871 transitions. [2021-10-28 23:18:07,828 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 23:18:07,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1271 states and 1871 transitions. [2021-10-28 23:18:07,839 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1208 [2021-10-28 23:18:07,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:07,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:07,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,841 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:07,842 INFO L791 eck$LassoCheckResult]: Stem: 8047#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8033#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8008#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7991#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 7741#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7742#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7947#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7916#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7917#L365-1 assume !(0 == ~M_E~0); 7949#L506-1 assume !(0 == ~T1_E~0); 7727#L511-1 assume !(0 == ~T2_E~0); 7728#L516-1 assume !(0 == ~T3_E~0); 7973#L521-1 assume !(0 == ~T4_E~0); 8000#L526-1 assume !(0 == ~E_M~0); 7955#L531-1 assume !(0 == ~E_1~0); 7903#L536-1 assume !(0 == ~E_2~0); 7904#L541-1 assume !(0 == ~E_3~0); 7899#L546-1 assume !(0 == ~E_4~0); 7900#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7946#L242 assume !(1 == ~m_pc~0); 7870#L242-2 is_master_triggered_~__retres1~0 := 0; 7871#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7909#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7981#L629 assume !(0 != activate_threads_~tmp~1); 7982#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8025#L261 assume !(1 == ~t1_pc~0); 7880#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 7686#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7687#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8012#L637 assume !(0 != activate_threads_~tmp___0~0); 7684#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7685#L280 assume !(1 == ~t2_pc~0); 7779#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 7780#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7752#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7753#L645 assume !(0 != activate_threads_~tmp___1~0); 7874#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7875#L299 assume !(1 == ~t3_pc~0); 7891#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 7890#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7896#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7984#L653 assume !(0 != activate_threads_~tmp___2~0); 7985#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7940#L318 assume 1 == ~t4_pc~0; 7941#L319 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7800#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7989#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7990#L661 assume !(0 != activate_threads_~tmp___3~0); 7843#L661-2 assume !(1 == ~M_E~0); 7844#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7895#L569-1 assume !(1 == ~T2_E~0); 7811#L574-1 assume !(1 == ~T3_E~0); 7812#L579-1 assume !(1 == ~T4_E~0); 7755#L584-1 assume !(1 == ~E_M~0); 7756#L589-1 assume !(1 == ~E_1~0); 7774#L594-1 assume !(1 == ~E_2~0); 7850#L599-1 assume !(1 == ~E_3~0); 7645#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7646#L795-1 [2021-10-28 23:18:07,842 INFO L793 eck$LassoCheckResult]: Loop: 7646#L795-1 assume !false; 7960#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7860#L481 assume !false; 7958#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7959#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7797#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7857#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7852#L420 assume !(0 != eval_~tmp~0); 7854#L496 start_simulation_~kernel_st~0 := 2; 7761#L338-1 start_simulation_~kernel_st~0 := 3; 7762#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8017#L506-4 assume !(0 == ~T1_E~0); 8028#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8003#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8004#L521-3 assume !(0 == ~T4_E~0); 7851#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7748#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7749#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7643#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7644#L546-3 assume !(0 == ~E_4~0); 7912#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8045#L242-18 assume !(1 == ~m_pc~0); 7830#L242-20 is_master_triggered_~__retres1~0 := 0; 7831#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7972#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7932#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7717#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7709#L261-18 assume !(1 == ~t1_pc~0); 7710#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 7712#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7996#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7994#L637-18 assume !(0 != activate_threads_~tmp___0~0); 7788#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7789#L280-18 assume !(1 == ~t2_pc~0); 7868#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 7848#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7849#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7894#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7915#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7771#L299-18 assume 1 == ~t3_pc~0; 7731#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7733#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7696#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7697#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7794#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7634#L318-18 assume 1 == ~t4_pc~0; 7635#L319-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7793#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7787#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7777#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7778#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7772#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7773#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7884#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8048#L579-3 assume !(1 == ~T4_E~0); 7840#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7673#L589-3 assume !(1 == ~E_1~0); 7674#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7838#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7865#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7866#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7825#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7660#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7745#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7795#L814 assume !(0 == start_simulation_~tmp~3); 7905#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7906#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7723#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7724#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7983#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7968#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 7657#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7658#L827 assume !(0 != start_simulation_~tmp___0~1); 7646#L795-1 [2021-10-28 23:18:07,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,842 INFO L85 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2021-10-28 23:18:07,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,843 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926528537] [2021-10-28 23:18:07,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,843 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,898 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926528537] [2021-10-28 23:18:07,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926528537] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,898 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:07,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974992226] [2021-10-28 23:18:07,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:07,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:07,900 INFO L85 PathProgramCache]: Analyzing trace with hash -386462903, now seen corresponding path program 1 times [2021-10-28 23:18:07,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:07,900 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905246721] [2021-10-28 23:18:07,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:07,900 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:07,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:07,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:07,939 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:07,939 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905246721] [2021-10-28 23:18:07,948 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905246721] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:07,948 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:07,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:07,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085664222] [2021-10-28 23:18:07,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:07,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:07,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:07,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:07,950 INFO L87 Difference]: Start difference. First operand 1271 states and 1871 transitions. cyclomatic complexity: 602 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:08,065 INFO L93 Difference]: Finished difference Result 2320 states and 3392 transitions. [2021-10-28 23:18:08,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:08,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2320 states and 3392 transitions. [2021-10-28 23:18:08,101 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2248 [2021-10-28 23:18:08,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2320 states to 2320 states and 3392 transitions. [2021-10-28 23:18:08,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2320 [2021-10-28 23:18:08,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2320 [2021-10-28 23:18:08,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2320 states and 3392 transitions. [2021-10-28 23:18:08,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:08,141 INFO L681 BuchiCegarLoop]: Abstraction has 2320 states and 3392 transitions. [2021-10-28 23:18:08,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2320 states and 3392 transitions. [2021-10-28 23:18:08,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2320 to 2312. [2021-10-28 23:18:08,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2312 states, 2312 states have (on average 1.4636678200692042) internal successors, (3384), 2311 states have internal predecessors, (3384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 3384 transitions. [2021-10-28 23:18:08,213 INFO L704 BuchiCegarLoop]: Abstraction has 2312 states and 3384 transitions. [2021-10-28 23:18:08,213 INFO L587 BuchiCegarLoop]: Abstraction has 2312 states and 3384 transitions. [2021-10-28 23:18:08,213 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 23:18:08,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2312 states and 3384 transitions. [2021-10-28 23:18:08,233 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2021-10-28 23:18:08,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:08,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:08,235 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,235 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,236 INFO L791 eck$LassoCheckResult]: Stem: 11695#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11674#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11635#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11615#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 11340#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11341#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11564#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11533#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11534#L365-1 assume !(0 == ~M_E~0); 11566#L506-1 assume !(0 == ~T1_E~0); 11326#L511-1 assume !(0 == ~T2_E~0); 11327#L516-1 assume !(0 == ~T3_E~0); 11595#L521-1 assume !(0 == ~T4_E~0); 11625#L526-1 assume !(0 == ~E_M~0); 11573#L531-1 assume !(0 == ~E_1~0); 11513#L536-1 assume !(0 == ~E_2~0); 11514#L541-1 assume !(0 == ~E_3~0); 11508#L546-1 assume !(0 == ~E_4~0); 11509#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11563#L242 assume !(1 == ~m_pc~0); 11479#L242-2 is_master_triggered_~__retres1~0 := 0; 11480#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11523#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11603#L629 assume !(0 != activate_threads_~tmp~1); 11604#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11659#L261 assume !(1 == ~t1_pc~0); 11489#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 11284#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11285#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11639#L637 assume !(0 != activate_threads_~tmp___0~0); 11282#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11283#L280 assume !(1 == ~t2_pc~0); 11380#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 11381#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11351#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11352#L645 assume !(0 != activate_threads_~tmp___1~0); 11483#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11484#L299 assume !(1 == ~t3_pc~0); 11500#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 11499#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11505#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11606#L653 assume !(0 != activate_threads_~tmp___2~0); 11607#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11558#L318 assume !(1 == ~t4_pc~0); 11400#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 11401#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11613#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11614#L661 assume !(0 != activate_threads_~tmp___3~0); 11447#L661-2 assume !(1 == ~M_E~0); 11448#L564-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11504#L569-1 assume !(1 == ~T2_E~0); 11412#L574-1 assume !(1 == ~T3_E~0); 11413#L579-1 assume !(1 == ~T4_E~0); 11354#L584-1 assume !(1 == ~E_M~0); 11355#L589-1 assume !(1 == ~E_1~0); 11375#L594-1 assume !(1 == ~E_2~0); 11455#L599-1 assume !(1 == ~E_3~0); 11243#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11244#L795-1 [2021-10-28 23:18:08,236 INFO L793 eck$LassoCheckResult]: Loop: 11244#L795-1 assume !false; 12477#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 12432#L481 assume !false; 12414#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12387#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 12382#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12377#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12375#L420 assume !(0 != eval_~tmp~0); 11517#L496 start_simulation_~kernel_st~0 := 2; 11518#L338-1 start_simulation_~kernel_st~0 := 3; 13429#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13428#L506-4 assume !(0 == ~T1_E~0); 13427#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13426#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13425#L521-3 assume !(0 == ~T4_E~0); 13364#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13363#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13362#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13361#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13360#L546-3 assume !(0 == ~E_4~0); 13359#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13358#L242-18 assume !(1 == ~m_pc~0); 13357#L242-20 is_master_triggered_~__retres1~0 := 0; 13356#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13355#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13354#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13353#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13351#L261-18 assume 1 == ~t1_pc~0; 13348#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13347#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13346#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13345#L637-18 assume !(0 != activate_threads_~tmp___0~0); 13344#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12663#L280-18 assume !(1 == ~t2_pc~0); 12660#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 12658#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12655#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12653#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12651#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12650#L299-18 assume !(1 == ~t3_pc~0); 12647#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 12645#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12643#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12641#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12639#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12637#L318-18 assume !(1 == ~t4_pc~0); 12634#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 12632#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12630#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12628#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12626#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 12624#L564-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12620#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12616#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12612#L579-3 assume !(1 == ~T4_E~0); 12608#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12604#L589-3 assume !(1 == ~E_1~0); 12599#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12595#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12590#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12586#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12579#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 12571#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12566#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 12560#L814 assume !(0 == start_simulation_~tmp~3); 12555#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12545#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 12538#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12536#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 12534#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12532#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 12497#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 12490#L827 assume !(0 != start_simulation_~tmp___0~1); 11244#L795-1 [2021-10-28 23:18:08,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:08,236 INFO L85 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2021-10-28 23:18:08,237 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:08,237 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909994483] [2021-10-28 23:18:08,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:08,237 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:08,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:08,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:08,289 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:08,292 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909994483] [2021-10-28 23:18:08,293 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909994483] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:08,293 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:08,293 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:08,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618896843] [2021-10-28 23:18:08,294 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:08,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:08,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1015547416, now seen corresponding path program 1 times [2021-10-28 23:18:08,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:08,295 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178772286] [2021-10-28 23:18:08,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:08,295 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:08,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:08,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:08,336 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:08,336 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178772286] [2021-10-28 23:18:08,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178772286] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:08,336 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:08,336 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:08,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305706119] [2021-10-28 23:18:08,337 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:08,337 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:08,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:08,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:08,338 INFO L87 Difference]: Start difference. First operand 2312 states and 3384 transitions. cyclomatic complexity: 1076 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:08,376 INFO L93 Difference]: Finished difference Result 2312 states and 3358 transitions. [2021-10-28 23:18:08,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:08,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2312 states and 3358 transitions. [2021-10-28 23:18:08,404 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2021-10-28 23:18:08,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2312 states to 2312 states and 3358 transitions. [2021-10-28 23:18:08,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2312 [2021-10-28 23:18:08,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2312 [2021-10-28 23:18:08,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2312 states and 3358 transitions. [2021-10-28 23:18:08,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:08,443 INFO L681 BuchiCegarLoop]: Abstraction has 2312 states and 3358 transitions. [2021-10-28 23:18:08,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2312 states and 3358 transitions. [2021-10-28 23:18:08,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2312 to 2312. [2021-10-28 23:18:08,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2312 states, 2312 states have (on average 1.4524221453287198) internal successors, (3358), 2311 states have internal predecessors, (3358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 3358 transitions. [2021-10-28 23:18:08,513 INFO L704 BuchiCegarLoop]: Abstraction has 2312 states and 3358 transitions. [2021-10-28 23:18:08,513 INFO L587 BuchiCegarLoop]: Abstraction has 2312 states and 3358 transitions. [2021-10-28 23:18:08,513 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 23:18:08,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2312 states and 3358 transitions. [2021-10-28 23:18:08,536 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2021-10-28 23:18:08,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:08,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:08,538 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,575 INFO L791 eck$LassoCheckResult]: Stem: 16304#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16286#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16255#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16234#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 15974#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15975#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16183#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16153#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16154#L365-1 assume !(0 == ~M_E~0); 16185#L506-1 assume !(0 == ~T1_E~0); 15959#L511-1 assume !(0 == ~T2_E~0); 15960#L516-1 assume !(0 == ~T3_E~0); 16216#L521-1 assume !(0 == ~T4_E~0); 16245#L526-1 assume !(0 == ~E_M~0); 16193#L531-1 assume !(0 == ~E_1~0); 16140#L536-1 assume !(0 == ~E_2~0); 16141#L541-1 assume !(0 == ~E_3~0); 16135#L546-1 assume !(0 == ~E_4~0); 16136#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16182#L242 assume !(1 == ~m_pc~0); 16106#L242-2 is_master_triggered_~__retres1~0 := 0; 16107#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16147#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16224#L629 assume !(0 != activate_threads_~tmp~1); 16225#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16273#L261 assume !(1 == ~t1_pc~0); 16116#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 15916#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15917#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16259#L637 assume !(0 != activate_threads_~tmp___0~0); 15914#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15915#L280 assume !(1 == ~t2_pc~0); 16010#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 16011#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15983#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15984#L645 assume !(0 != activate_threads_~tmp___1~0); 16110#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16111#L299 assume !(1 == ~t3_pc~0); 16127#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 16126#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16132#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16227#L653 assume !(0 != activate_threads_~tmp___2~0); 16228#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16177#L318 assume !(1 == ~t4_pc~0); 16030#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 16031#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16232#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16233#L661 assume !(0 != activate_threads_~tmp___3~0); 16077#L661-2 assume !(1 == ~M_E~0); 16078#L564-1 assume !(1 == ~T1_E~0); 16131#L569-1 assume !(1 == ~T2_E~0); 16042#L574-1 assume !(1 == ~T3_E~0); 16043#L579-1 assume !(1 == ~T4_E~0); 15986#L584-1 assume !(1 == ~E_M~0); 15987#L589-1 assume !(1 == ~E_1~0); 16005#L594-1 assume !(1 == ~E_2~0); 16084#L599-1 assume !(1 == ~E_3~0); 15873#L604-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15874#L795-1 [2021-10-28 23:18:08,576 INFO L793 eck$LassoCheckResult]: Loop: 15874#L795-1 assume !false; 16861#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 16725#L481 assume !false; 16858#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16856#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16850#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16849#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16847#L420 assume !(0 != eval_~tmp~0); 16848#L496 start_simulation_~kernel_st~0 := 2; 18143#L338-1 start_simulation_~kernel_st~0 := 3; 18142#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18141#L506-4 assume !(0 == ~T1_E~0); 18140#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18139#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18138#L521-3 assume !(0 == ~T4_E~0); 18137#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18136#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18135#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18134#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18133#L546-3 assume !(0 == ~E_4~0); 18132#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18131#L242-18 assume !(1 == ~m_pc~0); 18130#L242-20 is_master_triggered_~__retres1~0 := 0; 18128#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18076#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18075#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18074#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18073#L261-18 assume 1 == ~t1_pc~0; 18068#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18066#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18064#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18062#L637-18 assume !(0 != activate_threads_~tmp___0~0); 18060#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18057#L280-18 assume !(1 == ~t2_pc~0); 17655#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 18054#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18052#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 18050#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18048#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18047#L299-18 assume !(1 == ~t3_pc~0); 18044#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 18042#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18040#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18038#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18036#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18033#L318-18 assume !(1 == ~t4_pc~0); 18031#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 18029#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18027#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18026#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18025#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 18024#L564-3 assume !(1 == ~T1_E~0); 18023#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18021#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16308#L579-3 assume !(1 == ~T4_E~0); 16309#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17936#L589-3 assume !(1 == ~E_1~0); 17933#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17930#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17927#L604-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17924#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 17905#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 17898#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 17895#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 17891#L814 assume !(0 == start_simulation_~tmp~3); 17888#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16881#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16875#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16873#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 16870#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16868#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 16866#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 16864#L827 assume !(0 != start_simulation_~tmp___0~1); 15874#L795-1 [2021-10-28 23:18:08,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:08,576 INFO L85 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2021-10-28 23:18:08,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:08,577 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543700688] [2021-10-28 23:18:08,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:08,577 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:08,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:08,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:08,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:08,631 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543700688] [2021-10-28 23:18:08,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543700688] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:08,631 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:08,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2021-10-28 23:18:08,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560060554] [2021-10-28 23:18:08,633 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:08,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:08,634 INFO L85 PathProgramCache]: Analyzing trace with hash -796692698, now seen corresponding path program 1 times [2021-10-28 23:18:08,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:08,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288497226] [2021-10-28 23:18:08,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:08,635 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:08,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:08,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:08,686 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:08,686 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288497226] [2021-10-28 23:18:08,693 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288497226] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:08,693 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:08,693 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:08,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189081879] [2021-10-28 23:18:08,694 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:08,694 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:08,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:08,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:08,695 INFO L87 Difference]: Start difference. First operand 2312 states and 3358 transitions. cyclomatic complexity: 1050 Second operand has 3 states, 2 states have (on average 29.0) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:08,761 INFO L93 Difference]: Finished difference Result 2312 states and 3312 transitions. [2021-10-28 23:18:08,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:08,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2312 states and 3312 transitions. [2021-10-28 23:18:08,786 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2021-10-28 23:18:08,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2312 states to 2312 states and 3312 transitions. [2021-10-28 23:18:08,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2312 [2021-10-28 23:18:08,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2312 [2021-10-28 23:18:08,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2312 states and 3312 transitions. [2021-10-28 23:18:08,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:08,824 INFO L681 BuchiCegarLoop]: Abstraction has 2312 states and 3312 transitions. [2021-10-28 23:18:08,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2312 states and 3312 transitions. [2021-10-28 23:18:08,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2312 to 2312. [2021-10-28 23:18:08,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2312 states, 2312 states have (on average 1.4325259515570934) internal successors, (3312), 2311 states have internal predecessors, (3312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:08,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2312 states to 2312 states and 3312 transitions. [2021-10-28 23:18:08,903 INFO L704 BuchiCegarLoop]: Abstraction has 2312 states and 3312 transitions. [2021-10-28 23:18:08,903 INFO L587 BuchiCegarLoop]: Abstraction has 2312 states and 3312 transitions. [2021-10-28 23:18:08,903 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 23:18:08,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2312 states and 3312 transitions. [2021-10-28 23:18:08,918 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2021-10-28 23:18:08,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:08,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:08,920 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,920 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:08,920 INFO L791 eck$LassoCheckResult]: Stem: 20926#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20913#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20883#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20867#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 20602#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20603#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20817#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20786#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20787#L365-1 assume !(0 == ~M_E~0); 20819#L506-1 assume !(0 == ~T1_E~0); 20588#L511-1 assume !(0 == ~T2_E~0); 20589#L516-1 assume !(0 == ~T3_E~0); 20847#L521-1 assume !(0 == ~T4_E~0); 20876#L526-1 assume !(0 == ~E_M~0); 20825#L531-1 assume !(0 == ~E_1~0); 20773#L536-1 assume !(0 == ~E_2~0); 20774#L541-1 assume !(0 == ~E_3~0); 20768#L546-1 assume !(0 == ~E_4~0); 20769#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20816#L242 assume !(1 == ~m_pc~0); 20739#L242-2 is_master_triggered_~__retres1~0 := 0; 20740#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20780#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20855#L629 assume !(0 != activate_threads_~tmp~1); 20856#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20902#L261 assume !(1 == ~t1_pc~0); 20749#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 20547#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20548#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20887#L637 assume !(0 != activate_threads_~tmp___0~0); 20545#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20546#L280 assume !(1 == ~t2_pc~0); 20640#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 20641#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20613#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20614#L645 assume !(0 != activate_threads_~tmp___1~0); 20743#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20744#L299 assume !(1 == ~t3_pc~0); 20760#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 20759#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20765#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20858#L653 assume !(0 != activate_threads_~tmp___2~0); 20859#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20810#L318 assume !(1 == ~t4_pc~0); 20661#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 20662#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20865#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20866#L661 assume !(0 != activate_threads_~tmp___3~0); 20708#L661-2 assume !(1 == ~M_E~0); 20709#L564-1 assume !(1 == ~T1_E~0); 20764#L569-1 assume !(1 == ~T2_E~0); 20673#L574-1 assume !(1 == ~T3_E~0); 20674#L579-1 assume !(1 == ~T4_E~0); 20616#L584-1 assume !(1 == ~E_M~0); 20617#L589-1 assume !(1 == ~E_1~0); 20635#L594-1 assume !(1 == ~E_2~0); 20715#L599-1 assume !(1 == ~E_3~0); 20505#L604-1 assume !(1 == ~E_4~0); 20506#L795-1 [2021-10-28 23:18:08,921 INFO L793 eck$LassoCheckResult]: Loop: 20506#L795-1 assume !false; 22353#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 20896#L481 assume !false; 22352#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20905#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20659#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20722#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 20717#L420 assume !(0 != eval_~tmp~0); 20719#L496 start_simulation_~kernel_st~0 := 2; 22784#L338-1 start_simulation_~kernel_st~0 := 3; 22783#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22782#L506-4 assume !(0 == ~T1_E~0); 22781#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20879#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20880#L521-3 assume !(0 == ~T4_E~0); 20716#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20609#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20610#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20503#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20504#L546-3 assume !(0 == ~E_4~0); 20783#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20928#L242-18 assume !(1 == ~m_pc~0); 22773#L242-20 is_master_triggered_~__retres1~0 := 0; 20845#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20846#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20802#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20578#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20570#L261-18 assume !(1 == ~t1_pc~0); 20571#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 20573#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20872#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20870#L637-18 assume !(0 != activate_threads_~tmp___0~0); 20649#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20650#L280-18 assume !(1 == ~t2_pc~0); 22503#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 22502#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22501#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22500#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22499#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22498#L299-18 assume !(1 == ~t3_pc~0); 22496#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 22494#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22492#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22490#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22488#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22486#L318-18 assume !(1 == ~t4_pc~0); 22484#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 22481#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22479#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22477#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22475#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 22473#L564-3 assume !(1 == ~T1_E~0); 22471#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22469#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22467#L579-3 assume !(1 == ~T4_E~0); 22465#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22463#L589-3 assume !(1 == ~E_1~0); 22461#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22459#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22457#L604-3 assume !(1 == ~E_4~0); 22455#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22450#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22445#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22443#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 22441#L814 assume !(0 == start_simulation_~tmp~3); 22375#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22371#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22365#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22363#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 22360#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22358#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 22357#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22356#L827 assume !(0 != start_simulation_~tmp___0~1); 20506#L795-1 [2021-10-28 23:18:08,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:08,921 INFO L85 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2021-10-28 23:18:08,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:08,922 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694238165] [2021-10-28 23:18:08,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:08,922 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:08,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:08,949 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:08,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:09,028 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:09,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:09,029 INFO L85 PathProgramCache]: Analyzing trace with hash 1179152579, now seen corresponding path program 1 times [2021-10-28 23:18:09,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:09,029 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801827653] [2021-10-28 23:18:09,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:09,029 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:09,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:09,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:09,073 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:09,073 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801827653] [2021-10-28 23:18:09,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801827653] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:09,073 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:09,074 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:09,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552703243] [2021-10-28 23:18:09,074 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:09,074 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:09,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:09,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:09,075 INFO L87 Difference]: Start difference. First operand 2312 states and 3312 transitions. cyclomatic complexity: 1004 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:09,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:09,181 INFO L93 Difference]: Finished difference Result 4150 states and 5870 transitions. [2021-10-28 23:18:09,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:09,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4150 states and 5870 transitions. [2021-10-28 23:18:09,217 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4024 [2021-10-28 23:18:09,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4150 states to 4150 states and 5870 transitions. [2021-10-28 23:18:09,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4150 [2021-10-28 23:18:09,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4150 [2021-10-28 23:18:09,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4150 states and 5870 transitions. [2021-10-28 23:18:09,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:09,277 INFO L681 BuchiCegarLoop]: Abstraction has 4150 states and 5870 transitions. [2021-10-28 23:18:09,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4150 states and 5870 transitions. [2021-10-28 23:18:09,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4150 to 4118. [2021-10-28 23:18:09,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4118 states, 4118 states have (on average 1.4157357940747937) internal successors, (5830), 4117 states have internal predecessors, (5830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:09,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4118 states to 4118 states and 5830 transitions. [2021-10-28 23:18:09,440 INFO L704 BuchiCegarLoop]: Abstraction has 4118 states and 5830 transitions. [2021-10-28 23:18:09,440 INFO L587 BuchiCegarLoop]: Abstraction has 4118 states and 5830 transitions. [2021-10-28 23:18:09,440 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 23:18:09,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4118 states and 5830 transitions. [2021-10-28 23:18:09,464 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3996 [2021-10-28 23:18:09,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:09,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:09,466 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:09,466 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:09,466 INFO L791 eck$LassoCheckResult]: Stem: 27440#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27416#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27369#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27345#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 27070#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27071#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27288#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27257#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27258#L365-1 assume !(0 == ~M_E~0); 27291#L506-1 assume !(0 == ~T1_E~0); 27056#L511-1 assume !(0 == ~T2_E~0); 27057#L516-1 assume !(0 == ~T3_E~0); 27321#L521-1 assume !(0 == ~T4_E~0); 27360#L526-1 assume !(0 == ~E_M~0); 27298#L531-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27240#L536-1 assume !(0 == ~E_2~0); 27241#L541-1 assume !(0 == ~E_3~0); 27454#L546-1 assume !(0 == ~E_4~0); 27453#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27452#L242 assume !(1 == ~m_pc~0); 27204#L242-2 is_master_triggered_~__retres1~0 := 0; 27205#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27249#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 27450#L629 assume !(0 != activate_threads_~tmp~1); 27449#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27447#L261 assume !(1 == ~t1_pc~0); 27448#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 27016#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27017#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27373#L637 assume !(0 != activate_threads_~tmp___0~0); 27374#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27254#L280 assume !(1 == ~t2_pc~0); 27255#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 27238#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27239#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27398#L645 assume !(0 != activate_threads_~tmp___1~0); 27399#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27475#L299 assume !(1 == ~t3_pc~0); 27224#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 27223#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27341#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27342#L653 assume !(0 != activate_threads_~tmp___2~0); 27383#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27283#L318 assume !(1 == ~t4_pc~0); 27127#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 27128#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27343#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27344#L661 assume !(0 != activate_threads_~tmp___3~0); 27472#L661-2 assume !(1 == ~M_E~0); 27228#L564-1 assume !(1 == ~T1_E~0); 27229#L569-1 assume !(1 == ~T2_E~0); 27290#L574-1 assume !(1 == ~T3_E~0); 27152#L579-1 assume !(1 == ~T4_E~0); 27082#L584-1 assume !(1 == ~E_M~0); 27083#L589-1 assume 1 == ~E_1~0;~E_1~0 := 2; 27102#L594-1 assume !(1 == ~E_2~0); 27183#L599-1 assume !(1 == ~E_3~0); 26973#L604-1 assume !(1 == ~E_4~0); 26974#L795-1 [2021-10-28 23:18:09,467 INFO L793 eck$LassoCheckResult]: Loop: 26974#L795-1 assume !false; 28959#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 28956#L481 assume !false; 28954#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28952#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28946#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28944#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 28942#L420 assume !(0 != eval_~tmp~0); 28943#L496 start_simulation_~kernel_st~0 := 2; 29204#L338-1 start_simulation_~kernel_st~0 := 3; 29202#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29200#L506-4 assume !(0 == ~T1_E~0); 29198#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29196#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29194#L521-3 assume !(0 == ~T4_E~0); 29192#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29189#L531-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29187#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29185#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29183#L546-3 assume !(0 == ~E_4~0); 29181#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29179#L242-18 assume !(1 == ~m_pc~0); 29177#L242-20 is_master_triggered_~__retres1~0 := 0; 29175#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29173#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 29171#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 29169#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29166#L261-18 assume 1 == ~t1_pc~0; 29163#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 29161#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29159#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 29157#L637-18 assume !(0 != activate_threads_~tmp___0~0); 29155#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29153#L280-18 assume !(1 == ~t2_pc~0); 27726#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 29151#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29149#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 29147#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29145#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29143#L299-18 assume !(1 == ~t3_pc~0); 29139#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 29137#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29135#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29133#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29131#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29129#L318-18 assume !(1 == ~t4_pc~0); 29127#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 29125#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29123#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 29121#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29119#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 29117#L564-3 assume !(1 == ~T1_E~0); 29115#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29113#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29111#L579-3 assume !(1 == ~T4_E~0); 29109#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29108#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29106#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29105#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29103#L604-3 assume !(1 == ~E_4~0); 29101#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29036#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29031#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29029#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 29027#L814 assume !(0 == start_simulation_~tmp~3); 29025#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29024#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29019#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29018#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 29017#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29016#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 29015#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 29013#L827 assume !(0 != start_simulation_~tmp___0~1); 26974#L795-1 [2021-10-28 23:18:09,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:09,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1909498888, now seen corresponding path program 1 times [2021-10-28 23:18:09,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:09,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979557848] [2021-10-28 23:18:09,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:09,468 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:09,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:09,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:09,510 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:09,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979557848] [2021-10-28 23:18:09,511 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979557848] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:09,511 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:09,511 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:09,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366344343] [2021-10-28 23:18:09,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:09,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:09,514 INFO L85 PathProgramCache]: Analyzing trace with hash -219462046, now seen corresponding path program 1 times [2021-10-28 23:18:09,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:09,514 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946874333] [2021-10-28 23:18:09,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:09,515 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:09,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:09,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:09,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:09,584 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946874333] [2021-10-28 23:18:09,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946874333] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:09,584 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:09,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:18:09,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730779544] [2021-10-28 23:18:09,585 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:09,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:09,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:18:09,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:18:09,587 INFO L87 Difference]: Start difference. First operand 4118 states and 5830 transitions. cyclomatic complexity: 1716 Second operand has 4 states, 4 states have (on average 14.5) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:09,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:09,770 INFO L93 Difference]: Finished difference Result 5892 states and 8313 transitions. [2021-10-28 23:18:09,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:18:09,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5892 states and 8313 transitions. [2021-10-28 23:18:09,812 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5426 [2021-10-28 23:18:09,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5892 states to 5892 states and 8313 transitions. [2021-10-28 23:18:09,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5892 [2021-10-28 23:18:09,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5892 [2021-10-28 23:18:09,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5892 states and 8313 transitions. [2021-10-28 23:18:09,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:09,890 INFO L681 BuchiCegarLoop]: Abstraction has 5892 states and 8313 transitions. [2021-10-28 23:18:09,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5892 states and 8313 transitions. [2021-10-28 23:18:10,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5892 to 5579. [2021-10-28 23:18:10,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5579 states, 5579 states have (on average 1.414590428392185) internal successors, (7892), 5578 states have internal predecessors, (7892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:10,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5579 states to 5579 states and 7892 transitions. [2021-10-28 23:18:10,191 INFO L704 BuchiCegarLoop]: Abstraction has 5579 states and 7892 transitions. [2021-10-28 23:18:10,191 INFO L587 BuchiCegarLoop]: Abstraction has 5579 states and 7892 transitions. [2021-10-28 23:18:10,191 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 23:18:10,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5579 states and 7892 transitions. [2021-10-28 23:18:10,235 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5426 [2021-10-28 23:18:10,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:10,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:10,237 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:10,237 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:10,238 INFO L791 eck$LassoCheckResult]: Stem: 37478#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 37450#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37397#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37378#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 37091#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37092#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37318#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37283#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37284#L365-1 assume !(0 == ~M_E~0); 37322#L506-1 assume !(0 == ~T1_E~0); 37077#L511-1 assume !(0 == ~T2_E~0); 37078#L516-1 assume !(0 == ~T3_E~0); 37356#L521-1 assume !(0 == ~T4_E~0); 37389#L526-1 assume !(0 == ~E_M~0); 37330#L531-1 assume !(0 == ~E_1~0); 37268#L536-1 assume !(0 == ~E_2~0); 37269#L541-1 assume !(0 == ~E_3~0); 37262#L546-1 assume !(0 == ~E_4~0); 37263#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37316#L242 assume !(1 == ~m_pc~0); 37230#L242-2 is_master_triggered_~__retres1~0 := 0; 37231#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37275#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 37363#L629 assume !(0 != activate_threads_~tmp~1); 37364#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37427#L261 assume !(1 == ~t1_pc~0); 37240#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 37372#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37454#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37455#L637 assume !(0 != activate_threads_~tmp___0~0); 37034#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37035#L280 assume !(1 == ~t2_pc~0); 37131#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 37132#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37103#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37104#L645 assume !(0 != activate_threads_~tmp___1~0); 37235#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37236#L299 assume !(1 == ~t3_pc~0); 37251#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 37250#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37373#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37374#L653 assume !(0 != activate_threads_~tmp___2~0); 37416#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37417#L318 assume !(1 == ~t4_pc~0); 37152#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 37153#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37375#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 37376#L661 assume !(0 != activate_threads_~tmp___3~0); 37199#L661-2 assume !(1 == ~M_E~0); 37200#L564-1 assume !(1 == ~T1_E~0); 37320#L569-1 assume !(1 == ~T2_E~0); 37321#L574-1 assume !(1 == ~T3_E~0); 37176#L579-1 assume !(1 == ~T4_E~0); 37177#L584-1 assume 1 == ~E_M~0;~E_M~0 := 2; 39548#L589-1 assume !(1 == ~E_1~0); 37126#L594-1 assume !(1 == ~E_2~0); 37206#L599-1 assume !(1 == ~E_3~0); 36994#L604-1 assume !(1 == ~E_4~0); 36995#L795-1 [2021-10-28 23:18:10,238 INFO L793 eck$LassoCheckResult]: Loop: 36995#L795-1 assume !false; 40605#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 40604#L481 assume !false; 41252#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41251#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41246#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41245#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 41243#L420 assume !(0 != eval_~tmp~0); 41244#L496 start_simulation_~kernel_st~0 := 2; 42479#L338-1 start_simulation_~kernel_st~0 := 3; 42478#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42477#L506-4 assume !(0 == ~T1_E~0); 42475#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42473#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42471#L521-3 assume !(0 == ~T4_E~0); 42469#L526-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42467#L531-3 assume !(0 == ~E_1~0); 42465#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42463#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42461#L546-3 assume !(0 == ~E_4~0); 42459#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42457#L242-18 assume !(1 == ~m_pc~0); 42455#L242-20 is_master_triggered_~__retres1~0 := 0; 42453#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42451#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 42449#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 42447#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42445#L261-18 assume !(1 == ~t1_pc~0); 42442#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 42440#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42437#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42388#L637-18 assume !(0 != activate_threads_~tmp___0~0); 42385#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42374#L280-18 assume !(1 == ~t2_pc~0); 42372#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 42370#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42368#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42366#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42364#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42361#L299-18 assume !(1 == ~t3_pc~0); 42358#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 42356#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42354#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42352#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42350#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42348#L318-18 assume !(1 == ~t4_pc~0); 42346#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 42344#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42342#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42339#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 42337#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 42335#L564-3 assume !(1 == ~T1_E~0); 42333#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42331#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42329#L579-3 assume !(1 == ~T4_E~0); 42328#L584-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41412#L589-3 assume !(1 == ~E_1~0); 41409#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42327#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42326#L604-3 assume !(1 == ~E_4~0); 42325#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 40646#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 40643#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 40634#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 40635#L814 assume !(0 == start_simulation_~tmp~3); 40628#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 40629#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41269#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41268#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 41267#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41266#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 41264#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 40611#L827 assume !(0 != start_simulation_~tmp___0~1); 36995#L795-1 [2021-10-28 23:18:10,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:10,239 INFO L85 PathProgramCache]: Analyzing trace with hash -141676414, now seen corresponding path program 1 times [2021-10-28 23:18:10,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:10,239 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585359411] [2021-10-28 23:18:10,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:10,240 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:10,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:10,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:10,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:10,279 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585359411] [2021-10-28 23:18:10,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585359411] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:10,280 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:10,280 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:10,280 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683609447] [2021-10-28 23:18:10,282 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:10,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:10,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1854897467, now seen corresponding path program 1 times [2021-10-28 23:18:10,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:10,283 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575821761] [2021-10-28 23:18:10,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:10,283 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:10,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:10,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:10,336 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:10,336 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575821761] [2021-10-28 23:18:10,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575821761] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:10,337 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:10,337 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:18:10,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651093187] [2021-10-28 23:18:10,337 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:10,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:10,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:10,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:10,339 INFO L87 Difference]: Start difference. First operand 5579 states and 7892 transitions. cyclomatic complexity: 2321 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:10,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:10,399 INFO L93 Difference]: Finished difference Result 5578 states and 7796 transitions. [2021-10-28 23:18:10,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:10,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5578 states and 7796 transitions. [2021-10-28 23:18:10,439 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5426 [2021-10-28 23:18:10,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5578 states to 5578 states and 7796 transitions. [2021-10-28 23:18:10,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5578 [2021-10-28 23:18:10,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5578 [2021-10-28 23:18:10,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5578 states and 7796 transitions. [2021-10-28 23:18:10,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:10,509 INFO L681 BuchiCegarLoop]: Abstraction has 5578 states and 7796 transitions. [2021-10-28 23:18:10,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5578 states and 7796 transitions. [2021-10-28 23:18:10,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5578 to 4105. [2021-10-28 23:18:10,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4105 states, 4105 states have (on average 1.3926918392204628) internal successors, (5717), 4104 states have internal predecessors, (5717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:10,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4105 states to 4105 states and 5717 transitions. [2021-10-28 23:18:10,735 INFO L704 BuchiCegarLoop]: Abstraction has 4105 states and 5717 transitions. [2021-10-28 23:18:10,735 INFO L587 BuchiCegarLoop]: Abstraction has 4105 states and 5717 transitions. [2021-10-28 23:18:10,736 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 23:18:10,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4105 states and 5717 transitions. [2021-10-28 23:18:10,756 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3996 [2021-10-28 23:18:10,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:10,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:10,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:10,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:10,759 INFO L791 eck$LassoCheckResult]: Stem: 48640#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 48616#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 48567#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48547#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 48257#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48258#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48483#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48451#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48452#L365-1 assume !(0 == ~M_E~0); 48487#L506-1 assume !(0 == ~T1_E~0); 48243#L511-1 assume !(0 == ~T2_E~0); 48244#L516-1 assume !(0 == ~T3_E~0); 48525#L521-1 assume !(0 == ~T4_E~0); 48560#L526-1 assume !(0 == ~E_M~0); 48494#L531-1 assume !(0 == ~E_1~0); 48434#L536-1 assume !(0 == ~E_2~0); 48435#L541-1 assume !(0 == ~E_3~0); 48427#L546-1 assume !(0 == ~E_4~0); 48428#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48482#L242 assume !(1 == ~m_pc~0); 48395#L242-2 is_master_triggered_~__retres1~0 := 0; 48396#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48443#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48533#L629 assume !(0 != activate_threads_~tmp~1); 48534#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48592#L261 assume !(1 == ~t1_pc~0); 48405#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 48200#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48201#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48572#L637 assume !(0 != activate_threads_~tmp___0~0); 48573#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48448#L280 assume !(1 == ~t2_pc~0); 48449#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 48432#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48433#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 48593#L645 assume !(0 != activate_threads_~tmp___1~0); 48594#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48519#L299 assume !(1 == ~t3_pc~0); 48520#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 48423#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48424#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 48536#L653 assume !(0 != activate_threads_~tmp___2~0); 48537#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48476#L318 assume !(1 == ~t4_pc~0); 48477#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 48612#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48613#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 48579#L661 assume !(0 != activate_threads_~tmp___3~0); 48580#L661-2 assume !(1 == ~M_E~0); 48421#L564-1 assume !(1 == ~T1_E~0); 48422#L569-1 assume !(1 == ~T2_E~0); 48332#L574-1 assume !(1 == ~T3_E~0); 48333#L579-1 assume !(1 == ~T4_E~0); 48271#L584-1 assume !(1 == ~E_M~0); 48272#L589-1 assume !(1 == ~E_1~0); 48294#L594-1 assume !(1 == ~E_2~0); 48372#L599-1 assume !(1 == ~E_3~0); 48158#L604-1 assume !(1 == ~E_4~0); 48159#L795-1 [2021-10-28 23:18:10,759 INFO L793 eck$LassoCheckResult]: Loop: 48159#L795-1 assume !false; 51178#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 51175#L481 assume !false; 51173#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51171#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51165#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51163#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 51160#L420 assume !(0 != eval_~tmp~0); 51161#L496 start_simulation_~kernel_st~0 := 2; 52214#L338-1 start_simulation_~kernel_st~0 := 3; 52188#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52187#L506-4 assume !(0 == ~T1_E~0); 52185#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52180#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52179#L521-3 assume !(0 == ~T4_E~0); 48373#L526-3 assume !(0 == ~E_M~0); 48264#L531-3 assume !(0 == ~E_1~0); 48265#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48156#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48157#L546-3 assume !(0 == ~E_4~0); 48446#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48630#L242-18 assume !(1 == ~m_pc~0); 48352#L242-20 is_master_triggered_~__retres1~0 := 0; 48353#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48518#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 48522#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 52129#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52127#L261-18 assume 1 == ~t1_pc~0; 52128#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 51758#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51759#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51753#L637-18 assume !(0 != activate_threads_~tmp___0~0); 51754#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51748#L280-18 assume !(1 == ~t2_pc~0); 51747#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 51746#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51745#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 51744#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 51743#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51742#L299-18 assume !(1 == ~t3_pc~0); 51740#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 51739#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51738#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51737#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 51736#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51735#L318-18 assume !(1 == ~t4_pc~0); 51734#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 51733#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51732#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 51731#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 51730#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 51729#L564-3 assume !(1 == ~T1_E~0); 51728#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51727#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51726#L579-3 assume !(1 == ~T4_E~0); 51725#L584-3 assume !(1 == ~E_M~0); 51724#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51721#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51719#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51717#L604-3 assume !(1 == ~E_4~0); 51714#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51669#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51664#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51662#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 51660#L814 assume !(0 == start_simulation_~tmp~3); 51658#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51654#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51630#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48558#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 48535#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 48514#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 48171#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 48172#L827 assume !(0 != start_simulation_~tmp___0~1); 48159#L795-1 [2021-10-28 23:18:10,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:10,760 INFO L85 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2021-10-28 23:18:10,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:10,761 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799709635] [2021-10-28 23:18:10,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:10,761 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:10,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:10,774 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:10,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:10,826 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:10,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:10,829 INFO L85 PathProgramCache]: Analyzing trace with hash -518960416, now seen corresponding path program 1 times [2021-10-28 23:18:10,829 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:10,830 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848028482] [2021-10-28 23:18:10,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:10,831 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:10,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:10,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:10,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:10,872 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848028482] [2021-10-28 23:18:10,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848028482] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:10,872 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:10,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:18:10,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917036632] [2021-10-28 23:18:10,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:10,873 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:10,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:18:10,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:18:10,875 INFO L87 Difference]: Start difference. First operand 4105 states and 5717 transitions. cyclomatic complexity: 1616 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:11,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:11,019 INFO L93 Difference]: Finished difference Result 7249 states and 10027 transitions. [2021-10-28 23:18:11,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 23:18:11,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7249 states and 10027 transitions. [2021-10-28 23:18:11,126 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7120 [2021-10-28 23:18:11,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7249 states to 7249 states and 10027 transitions. [2021-10-28 23:18:11,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7249 [2021-10-28 23:18:11,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7249 [2021-10-28 23:18:11,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7249 states and 10027 transitions. [2021-10-28 23:18:11,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:11,191 INFO L681 BuchiCegarLoop]: Abstraction has 7249 states and 10027 transitions. [2021-10-28 23:18:11,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7249 states and 10027 transitions. [2021-10-28 23:18:11,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7249 to 4153. [2021-10-28 23:18:11,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4153 states, 4153 states have (on average 1.3881531423067661) internal successors, (5765), 4152 states have internal predecessors, (5765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:11,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4153 states to 4153 states and 5765 transitions. [2021-10-28 23:18:11,335 INFO L704 BuchiCegarLoop]: Abstraction has 4153 states and 5765 transitions. [2021-10-28 23:18:11,335 INFO L587 BuchiCegarLoop]: Abstraction has 4153 states and 5765 transitions. [2021-10-28 23:18:11,335 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 23:18:11,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4153 states and 5765 transitions. [2021-10-28 23:18:11,362 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4044 [2021-10-28 23:18:11,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:11,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:11,364 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:11,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:11,365 INFO L791 eck$LassoCheckResult]: Stem: 60021#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 59995#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 59945#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 59922#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 59628#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59629#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59863#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59831#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59832#L365-1 assume !(0 == ~M_E~0); 59865#L506-1 assume !(0 == ~T1_E~0); 59614#L511-1 assume !(0 == ~T2_E~0); 59615#L516-1 assume !(0 == ~T3_E~0); 59899#L521-1 assume !(0 == ~T4_E~0); 59933#L526-1 assume !(0 == ~E_M~0); 59872#L531-1 assume !(0 == ~E_1~0); 59810#L536-1 assume !(0 == ~E_2~0); 59811#L541-1 assume !(0 == ~E_3~0); 59803#L546-1 assume !(0 == ~E_4~0); 59804#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59862#L242 assume !(1 == ~m_pc~0); 59769#L242-2 is_master_triggered_~__retres1~0 := 0; 59770#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59821#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59908#L629 assume !(0 != activate_threads_~tmp~1); 59909#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59970#L261 assume !(1 == ~t1_pc~0); 59779#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 59570#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59571#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 59950#L637 assume !(0 != activate_threads_~tmp___0~0); 59951#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59827#L280 assume !(1 == ~t2_pc~0); 59828#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 59808#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59809#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 59971#L645 assume !(0 != activate_threads_~tmp___1~0); 59972#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60038#L299 assume !(1 == ~t3_pc~0); 59791#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 59790#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59919#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 59911#L653 assume !(0 != activate_threads_~tmp___2~0); 59912#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60036#L318 assume !(1 == ~t4_pc~0); 60035#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 59990#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59991#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 59958#L661 assume !(0 != activate_threads_~tmp___3~0); 59737#L661-2 assume !(1 == ~M_E~0); 59738#L564-1 assume !(1 == ~T1_E~0); 60033#L569-1 assume !(1 == ~T2_E~0); 60032#L574-1 assume !(1 == ~T3_E~0); 60031#L579-1 assume !(1 == ~T4_E~0); 60030#L584-1 assume !(1 == ~E_M~0); 60029#L589-1 assume !(1 == ~E_1~0); 59665#L594-1 assume !(1 == ~E_2~0); 59744#L599-1 assume !(1 == ~E_3~0); 59528#L604-1 assume !(1 == ~E_4~0); 59529#L795-1 [2021-10-28 23:18:11,365 INFO L793 eck$LassoCheckResult]: Loop: 59529#L795-1 assume !false; 63509#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 62961#L481 assume !false; 63507#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 63502#L378 assume !(0 == ~m_st~0); 63498#L382 assume !(0 == ~t1_st~0); 63499#L386 assume !(0 == ~t2_st~0); 63500#L390 assume !(0 == ~t3_st~0); 63501#L394 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 63503#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 60159#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 60160#L420 assume !(0 != eval_~tmp~0); 63494#L496 start_simulation_~kernel_st~0 := 2; 59650#L338-1 start_simulation_~kernel_st~0 := 3; 59651#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 59993#L506-4 assume !(0 == ~T1_E~0); 59994#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59938#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59939#L521-3 assume !(0 == ~T4_E~0); 59745#L526-3 assume !(0 == ~E_M~0); 59746#L531-3 assume !(0 == ~E_1~0); 60007#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60008#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59824#L546-3 assume !(0 == ~E_4~0); 59825#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60013#L242-18 assume !(1 == ~m_pc~0); 60014#L242-20 is_master_triggered_~__retres1~0 := 0; 59893#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59894#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59847#L629-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 59848#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59594#L261-18 assume !(1 == ~t1_pc~0); 59595#L261-20 is_transmit1_triggered_~__retres1~1 := 0; 59997#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59998#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 59927#L637-18 assume !(0 != activate_threads_~tmp___0~0); 59679#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59680#L280-18 assume !(1 == ~t2_pc~0); 63382#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 63497#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 63493#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 63492#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 63491#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 63490#L299-18 assume !(1 == ~t3_pc~0); 63488#L299-20 is_transmit3_triggered_~__retres1~3 := 0; 63486#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 63485#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 63479#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 63478#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 63477#L318-18 assume !(1 == ~t4_pc~0); 63476#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 63474#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 63475#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 63470#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 63471#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 63465#L564-3 assume !(1 == ~T1_E~0); 63466#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63459#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63460#L579-3 assume !(1 == ~T4_E~0); 63544#L584-3 assume !(1 == ~E_M~0); 63215#L589-3 assume !(1 == ~E_1~0); 59558#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59731#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59763#L604-3 assume !(1 == ~E_4~0); 59764#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 60015#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 63526#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 63525#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 63522#L814 assume !(0 == start_simulation_~tmp~3); 63521#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 63520#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 63515#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 63514#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 63513#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 63512#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 63511#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 63510#L827 assume !(0 != start_simulation_~tmp___0~1); 59529#L795-1 [2021-10-28 23:18:11,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:11,370 INFO L85 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2021-10-28 23:18:11,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:11,370 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306778294] [2021-10-28 23:18:11,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:11,371 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:11,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:11,389 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:11,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:11,433 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:11,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:11,434 INFO L85 PathProgramCache]: Analyzing trace with hash -1960891443, now seen corresponding path program 1 times [2021-10-28 23:18:11,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:11,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998451476] [2021-10-28 23:18:11,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:11,435 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:11,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:11,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:11,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:11,546 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998451476] [2021-10-28 23:18:11,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998451476] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:11,546 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:11,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:18:11,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403336624] [2021-10-28 23:18:11,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:11,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:11,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:18:11,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:18:11,549 INFO L87 Difference]: Start difference. First operand 4153 states and 5765 transitions. cyclomatic complexity: 1616 Second operand has 5 states, 5 states have (on average 15.4) internal successors, (77), 5 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:11,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:11,725 INFO L93 Difference]: Finished difference Result 4857 states and 6708 transitions. [2021-10-28 23:18:11,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 23:18:11,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4857 states and 6708 transitions. [2021-10-28 23:18:11,757 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4748 [2021-10-28 23:18:11,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4857 states to 4857 states and 6708 transitions. [2021-10-28 23:18:11,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4857 [2021-10-28 23:18:11,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4857 [2021-10-28 23:18:11,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4857 states and 6708 transitions. [2021-10-28 23:18:11,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:11,800 INFO L681 BuchiCegarLoop]: Abstraction has 4857 states and 6708 transitions. [2021-10-28 23:18:11,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4857 states and 6708 transitions. [2021-10-28 23:18:11,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4857 to 4165. [2021-10-28 23:18:11,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4165 states, 4165 states have (on average 1.3695078031212484) internal successors, (5704), 4164 states have internal predecessors, (5704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:12,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4165 states to 4165 states and 5704 transitions. [2021-10-28 23:18:12,021 INFO L704 BuchiCegarLoop]: Abstraction has 4165 states and 5704 transitions. [2021-10-28 23:18:12,021 INFO L587 BuchiCegarLoop]: Abstraction has 4165 states and 5704 transitions. [2021-10-28 23:18:12,022 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 23:18:12,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4165 states and 5704 transitions. [2021-10-28 23:18:12,036 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4056 [2021-10-28 23:18:12,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:12,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:12,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:12,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:12,039 INFO L791 eck$LassoCheckResult]: Stem: 69078#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 69038#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68984#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 68956#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 68649#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68650#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68895#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68860#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68861#L365-1 assume !(0 == ~M_E~0); 68898#L506-1 assume !(0 == ~T1_E~0); 68635#L511-1 assume !(0 == ~T2_E~0); 68636#L516-1 assume !(0 == ~T3_E~0); 68934#L521-1 assume !(0 == ~T4_E~0); 68972#L526-1 assume !(0 == ~E_M~0); 68905#L531-1 assume !(0 == ~E_1~0); 68839#L536-1 assume !(0 == ~E_2~0); 68840#L541-1 assume !(0 == ~E_3~0); 68831#L546-1 assume !(0 == ~E_4~0); 68832#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68894#L242 assume !(1 == ~m_pc~0); 68799#L242-2 is_master_triggered_~__retres1~0 := 0; 68800#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68850#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 68943#L629 assume !(0 != activate_threads_~tmp~1); 68944#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69008#L261 assume !(1 == ~t1_pc~0); 68809#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 68953#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69111#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 68989#L637 assume !(0 != activate_threads_~tmp___0~0); 68990#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69107#L280 assume !(1 == ~t2_pc~0); 69106#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 68838#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68662#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 68663#L645 assume !(0 != activate_threads_~tmp___1~0); 68804#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 68805#L299 assume !(1 == ~t3_pc~0); 68928#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 68827#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 68828#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 68945#L653 assume !(0 != activate_threads_~tmp___2~0); 68946#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69101#L318 assume !(1 == ~t4_pc~0); 69100#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 69099#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69095#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 69094#L661 assume !(0 != activate_threads_~tmp___3~0); 69093#L661-2 assume !(1 == ~M_E~0); 69092#L564-1 assume !(1 == ~T1_E~0); 69091#L569-1 assume !(1 == ~T2_E~0); 69090#L574-1 assume !(1 == ~T3_E~0); 69089#L579-1 assume !(1 == ~T4_E~0); 69088#L584-1 assume !(1 == ~E_M~0); 69087#L589-1 assume !(1 == ~E_1~0); 68687#L594-1 assume !(1 == ~E_2~0); 68773#L599-1 assume !(1 == ~E_3~0); 68552#L604-1 assume !(1 == ~E_4~0); 68553#L795-1 [2021-10-28 23:18:12,039 INFO L793 eck$LassoCheckResult]: Loop: 68553#L795-1 assume !false; 71001#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 70998#L481 assume !false; 70997#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 70996#L378 assume !(0 == ~m_st~0); 70991#L382 assume !(0 == ~t1_st~0); 70992#L386 assume !(0 == ~t2_st~0); 70995#L390 assume !(0 == ~t3_st~0); 70993#L394 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 70994#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 70953#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 70954#L420 assume !(0 != eval_~tmp~0); 71240#L496 start_simulation_~kernel_st~0 := 2; 71239#L338-1 start_simulation_~kernel_st~0 := 3; 71237#L506-2 assume 0 == ~M_E~0;~M_E~0 := 1; 71235#L506-4 assume !(0 == ~T1_E~0); 71233#L511-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71231#L516-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71229#L521-3 assume !(0 == ~T4_E~0); 71227#L526-3 assume !(0 == ~E_M~0); 71225#L531-3 assume !(0 == ~E_1~0); 71223#L536-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71221#L541-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71219#L546-3 assume !(0 == ~E_4~0); 71217#L551-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71215#L242-18 assume !(1 == ~m_pc~0); 71213#L242-20 is_master_triggered_~__retres1~0 := 0; 71211#L253-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71209#L254-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 71207#L629-18 assume !(0 != activate_threads_~tmp~1); 71204#L629-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71201#L261-18 assume 1 == ~t1_pc~0; 71200#L262-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 71189#L272-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71185#L273-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 71181#L637-18 assume !(0 != activate_threads_~tmp___0~0); 71176#L637-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 71173#L280-18 assume !(1 == ~t2_pc~0); 70574#L280-20 is_transmit2_triggered_~__retres1~2 := 0; 71167#L291-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 71163#L292-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 71159#L645-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 71156#L645-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 71151#L299-18 assume 1 == ~t3_pc~0; 71147#L300-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 71141#L310-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 71137#L311-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 71133#L653-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 71128#L653-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 71124#L318-18 assume !(1 == ~t4_pc~0); 71120#L318-20 is_transmit4_triggered_~__retres1~4 := 0; 71116#L329-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71112#L330-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 71108#L661-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 71104#L661-20 assume 1 == ~M_E~0;~M_E~0 := 2; 71100#L564-3 assume !(1 == ~T1_E~0); 71096#L569-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71092#L574-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71080#L579-3 assume !(1 == ~T4_E~0); 71079#L584-3 assume !(1 == ~E_M~0); 71077#L589-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71075#L594-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71074#L599-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71072#L604-3 assume !(1 == ~E_4~0); 71070#L609-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 71037#L378-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 71030#L405-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 71027#L406-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 71023#L814 assume !(0 == start_simulation_~tmp~3); 71020#L814-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 71018#L378-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 71012#L405-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 71010#L406-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 71008#L769 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 71006#L776 stop_simulation_#res := stop_simulation_~__retres2~0; 71004#L777 start_simulation_#t~ret21 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 71003#L827 assume !(0 != start_simulation_~tmp___0~1); 68553#L795-1 [2021-10-28 23:18:12,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:12,040 INFO L85 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2021-10-28 23:18:12,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:12,040 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239267420] [2021-10-28 23:18:12,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:12,041 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:12,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,055 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:12,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,084 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:12,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:12,085 INFO L85 PathProgramCache]: Analyzing trace with hash 208306251, now seen corresponding path program 1 times [2021-10-28 23:18:12,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:12,086 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458049970] [2021-10-28 23:18:12,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:12,086 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:12,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:12,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:12,121 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:12,121 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458049970] [2021-10-28 23:18:12,122 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458049970] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:12,123 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:12,123 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:12,123 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428372202] [2021-10-28 23:18:12,123 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:18:12,124 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:12,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:12,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:12,125 INFO L87 Difference]: Start difference. First operand 4165 states and 5704 transitions. cyclomatic complexity: 1543 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:12,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:12,174 INFO L93 Difference]: Finished difference Result 5831 states and 7905 transitions. [2021-10-28 23:18:12,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:12,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5831 states and 7905 transitions. [2021-10-28 23:18:12,206 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5643 [2021-10-28 23:18:12,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5831 states to 5831 states and 7905 transitions. [2021-10-28 23:18:12,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5831 [2021-10-28 23:18:12,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5831 [2021-10-28 23:18:12,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5831 states and 7905 transitions. [2021-10-28 23:18:12,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:12,250 INFO L681 BuchiCegarLoop]: Abstraction has 5831 states and 7905 transitions. [2021-10-28 23:18:12,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5831 states and 7905 transitions. [2021-10-28 23:18:12,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5831 to 5831. [2021-10-28 23:18:12,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5831 states, 5831 states have (on average 1.3556851311953353) internal successors, (7905), 5830 states have internal predecessors, (7905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:12,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5831 states to 5831 states and 7905 transitions. [2021-10-28 23:18:12,376 INFO L704 BuchiCegarLoop]: Abstraction has 5831 states and 7905 transitions. [2021-10-28 23:18:12,376 INFO L587 BuchiCegarLoop]: Abstraction has 5831 states and 7905 transitions. [2021-10-28 23:18:12,376 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 23:18:12,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5831 states and 7905 transitions. [2021-10-28 23:18:12,398 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5643 [2021-10-28 23:18:12,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:12,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:12,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:12,400 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:12,400 INFO L791 eck$LassoCheckResult]: Stem: 79022#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 78997#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 78953#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78932#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 78654#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78655#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78877#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78845#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78846#L365-1 assume !(0 == ~M_E~0); 78879#L506-1 assume !(0 == ~T1_E~0); 78639#L511-1 assume !(0 == ~T2_E~0); 78640#L516-1 assume !(0 == ~T3_E~0); 78913#L521-1 assume !(0 == ~T4_E~0); 78941#L526-1 assume !(0 == ~E_M~0); 78886#L531-1 assume !(0 == ~E_1~0); 78827#L536-1 assume !(0 == ~E_2~0); 78828#L541-1 assume !(0 == ~E_3~0); 78823#L546-1 assume !(0 == ~E_4~0); 78824#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78875#L242 assume !(1 == ~m_pc~0); 78793#L242-2 is_master_triggered_~__retres1~0 := 0; 78794#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78836#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78920#L629 assume !(0 != activate_threads_~tmp~1); 78921#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78980#L261 assume !(1 == ~t1_pc~0); 78803#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 78928#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 79111#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 79109#L637 assume !(0 != activate_threads_~tmp___0~0); 78595#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78596#L280 assume !(1 == ~t2_pc~0); 78694#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 78695#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78666#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 78667#L645 assume !(0 != activate_threads_~tmp___1~0); 78798#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78799#L299 assume !(1 == ~t3_pc~0); 78814#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 78813#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78820#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 78922#L653 assume !(0 != activate_threads_~tmp___2~0); 78923#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78872#L318 assume !(1 == ~t4_pc~0); 78715#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 78716#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78996#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 79031#L661 assume !(0 != activate_threads_~tmp___3~0); 79030#L661-2 assume !(1 == ~M_E~0); 79029#L564-1 assume !(1 == ~T1_E~0); 79028#L569-1 assume !(1 == ~T2_E~0); 79027#L574-1 assume !(1 == ~T3_E~0); 79026#L579-1 assume !(1 == ~T4_E~0); 79025#L584-1 assume !(1 == ~E_M~0); 79024#L589-1 assume !(1 == ~E_1~0); 78689#L594-1 assume !(1 == ~E_2~0); 78769#L599-1 assume !(1 == ~E_3~0); 78555#L604-1 assume !(1 == ~E_4~0); 78556#L795-1 assume !false; 81084#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 80940#L481 [2021-10-28 23:18:12,400 INFO L793 eck$LassoCheckResult]: Loop: 80940#L481 assume !false; 81080#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 81075#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 81072#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 81067#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 81008#L420 assume 0 != eval_~tmp~0; 80109#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 79020#L428 assume !(0 != eval_~tmp_ndt_1~0); 79021#L425 assume !(0 == ~t1_st~0); 80955#L439 assume !(0 == ~t2_st~0); 80948#L453 assume !(0 == ~t3_st~0); 80942#L467 assume !(0 == ~t4_st~0); 80940#L481 [2021-10-28 23:18:12,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:12,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2021-10-28 23:18:12,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:12,402 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290524966] [2021-10-28 23:18:12,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:12,402 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:12,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,414 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:12,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,449 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:12,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:12,450 INFO L85 PathProgramCache]: Analyzing trace with hash 1327245363, now seen corresponding path program 1 times [2021-10-28 23:18:12,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:12,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277462924] [2021-10-28 23:18:12,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:12,451 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:12,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,455 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:12,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:12,462 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:12,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:12,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1604310376, now seen corresponding path program 1 times [2021-10-28 23:18:12,463 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:12,463 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926167047] [2021-10-28 23:18:12,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:12,464 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:12,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:12,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:12,511 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:12,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926167047] [2021-10-28 23:18:12,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926167047] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:12,512 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:12,512 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:12,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380767323] [2021-10-28 23:18:12,662 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:12,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:12,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:12,663 INFO L87 Difference]: Start difference. First operand 5831 states and 7905 transitions. cyclomatic complexity: 2082 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:12,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:12,849 INFO L93 Difference]: Finished difference Result 10645 states and 14326 transitions. [2021-10-28 23:18:12,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:12,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10645 states and 14326 transitions. [2021-10-28 23:18:12,904 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10274 [2021-10-28 23:18:12,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10645 states to 10645 states and 14326 transitions. [2021-10-28 23:18:12,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10645 [2021-10-28 23:18:12,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10645 [2021-10-28 23:18:12,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10645 states and 14326 transitions. [2021-10-28 23:18:12,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:12,973 INFO L681 BuchiCegarLoop]: Abstraction has 10645 states and 14326 transitions. [2021-10-28 23:18:12,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10645 states and 14326 transitions. [2021-10-28 23:18:13,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10645 to 9999. [2021-10-28 23:18:13,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9999 states, 9999 states have (on average 1.3497349734973498) internal successors, (13496), 9998 states have internal predecessors, (13496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:13,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9999 states to 9999 states and 13496 transitions. [2021-10-28 23:18:13,185 INFO L704 BuchiCegarLoop]: Abstraction has 9999 states and 13496 transitions. [2021-10-28 23:18:13,185 INFO L587 BuchiCegarLoop]: Abstraction has 9999 states and 13496 transitions. [2021-10-28 23:18:13,185 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-28 23:18:13,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9999 states and 13496 transitions. [2021-10-28 23:18:13,223 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9628 [2021-10-28 23:18:13,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:13,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:13,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:13,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:13,225 INFO L791 eck$LassoCheckResult]: Stem: 95530#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 95508#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 95457#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 95430#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 95133#L345-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 95134#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96495#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96494#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96493#L365-1 assume !(0 == ~M_E~0); 96492#L506-1 assume !(0 == ~T1_E~0); 96491#L511-1 assume !(0 == ~T2_E~0); 96490#L516-1 assume !(0 == ~T3_E~0); 96489#L521-1 assume !(0 == ~T4_E~0); 96488#L526-1 assume !(0 == ~E_M~0); 96487#L531-1 assume !(0 == ~E_1~0); 96486#L536-1 assume !(0 == ~E_2~0); 96485#L541-1 assume !(0 == ~E_3~0); 96484#L546-1 assume !(0 == ~E_4~0); 96483#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96482#L242 assume !(1 == ~m_pc~0); 96481#L242-2 is_master_triggered_~__retres1~0 := 0; 96480#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 96479#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 96478#L629 assume !(0 != activate_threads_~tmp~1); 96477#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96476#L261 assume !(1 == ~t1_pc~0); 95424#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 95425#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 95511#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 95512#L637 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 95585#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96499#L280 assume !(1 == ~t2_pc~0); 96498#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 96497#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96496#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 95579#L645 assume !(0 != activate_threads_~tmp___1~0); 95282#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 95283#L299 assume !(1 == ~t3_pc~0); 95399#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 95574#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 95426#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 95427#L653 assume !(0 != activate_threads_~tmp___2~0); 95566#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 95567#L318 assume !(1 == ~t4_pc~0); 95562#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 95563#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 95556#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 95557#L661 assume !(0 != activate_threads_~tmp___3~0); 95244#L661-2 assume !(1 == ~M_E~0); 95245#L564-1 assume !(1 == ~T1_E~0); 95542#L569-1 assume !(1 == ~T2_E~0); 95543#L574-1 assume !(1 == ~T3_E~0); 95538#L579-1 assume !(1 == ~T4_E~0); 95539#L584-1 assume !(1 == ~E_M~0); 95535#L589-1 assume !(1 == ~E_1~0); 95170#L594-1 assume !(1 == ~E_2~0); 95251#L599-1 assume !(1 == ~E_3~0); 95252#L604-1 assume !(1 == ~E_4~0); 95734#L795-1 assume !false; 95735#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 95725#L481 [2021-10-28 23:18:13,226 INFO L793 eck$LassoCheckResult]: Loop: 95725#L481 assume !false; 95726#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 96413#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 96407#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 96398#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 96392#L420 assume 0 != eval_~tmp~0; 96384#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 96380#L428 assume !(0 != eval_~tmp_ndt_1~0); 96260#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 96256#L442 assume !(0 != eval_~tmp_ndt_2~0); 96253#L439 assume !(0 == ~t2_st~0); 96250#L453 assume !(0 == ~t3_st~0); 96429#L467 assume !(0 == ~t4_st~0); 95725#L481 [2021-10-28 23:18:13,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:13,226 INFO L85 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2021-10-28 23:18:13,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:13,227 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285556359] [2021-10-28 23:18:13,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:13,227 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:13,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:13,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:13,256 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:13,257 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285556359] [2021-10-28 23:18:13,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285556359] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:13,257 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:13,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:13,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912450866] [2021-10-28 23:18:13,258 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:18:13,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:13,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1950332302, now seen corresponding path program 1 times [2021-10-28 23:18:13,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:13,259 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848902473] [2021-10-28 23:18:13,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:13,260 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:13,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:13,355 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:13,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:13,360 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:13,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:13,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:13,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:13,531 INFO L87 Difference]: Start difference. First operand 9999 states and 13496 transitions. cyclomatic complexity: 3505 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:13,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:13,580 INFO L93 Difference]: Finished difference Result 9913 states and 13381 transitions. [2021-10-28 23:18:13,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:13,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9913 states and 13381 transitions. [2021-10-28 23:18:13,634 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9628 [2021-10-28 23:18:13,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9913 states to 9913 states and 13381 transitions. [2021-10-28 23:18:13,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9913 [2021-10-28 23:18:13,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9913 [2021-10-28 23:18:13,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9913 states and 13381 transitions. [2021-10-28 23:18:13,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:13,703 INFO L681 BuchiCegarLoop]: Abstraction has 9913 states and 13381 transitions. [2021-10-28 23:18:13,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9913 states and 13381 transitions. [2021-10-28 23:18:13,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9913 to 9913. [2021-10-28 23:18:13,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9913 states, 9913 states have (on average 1.3498436396650864) internal successors, (13381), 9912 states have internal predecessors, (13381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:14,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9913 states to 9913 states and 13381 transitions. [2021-10-28 23:18:14,029 INFO L704 BuchiCegarLoop]: Abstraction has 9913 states and 13381 transitions. [2021-10-28 23:18:14,029 INFO L587 BuchiCegarLoop]: Abstraction has 9913 states and 13381 transitions. [2021-10-28 23:18:14,029 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-28 23:18:14,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9913 states and 13381 transitions. [2021-10-28 23:18:14,080 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9628 [2021-10-28 23:18:14,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:14,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:14,081 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:14,081 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:14,082 INFO L791 eck$LassoCheckResult]: Stem: 115427#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 115403#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 115357#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 115331#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 115052#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115053#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115280#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115246#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115247#L365-1 assume !(0 == ~M_E~0); 115282#L506-1 assume !(0 == ~T1_E~0); 115038#L511-1 assume !(0 == ~T2_E~0); 115039#L516-1 assume !(0 == ~T3_E~0); 115311#L521-1 assume !(0 == ~T4_E~0); 115346#L526-1 assume !(0 == ~E_M~0); 115287#L531-1 assume !(0 == ~E_1~0); 115229#L536-1 assume !(0 == ~E_2~0); 115230#L541-1 assume !(0 == ~E_3~0); 115221#L546-1 assume !(0 == ~E_4~0); 115222#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 115279#L242 assume !(1 == ~m_pc~0); 115187#L242-2 is_master_triggered_~__retres1~0 := 0; 115188#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 115237#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 115319#L629 assume !(0 != activate_threads_~tmp~1); 115320#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 115384#L261 assume !(1 == ~t1_pc~0); 115198#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 114996#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114997#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 115361#L637 assume !(0 != activate_threads_~tmp___0~0); 115362#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 115242#L280 assume !(1 == ~t2_pc~0); 115243#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 115227#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 115228#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 115385#L645 assume !(0 != activate_threads_~tmp___1~0); 115386#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 115441#L299 assume !(1 == ~t3_pc~0); 115210#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 115209#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 115328#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 115322#L653 assume !(0 != activate_threads_~tmp___2~0); 115323#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 115439#L318 assume !(1 == ~t4_pc~0); 115438#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 115401#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 115402#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 115369#L661 assume !(0 != activate_threads_~tmp___3~0); 115154#L661-2 assume !(1 == ~M_E~0); 115155#L564-1 assume !(1 == ~T1_E~0); 115436#L569-1 assume !(1 == ~T2_E~0); 115435#L574-1 assume !(1 == ~T3_E~0); 115434#L579-1 assume !(1 == ~T4_E~0); 115433#L584-1 assume !(1 == ~E_M~0); 115432#L589-1 assume !(1 == ~E_1~0); 115086#L594-1 assume !(1 == ~E_2~0); 115161#L599-1 assume !(1 == ~E_3~0); 114956#L604-1 assume !(1 == ~E_4~0); 114957#L795-1 assume !false; 115975#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 115969#L481 [2021-10-28 23:18:14,082 INFO L793 eck$LassoCheckResult]: Loop: 115969#L481 assume !false; 115966#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 115962#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 115958#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 115955#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 115952#L420 assume 0 != eval_~tmp~0; 115948#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 115941#L428 assume !(0 != eval_~tmp_ndt_1~0); 115933#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 115931#L442 assume !(0 != eval_~tmp_ndt_2~0); 115929#L439 assume !(0 == ~t2_st~0); 115927#L453 assume !(0 == ~t3_st~0); 115976#L467 assume !(0 == ~t4_st~0); 115969#L481 [2021-10-28 23:18:14,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:14,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2021-10-28 23:18:14,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:14,083 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993686949] [2021-10-28 23:18:14,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:14,084 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:14,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:14,097 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:14,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:14,126 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:14,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:14,128 INFO L85 PathProgramCache]: Analyzing trace with hash -1950332302, now seen corresponding path program 2 times [2021-10-28 23:18:14,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:14,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221768161] [2021-10-28 23:18:14,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:14,129 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:14,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:14,134 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:14,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:14,140 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:14,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:14,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1660720301, now seen corresponding path program 1 times [2021-10-28 23:18:14,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:14,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178821] [2021-10-28 23:18:14,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:14,142 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:14,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:14,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:14,185 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:14,185 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178821] [2021-10-28 23:18:14,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178821] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:14,186 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:14,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:14,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729394150] [2021-10-28 23:18:14,322 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:14,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:14,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:14,323 INFO L87 Difference]: Start difference. First operand 9913 states and 13381 transitions. cyclomatic complexity: 3476 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:14,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:14,463 INFO L93 Difference]: Finished difference Result 18267 states and 24509 transitions. [2021-10-28 23:18:14,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:14,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18267 states and 24509 transitions. [2021-10-28 23:18:14,581 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17788 [2021-10-28 23:18:14,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18267 states to 18267 states and 24509 transitions. [2021-10-28 23:18:14,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18267 [2021-10-28 23:18:14,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18267 [2021-10-28 23:18:14,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18267 states and 24509 transitions. [2021-10-28 23:18:14,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:14,837 INFO L681 BuchiCegarLoop]: Abstraction has 18267 states and 24509 transitions. [2021-10-28 23:18:14,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18267 states and 24509 transitions. [2021-10-28 23:18:15,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18267 to 17803. [2021-10-28 23:18:15,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17803 states, 17803 states have (on average 1.343425265404707) internal successors, (23917), 17802 states have internal predecessors, (23917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:15,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17803 states to 17803 states and 23917 transitions. [2021-10-28 23:18:15,311 INFO L704 BuchiCegarLoop]: Abstraction has 17803 states and 23917 transitions. [2021-10-28 23:18:15,311 INFO L587 BuchiCegarLoop]: Abstraction has 17803 states and 23917 transitions. [2021-10-28 23:18:15,311 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-28 23:18:15,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17803 states and 23917 transitions. [2021-10-28 23:18:15,373 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17324 [2021-10-28 23:18:15,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:15,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:15,374 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:15,374 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:15,375 INFO L791 eck$LassoCheckResult]: Stem: 143637#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 143602#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 143552#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 143527#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 143241#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143242#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143472#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143436#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143437#L365-1 assume !(0 == ~M_E~0); 143474#L506-1 assume !(0 == ~T1_E~0); 143227#L511-1 assume !(0 == ~T2_E~0); 143228#L516-1 assume !(0 == ~T3_E~0); 143506#L521-1 assume !(0 == ~T4_E~0); 143541#L526-1 assume !(0 == ~E_M~0); 143480#L531-1 assume !(0 == ~E_1~0); 143415#L536-1 assume !(0 == ~E_2~0); 143416#L541-1 assume !(0 == ~E_3~0); 143408#L546-1 assume !(0 == ~E_4~0); 143409#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 143471#L242 assume !(1 == ~m_pc~0); 143375#L242-2 is_master_triggered_~__retres1~0 := 0; 143376#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 143424#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 143514#L629 assume !(0 != activate_threads_~tmp~1); 143515#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 143578#L261 assume !(1 == ~t1_pc~0); 143387#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 143186#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143187#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 143558#L637 assume !(0 != activate_threads_~tmp___0~0); 143559#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143431#L280 assume !(1 == ~t2_pc~0); 143432#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 143413#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 143414#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 143579#L645 assume !(0 != activate_threads_~tmp___1~0); 143580#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 143653#L299 assume !(1 == ~t3_pc~0); 143399#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 143398#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 143523#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 143524#L653 assume !(0 != activate_threads_~tmp___2~0); 143566#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 143468#L318 assume !(1 == ~t4_pc~0); 143300#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 143301#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 143525#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 143526#L661 assume !(0 != activate_threads_~tmp___3~0); 143650#L661-2 assume !(1 == ~M_E~0); 143649#L564-1 assume !(1 == ~T1_E~0); 143648#L569-1 assume !(1 == ~T2_E~0); 143647#L574-1 assume !(1 == ~T3_E~0); 143646#L579-1 assume !(1 == ~T4_E~0); 143645#L584-1 assume !(1 == ~E_M~0); 143644#L589-1 assume !(1 == ~E_1~0); 143275#L594-1 assume !(1 == ~E_2~0); 143350#L599-1 assume !(1 == ~E_3~0); 143144#L604-1 assume !(1 == ~E_4~0); 143145#L795-1 assume !false; 148088#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 148087#L481 [2021-10-28 23:18:15,375 INFO L793 eck$LassoCheckResult]: Loop: 148087#L481 assume !false; 148073#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 148074#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 148051#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 148052#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 147943#L420 assume 0 != eval_~tmp~0; 147944#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 147921#L428 assume !(0 != eval_~tmp_ndt_1~0); 147421#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 147414#L442 assume !(0 != eval_~tmp_ndt_2~0); 146244#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 145713#L456 assume !(0 != eval_~tmp_ndt_3~0); 145715#L453 assume !(0 == ~t3_st~0); 147864#L467 assume !(0 == ~t4_st~0); 148087#L481 [2021-10-28 23:18:15,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:15,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2021-10-28 23:18:15,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:15,376 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476232189] [2021-10-28 23:18:15,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:15,377 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:15,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:15,390 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:15,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:15,415 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:15,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:15,416 INFO L85 PathProgramCache]: Analyzing trace with hash -335443967, now seen corresponding path program 1 times [2021-10-28 23:18:15,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:15,417 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692745668] [2021-10-28 23:18:15,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:15,417 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:15,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:15,422 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:15,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:15,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:15,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:15,428 INFO L85 PathProgramCache]: Analyzing trace with hash -61962970, now seen corresponding path program 1 times [2021-10-28 23:18:15,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:15,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901689464] [2021-10-28 23:18:15,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:15,429 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:15,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:15,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:15,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:15,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901689464] [2021-10-28 23:18:15,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901689464] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:15,469 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:15,469 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:18:15,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77036268] [2021-10-28 23:18:15,633 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:15,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:15,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:15,635 INFO L87 Difference]: Start difference. First operand 17803 states and 23917 transitions. cyclomatic complexity: 6122 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:15,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:15,811 INFO L93 Difference]: Finished difference Result 31019 states and 41419 transitions. [2021-10-28 23:18:15,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:15,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31019 states and 41419 transitions. [2021-10-28 23:18:16,161 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 30152 [2021-10-28 23:18:16,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31019 states to 31019 states and 41419 transitions. [2021-10-28 23:18:16,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31019 [2021-10-28 23:18:16,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31019 [2021-10-28 23:18:16,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31019 states and 41419 transitions. [2021-10-28 23:18:16,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:16,483 INFO L681 BuchiCegarLoop]: Abstraction has 31019 states and 41419 transitions. [2021-10-28 23:18:16,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31019 states and 41419 transitions. [2021-10-28 23:18:17,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31019 to 29947. [2021-10-28 23:18:17,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29947 states, 29947 states have (on average 1.3392660366647744) internal successors, (40107), 29946 states have internal predecessors, (40107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:17,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29947 states to 29947 states and 40107 transitions. [2021-10-28 23:18:17,184 INFO L704 BuchiCegarLoop]: Abstraction has 29947 states and 40107 transitions. [2021-10-28 23:18:17,185 INFO L587 BuchiCegarLoop]: Abstraction has 29947 states and 40107 transitions. [2021-10-28 23:18:17,185 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-28 23:18:17,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29947 states and 40107 transitions. [2021-10-28 23:18:17,298 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 29080 [2021-10-28 23:18:17,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:17,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:17,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:17,301 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:17,301 INFO L791 eck$LassoCheckResult]: Stem: 192484#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 192441#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 192384#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 192358#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 192072#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 192073#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192304#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192269#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 192270#L365-1 assume !(0 == ~M_E~0); 192306#L506-1 assume !(0 == ~T1_E~0); 192058#L511-1 assume !(0 == ~T2_E~0); 192059#L516-1 assume !(0 == ~T3_E~0); 192334#L521-1 assume !(0 == ~T4_E~0); 192374#L526-1 assume !(0 == ~E_M~0); 192311#L531-1 assume !(0 == ~E_1~0); 192246#L536-1 assume !(0 == ~E_2~0); 192247#L541-1 assume !(0 == ~E_3~0); 192239#L546-1 assume !(0 == ~E_4~0); 192240#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 192303#L242 assume !(1 == ~m_pc~0); 192206#L242-2 is_master_triggered_~__retres1~0 := 0; 192207#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 192256#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 192343#L629 assume !(0 != activate_threads_~tmp~1); 192344#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 192413#L261 assume !(1 == ~t1_pc~0); 192216#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 192014#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 192015#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 192389#L637 assume !(0 != activate_threads_~tmp___0~0); 192390#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 192264#L280 assume !(1 == ~t2_pc~0); 192265#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 192244#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 192245#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 192414#L645 assume !(0 != activate_threads_~tmp___1~0); 192415#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 192500#L299 assume !(1 == ~t3_pc~0); 192228#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 192227#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 192355#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 192346#L653 assume !(0 != activate_threads_~tmp___2~0); 192347#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 192498#L318 assume !(1 == ~t4_pc~0); 192497#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 192439#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 192440#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 192397#L661 assume !(0 != activate_threads_~tmp___3~0); 192175#L661-2 assume !(1 == ~M_E~0); 192176#L564-1 assume !(1 == ~T1_E~0); 192495#L569-1 assume !(1 == ~T2_E~0); 192494#L574-1 assume !(1 == ~T3_E~0); 192493#L579-1 assume !(1 == ~T4_E~0); 192492#L584-1 assume !(1 == ~E_M~0); 192491#L589-1 assume !(1 == ~E_1~0); 192105#L594-1 assume !(1 == ~E_2~0); 192183#L599-1 assume !(1 == ~E_3~0); 191974#L604-1 assume !(1 == ~E_4~0); 191975#L795-1 assume !false; 199825#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 199818#L481 [2021-10-28 23:18:17,302 INFO L793 eck$LassoCheckResult]: Loop: 199818#L481 assume !false; 199814#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 199809#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 199803#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 199795#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 199790#L420 assume 0 != eval_~tmp~0; 199785#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 199780#L428 assume !(0 != eval_~tmp_ndt_1~0); 198502#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 198500#L442 assume !(0 != eval_~tmp_ndt_2~0); 196872#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 196867#L456 assume !(0 != eval_~tmp_ndt_3~0); 196868#L453 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 198706#L470 assume !(0 != eval_~tmp_ndt_4~0); 199640#L467 assume !(0 == ~t4_st~0); 199818#L481 [2021-10-28 23:18:17,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:17,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2021-10-28 23:18:17,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:17,303 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111098499] [2021-10-28 23:18:17,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:17,303 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:17,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:17,316 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:17,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:17,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:17,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:17,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1808978268, now seen corresponding path program 1 times [2021-10-28 23:18:17,497 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:17,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033147697] [2021-10-28 23:18:17,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:17,498 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:17,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:17,509 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:17,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:17,516 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:17,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:17,517 INFO L85 PathProgramCache]: Analyzing trace with hash -1921001953, now seen corresponding path program 1 times [2021-10-28 23:18:17,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:17,517 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80204312] [2021-10-28 23:18:17,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:17,517 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:17,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:18:17,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:18:17,559 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:18:17,559 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80204312] [2021-10-28 23:18:17,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [80204312] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:18:17,560 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:18:17,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:18:17,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55982539] [2021-10-28 23:18:17,779 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:18:17,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:18:17,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:18:17,781 INFO L87 Difference]: Start difference. First operand 29947 states and 40107 transitions. cyclomatic complexity: 10168 Second operand has 3 states, 2 states have (on average 37.5) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:17,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:18:17,977 INFO L93 Difference]: Finished difference Result 38231 states and 50951 transitions. [2021-10-28 23:18:17,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:18:17,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38231 states and 50951 transitions. [2021-10-28 23:18:18,427 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 37348 [2021-10-28 23:18:18,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38231 states to 38231 states and 50951 transitions. [2021-10-28 23:18:18,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38231 [2021-10-28 23:18:18,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38231 [2021-10-28 23:18:18,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38231 states and 50951 transitions. [2021-10-28 23:18:18,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:18:18,823 INFO L681 BuchiCegarLoop]: Abstraction has 38231 states and 50951 transitions. [2021-10-28 23:18:18,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38231 states and 50951 transitions. [2021-10-28 23:18:19,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38231 to 37847. [2021-10-28 23:18:19,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37847 states, 37847 states have (on average 1.336090046767247) internal successors, (50567), 37846 states have internal predecessors, (50567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:18:19,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37847 states to 37847 states and 50567 transitions. [2021-10-28 23:18:19,449 INFO L704 BuchiCegarLoop]: Abstraction has 37847 states and 50567 transitions. [2021-10-28 23:18:19,449 INFO L587 BuchiCegarLoop]: Abstraction has 37847 states and 50567 transitions. [2021-10-28 23:18:19,449 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-28 23:18:19,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37847 states and 50567 transitions. [2021-10-28 23:18:19,840 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 36964 [2021-10-28 23:18:19,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:18:19,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:18:19,858 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:19,859 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:18:19,861 INFO L791 eck$LassoCheckResult]: Stem: 260681#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 260636#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 260573#L758 havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 260544#L338 assume 1 == ~m_i~0;~m_st~0 := 0; 260257#L345-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 260258#L350-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 260490#L355-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 260456#L360-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 260457#L365-1 assume !(0 == ~M_E~0); 260492#L506-1 assume !(0 == ~T1_E~0); 260243#L511-1 assume !(0 == ~T2_E~0); 260244#L516-1 assume !(0 == ~T3_E~0); 260524#L521-1 assume !(0 == ~T4_E~0); 260562#L526-1 assume !(0 == ~E_M~0); 260498#L531-1 assume !(0 == ~E_1~0); 260433#L536-1 assume !(0 == ~E_2~0); 260434#L541-1 assume !(0 == ~E_3~0); 260426#L546-1 assume !(0 == ~E_4~0); 260427#L551-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 260488#L242 assume !(1 == ~m_pc~0); 260391#L242-2 is_master_triggered_~__retres1~0 := 0; 260392#L253 is_master_triggered_#res := is_master_triggered_~__retres1~0; 260444#L254 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 260532#L629 assume !(0 != activate_threads_~tmp~1); 260533#L629-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 260603#L261 assume !(1 == ~t1_pc~0); 260404#L261-2 is_transmit1_triggered_~__retres1~1 := 0; 260200#L272 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 260201#L273 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 260580#L637 assume !(0 != activate_threads_~tmp___0~0); 260581#L637-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 260452#L280 assume !(1 == ~t2_pc~0); 260453#L280-2 is_transmit2_triggered_~__retres1~2 := 0; 260431#L291 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 260432#L292 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 260604#L645 assume !(0 != activate_threads_~tmp___1~0); 260605#L645-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 260702#L299 assume !(1 == ~t3_pc~0); 260416#L299-2 is_transmit3_triggered_~__retres1~3 := 0; 260415#L310 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 260541#L311 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 260535#L653 assume !(0 != activate_threads_~tmp___2~0); 260536#L653-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 260700#L318 assume !(1 == ~t4_pc~0); 260699#L318-2 is_transmit4_triggered_~__retres1~4 := 0; 260631#L329 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 260632#L330 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 260589#L661 assume !(0 != activate_threads_~tmp___3~0); 260358#L661-2 assume !(1 == ~M_E~0); 260359#L564-1 assume !(1 == ~T1_E~0); 260697#L569-1 assume !(1 == ~T2_E~0); 260696#L574-1 assume !(1 == ~T3_E~0); 260695#L579-1 assume !(1 == ~T4_E~0); 260694#L584-1 assume !(1 == ~E_M~0); 260693#L589-1 assume !(1 == ~E_1~0); 260290#L594-1 assume !(1 == ~E_2~0); 260365#L599-1 assume !(1 == ~E_3~0); 260160#L604-1 assume !(1 == ~E_4~0); 260161#L795-1 assume !false; 278426#L796 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 278421#L481 [2021-10-28 23:18:19,861 INFO L793 eck$LassoCheckResult]: Loop: 278421#L481 assume !false; 278418#L416 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 278414#L378 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 278395#L405 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 278389#L406 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 278382#L420 assume 0 != eval_~tmp~0; 278375#L420-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 278313#L428 assume !(0 != eval_~tmp_ndt_1~0); 277814#L425 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 277803#L442 assume !(0 != eval_~tmp_ndt_2~0); 277796#L439 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 274968#L456 assume !(0 != eval_~tmp_ndt_3~0); 277786#L453 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 277875#L470 assume !(0 != eval_~tmp_ndt_4~0); 278006#L467 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 278424#L484 assume !(0 != eval_~tmp_ndt_5~0); 278421#L481 [2021-10-28 23:18:19,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:19,862 INFO L85 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2021-10-28 23:18:19,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:19,863 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154683750] [2021-10-28 23:18:19,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:19,863 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:19,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,888 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:19,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,913 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:19,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:19,914 INFO L85 PathProgramCache]: Analyzing trace with hash -243755057, now seen corresponding path program 1 times [2021-10-28 23:18:19,914 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:19,915 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934313836] [2021-10-28 23:18:19,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:19,915 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:19,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,920 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:19,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,926 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:19,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:18:19,927 INFO L85 PathProgramCache]: Analyzing trace with hash 578478004, now seen corresponding path program 1 times [2021-10-28 23:18:19,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:18:19,927 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540074303] [2021-10-28 23:18:19,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:18:19,928 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:18:19,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,947 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:18:19,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:18:19,980 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:18:22,477 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 11:18:22 BoogieIcfgContainer [2021-10-28 23:18:22,478 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 23:18:22,479 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 23:18:22,479 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 23:18:22,479 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 23:18:22,480 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:18:05" (3/4) ... [2021-10-28 23:18:22,483 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 23:18:22,577 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/witness.graphml [2021-10-28 23:18:22,577 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 23:18:22,580 INFO L168 Benchmark]: Toolchain (without parser) took 19847.56 ms. Allocated memory was 117.4 MB in the beginning and 4.6 GB in the end (delta: 4.5 GB). Free memory was 84.9 MB in the beginning and 3.9 GB in the end (delta: -3.8 GB). Peak memory consumption was 660.9 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,580 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 79.7 MB. Free memory is still 37.3 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 23:18:22,581 INFO L168 Benchmark]: CACSL2BoogieTranslator took 524.33 ms. Allocated memory is still 117.4 MB. Free memory was 84.6 MB in the beginning and 88.4 MB in the end (delta: -3.8 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,582 INFO L168 Benchmark]: Boogie Procedure Inliner took 144.17 ms. Allocated memory is still 117.4 MB. Free memory was 88.4 MB in the beginning and 84.3 MB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,582 INFO L168 Benchmark]: Boogie Preprocessor took 116.02 ms. Allocated memory is still 117.4 MB. Free memory was 84.3 MB in the beginning and 80.1 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,583 INFO L168 Benchmark]: RCFGBuilder took 1561.52 ms. Allocated memory was 117.4 MB in the beginning and 146.8 MB in the end (delta: 29.4 MB). Free memory was 80.1 MB in the beginning and 113.7 MB in the end (delta: -33.6 MB). Peak memory consumption was 40.0 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,583 INFO L168 Benchmark]: BuchiAutomizer took 17388.16 ms. Allocated memory was 146.8 MB in the beginning and 4.6 GB in the end (delta: 4.5 GB). Free memory was 113.7 MB in the beginning and 3.9 GB in the end (delta: -3.8 GB). Peak memory consumption was 657.4 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,584 INFO L168 Benchmark]: Witness Printer took 98.50 ms. Allocated memory is still 4.6 GB. Free memory was 3.9 GB in the beginning and 3.9 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:18:22,587 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 79.7 MB. Free memory is still 37.3 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 524.33 ms. Allocated memory is still 117.4 MB. Free memory was 84.6 MB in the beginning and 88.4 MB in the end (delta: -3.8 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 144.17 ms. Allocated memory is still 117.4 MB. Free memory was 88.4 MB in the beginning and 84.3 MB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 116.02 ms. Allocated memory is still 117.4 MB. Free memory was 84.3 MB in the beginning and 80.1 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1561.52 ms. Allocated memory was 117.4 MB in the beginning and 146.8 MB in the end (delta: 29.4 MB). Free memory was 80.1 MB in the beginning and 113.7 MB in the end (delta: -33.6 MB). Peak memory consumption was 40.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 17388.16 ms. Allocated memory was 146.8 MB in the beginning and 4.6 GB in the end (delta: 4.5 GB). Free memory was 113.7 MB in the beginning and 3.9 GB in the end (delta: -3.8 GB). Peak memory consumption was 657.4 MB. Max. memory is 16.1 GB. * Witness Printer took 98.50 ms. Allocated memory is still 4.6 GB. Free memory was 3.9 GB in the beginning and 3.9 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 37847 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 17.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 6.5s. Construction of modules took 0.7s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 3.9s AutomataMinimizationTime, 21 MinimizatonAttempts, 8550 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 2.4s Buchi closure took 0.3s. Biggest automaton had 37847 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 13029 SDtfs, 13718 SDslu, 8135 SDs, 0 SdLazy, 473 SolverSat, 231 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 415]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=32008} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=32008, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27df7a77=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@78e1868c=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@389a4511=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1627cbc5=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@26f43675=0, tmp=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1609acfa=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ce0021b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6805519=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6696bbd9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3de3db73=0, NULL=32011, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@580b6ff0=0, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=32010, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=32009, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12044cf8=0, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b4e9f99=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 415]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int T2_E = 2; [L34] int T3_E = 2; [L35] int T4_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L47] int token ; [L49] int local ; [L840] int __retres1 ; [L752] m_i = 1 [L753] t1_i = 1 [L754] t2_i = 1 [L755] t3_i = 1 [L756] t4_i = 1 [L781] int kernel_st ; [L782] int tmp ; [L783] int tmp___0 ; [L787] kernel_st = 0 [L345] COND TRUE m_i == 1 [L346] m_st = 0 [L350] COND TRUE t1_i == 1 [L351] t1_st = 0 [L355] COND TRUE t2_i == 1 [L356] t2_st = 0 [L360] COND TRUE t3_i == 1 [L361] t3_st = 0 [L365] COND TRUE t4_i == 1 [L366] t4_st = 0 [L506] COND FALSE !(M_E == 0) [L511] COND FALSE !(T1_E == 0) [L516] COND FALSE !(T2_E == 0) [L521] COND FALSE !(T3_E == 0) [L526] COND FALSE !(T4_E == 0) [L531] COND FALSE !(E_M == 0) [L536] COND FALSE !(E_1 == 0) [L541] COND FALSE !(E_2 == 0) [L546] COND FALSE !(E_3 == 0) [L551] COND FALSE !(E_4 == 0) [L619] int tmp ; [L620] int tmp___0 ; [L621] int tmp___1 ; [L622] int tmp___2 ; [L623] int tmp___3 ; [L239] int __retres1 ; [L242] COND FALSE !(m_pc == 1) [L252] __retres1 = 0 [L254] return (__retres1); [L627] tmp = is_master_triggered() [L629] COND FALSE !(\read(tmp)) [L258] int __retres1 ; [L261] COND FALSE !(t1_pc == 1) [L271] __retres1 = 0 [L273] return (__retres1); [L635] tmp___0 = is_transmit1_triggered() [L637] COND FALSE !(\read(tmp___0)) [L277] int __retres1 ; [L280] COND FALSE !(t2_pc == 1) [L290] __retres1 = 0 [L292] return (__retres1); [L643] tmp___1 = is_transmit2_triggered() [L645] COND FALSE !(\read(tmp___1)) [L296] int __retres1 ; [L299] COND FALSE !(t3_pc == 1) [L309] __retres1 = 0 [L311] return (__retres1); [L651] tmp___2 = is_transmit3_triggered() [L653] COND FALSE !(\read(tmp___2)) [L315] int __retres1 ; [L318] COND FALSE !(t4_pc == 1) [L328] __retres1 = 0 [L330] return (__retres1); [L659] tmp___3 = is_transmit4_triggered() [L661] COND FALSE !(\read(tmp___3)) [L564] COND FALSE !(M_E == 1) [L569] COND FALSE !(T1_E == 1) [L574] COND FALSE !(T2_E == 1) [L579] COND FALSE !(T3_E == 1) [L584] COND FALSE !(T4_E == 1) [L589] COND FALSE !(E_M == 1) [L594] COND FALSE !(E_1 == 1) [L599] COND FALSE !(E_2 == 1) [L604] COND FALSE !(E_3 == 1) [L609] COND FALSE !(E_4 == 1) [L795] COND TRUE 1 [L798] kernel_st = 1 [L411] int tmp ; Loop: [L415] COND TRUE 1 [L375] int __retres1 ; [L378] COND TRUE m_st == 0 [L379] __retres1 = 1 [L406] return (__retres1); [L418] tmp = exists_runnable_thread() [L420] COND TRUE \read(tmp) [L425] COND TRUE m_st == 0 [L426] int tmp_ndt_1; [L427] tmp_ndt_1 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_1)) [L439] COND TRUE t1_st == 0 [L440] int tmp_ndt_2; [L441] tmp_ndt_2 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_2)) [L453] COND TRUE t2_st == 0 [L454] int tmp_ndt_3; [L455] tmp_ndt_3 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_3)) [L467] COND TRUE t3_st == 0 [L468] int tmp_ndt_4; [L469] tmp_ndt_4 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_4)) [L481] COND TRUE t4_st == 0 [L482] int tmp_ndt_5; [L483] tmp_ndt_5 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 23:18:22,687 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6b43c1f3-348a-4704-b494-d6fc4285ce0b/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...