./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash baf2862afdca861ecfab5536f844964e557a2feed6de3725a6fb79b602497014 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 23:19:01,544 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 23:19:01,546 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 23:19:01,575 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 23:19:01,576 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 23:19:01,577 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 23:19:01,579 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 23:19:01,582 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 23:19:01,584 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 23:19:01,585 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 23:19:01,586 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 23:19:01,588 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 23:19:01,589 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 23:19:01,590 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 23:19:01,592 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 23:19:01,593 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 23:19:01,594 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 23:19:01,595 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 23:19:01,598 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 23:19:01,600 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 23:19:01,602 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 23:19:01,603 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 23:19:01,605 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 23:19:01,606 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 23:19:01,610 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 23:19:01,610 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 23:19:01,611 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 23:19:01,612 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 23:19:01,612 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 23:19:01,614 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 23:19:01,614 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 23:19:01,615 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 23:19:01,616 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 23:19:01,617 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 23:19:01,618 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 23:19:01,619 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 23:19:01,620 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 23:19:01,620 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 23:19:01,620 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 23:19:01,622 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 23:19:01,623 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 23:19:01,623 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 23:19:01,647 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 23:19:01,647 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 23:19:01,647 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 23:19:01,648 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 23:19:01,649 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 23:19:01,649 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 23:19:01,649 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 23:19:01,650 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 23:19:01,650 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 23:19:01,650 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 23:19:01,650 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 23:19:01,650 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 23:19:01,651 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 23:19:01,651 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 23:19:01,651 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 23:19:01,651 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 23:19:01,652 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 23:19:01,652 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 23:19:01,652 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 23:19:01,652 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 23:19:01,652 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 23:19:01,653 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 23:19:01,653 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 23:19:01,653 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 23:19:01,653 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 23:19:01,654 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 23:19:01,654 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 23:19:01,654 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 23:19:01,654 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 23:19:01,655 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 23:19:01,655 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 23:19:01,655 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 23:19:01,656 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 23:19:01,656 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> baf2862afdca861ecfab5536f844964e557a2feed6de3725a6fb79b602497014 [2021-10-28 23:19:01,912 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 23:19:01,932 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 23:19:01,934 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 23:19:01,936 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 23:19:01,937 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 23:19:01,937 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-10-28 23:19:02,023 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/data/e7de86306/eb19ef7baa95400e99af144aac5c886c/FLAG502190b39 [2021-10-28 23:19:02,576 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 23:19:02,578 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-10-28 23:19:02,590 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/data/e7de86306/eb19ef7baa95400e99af144aac5c886c/FLAG502190b39 [2021-10-28 23:19:02,947 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/data/e7de86306/eb19ef7baa95400e99af144aac5c886c [2021-10-28 23:19:02,949 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 23:19:02,951 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 23:19:02,952 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 23:19:02,958 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 23:19:02,961 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 23:19:02,962 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:19:02" (1/1) ... [2021-10-28 23:19:02,963 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@39a7e51e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:02, skipping insertion in model container [2021-10-28 23:19:02,968 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:19:02" (1/1) ... [2021-10-28 23:19:02,974 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 23:19:03,011 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 23:19:03,154 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/sv-benchmarks/c/systemc/transmitter.02.cil.c[401,414] [2021-10-28 23:19:03,268 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:19:03,281 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 23:19:03,291 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/sv-benchmarks/c/systemc/transmitter.02.cil.c[401,414] [2021-10-28 23:19:03,326 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:19:03,344 INFO L208 MainTranslator]: Completed translation [2021-10-28 23:19:03,344 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03 WrapperNode [2021-10-28 23:19:03,344 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 23:19:03,345 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 23:19:03,345 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 23:19:03,345 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 23:19:03,353 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,361 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,404 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 23:19:03,405 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 23:19:03,405 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 23:19:03,405 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 23:19:03,413 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,413 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,418 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,418 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,429 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,439 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,442 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,448 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 23:19:03,449 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 23:19:03,449 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 23:19:03,449 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 23:19:03,465 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (1/1) ... [2021-10-28 23:19:03,473 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:19:03,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:19:03,506 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:19:03,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 23:19:03,564 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 23:19:03,564 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 23:19:03,564 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 23:19:03,564 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 23:19:04,143 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 23:19:04,144 INFO L299 CfgBuilder]: Removed 94 assume(true) statements. [2021-10-28 23:19:04,146 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:19:04 BoogieIcfgContainer [2021-10-28 23:19:04,146 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 23:19:04,147 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 23:19:04,148 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 23:19:04,151 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 23:19:04,151 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:19:04,152 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 11:19:02" (1/3) ... [2021-10-28 23:19:04,153 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f9892a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:19:04, skipping insertion in model container [2021-10-28 23:19:04,153 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:19:04,154 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:19:03" (2/3) ... [2021-10-28 23:19:04,154 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f9892a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:19:04, skipping insertion in model container [2021-10-28 23:19:04,169 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:19:04,169 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:19:04" (3/3) ... [2021-10-28 23:19:04,170 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2021-10-28 23:19:04,227 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 23:19:04,227 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 23:19:04,227 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 23:19:04,233 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 23:19:04,233 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 23:19:04,233 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 23:19:04,234 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 23:19:04,234 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 23:19:04,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-10-28 23:19:04,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:04,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:04,322 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,322 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,322 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 23:19:04,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-10-28 23:19:04,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:04,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:04,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,363 INFO L791 eck$LassoCheckResult]: Stem: 167#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 62#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 146#L483true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 50#L206true assume !(1 == ~m_i~0);~m_st~0 := 2; 164#L213-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 65#L218-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6#L223-1true assume !(0 == ~M_E~0); 34#L326-1true assume !(0 == ~T1_E~0); 38#L331-1true assume !(0 == ~T2_E~0); 8#L336-1true assume !(0 == ~E_1~0); 188#L341-1true assume !(0 == ~E_2~0); 33#L346-1true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45#L148true assume !(1 == ~m_pc~0); 57#L148-2true is_master_triggered_~__retres1~0 := 0; 103#L159true is_master_triggered_#res := is_master_triggered_~__retres1~0; 128#L160true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 179#L397true assume !(0 != activate_threads_~tmp~1); 23#L397-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27#L167true assume 1 == ~t1_pc~0; 7#L168true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 43#L178true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 177#L179true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114#L405true assume !(0 != activate_threads_~tmp___0~0); 91#L405-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 92#L186true assume !(1 == ~t2_pc~0); 12#L186-2true is_transmit2_triggered_~__retres1~2 := 0; 104#L197true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 99#L198true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 180#L413true assume !(0 != activate_threads_~tmp___1~0); 133#L413-2true assume !(1 == ~M_E~0); 123#L359-1true assume !(1 == ~T1_E~0); 61#L364-1true assume !(1 == ~T2_E~0); 70#L369-1true assume !(1 == ~E_1~0); 142#L374-1true assume !(1 == ~E_2~0); 21#L520-1true [2021-10-28 23:19:04,365 INFO L793 eck$LassoCheckResult]: Loop: 21#L520-1true assume !false; 132#L521true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 125#L301true assume false; 159#L316true start_simulation_~kernel_st~0 := 2; 117#L206-1true start_simulation_~kernel_st~0 := 3; 22#L326-2true assume 0 == ~M_E~0;~M_E~0 := 1; 175#L326-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 74#L331-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 15#L336-3true assume 0 == ~E_1~0;~E_1~0 := 1; 26#L341-3true assume !(0 == ~E_2~0); 79#L346-3true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53#L148-9true assume 1 == ~m_pc~0; 63#L149-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 155#L159-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 193#L160-3true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 190#L397-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 47#L397-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 136#L167-9true assume !(1 == ~t1_pc~0); 169#L167-11true is_transmit1_triggered_~__retres1~1 := 0; 59#L178-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9#L179-3true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 185#L405-9true assume !(0 != activate_threads_~tmp___0~0); 30#L405-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48#L186-9true assume 1 == ~t2_pc~0; 170#L187-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 77#L197-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145#L198-3true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 56#L413-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41#L413-11true assume 1 == ~M_E~0;~M_E~0 := 2; 144#L359-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 113#L364-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 111#L369-3true assume !(1 == ~E_1~0); 71#L374-3true assume 1 == ~E_2~0;~E_2~0 := 2; 101#L379-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 192#L236-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 32#L253-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 14#L254-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 72#L539true assume !(0 == start_simulation_~tmp~3); 75#L539-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 84#L236-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 181#L253-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 42#L254-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 110#L494true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 68#L501true stop_simulation_#res := stop_simulation_~__retres2~0; 64#L502true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 66#L552true assume !(0 != start_simulation_~tmp___0~1); 21#L520-1true [2021-10-28 23:19:04,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2021-10-28 23:19:04,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,382 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249598125] [2021-10-28 23:19:04,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,383 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:04,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:04,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:04,552 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:04,552 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249598125] [2021-10-28 23:19:04,553 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249598125] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:04,554 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:04,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:04,556 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201019304] [2021-10-28 23:19:04,561 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:19:04,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1231104429, now seen corresponding path program 1 times [2021-10-28 23:19:04,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,563 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625648531] [2021-10-28 23:19:04,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,563 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:04,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:04,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:04,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:04,588 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625648531] [2021-10-28 23:19:04,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625648531] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:04,588 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:04,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:19:04,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698839744] [2021-10-28 23:19:04,590 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:04,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:04,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:04,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:04,610 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:04,645 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2021-10-28 23:19:04,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:04,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2021-10-28 23:19:04,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 23:19:04,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2021-10-28 23:19:04,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-10-28 23:19:04,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-10-28 23:19:04,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2021-10-28 23:19:04,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:04,665 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 23:19:04,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2021-10-28 23:19:04,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-10-28 23:19:04,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.510752688172043) internal successors, (281), 185 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2021-10-28 23:19:04,707 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 23:19:04,707 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-10-28 23:19:04,707 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 23:19:04,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2021-10-28 23:19:04,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 23:19:04,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:04,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:04,713 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,714 INFO L791 eck$LassoCheckResult]: Stem: 574#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 493#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 494#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 471#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 495#L218-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 396#L223-1 assume !(0 == ~M_E~0); 397#L326-1 assume !(0 == ~T1_E~0); 450#L331-1 assume !(0 == ~T2_E~0); 403#L336-1 assume !(0 == ~E_1~0); 404#L341-1 assume !(0 == ~E_2~0); 447#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 448#L148 assume !(1 == ~m_pc~0); 462#L148-2 is_master_triggered_~__retres1~0 := 0; 484#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 543#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 560#L397 assume !(0 != activate_threads_~tmp~1); 432#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 433#L167 assume 1 == ~t1_pc~0; 398#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 399#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 461#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 552#L405 assume !(0 != activate_threads_~tmp___0~0); 526#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 527#L186 assume !(1 == ~t2_pc~0); 409#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 410#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 536#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 537#L413 assume !(0 != activate_threads_~tmp___1~0); 562#L413-2 assume !(1 == ~M_E~0); 558#L359-1 assume !(1 == ~T1_E~0); 488#L364-1 assume !(1 == ~T2_E~0); 489#L369-1 assume !(1 == ~E_1~0); 500#L374-1 assume !(1 == ~E_2~0); 428#L520-1 [2021-10-28 23:19:04,714 INFO L793 eck$LassoCheckResult]: Loop: 428#L520-1 assume !false; 429#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 530#L301 assume !false; 523#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 518#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 412#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 507#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 440#L268 assume !(0 != eval_~tmp~0); 442#L316 start_simulation_~kernel_st~0 := 2; 555#L206-1 start_simulation_~kernel_st~0 := 3; 430#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 431#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 504#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 418#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 419#L341-3 assume !(0 == ~E_2~0); 438#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 476#L148-9 assume 1 == ~m_pc~0; 477#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 490#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 571#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 576#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 465#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 466#L167-9 assume 1 == ~t1_pc~0; 541#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 485#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 401#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 402#L405-9 assume !(0 != activate_threads_~tmp___0~0); 444#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 445#L186-9 assume 1 == ~t2_pc~0; 467#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 406#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 506#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 482#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 455#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 456#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 551#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 549#L369-3 assume !(1 == ~E_1~0); 501#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 502#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 538#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 446#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 413#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 414#L539 assume !(0 == start_simulation_~tmp~3); 499#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 505#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 470#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 457#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 458#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 497#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 491#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 492#L552 assume !(0 != start_simulation_~tmp___0~1); 428#L520-1 [2021-10-28 23:19:04,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2021-10-28 23:19:04,716 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,716 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396365955] [2021-10-28 23:19:04,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,716 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:04,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:04,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:04,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:04,765 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396365955] [2021-10-28 23:19:04,765 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [396365955] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:04,766 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:04,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:04,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184549364] [2021-10-28 23:19:04,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:19:04,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,768 INFO L85 PathProgramCache]: Analyzing trace with hash -2087706241, now seen corresponding path program 1 times [2021-10-28 23:19:04,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015073773] [2021-10-28 23:19:04,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,769 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:04,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:04,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:04,827 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:04,828 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015073773] [2021-10-28 23:19:04,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015073773] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:04,828 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:04,829 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:04,829 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352426740] [2021-10-28 23:19:04,830 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:04,830 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:04,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:04,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:04,832 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:04,856 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2021-10-28 23:19:04,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:04,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2021-10-28 23:19:04,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 23:19:04,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2021-10-28 23:19:04,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-10-28 23:19:04,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-10-28 23:19:04,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2021-10-28 23:19:04,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:04,869 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 23:19:04,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2021-10-28 23:19:04,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-10-28 23:19:04,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.5053763440860215) internal successors, (280), 185 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:04,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2021-10-28 23:19:04,899 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 23:19:04,900 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-10-28 23:19:04,900 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 23:19:04,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2021-10-28 23:19:04,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-10-28 23:19:04,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:04,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:04,909 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,909 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:04,909 INFO L791 eck$LassoCheckResult]: Stem: 953#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 869#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 870#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 848#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 849#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 775#L223-1 assume !(0 == ~M_E~0); 776#L326-1 assume !(0 == ~T1_E~0); 828#L331-1 assume !(0 == ~T2_E~0); 780#L336-1 assume !(0 == ~E_1~0); 781#L341-1 assume !(0 == ~E_2~0); 826#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 827#L148 assume !(1 == ~m_pc~0); 841#L148-2 is_master_triggered_~__retres1~0 := 0; 862#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 920#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 939#L397 assume !(0 != activate_threads_~tmp~1); 811#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 812#L167 assume 1 == ~t1_pc~0; 777#L168 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 778#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 838#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 931#L405 assume !(0 != activate_threads_~tmp___0~0); 905#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 906#L186 assume !(1 == ~t2_pc~0); 788#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 789#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 913#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 914#L413 assume !(0 != activate_threads_~tmp___1~0); 941#L413-2 assume !(1 == ~M_E~0); 937#L359-1 assume !(1 == ~T1_E~0); 867#L364-1 assume !(1 == ~T2_E~0); 868#L369-1 assume !(1 == ~E_1~0); 879#L374-1 assume !(1 == ~E_2~0); 807#L520-1 [2021-10-28 23:19:04,910 INFO L793 eck$LassoCheckResult]: Loop: 807#L520-1 assume !false; 808#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 909#L301 assume !false; 902#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 897#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 791#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 885#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 819#L268 assume !(0 != eval_~tmp~0); 821#L316 start_simulation_~kernel_st~0 := 2; 932#L206-1 start_simulation_~kernel_st~0 := 3; 809#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 810#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 883#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 797#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 798#L341-3 assume !(0 == ~E_2~0); 817#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 855#L148-9 assume 1 == ~m_pc~0; 856#L149-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 871#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 950#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 955#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 844#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 845#L167-9 assume 1 == ~t1_pc~0; 921#L168-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 864#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 782#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 783#L405-9 assume !(0 != activate_threads_~tmp___0~0); 823#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 824#L186-9 assume !(1 == ~t2_pc~0); 784#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 785#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 886#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 861#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 834#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 835#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 930#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 928#L369-3 assume !(1 == ~E_1~0); 880#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 881#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 917#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 825#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 792#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 793#L539 assume !(0 == start_simulation_~tmp~3); 878#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 884#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 851#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 836#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 837#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 876#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 872#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 873#L552 assume !(0 != start_simulation_~tmp___0~1); 807#L520-1 [2021-10-28 23:19:04,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,911 INFO L85 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2021-10-28 23:19:04,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,912 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560513833] [2021-10-28 23:19:04,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,912 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:04,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:04,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:04,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:04,977 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560513833] [2021-10-28 23:19:04,978 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560513833] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:04,978 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:04,978 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:04,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217479594] [2021-10-28 23:19:04,979 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:19:04,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:04,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1307725312, now seen corresponding path program 1 times [2021-10-28 23:19:04,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:04,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566676009] [2021-10-28 23:19:04,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:04,981 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:05,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:05,063 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:05,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566676009] [2021-10-28 23:19:05,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566676009] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:05,065 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:05,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:05,067 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102126585] [2021-10-28 23:19:05,067 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:05,068 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:05,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:19:05,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:19:05,069 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:05,197 INFO L93 Difference]: Finished difference Result 441 states and 644 transitions. [2021-10-28 23:19:05,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:19:05,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 644 transitions. [2021-10-28 23:19:05,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 377 [2021-10-28 23:19:05,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 441 states and 644 transitions. [2021-10-28 23:19:05,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 [2021-10-28 23:19:05,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 [2021-10-28 23:19:05,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 441 states and 644 transitions. [2021-10-28 23:19:05,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:05,212 INFO L681 BuchiCegarLoop]: Abstraction has 441 states and 644 transitions. [2021-10-28 23:19:05,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states and 644 transitions. [2021-10-28 23:19:05,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 403. [2021-10-28 23:19:05,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 403 states, 403 states have (on average 1.478908188585608) internal successors, (596), 402 states have internal predecessors, (596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 596 transitions. [2021-10-28 23:19:05,283 INFO L704 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-10-28 23:19:05,283 INFO L587 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-10-28 23:19:05,283 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 23:19:05,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 596 transitions. [2021-10-28 23:19:05,297 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2021-10-28 23:19:05,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:05,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:05,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,299 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,299 INFO L791 eck$LassoCheckResult]: Stem: 1607#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1509#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1510#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1486#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 1487#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1511#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1412#L223-1 assume !(0 == ~M_E~0); 1413#L326-1 assume !(0 == ~T1_E~0); 1465#L331-1 assume !(0 == ~T2_E~0); 1416#L336-1 assume !(0 == ~E_1~0); 1417#L341-1 assume !(0 == ~E_2~0); 1463#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1464#L148 assume !(1 == ~m_pc~0); 1478#L148-2 is_master_triggered_~__retres1~0 := 0; 1498#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1564#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1582#L397 assume !(0 != activate_threads_~tmp~1); 1445#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1446#L167 assume !(1 == ~t1_pc~0); 1454#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 1470#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1477#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1574#L405 assume !(0 != activate_threads_~tmp___0~0); 1544#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1545#L186 assume !(1 == ~t2_pc~0); 1424#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 1425#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1555#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1556#L413 assume !(0 != activate_threads_~tmp___1~0); 1585#L413-2 assume !(1 == ~M_E~0); 1580#L359-1 assume !(1 == ~T1_E~0); 1502#L364-1 assume !(1 == ~T2_E~0); 1503#L369-1 assume !(1 == ~E_1~0); 1516#L374-1 assume !(1 == ~E_2~0); 1441#L520-1 [2021-10-28 23:19:05,299 INFO L793 eck$LassoCheckResult]: Loop: 1441#L520-1 assume !false; 1442#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1749#L301 assume !false; 1694#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1688#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1684#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1680#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1677#L268 assume !(0 != eval_~tmp~0); 1603#L316 start_simulation_~kernel_st~0 := 2; 1575#L206-1 start_simulation_~kernel_st~0 := 3; 1443#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1444#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1521#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1428#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1429#L341-3 assume !(0 == ~E_2~0); 1772#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1489#L148-9 assume !(1 == ~m_pc~0); 1490#L148-11 is_master_triggered_~__retres1~0 := 0; 1568#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1599#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1615#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1480#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1481#L167-9 assume !(1 == ~t1_pc~0); 1587#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 1499#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1414#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1415#L405-9 assume !(0 != activate_threads_~tmp___0~0); 1458#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1459#L186-9 assume 1 == ~t2_pc~0; 1482#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1419#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1524#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1496#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1471#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 1472#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1573#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1571#L369-3 assume !(1 == ~E_1~0); 1517#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1518#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1616#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1461#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1462#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1756#L539 assume !(0 == start_simulation_~tmp~3); 1515#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1770#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1767#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1473#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1474#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1513#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 1507#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1508#L552 assume !(0 != start_simulation_~tmp___0~1); 1441#L520-1 [2021-10-28 23:19:05,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,300 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2021-10-28 23:19:05,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,301 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682284673] [2021-10-28 23:19:05,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,313 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:05,345 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:05,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:05,417 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:05,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,422 INFO L85 PathProgramCache]: Analyzing trace with hash -2007931839, now seen corresponding path program 1 times [2021-10-28 23:19:05,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,422 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188943418] [2021-10-28 23:19:05,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,424 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:05,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:05,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:05,494 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188943418] [2021-10-28 23:19:05,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188943418] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:05,503 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:05,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:05,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810523508] [2021-10-28 23:19:05,505 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:05,505 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:05,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:05,506 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:05,506 INFO L87 Difference]: Start difference. First operand 403 states and 596 transitions. cyclomatic complexity: 195 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:05,564 INFO L93 Difference]: Finished difference Result 570 states and 836 transitions. [2021-10-28 23:19:05,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:05,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 570 states and 836 transitions. [2021-10-28 23:19:05,576 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2021-10-28 23:19:05,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 570 states to 570 states and 836 transitions. [2021-10-28 23:19:05,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 570 [2021-10-28 23:19:05,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 570 [2021-10-28 23:19:05,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 570 states and 836 transitions. [2021-10-28 23:19:05,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:05,586 INFO L681 BuchiCegarLoop]: Abstraction has 570 states and 836 transitions. [2021-10-28 23:19:05,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states and 836 transitions. [2021-10-28 23:19:05,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 568. [2021-10-28 23:19:05,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 568 states, 568 states have (on average 1.4683098591549295) internal successors, (834), 567 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 834 transitions. [2021-10-28 23:19:05,617 INFO L704 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-10-28 23:19:05,618 INFO L587 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-10-28 23:19:05,618 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 23:19:05,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 568 states and 834 transitions. [2021-10-28 23:19:05,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 504 [2021-10-28 23:19:05,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:05,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:05,624 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,624 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,624 INFO L791 eck$LassoCheckResult]: Stem: 2601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2491#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2492#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2467#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 2468#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2493#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2391#L223-1 assume !(0 == ~M_E~0); 2392#L326-1 assume !(0 == ~T1_E~0); 2445#L331-1 assume !(0 == ~T2_E~0); 2395#L336-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2396#L341-1 assume !(0 == ~E_2~0); 2443#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2444#L148 assume !(1 == ~m_pc~0); 2458#L148-2 is_master_triggered_~__retres1~0 := 0; 2480#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2545#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2567#L397 assume !(0 != activate_threads_~tmp~1); 2426#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2427#L167 assume !(1 == ~t1_pc~0); 2435#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 2450#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2457#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2555#L405 assume !(0 != activate_threads_~tmp___0~0); 2525#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2526#L186 assume !(1 == ~t2_pc~0); 2404#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 2405#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2538#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2539#L413 assume !(0 != activate_threads_~tmp___1~0); 2570#L413-2 assume !(1 == ~M_E~0); 2565#L359-1 assume !(1 == ~T1_E~0); 2484#L364-1 assume !(1 == ~T2_E~0); 2485#L369-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2499#L374-1 assume !(1 == ~E_2~0); 2494#L520-1 [2021-10-28 23:19:05,625 INFO L793 eck$LassoCheckResult]: Loop: 2494#L520-1 assume !false; 2730#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2729#L301 assume !false; 2727#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2725#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2723#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2721#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2719#L268 assume !(0 != eval_~tmp~0); 2594#L316 start_simulation_~kernel_st~0 := 2; 2557#L206-1 start_simulation_~kernel_st~0 := 3; 2424#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2425#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2503#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2408#L336-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2409#L341-3 assume !(0 == ~E_2~0); 2433#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2509#L148-9 assume !(1 == ~m_pc~0); 2952#L148-11 is_master_triggered_~__retres1~0 := 0; 2951#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2950#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2918#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2914#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2909#L167-9 assume !(1 == ~t1_pc~0); 2906#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 2902#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2899#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2896#L405-9 assume !(0 != activate_threads_~tmp___0~0); 2440#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2441#L186-9 assume 1 == ~t2_pc~0; 2883#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2879#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2876#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2477#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2451#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2452#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2553#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2552#L369-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2500#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2501#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2540#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2442#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2406#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2407#L539 assume !(0 == start_simulation_~tmp~3); 2498#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2504#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2466#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2453#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2454#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2496#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 2486#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2487#L552 assume !(0 != start_simulation_~tmp___0~1); 2494#L520-1 [2021-10-28 23:19:05,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,626 INFO L85 PathProgramCache]: Analyzing trace with hash 713469919, now seen corresponding path program 1 times [2021-10-28 23:19:05,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,627 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370200445] [2021-10-28 23:19:05,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,627 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:05,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:05,692 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:05,693 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370200445] [2021-10-28 23:19:05,693 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370200445] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:05,693 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:05,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:19:05,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112702491] [2021-10-28 23:19:05,694 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:19:05,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,695 INFO L85 PathProgramCache]: Analyzing trace with hash -728068161, now seen corresponding path program 1 times [2021-10-28 23:19:05,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,696 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054839998] [2021-10-28 23:19:05,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,696 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:05,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:05,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:05,748 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054839998] [2021-10-28 23:19:05,748 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054839998] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:05,748 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:05,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:19:05,749 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242004927] [2021-10-28 23:19:05,749 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:05,749 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:05,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:05,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:05,750 INFO L87 Difference]: Start difference. First operand 568 states and 834 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 2 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:05,774 INFO L93 Difference]: Finished difference Result 402 states and 580 transitions. [2021-10-28 23:19:05,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:05,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402 states and 580 transitions. [2021-10-28 23:19:05,778 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-10-28 23:19:05,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402 states to 402 states and 580 transitions. [2021-10-28 23:19:05,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402 [2021-10-28 23:19:05,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 402 [2021-10-28 23:19:05,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 402 states and 580 transitions. [2021-10-28 23:19:05,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:05,784 INFO L681 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 23:19:05,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states and 580 transitions. [2021-10-28 23:19:05,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 402. [2021-10-28 23:19:05,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 402 states have (on average 1.4427860696517414) internal successors, (580), 401 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 580 transitions. [2021-10-28 23:19:05,794 INFO L704 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 23:19:05,795 INFO L587 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-10-28 23:19:05,795 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 23:19:05,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402 states and 580 transitions. [2021-10-28 23:19:05,798 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-10-28 23:19:05,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:05,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:05,799 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,799 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:05,799 INFO L791 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3465#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3466#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3442#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 3443#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3467#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3370#L223-1 assume !(0 == ~M_E~0); 3371#L326-1 assume !(0 == ~T1_E~0); 3421#L331-1 assume !(0 == ~T2_E~0); 3374#L336-1 assume !(0 == ~E_1~0); 3375#L341-1 assume !(0 == ~E_2~0); 3419#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3420#L148 assume !(1 == ~m_pc~0); 3434#L148-2 is_master_triggered_~__retres1~0 := 0; 3453#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3517#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3537#L397 assume !(0 != activate_threads_~tmp~1); 3403#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3404#L167 assume !(1 == ~t1_pc~0); 3411#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 3426#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3433#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3527#L405 assume !(0 != activate_threads_~tmp___0~0); 3499#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3500#L186 assume !(1 == ~t2_pc~0); 3382#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 3383#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3510#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3511#L413 assume !(0 != activate_threads_~tmp___1~0); 3539#L413-2 assume !(1 == ~M_E~0); 3535#L359-1 assume !(1 == ~T1_E~0); 3458#L364-1 assume !(1 == ~T2_E~0); 3459#L369-1 assume !(1 == ~E_1~0); 3473#L374-1 assume !(1 == ~E_2~0); 3542#L520-1 [2021-10-28 23:19:05,800 INFO L793 eck$LassoCheckResult]: Loop: 3542#L520-1 assume !false; 3738#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3737#L301 assume !false; 3726#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3724#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3532#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3480#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3412#L268 assume !(0 != eval_~tmp~0); 3414#L316 start_simulation_~kernel_st~0 := 2; 3528#L206-1 start_simulation_~kernel_st~0 := 3; 3401#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3402#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3477#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3389#L336-3 assume !(0 == ~E_1~0); 3390#L341-3 assume !(0 == ~E_2~0); 3409#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3447#L148-9 assume !(1 == ~m_pc~0); 3448#L148-11 is_master_triggered_~__retres1~0 := 0; 3521#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3553#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3566#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3437#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3438#L167-9 assume !(1 == ~t1_pc~0); 3540#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 3455#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3372#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3373#L405-9 assume !(0 != activate_threads_~tmp___0~0); 3415#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3416#L186-9 assume !(1 == ~t2_pc~0); 3376#L186-11 is_transmit2_triggered_~__retres1~2 := 0; 3377#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3479#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3452#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3427#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3428#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3526#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3524#L369-3 assume !(1 == ~E_1~0); 3474#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3475#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3512#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3418#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3384#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3385#L539 assume !(0 == start_simulation_~tmp~3); 3472#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3478#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3441#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3429#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3430#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3470#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 3463#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3464#L552 assume !(0 != start_simulation_~tmp___0~1); 3542#L520-1 [2021-10-28 23:19:05,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,800 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2021-10-28 23:19:05,801 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,801 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436542931] [2021-10-28 23:19:05,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,801 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:05,812 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:05,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:05,830 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:05,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:05,831 INFO L85 PathProgramCache]: Analyzing trace with hash 2037657088, now seen corresponding path program 1 times [2021-10-28 23:19:05,831 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:05,831 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614023088] [2021-10-28 23:19:05,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:05,832 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:05,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:05,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:05,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:05,874 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614023088] [2021-10-28 23:19:05,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614023088] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:05,874 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:05,874 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:19:05,875 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933805908] [2021-10-28 23:19:05,876 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:05,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:05,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:19:05,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:19:05,878 INFO L87 Difference]: Start difference. First operand 402 states and 580 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.2) internal successors, (51), 5 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:05,963 INFO L93 Difference]: Finished difference Result 670 states and 947 transitions. [2021-10-28 23:19:05,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 23:19:05,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 670 states and 947 transitions. [2021-10-28 23:19:05,970 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2021-10-28 23:19:05,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 670 states to 670 states and 947 transitions. [2021-10-28 23:19:05,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 670 [2021-10-28 23:19:05,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 670 [2021-10-28 23:19:05,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 670 states and 947 transitions. [2021-10-28 23:19:05,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:05,982 INFO L681 BuchiCegarLoop]: Abstraction has 670 states and 947 transitions. [2021-10-28 23:19:05,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 670 states and 947 transitions. [2021-10-28 23:19:05,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 670 to 411. [2021-10-28 23:19:05,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.4330900243309002) internal successors, (589), 410 states have internal predecessors, (589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:05,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 589 transitions. [2021-10-28 23:19:05,995 INFO L704 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-10-28 23:19:05,998 INFO L587 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-10-28 23:19:05,998 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 23:19:05,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 589 transitions. [2021-10-28 23:19:06,001 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 371 [2021-10-28 23:19:06,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:06,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:06,004 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,006 INFO L791 eck$LassoCheckResult]: Stem: 4659#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4557#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4558#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4533#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 4534#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4559#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4458#L223-1 assume !(0 == ~M_E~0); 4459#L326-1 assume !(0 == ~T1_E~0); 4510#L331-1 assume !(0 == ~T2_E~0); 4462#L336-1 assume !(0 == ~E_1~0); 4463#L341-1 assume !(0 == ~E_2~0); 4508#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4509#L148 assume !(1 == ~m_pc~0); 4523#L148-2 is_master_triggered_~__retres1~0 := 0; 4545#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4611#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4635#L397 assume !(0 != activate_threads_~tmp~1); 4492#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4493#L167 assume !(1 == ~t1_pc~0); 4501#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 4515#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4522#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4623#L405 assume !(0 != activate_threads_~tmp___0~0); 4595#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4596#L186 assume !(1 == ~t2_pc~0); 4471#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 4472#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4603#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4604#L413 assume !(0 != activate_threads_~tmp___1~0); 4638#L413-2 assume !(1 == ~M_E~0); 4632#L359-1 assume !(1 == ~T1_E~0); 4550#L364-1 assume !(1 == ~T2_E~0); 4551#L369-1 assume !(1 == ~E_1~0); 4564#L374-1 assume !(1 == ~E_2~0); 4488#L520-1 [2021-10-28 23:19:06,006 INFO L793 eck$LassoCheckResult]: Loop: 4488#L520-1 assume !false; 4489#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4796#L301 assume !false; 4591#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4585#L236 assume !(0 == ~m_st~0); 4511#L240 assume !(0 == ~t1_st~0); 4468#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4469#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4692#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4689#L268 assume !(0 != eval_~tmp~0); 4690#L316 start_simulation_~kernel_st~0 := 2; 4624#L206-1 start_simulation_~kernel_st~0 := 3; 4625#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4740#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4569#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4570#L336-3 assume !(0 == ~E_1~0); 4498#L341-3 assume !(0 == ~E_2~0); 4499#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4538#L148-9 assume !(1 == ~m_pc~0); 4539#L148-11 is_master_triggered_~__retres1~0 := 0; 4794#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4793#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4792#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4791#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4790#L167-9 assume !(1 == ~t1_pc~0); 4789#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 4788#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4787#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4786#L405-9 assume !(0 != activate_threads_~tmp___0~0); 4785#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4525#L186-9 assume 1 == ~t2_pc~0; 4526#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4573#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4574#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4784#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4516#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 4517#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4783#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4782#L369-3 assume !(1 == ~E_1~0); 4565#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4566#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4668#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4507#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4473#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4474#L539 assume !(0 == start_simulation_~tmp~3); 4567#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4829#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4825#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4518#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4519#L494 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4561#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 4552#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4553#L552 assume !(0 != start_simulation_~tmp___0~1); 4488#L520-1 [2021-10-28 23:19:06,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,009 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2021-10-28 23:19:06,009 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,009 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452902480] [2021-10-28 23:19:06,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,010 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,040 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,061 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:06,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,065 INFO L85 PathProgramCache]: Analyzing trace with hash 805723206, now seen corresponding path program 1 times [2021-10-28 23:19:06,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,073 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097627258] [2021-10-28 23:19:06,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,075 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:06,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:06,134 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:06,134 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097627258] [2021-10-28 23:19:06,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097627258] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:06,135 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:06,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:19:06,135 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837920612] [2021-10-28 23:19:06,137 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:06,137 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:06,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:19:06,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:19:06,138 INFO L87 Difference]: Start difference. First operand 411 states and 589 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:06,235 INFO L93 Difference]: Finished difference Result 1194 states and 1698 transitions. [2021-10-28 23:19:06,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 23:19:06,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1698 transitions. [2021-10-28 23:19:06,263 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1139 [2021-10-28 23:19:06,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1698 transitions. [2021-10-28 23:19:06,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2021-10-28 23:19:06,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2021-10-28 23:19:06,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1698 transitions. [2021-10-28 23:19:06,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:06,277 INFO L681 BuchiCegarLoop]: Abstraction has 1194 states and 1698 transitions. [2021-10-28 23:19:06,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1698 transitions. [2021-10-28 23:19:06,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 420. [2021-10-28 23:19:06,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 420 states, 420 states have (on average 1.4238095238095239) internal successors, (598), 419 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 598 transitions. [2021-10-28 23:19:06,293 INFO L704 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-10-28 23:19:06,293 INFO L587 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-10-28 23:19:06,293 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 23:19:06,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 420 states and 598 transitions. [2021-10-28 23:19:06,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 380 [2021-10-28 23:19:06,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:06,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:06,297 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,297 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,298 INFO L791 eck$LassoCheckResult]: Stem: 6296#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6179#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6180#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6156#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 6157#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6184#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6080#L223-1 assume !(0 == ~M_E~0); 6081#L326-1 assume !(0 == ~T1_E~0); 6132#L331-1 assume !(0 == ~T2_E~0); 6082#L336-1 assume !(0 == ~E_1~0); 6083#L341-1 assume !(0 == ~E_2~0); 6130#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6131#L148 assume !(1 == ~m_pc~0); 6148#L148-2 is_master_triggered_~__retres1~0 := 0; 6171#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6241#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6268#L397 assume !(0 != activate_threads_~tmp~1); 6114#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6115#L167 assume !(1 == ~t1_pc~0); 6122#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 6138#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6145#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6255#L405 assume !(0 != activate_threads_~tmp___0~0); 6225#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6226#L186 assume !(1 == ~t2_pc~0); 6090#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 6091#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6233#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6234#L413 assume !(0 != activate_threads_~tmp___1~0); 6270#L413-2 assume !(1 == ~M_E~0); 6264#L359-1 assume !(1 == ~T1_E~0); 6177#L364-1 assume !(1 == ~T2_E~0); 6178#L369-1 assume !(1 == ~E_1~0); 6192#L374-1 assume !(1 == ~E_2~0); 6185#L520-1 [2021-10-28 23:19:06,298 INFO L793 eck$LassoCheckResult]: Loop: 6185#L520-1 assume !false; 6434#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6433#L301 assume !false; 6220#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6221#L236 assume !(0 == ~m_st~0); 6432#L240 assume !(0 == ~t1_st~0); 6092#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6093#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6198#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6199#L268 assume !(0 != eval_~tmp~0); 6420#L316 start_simulation_~kernel_st~0 := 2; 6256#L206-1 start_simulation_~kernel_st~0 := 3; 6257#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6300#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6301#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6473#L336-3 assume !(0 == ~E_1~0); 6120#L341-3 assume !(0 == ~E_2~0); 6121#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6472#L148-9 assume !(1 == ~m_pc~0); 6471#L148-11 is_master_triggered_~__retres1~0 := 0; 6286#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6287#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6306#L397-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6307#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6272#L167-9 assume !(1 == ~t1_pc~0); 6273#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 6470#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6084#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6085#L405-9 assume !(0 != activate_threads_~tmp___0~0); 6469#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6152#L186-9 assume 1 == ~t2_pc~0; 6153#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6200#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6201#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6468#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6467#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 6276#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6277#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6250#L369-3 assume !(1 == ~E_1~0); 6251#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6237#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6238#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6129#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6095#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6096#L539 assume !(0 == start_simulation_~tmp~3); 6191#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6197#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6159#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6303#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 6440#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6189#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 6182#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6183#L552 assume !(0 != start_simulation_~tmp___0~1); 6185#L520-1 [2021-10-28 23:19:06,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,298 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2021-10-28 23:19:06,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,299 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436186743] [2021-10-28 23:19:06,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,299 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,307 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,322 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:06,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,323 INFO L85 PathProgramCache]: Analyzing trace with hash 805663624, now seen corresponding path program 1 times [2021-10-28 23:19:06,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,324 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543653794] [2021-10-28 23:19:06,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,324 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:06,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:06,380 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:06,380 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543653794] [2021-10-28 23:19:06,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543653794] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:06,380 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:06,381 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:19:06,381 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371001349] [2021-10-28 23:19:06,381 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:06,381 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:06,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:19:06,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:19:06,382 INFO L87 Difference]: Start difference. First operand 420 states and 598 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:06,483 INFO L93 Difference]: Finished difference Result 921 states and 1298 transitions. [2021-10-28 23:19:06,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 23:19:06,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 921 states and 1298 transitions. [2021-10-28 23:19:06,492 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2021-10-28 23:19:06,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 921 states to 921 states and 1298 transitions. [2021-10-28 23:19:06,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 921 [2021-10-28 23:19:06,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 921 [2021-10-28 23:19:06,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 921 states and 1298 transitions. [2021-10-28 23:19:06,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:06,504 INFO L681 BuchiCegarLoop]: Abstraction has 921 states and 1298 transitions. [2021-10-28 23:19:06,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 921 states and 1298 transitions. [2021-10-28 23:19:06,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 921 to 441. [2021-10-28 23:19:06,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 441 states have (on average 1.3968253968253967) internal successors, (616), 440 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 616 transitions. [2021-10-28 23:19:06,517 INFO L704 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-10-28 23:19:06,517 INFO L587 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-10-28 23:19:06,517 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 23:19:06,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 616 transitions. [2021-10-28 23:19:06,520 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 401 [2021-10-28 23:19:06,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:06,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:06,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,522 INFO L791 eck$LassoCheckResult]: Stem: 7635#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7526#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7527#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7504#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 7505#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7533#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7434#L223-1 assume !(0 == ~M_E~0); 7435#L326-1 assume !(0 == ~T1_E~0); 7485#L331-1 assume !(0 == ~T2_E~0); 7436#L336-1 assume !(0 == ~E_1~0); 7437#L341-1 assume !(0 == ~E_2~0); 7483#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7484#L148 assume !(1 == ~m_pc~0); 7498#L148-2 is_master_triggered_~__retres1~0 := 0; 7519#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7585#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7607#L397 assume !(0 != activate_threads_~tmp~1); 7468#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7469#L167 assume !(1 == ~t1_pc~0); 7475#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 7489#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7495#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7598#L405 assume !(0 != activate_threads_~tmp___0~0); 7568#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7569#L186 assume !(1 == ~t2_pc~0); 7444#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 7445#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7578#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7579#L413 assume !(0 != activate_threads_~tmp___1~0); 7609#L413-2 assume !(1 == ~M_E~0); 7604#L359-1 assume !(1 == ~T1_E~0); 7524#L364-1 assume !(1 == ~T2_E~0); 7525#L369-1 assume !(1 == ~E_1~0); 7538#L374-1 assume !(1 == ~E_2~0); 7614#L520-1 [2021-10-28 23:19:06,522 INFO L793 eck$LassoCheckResult]: Loop: 7614#L520-1 assume !false; 7674#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7673#L301 assume !false; 7672#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7671#L236 assume !(0 == ~m_st~0); 7670#L240 assume !(0 == ~t1_st~0); 7668#L244 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 7667#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7666#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7664#L268 assume !(0 != eval_~tmp~0); 7663#L316 start_simulation_~kernel_st~0 := 2; 7662#L206-1 start_simulation_~kernel_st~0 := 3; 7661#L326-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7660#L326-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7659#L331-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7658#L336-3 assume !(0 == ~E_1~0); 7657#L341-3 assume !(0 == ~E_2~0); 7656#L346-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7513#L148-9 assume !(1 == ~m_pc~0); 7514#L148-11 is_master_triggered_~__retres1~0 := 0; 7742#L159-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7741#L160-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7740#L397-9 assume !(0 != activate_threads_~tmp~1); 7739#L397-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7738#L167-9 assume !(1 == ~t1_pc~0); 7736#L167-11 is_transmit1_triggered_~__retres1~1 := 0; 7734#L178-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7732#L179-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7730#L405-9 assume !(0 != activate_threads_~tmp___0~0); 7728#L405-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7726#L186-9 assume 1 == ~t2_pc~0; 7723#L187-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7721#L197-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7719#L198-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7717#L413-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7715#L413-11 assume 1 == ~M_E~0;~M_E~0 := 2; 7712#L359-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7710#L364-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7708#L369-3 assume !(1 == ~E_1~0); 7706#L374-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7704#L379-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7702#L236-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7698#L253-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7696#L254-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7695#L539 assume !(0 == start_simulation_~tmp~3); 7693#L539-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7692#L236-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7688#L253-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7686#L254-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7685#L494 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7683#L501 stop_simulation_#res := stop_simulation_~__retres2~0; 7682#L502 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7680#L552 assume !(0 != start_simulation_~tmp___0~1); 7614#L520-1 [2021-10-28 23:19:06,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,523 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 5 times [2021-10-28 23:19:06,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,523 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855223918] [2021-10-28 23:19:06,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,524 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,546 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:06,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1507263498, now seen corresponding path program 1 times [2021-10-28 23:19:06,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,547 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724275466] [2021-10-28 23:19:06,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,548 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:06,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:06,570 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:06,570 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724275466] [2021-10-28 23:19:06,570 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724275466] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:06,570 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:06,571 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:06,571 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510379380] [2021-10-28 23:19:06,571 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:19:06,571 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:06,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:06,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:06,572 INFO L87 Difference]: Start difference. First operand 441 states and 616 transitions. cyclomatic complexity: 177 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:06,604 INFO L93 Difference]: Finished difference Result 675 states and 925 transitions. [2021-10-28 23:19:06,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:06,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 675 states and 925 transitions. [2021-10-28 23:19:06,610 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 633 [2021-10-28 23:19:06,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 675 states to 675 states and 925 transitions. [2021-10-28 23:19:06,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 675 [2021-10-28 23:19:06,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 675 [2021-10-28 23:19:06,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 675 states and 925 transitions. [2021-10-28 23:19:06,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:06,619 INFO L681 BuchiCegarLoop]: Abstraction has 675 states and 925 transitions. [2021-10-28 23:19:06,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 675 states and 925 transitions. [2021-10-28 23:19:06,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 675 to 643. [2021-10-28 23:19:06,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 643 states, 643 states have (on average 1.374805598755832) internal successors, (884), 642 states have internal predecessors, (884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 884 transitions. [2021-10-28 23:19:06,634 INFO L704 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-10-28 23:19:06,634 INFO L587 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-10-28 23:19:06,634 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 23:19:06,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states and 884 transitions. [2021-10-28 23:19:06,638 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 601 [2021-10-28 23:19:06,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:06,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:06,639 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,639 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,640 INFO L791 eck$LassoCheckResult]: Stem: 8753#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8652#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8653#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8629#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 8630#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8654#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8556#L223-1 assume !(0 == ~M_E~0); 8557#L326-1 assume !(0 == ~T1_E~0); 8607#L331-1 assume !(0 == ~T2_E~0); 8558#L336-1 assume !(0 == ~E_1~0); 8559#L341-1 assume !(0 == ~E_2~0); 8605#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8606#L148 assume !(1 == ~m_pc~0); 8620#L148-2 is_master_triggered_~__retres1~0 := 0; 8640#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8706#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8730#L397 assume !(0 != activate_threads_~tmp~1); 8590#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8591#L167 assume !(1 == ~t1_pc~0); 8597#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 8612#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8619#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8719#L405 assume !(0 != activate_threads_~tmp___0~0); 8688#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8689#L186 assume !(1 == ~t2_pc~0); 8566#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 8567#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8699#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8700#L413 assume !(0 != activate_threads_~tmp___1~0); 8732#L413-2 assume !(1 == ~M_E~0); 8727#L359-1 assume !(1 == ~T1_E~0); 8645#L364-1 assume !(1 == ~T2_E~0); 8646#L369-1 assume !(1 == ~E_1~0); 8659#L374-1 assume !(1 == ~E_2~0); 8737#L520-1 assume !false; 8890#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 8886#L301 [2021-10-28 23:19:06,640 INFO L793 eck$LassoCheckResult]: Loop: 8886#L301 assume !false; 8883#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8879#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 8876#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8873#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8870#L268 assume 0 != eval_~tmp~0; 8867#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 8551#L276 assume !(0 != eval_~tmp_ndt_1~0); 8553#L273 assume !(0 == ~t1_st~0); 8893#L287 assume !(0 == ~t2_st~0); 8886#L301 [2021-10-28 23:19:06,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,641 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2021-10-28 23:19:06,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,641 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084228319] [2021-10-28 23:19:06,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,641 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,649 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,663 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:06,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1206180399, now seen corresponding path program 1 times [2021-10-28 23:19:06,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687926895] [2021-10-28 23:19:06,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,664 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,667 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,671 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:06,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,672 INFO L85 PathProgramCache]: Analyzing trace with hash 202160337, now seen corresponding path program 1 times [2021-10-28 23:19:06,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,673 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352555389] [2021-10-28 23:19:06,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,673 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:06,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:06,697 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:06,697 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352555389] [2021-10-28 23:19:06,697 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352555389] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:06,697 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:06,697 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:06,698 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124883053] [2021-10-28 23:19:06,764 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:06,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:06,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:06,765 INFO L87 Difference]: Start difference. First operand 643 states and 884 transitions. cyclomatic complexity: 244 Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:06,827 INFO L93 Difference]: Finished difference Result 1127 states and 1531 transitions. [2021-10-28 23:19:06,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:06,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1127 states and 1531 transitions. [2021-10-28 23:19:06,837 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 995 [2021-10-28 23:19:06,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1127 states to 1127 states and 1531 transitions. [2021-10-28 23:19:06,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1127 [2021-10-28 23:19:06,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1127 [2021-10-28 23:19:06,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1127 states and 1531 transitions. [2021-10-28 23:19:06,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:06,866 INFO L681 BuchiCegarLoop]: Abstraction has 1127 states and 1531 transitions. [2021-10-28 23:19:06,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1127 states and 1531 transitions. [2021-10-28 23:19:06,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1127 to 1058. [2021-10-28 23:19:06,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1058 states, 1058 states have (on average 1.3648393194706994) internal successors, (1444), 1057 states have internal predecessors, (1444), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:06,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1058 states to 1058 states and 1444 transitions. [2021-10-28 23:19:06,921 INFO L704 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-10-28 23:19:06,921 INFO L587 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-10-28 23:19:06,921 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 23:19:06,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1058 states and 1444 transitions. [2021-10-28 23:19:06,927 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2021-10-28 23:19:06,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:06,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:06,936 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,936 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:06,936 INFO L791 eck$LassoCheckResult]: Stem: 10557#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10430#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10431#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10408#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 10409#L213-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 10551#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11304#L223-1 assume !(0 == ~M_E~0); 11303#L326-1 assume !(0 == ~T1_E~0); 11302#L331-1 assume !(0 == ~T2_E~0); 11301#L336-1 assume !(0 == ~E_1~0); 11300#L341-1 assume !(0 == ~E_2~0); 11299#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11298#L148 assume !(1 == ~m_pc~0); 11297#L148-2 is_master_triggered_~__retres1~0 := 0; 11296#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11295#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11294#L397 assume !(0 != activate_threads_~tmp~1); 11293#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11292#L167 assume !(1 == ~t1_pc~0); 11291#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 11290#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11289#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11288#L405 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10476#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10477#L186 assume !(1 == ~t2_pc~0); 10344#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 10345#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10485#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10486#L413 assume !(0 != activate_threads_~tmp___1~0); 10523#L413-2 assume !(1 == ~M_E~0); 10524#L359-1 assume !(1 == ~T1_E~0); 11278#L364-1 assume !(1 == ~T2_E~0); 10443#L369-1 assume !(1 == ~E_1~0); 10444#L374-1 assume !(1 == ~E_2~0); 10530#L520-1 assume !false; 11245#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11243#L301 [2021-10-28 23:19:06,936 INFO L793 eck$LassoCheckResult]: Loop: 11243#L301 assume !false; 11241#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11239#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11238#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11237#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11235#L268 assume 0 != eval_~tmp~0; 11066#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 11067#L276 assume !(0 != eval_~tmp_ndt_1~0); 10794#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 10789#L290 assume !(0 != eval_~tmp_ndt_2~0); 10790#L287 assume !(0 == ~t2_st~0); 11243#L301 [2021-10-28 23:19:06,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2021-10-28 23:19:06,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810828354] [2021-10-28 23:19:06,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,938 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:06,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:06,971 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:06,971 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810828354] [2021-10-28 23:19:06,971 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810828354] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:06,971 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:06,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:19:06,971 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736723291] [2021-10-28 23:19:06,972 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:19:06,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:06,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 1 times [2021-10-28 23:19:06,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:06,973 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523770059] [2021-10-28 23:19:06,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:06,973 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:06,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,977 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:06,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:06,981 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:07,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:07,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:07,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:07,078 INFO L87 Difference]: Start difference. First operand 1058 states and 1444 transitions. cyclomatic complexity: 390 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:07,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:07,092 INFO L93 Difference]: Finished difference Result 890 states and 1214 transitions. [2021-10-28 23:19:07,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:07,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 890 states and 1214 transitions. [2021-10-28 23:19:07,099 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-10-28 23:19:07,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 890 states to 890 states and 1214 transitions. [2021-10-28 23:19:07,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 890 [2021-10-28 23:19:07,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 890 [2021-10-28 23:19:07,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 890 states and 1214 transitions. [2021-10-28 23:19:07,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:07,109 INFO L681 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 23:19:07,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states and 1214 transitions. [2021-10-28 23:19:07,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 890. [2021-10-28 23:19:07,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 890 states, 890 states have (on average 1.3640449438202247) internal successors, (1214), 889 states have internal predecessors, (1214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:07,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1214 transitions. [2021-10-28 23:19:07,130 INFO L704 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 23:19:07,130 INFO L587 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-10-28 23:19:07,130 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 23:19:07,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 890 states and 1214 transitions. [2021-10-28 23:19:07,136 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-10-28 23:19:07,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:07,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:07,137 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:07,137 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:07,137 INFO L791 eck$LassoCheckResult]: Stem: 12505#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12384#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12385#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12361#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 12362#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12391#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12288#L223-1 assume !(0 == ~M_E~0); 12289#L326-1 assume !(0 == ~T1_E~0); 12340#L331-1 assume !(0 == ~T2_E~0); 12290#L336-1 assume !(0 == ~E_1~0); 12291#L341-1 assume !(0 == ~E_2~0); 12338#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12339#L148 assume !(1 == ~m_pc~0); 12354#L148-2 is_master_triggered_~__retres1~0 := 0; 12377#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12451#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12476#L397 assume !(0 != activate_threads_~tmp~1); 12322#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12323#L167 assume !(1 == ~t1_pc~0); 12330#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 12345#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12351#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12464#L405 assume !(0 != activate_threads_~tmp___0~0); 12431#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12432#L186 assume !(1 == ~t2_pc~0); 12298#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 12299#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12443#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12444#L413 assume !(0 != activate_threads_~tmp___1~0); 12478#L413-2 assume !(1 == ~M_E~0); 12473#L359-1 assume !(1 == ~T1_E~0); 12382#L364-1 assume !(1 == ~T2_E~0); 12383#L369-1 assume !(1 == ~E_1~0); 12398#L374-1 assume !(1 == ~E_2~0); 12484#L520-1 assume !false; 12582#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 12581#L301 [2021-10-28 23:19:07,137 INFO L793 eck$LassoCheckResult]: Loop: 12581#L301 assume !false; 12580#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 12579#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 12578#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 12577#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 12576#L268 assume 0 != eval_~tmp~0; 12575#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 12573#L276 assume !(0 != eval_~tmp_ndt_1~0); 12574#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 12587#L290 assume !(0 != eval_~tmp_ndt_2~0); 12585#L287 assume !(0 == ~t2_st~0); 12581#L301 [2021-10-28 23:19:07,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,139 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2021-10-28 23:19:07,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,139 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003883458] [2021-10-28 23:19:07,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,140 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,150 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:07,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,170 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:07,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,171 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 2 times [2021-10-28 23:19:07,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,171 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181444435] [2021-10-28 23:19:07,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,172 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,177 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:07,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,183 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:07,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1971900397, now seen corresponding path program 1 times [2021-10-28 23:19:07,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,186 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238175195] [2021-10-28 23:19:07,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,186 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:19:07,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:19:07,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:19:07,253 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238175195] [2021-10-28 23:19:07,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238175195] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:19:07,253 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:19:07,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:19:07,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811972444] [2021-10-28 23:19:07,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:19:07,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:19:07,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:19:07,351 INFO L87 Difference]: Start difference. First operand 890 states and 1214 transitions. cyclomatic complexity: 326 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:07,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:19:07,393 INFO L93 Difference]: Finished difference Result 1558 states and 2113 transitions. [2021-10-28 23:19:07,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:19:07,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1558 states and 2113 transitions. [2021-10-28 23:19:07,405 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-10-28 23:19:07,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-10-28 23:19:07,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1558 [2021-10-28 23:19:07,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1558 [2021-10-28 23:19:07,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1558 states and 2113 transitions. [2021-10-28 23:19:07,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:19:07,422 INFO L681 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 23:19:07,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1558 states and 2113 transitions. [2021-10-28 23:19:07,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1558 to 1558. [2021-10-28 23:19:07,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1558 states, 1558 states have (on average 1.3562259306803595) internal successors, (2113), 1557 states have internal predecessors, (2113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:19:07,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-10-28 23:19:07,455 INFO L704 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 23:19:07,455 INFO L587 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-10-28 23:19:07,455 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 23:19:07,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1558 states and 2113 transitions. [2021-10-28 23:19:07,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-10-28 23:19:07,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:19:07,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:19:07,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:07,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:19:07,465 INFO L791 eck$LassoCheckResult]: Stem: 14958#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 14840#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14841#L483 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14817#L206 assume 1 == ~m_i~0;~m_st~0 := 0; 14818#L213-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14847#L218-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14744#L223-1 assume !(0 == ~M_E~0); 14745#L326-1 assume !(0 == ~T1_E~0); 14796#L331-1 assume !(0 == ~T2_E~0); 14746#L336-1 assume !(0 == ~E_1~0); 14747#L341-1 assume !(0 == ~E_2~0); 14794#L346-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14795#L148 assume !(1 == ~m_pc~0); 14811#L148-2 is_master_triggered_~__retres1~0 := 0; 14833#L159 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14902#L160 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14929#L397 assume !(0 != activate_threads_~tmp~1); 14777#L397-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14778#L167 assume !(1 == ~t1_pc~0); 14785#L167-2 is_transmit1_triggered_~__retres1~1 := 0; 14801#L178 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14808#L179 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14915#L405 assume !(0 != activate_threads_~tmp___0~0); 14884#L405-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14885#L186 assume !(1 == ~t2_pc~0); 14754#L186-2 is_transmit2_triggered_~__retres1~2 := 0; 14755#L197 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14895#L198 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14896#L413 assume !(0 != activate_threads_~tmp___1~0); 14931#L413-2 assume !(1 == ~M_E~0); 14925#L359-1 assume !(1 == ~T1_E~0); 14838#L364-1 assume !(1 == ~T2_E~0); 14839#L369-1 assume !(1 == ~E_1~0); 14853#L374-1 assume !(1 == ~E_2~0); 14938#L520-1 assume !false; 16266#L521 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16254#L301 [2021-10-28 23:19:07,465 INFO L793 eck$LassoCheckResult]: Loop: 16254#L301 assume !false; 16255#L264 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16256#L236 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 14922#L253 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 14861#L254 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 14788#L268 assume 0 != eval_~tmp~0; 14789#L268-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 14739#L276 assume !(0 != eval_~tmp_ndt_1~0); 14741#L273 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 15931#L290 assume !(0 != eval_~tmp_ndt_2~0); 15932#L287 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 16248#L304 assume !(0 != eval_~tmp_ndt_3~0); 16254#L301 [2021-10-28 23:19:07,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,466 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2021-10-28 23:19:07,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959851157] [2021-10-28 23:19:07,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,467 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,475 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:07,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,489 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:07,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,490 INFO L85 PathProgramCache]: Analyzing trace with hash 498620433, now seen corresponding path program 1 times [2021-10-28 23:19:07,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363760061] [2021-10-28 23:19:07,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,491 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,496 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:07,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,500 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:07,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:19:07,500 INFO L85 PathProgramCache]: Analyzing trace with hash 999369489, now seen corresponding path program 1 times [2021-10-28 23:19:07,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:19:07,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933625662] [2021-10-28 23:19:07,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:19:07,501 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:19:07,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,513 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:19:07,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:19:07,526 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:19:08,666 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 11:19:08 BoogieIcfgContainer [2021-10-28 23:19:08,666 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 23:19:08,667 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 23:19:08,667 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 23:19:08,667 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 23:19:08,667 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:19:04" (3/4) ... [2021-10-28 23:19:08,670 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 23:19:08,714 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/witness.graphml [2021-10-28 23:19:08,714 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 23:19:08,716 INFO L168 Benchmark]: Toolchain (without parser) took 5764.06 ms. Allocated memory was 104.9 MB in the beginning and 178.3 MB in the end (delta: 73.4 MB). Free memory was 70.9 MB in the beginning and 83.2 MB in the end (delta: -12.3 MB). Peak memory consumption was 60.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,716 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 81.8 MB. Free memory is still 38.0 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 23:19:08,716 INFO L168 Benchmark]: CACSL2BoogieTranslator took 391.76 ms. Allocated memory is still 104.9 MB. Free memory was 70.7 MB in the beginning and 77.2 MB in the end (delta: -6.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,717 INFO L168 Benchmark]: Boogie Procedure Inliner took 58.94 ms. Allocated memory is still 104.9 MB. Free memory was 77.2 MB in the beginning and 74.6 MB in the end (delta: 2.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,717 INFO L168 Benchmark]: Boogie Preprocessor took 43.66 ms. Allocated memory is still 104.9 MB. Free memory was 74.2 MB in the beginning and 72.1 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,718 INFO L168 Benchmark]: RCFGBuilder took 697.55 ms. Allocated memory is still 104.9 MB. Free memory was 72.1 MB in the beginning and 50.3 MB in the end (delta: 21.8 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,718 INFO L168 Benchmark]: BuchiAutomizer took 4518.81 ms. Allocated memory was 104.9 MB in the beginning and 178.3 MB in the end (delta: 73.4 MB). Free memory was 50.3 MB in the beginning and 85.3 MB in the end (delta: -35.0 MB). Peak memory consumption was 61.0 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,719 INFO L168 Benchmark]: Witness Printer took 47.70 ms. Allocated memory is still 178.3 MB. Free memory was 85.3 MB in the beginning and 83.2 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:19:08,721 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 81.8 MB. Free memory is still 38.0 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 391.76 ms. Allocated memory is still 104.9 MB. Free memory was 70.7 MB in the beginning and 77.2 MB in the end (delta: -6.5 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 58.94 ms. Allocated memory is still 104.9 MB. Free memory was 77.2 MB in the beginning and 74.6 MB in the end (delta: 2.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 43.66 ms. Allocated memory is still 104.9 MB. Free memory was 74.2 MB in the beginning and 72.1 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 697.55 ms. Allocated memory is still 104.9 MB. Free memory was 72.1 MB in the beginning and 50.3 MB in the end (delta: 21.8 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 4518.81 ms. Allocated memory was 104.9 MB in the beginning and 178.3 MB in the end (delta: 73.4 MB). Free memory was 50.3 MB in the beginning and 85.3 MB in the end (delta: -35.0 MB). Peak memory consumption was 61.0 MB. Max. memory is 16.1 GB. * Witness Printer took 47.70 ms. Allocated memory is still 178.3 MB. Free memory was 85.3 MB in the beginning and 83.2 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1558 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.4s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 2.8s. Construction of modules took 0.3s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 1654 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 1558 states and ocurred in iteration 12. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 3637 SDtfs, 4123 SDslu, 4299 SDs, 0 SdLazy, 293 SolverSat, 119 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 263]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=21208} State at position 1 is {NULL=0, NULL=21208, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3aa7d986=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@563e6286=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@727e4fe6=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@308cf120=0, NULL=21209, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=21210, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=21211, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1604a89b=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79308476=0, t2_pc=0, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3fd859ca=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@222f29e7=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f4b9554=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 263]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int E_1 = 2; [L30] int E_2 = 2; [L565] int __retres1 ; [L479] m_i = 1 [L480] t1_i = 1 [L481] t2_i = 1 [L506] int kernel_st ; [L507] int tmp ; [L508] int tmp___0 ; [L512] kernel_st = 0 [L213] COND TRUE m_i == 1 [L214] m_st = 0 [L218] COND TRUE t1_i == 1 [L219] t1_st = 0 [L223] COND TRUE t2_i == 1 [L224] t2_st = 0 [L326] COND FALSE !(M_E == 0) [L331] COND FALSE !(T1_E == 0) [L336] COND FALSE !(T2_E == 0) [L341] COND FALSE !(E_1 == 0) [L346] COND FALSE !(E_2 == 0) [L389] int tmp ; [L390] int tmp___0 ; [L391] int tmp___1 ; [L145] int __retres1 ; [L148] COND FALSE !(m_pc == 1) [L158] __retres1 = 0 [L160] return (__retres1); [L395] tmp = is_master_triggered() [L397] COND FALSE !(\read(tmp)) [L164] int __retres1 ; [L167] COND FALSE !(t1_pc == 1) [L177] __retres1 = 0 [L179] return (__retres1); [L403] tmp___0 = is_transmit1_triggered() [L405] COND FALSE !(\read(tmp___0)) [L183] int __retres1 ; [L186] COND FALSE !(t2_pc == 1) [L196] __retres1 = 0 [L198] return (__retres1); [L411] tmp___1 = is_transmit2_triggered() [L413] COND FALSE !(\read(tmp___1)) [L359] COND FALSE !(M_E == 1) [L364] COND FALSE !(T1_E == 1) [L369] COND FALSE !(T2_E == 1) [L374] COND FALSE !(E_1 == 1) [L379] COND FALSE !(E_2 == 1) [L520] COND TRUE 1 [L523] kernel_st = 1 [L259] int tmp ; Loop: [L263] COND TRUE 1 [L233] int __retres1 ; [L236] COND TRUE m_st == 0 [L237] __retres1 = 1 [L254] return (__retres1); [L266] tmp = exists_runnable_thread() [L268] COND TRUE \read(tmp) [L273] COND TRUE m_st == 0 [L274] int tmp_ndt_1; [L275] tmp_ndt_1 = __VERIFIER_nondet_int() [L276] COND FALSE !(\read(tmp_ndt_1)) [L287] COND TRUE t1_st == 0 [L288] int tmp_ndt_2; [L289] tmp_ndt_2 = __VERIFIER_nondet_int() [L290] COND FALSE !(\read(tmp_ndt_2)) [L301] COND TRUE t2_st == 0 [L302] int tmp_ndt_3; [L303] tmp_ndt_3 = __VERIFIER_nondet_int() [L304] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 23:19:08,776 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1848ff21-9eca-4a7b-ac1a-02243562ef01/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...