./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1ec3ea32382f407cf861c3067ab994313a1de2b62bed831e309aa68653121144 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 23:45:41,475 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 23:45:41,478 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 23:45:41,519 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 23:45:41,520 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 23:45:41,521 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 23:45:41,523 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 23:45:41,525 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 23:45:41,527 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 23:45:41,529 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 23:45:41,530 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 23:45:41,532 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 23:45:41,532 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 23:45:41,534 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 23:45:41,536 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 23:45:41,537 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 23:45:41,538 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 23:45:41,540 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 23:45:41,542 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 23:45:41,545 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 23:45:41,547 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 23:45:41,549 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 23:45:41,551 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 23:45:41,552 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 23:45:41,556 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 23:45:41,557 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 23:45:41,557 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 23:45:41,558 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 23:45:41,559 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 23:45:41,567 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 23:45:41,567 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 23:45:41,568 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 23:45:41,571 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 23:45:41,572 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 23:45:41,574 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 23:45:41,574 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 23:45:41,575 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 23:45:41,575 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 23:45:41,576 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 23:45:41,577 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 23:45:41,578 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 23:45:41,579 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-10-28 23:45:41,626 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 23:45:41,626 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 23:45:41,627 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 23:45:41,627 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 23:45:41,629 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 23:45:41,629 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 23:45:41,629 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 23:45:41,630 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 23:45:41,630 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 23:45:41,630 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 23:45:41,631 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 23:45:41,631 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 23:45:41,632 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 23:45:41,632 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 23:45:41,632 INFO L138 SettingsManager]: * sizeof long=4 [2021-10-28 23:45:41,632 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 23:45:41,632 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 23:45:41,633 INFO L138 SettingsManager]: * sizeof long double=12 [2021-10-28 23:45:41,634 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 23:45:41,634 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 23:45:41,634 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 23:45:41,636 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 23:45:41,636 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 23:45:41,636 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 23:45:41,636 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 23:45:41,637 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 23:45:41,637 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 23:45:41,638 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 23:45:41,638 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1ec3ea32382f407cf861c3067ab994313a1de2b62bed831e309aa68653121144 [2021-10-28 23:45:41,981 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 23:45:42,012 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 23:45:42,015 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 23:45:42,017 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 23:45:42,018 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 23:45:42,019 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-10-28 23:45:42,085 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/data/afdede738/1436c65bac9c435f9394ae8a2f3ded4e/FLAG8d0544537 [2021-10-28 23:45:42,638 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 23:45:42,639 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-10-28 23:45:42,650 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/data/afdede738/1436c65bac9c435f9394ae8a2f3ded4e/FLAG8d0544537 [2021-10-28 23:45:42,991 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/data/afdede738/1436c65bac9c435f9394ae8a2f3ded4e [2021-10-28 23:45:42,998 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 23:45:43,001 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 23:45:43,004 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 23:45:43,004 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 23:45:43,008 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 23:45:43,009 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:45:42" (1/1) ... [2021-10-28 23:45:43,011 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1967d5ba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43, skipping insertion in model container [2021-10-28 23:45:43,012 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:45:42" (1/1) ... [2021-10-28 23:45:43,019 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 23:45:43,082 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 23:45:43,316 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] [2021-10-28 23:45:43,416 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:45:43,435 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 23:45:43,447 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] [2021-10-28 23:45:43,491 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:45:43,506 INFO L208 MainTranslator]: Completed translation [2021-10-28 23:45:43,506 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43 WrapperNode [2021-10-28 23:45:43,507 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 23:45:43,508 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 23:45:43,508 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 23:45:43,508 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 23:45:43,520 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,546 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,618 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 23:45:43,619 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 23:45:43,619 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 23:45:43,619 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 23:45:43,628 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,628 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,638 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,638 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,654 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,675 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,698 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,703 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 23:45:43,704 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 23:45:43,705 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 23:45:43,705 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 23:45:43,709 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (1/1) ... [2021-10-28 23:45:43,716 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:45:43,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:45:43,741 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:45:43,764 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 23:45:43,793 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-28 23:45:43,793 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-28 23:45:43,794 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 23:45:43,794 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 23:45:44,815 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 23:45:44,816 INFO L299 CfgBuilder]: Removed 148 assume(true) statements. [2021-10-28 23:45:44,819 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:45:44 BoogieIcfgContainer [2021-10-28 23:45:44,819 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 23:45:44,820 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 23:45:44,820 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 23:45:44,824 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 23:45:44,825 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:45:44,825 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 11:45:42" (1/3) ... [2021-10-28 23:45:44,826 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fdcf547 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:45:44, skipping insertion in model container [2021-10-28 23:45:44,827 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:45:44,827 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:45:43" (2/3) ... [2021-10-28 23:45:44,827 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5fdcf547 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:45:44, skipping insertion in model container [2021-10-28 23:45:44,828 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:45:44,828 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:45:44" (3/3) ... [2021-10-28 23:45:44,829 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2021-10-28 23:45:44,874 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 23:45:44,874 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 23:45:44,874 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 23:45:44,874 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 23:45:44,875 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 23:45:44,875 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 23:45:44,875 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 23:45:44,875 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 23:45:44,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:44,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2021-10-28 23:45:44,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:44,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:44,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:44,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:44,957 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 23:45:44,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:44,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2021-10-28 23:45:44,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:44,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:44,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:44,976 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:44,984 INFO L791 eck$LassoCheckResult]: Stem: 354#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 254#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 145#L731true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 241#L326true assume !(1 == ~m_i~0);~m_st~0 := 2; 344#L333-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 146#L338-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 78#L343-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 315#L348-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 185#L353-1true assume !(0 == ~M_E~0); 172#L494-1true assume !(0 == ~T1_E~0); 74#L499-1true assume !(0 == ~T2_E~0); 139#L504-1true assume !(0 == ~T3_E~0); 296#L509-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 61#L514-1true assume !(0 == ~E_1~0); 200#L519-1true assume !(0 == ~E_2~0); 67#L524-1true assume !(0 == ~E_3~0); 198#L529-1true assume !(0 == ~E_4~0); 204#L534-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 287#L230true assume !(1 == ~m_pc~0); 353#L230-2true is_master_triggered_~__retres1~0 := 0; 45#L241true is_master_triggered_#res := is_master_triggered_~__retres1~0; 372#L242true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53#L607true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 99#L607-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9#L249true assume 1 == ~t1_pc~0; 309#L250true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 281#L260true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 202#L261true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 214#L615true assume !(0 != activate_threads_~tmp___0~0); 20#L615-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 235#L268true assume !(1 == ~t2_pc~0); 330#L268-2true is_transmit2_triggered_~__retres1~2 := 0; 94#L279true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 316#L280true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6#L623true assume !(0 != activate_threads_~tmp___1~0); 47#L623-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 277#L287true assume 1 == ~t3_pc~0; 44#L288true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 244#L298true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62#L299true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 285#L631true assume !(0 != activate_threads_~tmp___2~0); 304#L631-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 194#L306true assume !(1 == ~t4_pc~0); 76#L306-2true is_transmit4_triggered_~__retres1~4 := 0; 210#L317true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 366#L318true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 250#L639true assume !(0 != activate_threads_~tmp___3~0); 240#L639-2true assume !(1 == ~M_E~0); 319#L547-1true assume !(1 == ~T1_E~0); 289#L552-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 128#L557-1true assume !(1 == ~T3_E~0); 370#L562-1true assume !(1 == ~T4_E~0); 133#L567-1true assume !(1 == ~E_1~0); 126#L572-1true assume !(1 == ~E_2~0); 82#L577-1true assume !(1 == ~E_3~0); 51#L582-1true assume !(1 == ~E_4~0); 280#L768-1true [2021-10-28 23:45:44,986 INFO L793 eck$LassoCheckResult]: Loop: 280#L768-1true assume !false; 83#L769true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 23#L469true assume !true; 186#L484true start_simulation_~kernel_st~0 := 2; 38#L326-1true start_simulation_~kernel_st~0 := 3; 348#L494-2true assume !(0 == ~M_E~0); 5#L494-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 346#L499-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 124#L504-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 24#L509-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 343#L514-3true assume 0 == ~E_1~0;~E_1~0 := 1; 190#L519-3true assume 0 == ~E_2~0;~E_2~0 := 1; 50#L524-3true assume 0 == ~E_3~0;~E_3~0 := 1; 161#L529-3true assume !(0 == ~E_4~0); 301#L534-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 340#L230-15true assume 1 == ~m_pc~0; 243#L231-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 238#L241-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 65#L242-5true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 347#L607-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 166#L607-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96#L249-15true assume 1 == ~t1_pc~0; 321#L250-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 49#L260-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 292#L261-5true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 70#L615-15true assume !(0 != activate_threads_~tmp___0~0); 302#L615-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110#L268-15true assume 1 == ~t2_pc~0; 320#L269-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 142#L279-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 213#L280-5true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 215#L623-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 231#L623-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 119#L287-15true assume 1 == ~t3_pc~0; 369#L288-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 57#L298-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46#L299-5true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 367#L631-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 183#L631-17true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 225#L306-15true assume !(1 == ~t4_pc~0); 324#L306-17true is_transmit4_triggered_~__retres1~4 := 0; 116#L317-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 341#L318-5true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 326#L639-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 251#L639-17true assume 1 == ~M_E~0;~M_E~0 := 2; 109#L547-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 58#L552-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 127#L557-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 327#L562-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 361#L567-3true assume 1 == ~E_1~0;~E_1~0 := 2; 350#L572-3true assume !(1 == ~E_2~0); 211#L577-3true assume 1 == ~E_3~0;~E_3~0 := 2; 60#L582-3true assume 1 == ~E_4~0;~E_4~0 := 2; 268#L587-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 226#L366-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 195#L393-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 263#L394-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 355#L787true assume !(0 == start_simulation_~tmp~3); 105#L787-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 152#L366-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 174#L393-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 332#L394-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 63#L742true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 209#L749true stop_simulation_#res := stop_simulation_~__retres2~0; 335#L750true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 223#L800true assume !(0 != start_simulation_~tmp___0~1); 280#L768-1true [2021-10-28 23:45:44,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:44,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1688618289, now seen corresponding path program 1 times [2021-10-28 23:45:45,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,003 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995993885] [2021-10-28 23:45:45,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,004 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,194 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,194 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995993885] [2021-10-28 23:45:45,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995993885] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,195 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965799318] [2021-10-28 23:45:45,203 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:45,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1422200322, now seen corresponding path program 1 times [2021-10-28 23:45:45,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,205 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651583272] [2021-10-28 23:45:45,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,206 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,236 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651583272] [2021-10-28 23:45:45,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651583272] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,236 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:45:45,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919788933] [2021-10-28 23:45:45,239 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:45,240 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:45,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:45,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:45,260 INFO L87 Difference]: Start difference. First operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:45,308 INFO L93 Difference]: Finished difference Result 373 states and 564 transitions. [2021-10-28 23:45:45,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:45,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 373 states and 564 transitions. [2021-10-28 23:45:45,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 373 states to 368 states and 559 transitions. [2021-10-28 23:45:45,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-10-28 23:45:45,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-10-28 23:45:45,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 559 transitions. [2021-10-28 23:45:45,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:45,334 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-10-28 23:45:45,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 559 transitions. [2021-10-28 23:45:45,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-10-28 23:45:45,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.5190217391304348) internal successors, (559), 367 states have internal predecessors, (559), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 559 transitions. [2021-10-28 23:45:45,385 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-10-28 23:45:45,386 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-10-28 23:45:45,386 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 23:45:45,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 559 transitions. [2021-10-28 23:45:45,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:45,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:45,394 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,395 INFO L791 eck$LassoCheckResult]: Stem: 1122#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1102#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1012#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1013#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1094#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1014#L338-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 916#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 917#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1052#L353-1 assume !(0 == ~M_E~0); 1043#L494-1 assume !(0 == ~T1_E~0); 907#L499-1 assume !(0 == ~T2_E~0); 908#L504-1 assume !(0 == ~T3_E~0); 1005#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 881#L514-1 assume !(0 == ~E_1~0); 882#L519-1 assume !(0 == ~E_2~0); 893#L524-1 assume !(0 == ~E_3~0); 894#L529-1 assume !(0 == ~E_4~0); 1063#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1069#L230 assume !(1 == ~m_pc~0); 986#L230-2 is_master_triggered_~__retres1~0 := 0; 851#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 852#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 863#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 864#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 774#L249 assume 1 == ~t1_pc~0; 775#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 840#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1064#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1065#L615 assume !(0 != activate_threads_~tmp___0~0); 801#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 802#L268 assume !(1 == ~t2_pc~0); 955#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 939#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 940#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 763#L623 assume !(0 != activate_threads_~tmp___1~0); 764#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 853#L287 assume 1 == ~t3_pc~0; 846#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 847#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 883#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 884#L631 assume !(0 != activate_threads_~tmp___2~0); 1108#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1058#L306 assume !(1 == ~t4_pc~0); 909#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 910#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1073#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1099#L639 assume !(0 != activate_threads_~tmp___3~0); 1092#L639-2 assume !(1 == ~M_E~0); 1093#L547-1 assume !(1 == ~T1_E~0); 1109#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 990#L557-1 assume !(1 == ~T3_E~0); 991#L562-1 assume !(1 == ~T4_E~0); 995#L567-1 assume !(1 == ~E_1~0); 989#L572-1 assume !(1 == ~E_2~0); 920#L577-1 assume !(1 == ~E_3~0); 861#L582-1 assume !(1 == ~E_4~0); 862#L768-1 [2021-10-28 23:45:45,395 INFO L793 eck$LassoCheckResult]: Loop: 862#L768-1 assume !false; 921#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 803#L469 assume !false; 804#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1033#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 780#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1082#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1083#L408 assume !(0 != eval_~tmp~0); 1053#L484 start_simulation_~kernel_st~0 := 2; 836#L326-1 start_simulation_~kernel_st~0 := 3; 837#L494-2 assume !(0 == ~M_E~0); 759#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 760#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 987#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 805#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 806#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1054#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 857#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 858#L529-3 assume !(0 == ~E_4~0); 1030#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1112#L230-15 assume 1 == ~m_pc~0; 1095#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 937#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 887#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 888#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1034#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 941#L249-15 assume !(1 == ~t1_pc~0); 942#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 854#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 855#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 895#L615-15 assume !(0 != activate_threads_~tmp___0~0); 896#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 962#L268-15 assume 1 == ~t2_pc~0; 963#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 845#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1006#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1074#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1075#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 974#L287-15 assume !(1 == ~t3_pc~0); 958#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 872#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 849#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 850#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1049#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1050#L306-15 assume 1 == ~t4_pc~0; 1084#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 972#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 973#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1118#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1100#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 961#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 873#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 874#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 988#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1119#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1121#L572-3 assume !(1 == ~E_2~0); 1072#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 877#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 878#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1086#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 786#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1057#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1104#L787 assume !(0 == start_simulation_~tmp~3); 956#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 957#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 816#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1042#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 879#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 880#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 1070#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1081#L800 assume !(0 != start_simulation_~tmp___0~1); 862#L768-1 [2021-10-28 23:45:45,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1244717615, now seen corresponding path program 1 times [2021-10-28 23:45:45,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,397 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031124164] [2021-10-28 23:45:45,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,398 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,453 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031124164] [2021-10-28 23:45:45,453 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031124164] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,453 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,453 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,454 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418759083] [2021-10-28 23:45:45,454 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:45,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,455 INFO L85 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 1 times [2021-10-28 23:45:45,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,456 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94965984] [2021-10-28 23:45:45,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,457 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,533 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94965984] [2021-10-28 23:45:45,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94965984] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,534 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552242947] [2021-10-28 23:45:45,535 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:45,535 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:45,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:45,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:45,537 INFO L87 Difference]: Start difference. First operand 368 states and 559 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:45,560 INFO L93 Difference]: Finished difference Result 368 states and 558 transitions. [2021-10-28 23:45:45,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:45,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 558 transitions. [2021-10-28 23:45:45,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 558 transitions. [2021-10-28 23:45:45,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-10-28 23:45:45,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-10-28 23:45:45,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 558 transitions. [2021-10-28 23:45:45,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:45,597 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-10-28 23:45:45,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 558 transitions. [2021-10-28 23:45:45,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-10-28 23:45:45,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.516304347826087) internal successors, (558), 367 states have internal predecessors, (558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 558 transitions. [2021-10-28 23:45:45,620 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-10-28 23:45:45,620 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-10-28 23:45:45,620 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 23:45:45,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 558 transitions. [2021-10-28 23:45:45,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:45,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:45,628 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,628 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,628 INFO L791 eck$LassoCheckResult]: Stem: 1865#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1845#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1752#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1753#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1837#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1754#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1656#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1657#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1794#L353-1 assume !(0 == ~M_E~0); 1785#L494-1 assume !(0 == ~T1_E~0); 1648#L499-1 assume !(0 == ~T2_E~0); 1649#L504-1 assume !(0 == ~T3_E~0); 1747#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1622#L514-1 assume !(0 == ~E_1~0); 1623#L519-1 assume !(0 == ~E_2~0); 1634#L524-1 assume !(0 == ~E_3~0); 1635#L529-1 assume !(0 == ~E_4~0); 1806#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1810#L230 assume !(1 == ~m_pc~0); 1729#L230-2 is_master_triggered_~__retres1~0 := 0; 1592#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1593#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1606#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1607#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1511#L249 assume 1 == ~t1_pc~0; 1512#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1581#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1807#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1808#L615 assume !(0 != activate_threads_~tmp___0~0); 1538#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1539#L268 assume !(1 == ~t2_pc~0); 1696#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 1681#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1682#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1504#L623 assume !(0 != activate_threads_~tmp___1~0); 1505#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1596#L287 assume 1 == ~t3_pc~0; 1589#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1590#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1624#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1625#L631 assume !(0 != activate_threads_~tmp___2~0); 1851#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1800#L306 assume !(1 == ~t4_pc~0); 1652#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 1653#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1815#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1842#L639 assume !(0 != activate_threads_~tmp___3~0); 1835#L639-2 assume !(1 == ~M_E~0); 1836#L547-1 assume !(1 == ~T1_E~0); 1852#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1733#L557-1 assume !(1 == ~T3_E~0); 1734#L562-1 assume !(1 == ~T4_E~0); 1738#L567-1 assume !(1 == ~E_1~0); 1731#L572-1 assume !(1 == ~E_2~0); 1661#L577-1 assume !(1 == ~E_3~0); 1602#L582-1 assume !(1 == ~E_4~0); 1603#L768-1 [2021-10-28 23:45:45,629 INFO L793 eck$LassoCheckResult]: Loop: 1603#L768-1 assume !false; 1662#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1546#L469 assume !false; 1547#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1776#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1521#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1824#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1825#L408 assume !(0 != eval_~tmp~0); 1795#L484 start_simulation_~kernel_st~0 := 2; 1579#L326-1 start_simulation_~kernel_st~0 := 3; 1580#L494-2 assume !(0 == ~M_E~0); 1502#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1503#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1730#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1548#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1549#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1798#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1600#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1601#L529-3 assume !(0 == ~E_4~0); 1773#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1855#L230-15 assume 1 == ~m_pc~0; 1838#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1680#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1630#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1631#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1777#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1684#L249-15 assume !(1 == ~t1_pc~0); 1685#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 1598#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1599#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1641#L615-15 assume !(0 != activate_threads_~tmp___0~0); 1642#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1705#L268-15 assume !(1 == ~t2_pc~0); 1587#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 1588#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1749#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1817#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1818#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1720#L287-15 assume !(1 == ~t3_pc~0); 1701#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 1615#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1594#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1595#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1792#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1793#L306-15 assume 1 == ~t4_pc~0; 1827#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1715#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1716#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1861#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1843#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1704#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1616#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1617#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1732#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1862#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1864#L572-3 assume !(1 == ~E_2~0); 1816#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1620#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1621#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1829#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1529#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1802#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1847#L787 assume !(0 == start_simulation_~tmp~3); 1699#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1700#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1559#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1786#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1626#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1627#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 1814#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1826#L800 assume !(0 != start_simulation_~tmp___0~1); 1603#L768-1 [2021-10-28 23:45:45,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,630 INFO L85 PathProgramCache]: Analyzing trace with hash -1021663571, now seen corresponding path program 1 times [2021-10-28 23:45:45,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,630 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898062424] [2021-10-28 23:45:45,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,631 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,726 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,726 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898062424] [2021-10-28 23:45:45,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898062424] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,727 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325799901] [2021-10-28 23:45:45,728 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:45,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1442246050, now seen corresponding path program 1 times [2021-10-28 23:45:45,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,729 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027839855] [2021-10-28 23:45:45,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,730 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,782 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,783 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027839855] [2021-10-28 23:45:45,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027839855] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,783 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,783 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821364227] [2021-10-28 23:45:45,784 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:45,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:45,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:45,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:45,786 INFO L87 Difference]: Start difference. First operand 368 states and 558 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:45,799 INFO L93 Difference]: Finished difference Result 368 states and 557 transitions. [2021-10-28 23:45:45,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:45,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 557 transitions. [2021-10-28 23:45:45,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 557 transitions. [2021-10-28 23:45:45,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-10-28 23:45:45,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-10-28 23:45:45,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 557 transitions. [2021-10-28 23:45:45,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:45,810 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-10-28 23:45:45,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 557 transitions. [2021-10-28 23:45:45,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-10-28 23:45:45,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.513586956521739) internal successors, (557), 367 states have internal predecessors, (557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 557 transitions. [2021-10-28 23:45:45,825 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-10-28 23:45:45,825 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-10-28 23:45:45,826 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 23:45:45,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 557 transitions. [2021-10-28 23:45:45,829 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:45,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:45,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:45,831 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,832 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:45,832 INFO L791 eck$LassoCheckResult]: Stem: 2608#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2588#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2498#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2499#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 2580#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2500#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2401#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2402#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2538#L353-1 assume !(0 == ~M_E~0); 2529#L494-1 assume !(0 == ~T1_E~0); 2393#L499-1 assume !(0 == ~T2_E~0); 2394#L504-1 assume !(0 == ~T3_E~0); 2490#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2367#L514-1 assume !(0 == ~E_1~0); 2368#L519-1 assume !(0 == ~E_2~0); 2379#L524-1 assume !(0 == ~E_3~0); 2380#L529-1 assume !(0 == ~E_4~0); 2549#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2555#L230 assume !(1 == ~m_pc~0); 2472#L230-2 is_master_triggered_~__retres1~0 := 0; 2337#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2338#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2349#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2350#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2260#L249 assume 1 == ~t1_pc~0; 2261#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2326#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2550#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2551#L615 assume !(0 != activate_threads_~tmp___0~0); 2287#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2288#L268 assume !(1 == ~t2_pc~0); 2441#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 2425#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2426#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2249#L623 assume !(0 != activate_threads_~tmp___1~0); 2250#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2339#L287 assume 1 == ~t3_pc~0; 2332#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2333#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2369#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2370#L631 assume !(0 != activate_threads_~tmp___2~0); 2594#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2544#L306 assume !(1 == ~t4_pc~0); 2395#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 2396#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2559#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2585#L639 assume !(0 != activate_threads_~tmp___3~0); 2578#L639-2 assume !(1 == ~M_E~0); 2579#L547-1 assume !(1 == ~T1_E~0); 2595#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2476#L557-1 assume !(1 == ~T3_E~0); 2477#L562-1 assume !(1 == ~T4_E~0); 2481#L567-1 assume !(1 == ~E_1~0); 2475#L572-1 assume !(1 == ~E_2~0); 2406#L577-1 assume !(1 == ~E_3~0); 2347#L582-1 assume !(1 == ~E_4~0); 2348#L768-1 [2021-10-28 23:45:45,833 INFO L793 eck$LassoCheckResult]: Loop: 2348#L768-1 assume !false; 2407#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2289#L469 assume !false; 2290#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2519#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2264#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2568#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2569#L408 assume !(0 != eval_~tmp~0); 2539#L484 start_simulation_~kernel_st~0 := 2; 2322#L326-1 start_simulation_~kernel_st~0 := 3; 2323#L494-2 assume !(0 == ~M_E~0); 2245#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2246#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2473#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2291#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2292#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2541#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2343#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2344#L529-3 assume !(0 == ~E_4~0); 2516#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2598#L230-15 assume 1 == ~m_pc~0; 2581#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2423#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2373#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2374#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2520#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2427#L249-15 assume !(1 == ~t1_pc~0); 2428#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 2340#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2341#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2381#L615-15 assume !(0 != activate_threads_~tmp___0~0); 2382#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2448#L268-15 assume 1 == ~t2_pc~0; 2449#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2331#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2492#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2560#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2561#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2460#L287-15 assume !(1 == ~t3_pc~0); 2444#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 2358#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2335#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2336#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2535#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2536#L306-15 assume 1 == ~t4_pc~0; 2570#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2458#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2459#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2604#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2586#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2447#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2359#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2360#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2474#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2605#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2607#L572-3 assume !(1 == ~E_2~0); 2558#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2363#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2364#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2572#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2272#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2543#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2590#L787 assume !(0 == start_simulation_~tmp~3); 2442#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2443#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2302#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2528#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 2365#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2366#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 2556#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2567#L800 assume !(0 != start_simulation_~tmp___0~1); 2348#L768-1 [2021-10-28 23:45:45,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,833 INFO L85 PathProgramCache]: Analyzing trace with hash -540583313, now seen corresponding path program 1 times [2021-10-28 23:45:45,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,834 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086548530] [2021-10-28 23:45:45,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,835 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,887 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086548530] [2021-10-28 23:45:45,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086548530] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,888 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,888 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701485655] [2021-10-28 23:45:45,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:45,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:45,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 2 times [2021-10-28 23:45:45,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:45,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347924375] [2021-10-28 23:45:45,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:45,890 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:45,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:45,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:45,978 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:45,978 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347924375] [2021-10-28 23:45:45,978 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347924375] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:45,978 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:45,978 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:45,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960174122] [2021-10-28 23:45:45,979 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:45,979 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:45,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:45,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:45,980 INFO L87 Difference]: Start difference. First operand 368 states and 557 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:45,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:45,995 INFO L93 Difference]: Finished difference Result 368 states and 556 transitions. [2021-10-28 23:45:45,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:45,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 556 transitions. [2021-10-28 23:45:45,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:46,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 556 transitions. [2021-10-28 23:45:46,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-10-28 23:45:46,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-10-28 23:45:46,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 556 transitions. [2021-10-28 23:45:46,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:46,005 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-10-28 23:45:46,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 556 transitions. [2021-10-28 23:45:46,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-10-28 23:45:46,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.5108695652173914) internal successors, (556), 367 states have internal predecessors, (556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 556 transitions. [2021-10-28 23:45:46,017 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-10-28 23:45:46,017 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-10-28 23:45:46,017 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 23:45:46,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 556 transitions. [2021-10-28 23:45:46,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:46,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:46,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:46,023 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,023 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,024 INFO L791 eck$LassoCheckResult]: Stem: 3351#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3331#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3238#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3239#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 3323#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3240#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3142#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3143#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3280#L353-1 assume !(0 == ~M_E~0); 3271#L494-1 assume !(0 == ~T1_E~0); 3134#L499-1 assume !(0 == ~T2_E~0); 3135#L504-1 assume !(0 == ~T3_E~0); 3233#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3108#L514-1 assume !(0 == ~E_1~0); 3109#L519-1 assume !(0 == ~E_2~0); 3120#L524-1 assume !(0 == ~E_3~0); 3121#L529-1 assume !(0 == ~E_4~0); 3292#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3296#L230 assume !(1 == ~m_pc~0); 3215#L230-2 is_master_triggered_~__retres1~0 := 0; 3078#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3079#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3092#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3093#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2997#L249 assume 1 == ~t1_pc~0; 2998#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3067#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3293#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3294#L615 assume !(0 != activate_threads_~tmp___0~0); 3024#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3025#L268 assume !(1 == ~t2_pc~0); 3182#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3167#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3168#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2990#L623 assume !(0 != activate_threads_~tmp___1~0); 2991#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3082#L287 assume 1 == ~t3_pc~0; 3075#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3076#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3110#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3111#L631 assume !(0 != activate_threads_~tmp___2~0); 3337#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3286#L306 assume !(1 == ~t4_pc~0); 3138#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3139#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3301#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3328#L639 assume !(0 != activate_threads_~tmp___3~0); 3321#L639-2 assume !(1 == ~M_E~0); 3322#L547-1 assume !(1 == ~T1_E~0); 3338#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3219#L557-1 assume !(1 == ~T3_E~0); 3220#L562-1 assume !(1 == ~T4_E~0); 3224#L567-1 assume !(1 == ~E_1~0); 3217#L572-1 assume !(1 == ~E_2~0); 3147#L577-1 assume !(1 == ~E_3~0); 3088#L582-1 assume !(1 == ~E_4~0); 3089#L768-1 [2021-10-28 23:45:46,026 INFO L793 eck$LassoCheckResult]: Loop: 3089#L768-1 assume !false; 3148#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3032#L469 assume !false; 3033#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3262#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3007#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3310#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3311#L408 assume !(0 != eval_~tmp~0); 3281#L484 start_simulation_~kernel_st~0 := 2; 3065#L326-1 start_simulation_~kernel_st~0 := 3; 3066#L494-2 assume !(0 == ~M_E~0); 2988#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2989#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3216#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3034#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3035#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3284#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3086#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3087#L529-3 assume !(0 == ~E_4~0); 3259#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3341#L230-15 assume 1 == ~m_pc~0; 3324#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3166#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3116#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3117#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3263#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3170#L249-15 assume !(1 == ~t1_pc~0); 3171#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 3084#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3085#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3127#L615-15 assume !(0 != activate_threads_~tmp___0~0); 3128#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3191#L268-15 assume !(1 == ~t2_pc~0); 3073#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 3074#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3235#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3303#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3304#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3206#L287-15 assume !(1 == ~t3_pc~0); 3187#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 3101#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3080#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3081#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3278#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3279#L306-15 assume 1 == ~t4_pc~0; 3313#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3201#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3202#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3347#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3329#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3190#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3102#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3103#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3218#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3348#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3350#L572-3 assume !(1 == ~E_2~0); 3302#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3106#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3107#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3315#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3015#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3288#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3333#L787 assume !(0 == start_simulation_~tmp~3); 3185#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3186#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3045#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3272#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3112#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3113#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 3300#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3312#L800 assume !(0 != start_simulation_~tmp___0~1); 3089#L768-1 [2021-10-28 23:45:46,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,027 INFO L85 PathProgramCache]: Analyzing trace with hash -525064595, now seen corresponding path program 1 times [2021-10-28 23:45:46,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,028 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550577063] [2021-10-28 23:45:46,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,028 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550577063] [2021-10-28 23:45:46,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550577063] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,105 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:45:46,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087688396] [2021-10-28 23:45:46,106 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:46,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1442246050, now seen corresponding path program 2 times [2021-10-28 23:45:46,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802585511] [2021-10-28 23:45:46,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,108 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,141 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802585511] [2021-10-28 23:45:46,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802585511] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,142 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,142 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877244337] [2021-10-28 23:45:46,143 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:46,143 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:46,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:46,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:46,144 INFO L87 Difference]: Start difference. First operand 368 states and 556 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:46,162 INFO L93 Difference]: Finished difference Result 368 states and 551 transitions. [2021-10-28 23:45:46,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:46,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 551 transitions. [2021-10-28 23:45:46,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:46,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 551 transitions. [2021-10-28 23:45:46,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-10-28 23:45:46,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-10-28 23:45:46,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 551 transitions. [2021-10-28 23:45:46,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:46,172 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-10-28 23:45:46,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 551 transitions. [2021-10-28 23:45:46,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-10-28 23:45:46,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.497282608695652) internal successors, (551), 367 states have internal predecessors, (551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 551 transitions. [2021-10-28 23:45:46,182 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-10-28 23:45:46,182 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-10-28 23:45:46,183 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 23:45:46,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 551 transitions. [2021-10-28 23:45:46,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-10-28 23:45:46,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:46,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:46,187 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,187 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,188 INFO L791 eck$LassoCheckResult]: Stem: 4094#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4074#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3981#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3982#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 4066#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3983#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3885#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3886#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4023#L353-1 assume !(0 == ~M_E~0); 4015#L494-1 assume !(0 == ~T1_E~0); 3879#L499-1 assume !(0 == ~T2_E~0); 3880#L504-1 assume !(0 == ~T3_E~0); 3976#L509-1 assume !(0 == ~T4_E~0); 3853#L514-1 assume !(0 == ~E_1~0); 3854#L519-1 assume !(0 == ~E_2~0); 3865#L524-1 assume !(0 == ~E_3~0); 3866#L529-1 assume !(0 == ~E_4~0); 4035#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4039#L230 assume !(1 == ~m_pc~0); 3958#L230-2 is_master_triggered_~__retres1~0 := 0; 3823#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3824#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3835#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3836#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3744#L249 assume 1 == ~t1_pc~0; 3745#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3812#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4036#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4037#L615 assume !(0 != activate_threads_~tmp___0~0); 3770#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3771#L268 assume !(1 == ~t2_pc~0); 3927#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3910#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3911#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3735#L623 assume !(0 != activate_threads_~tmp___1~0); 3736#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3825#L287 assume 1 == ~t3_pc~0; 3818#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3819#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3855#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3856#L631 assume !(0 != activate_threads_~tmp___2~0); 4080#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4030#L306 assume !(1 == ~t4_pc~0); 3881#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3882#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4045#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4071#L639 assume !(0 != activate_threads_~tmp___3~0); 4064#L639-2 assume !(1 == ~M_E~0); 4065#L547-1 assume !(1 == ~T1_E~0); 4081#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3962#L557-1 assume !(1 == ~T3_E~0); 3963#L562-1 assume !(1 == ~T4_E~0); 3967#L567-1 assume !(1 == ~E_1~0); 3961#L572-1 assume !(1 == ~E_2~0); 3892#L577-1 assume !(1 == ~E_3~0); 3831#L582-1 assume !(1 == ~E_4~0); 3832#L768-1 [2021-10-28 23:45:46,188 INFO L793 eck$LassoCheckResult]: Loop: 3832#L768-1 assume !false; 3893#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3775#L469 assume !false; 3776#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4005#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3750#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4054#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4055#L408 assume !(0 != eval_~tmp~0); 4024#L484 start_simulation_~kernel_st~0 := 2; 3808#L326-1 start_simulation_~kernel_st~0 := 3; 3809#L494-2 assume !(0 == ~M_E~0); 3731#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3732#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3959#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3777#L509-3 assume !(0 == ~T4_E~0); 3778#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4027#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3829#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3830#L529-3 assume !(0 == ~E_4~0); 4002#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4084#L230-15 assume 1 == ~m_pc~0; 4067#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3909#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3859#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3860#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4009#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3913#L249-15 assume !(1 == ~t1_pc~0); 3914#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 3827#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3828#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3870#L615-15 assume !(0 != activate_threads_~tmp___0~0); 3871#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3934#L268-15 assume !(1 == ~t2_pc~0); 3816#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 3817#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3978#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4046#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4047#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3946#L287-15 assume !(1 == ~t3_pc~0); 3930#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 3844#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3821#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3822#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4021#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4022#L306-15 assume 1 == ~t4_pc~0; 4056#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3944#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3945#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4090#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4072#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3932#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3845#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3846#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3960#L562-3 assume !(1 == ~T4_E~0); 4091#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4093#L572-3 assume !(1 == ~E_2~0); 4044#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3849#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3850#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4058#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3758#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4029#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4076#L787 assume !(0 == start_simulation_~tmp~3); 3928#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3929#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3788#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4014#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3851#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3852#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 4042#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4053#L800 assume !(0 != start_simulation_~tmp___0~1); 3832#L768-1 [2021-10-28 23:45:46,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1720514859, now seen corresponding path program 1 times [2021-10-28 23:45:46,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,190 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144222225] [2021-10-28 23:45:46,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,190 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,260 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,261 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144222225] [2021-10-28 23:45:46,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144222225] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,262 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:45:46,262 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764595789] [2021-10-28 23:45:46,263 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:46,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,264 INFO L85 PathProgramCache]: Analyzing trace with hash 709018594, now seen corresponding path program 1 times [2021-10-28 23:45:46,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726961736] [2021-10-28 23:45:46,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,266 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,331 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726961736] [2021-10-28 23:45:46,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726961736] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,331 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244522713] [2021-10-28 23:45:46,332 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:46,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:46,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:45:46,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:45:46,333 INFO L87 Difference]: Start difference. First operand 368 states and 551 transitions. cyclomatic complexity: 184 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:46,514 INFO L93 Difference]: Finished difference Result 1005 states and 1494 transitions. [2021-10-28 23:45:46,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 23:45:46,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1005 states and 1494 transitions. [2021-10-28 23:45:46,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 867 [2021-10-28 23:45:46,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1005 states to 1005 states and 1494 transitions. [2021-10-28 23:45:46,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1005 [2021-10-28 23:45:46,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1005 [2021-10-28 23:45:46,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1005 states and 1494 transitions. [2021-10-28 23:45:46,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:46,545 INFO L681 BuchiCegarLoop]: Abstraction has 1005 states and 1494 transitions. [2021-10-28 23:45:46,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1005 states and 1494 transitions. [2021-10-28 23:45:46,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1005 to 389. [2021-10-28 23:45:46,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2021-10-28 23:45:46,560 INFO L704 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2021-10-28 23:45:46,560 INFO L587 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2021-10-28 23:45:46,560 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 23:45:46,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2021-10-28 23:45:46,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 325 [2021-10-28 23:45:46,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:46,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:46,565 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,565 INFO L791 eck$LassoCheckResult]: Stem: 5499#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5469#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5372#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5373#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 5460#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5374#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5271#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5272#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5415#L353-1 assume !(0 == ~M_E~0); 5405#L494-1 assume !(0 == ~T1_E~0); 5263#L499-1 assume !(0 == ~T2_E~0); 5264#L504-1 assume !(0 == ~T3_E~0); 5366#L509-1 assume !(0 == ~T4_E~0); 5237#L514-1 assume !(0 == ~E_1~0); 5238#L519-1 assume !(0 == ~E_2~0); 5249#L524-1 assume !(0 == ~E_3~0); 5250#L529-1 assume !(0 == ~E_4~0); 5427#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5431#L230 assume !(1 == ~m_pc~0); 5348#L230-2 is_master_triggered_~__retres1~0 := 0; 5207#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5208#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5221#L607 assume !(0 != activate_threads_~tmp~1); 5222#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5126#L249 assume 1 == ~t1_pc~0; 5127#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5196#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5428#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5429#L615 assume !(0 != activate_threads_~tmp___0~0); 5153#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5154#L268 assume !(1 == ~t2_pc~0); 5313#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 5297#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5298#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5119#L623 assume !(0 != activate_threads_~tmp___1~0); 5120#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5211#L287 assume 1 == ~t3_pc~0; 5204#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5205#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5239#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5240#L631 assume !(0 != activate_threads_~tmp___2~0); 5483#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5421#L306 assume !(1 == ~t4_pc~0); 5267#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 5268#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5436#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5466#L639 assume !(0 != activate_threads_~tmp___3~0); 5458#L639-2 assume !(1 == ~M_E~0); 5459#L547-1 assume !(1 == ~T1_E~0); 5484#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5352#L557-1 assume !(1 == ~T3_E~0); 5353#L562-1 assume !(1 == ~T4_E~0); 5357#L567-1 assume !(1 == ~E_1~0); 5350#L572-1 assume !(1 == ~E_2~0); 5276#L577-1 assume !(1 == ~E_3~0); 5217#L582-1 assume !(1 == ~E_4~0); 5218#L768-1 [2021-10-28 23:45:46,566 INFO L793 eck$LassoCheckResult]: Loop: 5218#L768-1 assume !false; 5277#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5161#L469 assume !false; 5162#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5396#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5136#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5445#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5446#L408 assume !(0 != eval_~tmp~0); 5416#L484 start_simulation_~kernel_st~0 := 2; 5194#L326-1 start_simulation_~kernel_st~0 := 3; 5195#L494-2 assume !(0 == ~M_E~0); 5117#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5118#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5349#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5163#L509-3 assume !(0 == ~T4_E~0); 5164#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5419#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5215#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5216#L529-3 assume !(0 == ~E_4~0); 5393#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5487#L230-15 assume 1 == ~m_pc~0; 5461#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5462#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5245#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5246#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5397#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5300#L249-15 assume !(1 == ~t1_pc~0); 5301#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 5213#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5214#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5256#L615-15 assume !(0 != activate_threads_~tmp___0~0); 5257#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5322#L268-15 assume !(1 == ~t2_pc~0); 5202#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 5203#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5369#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5438#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5439#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5337#L287-15 assume !(1 == ~t3_pc~0); 5318#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 5230#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5209#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5210#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5413#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5414#L306-15 assume 1 == ~t4_pc~0; 5448#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5332#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5333#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5493#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5467#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5321#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5231#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5232#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5351#L562-3 assume !(1 == ~T4_E~0); 5494#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5497#L572-3 assume !(1 == ~E_2~0); 5437#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5235#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5236#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5450#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5144#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5423#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5477#L787 assume !(0 == start_simulation_~tmp~3); 5316#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5317#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5174#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5406#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 5241#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5242#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 5435#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5447#L800 assume !(0 != start_simulation_~tmp___0~1); 5218#L768-1 [2021-10-28 23:45:46,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,566 INFO L85 PathProgramCache]: Analyzing trace with hash -523468439, now seen corresponding path program 1 times [2021-10-28 23:45:46,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993099932] [2021-10-28 23:45:46,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,568 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,621 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,621 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993099932] [2021-10-28 23:45:46,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993099932] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,622 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219801373] [2021-10-28 23:45:46,622 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:46,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,623 INFO L85 PathProgramCache]: Analyzing trace with hash 709018594, now seen corresponding path program 2 times [2021-10-28 23:45:46,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,624 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356649093] [2021-10-28 23:45:46,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,624 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,661 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,661 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356649093] [2021-10-28 23:45:46,661 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [356649093] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,661 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,662 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208877498] [2021-10-28 23:45:46,663 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:46,663 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:46,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:45:46,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:45:46,664 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:46,798 INFO L93 Difference]: Finished difference Result 952 states and 1374 transitions. [2021-10-28 23:45:46,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:45:46,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1374 transitions. [2021-10-28 23:45:46,809 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-10-28 23:45:46,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1374 transitions. [2021-10-28 23:45:46,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2021-10-28 23:45:46,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2021-10-28 23:45:46,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1374 transitions. [2021-10-28 23:45:46,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:46,821 INFO L681 BuchiCegarLoop]: Abstraction has 952 states and 1374 transitions. [2021-10-28 23:45:46,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1374 transitions. [2021-10-28 23:45:46,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 886. [2021-10-28 23:45:46,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 886 states, 886 states have (on average 1.4525959367945824) internal successors, (1287), 885 states have internal predecessors, (1287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:46,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 886 states to 886 states and 1287 transitions. [2021-10-28 23:45:46,846 INFO L704 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2021-10-28 23:45:46,846 INFO L587 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2021-10-28 23:45:46,846 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 23:45:46,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 886 states and 1287 transitions. [2021-10-28 23:45:46,852 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 822 [2021-10-28 23:45:46,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:46,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:46,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,854 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:46,854 INFO L791 eck$LassoCheckResult]: Stem: 6856#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6822#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6715#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6716#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 6811#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6717#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6618#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6619#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6764#L353-1 assume !(0 == ~M_E~0); 6749#L494-1 assume !(0 == ~T1_E~0); 6611#L499-1 assume !(0 == ~T2_E~0); 6612#L504-1 assume !(0 == ~T3_E~0); 6708#L509-1 assume !(0 == ~T4_E~0); 6586#L514-1 assume !(0 == ~E_1~0); 6587#L519-1 assume !(0 == ~E_2~0); 6596#L524-1 assume !(0 == ~E_3~0); 6597#L529-1 assume !(0 == ~E_4~0); 6776#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6780#L230 assume !(1 == ~m_pc~0); 6832#L230-2 is_master_triggered_~__retres1~0 := 0; 6557#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6558#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6569#L607 assume !(0 != activate_threads_~tmp~1); 6570#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6480#L249 assume !(1 == ~t1_pc~0); 6481#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 6544#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6777#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6778#L615 assume !(0 != activate_threads_~tmp___0~0); 6501#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6502#L268 assume !(1 == ~t2_pc~0); 6657#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 6642#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6643#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6471#L623 assume !(0 != activate_threads_~tmp___1~0); 6472#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6559#L287 assume 1 == ~t3_pc~0; 6552#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6553#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6588#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6589#L631 assume !(0 != activate_threads_~tmp___2~0); 6831#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6771#L306 assume !(1 == ~t4_pc~0); 6613#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 6614#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6786#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6819#L639 assume !(0 != activate_threads_~tmp___3~0); 6809#L639-2 assume !(1 == ~M_E~0); 6810#L547-1 assume !(1 == ~T1_E~0); 6833#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6692#L557-1 assume !(1 == ~T3_E~0); 6693#L562-1 assume !(1 == ~T4_E~0); 6697#L567-1 assume !(1 == ~E_1~0); 6691#L572-1 assume !(1 == ~E_2~0); 6625#L577-1 assume !(1 == ~E_3~0); 6565#L582-1 assume !(1 == ~E_4~0); 6566#L768-1 [2021-10-28 23:45:46,854 INFO L793 eck$LassoCheckResult]: Loop: 6566#L768-1 assume !false; 6622#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 6511#L469 assume !false; 6512#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6739#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 6485#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6797#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6798#L408 assume !(0 != eval_~tmp~0); 6763#L484 start_simulation_~kernel_st~0 := 2; 6542#L326-1 start_simulation_~kernel_st~0 := 3; 6543#L494-2 assume !(0 == ~M_E~0); 6467#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6468#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6689#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6509#L509-3 assume !(0 == ~T4_E~0); 6510#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6766#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6563#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6564#L529-3 assume !(0 == ~E_4~0); 6736#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6840#L230-15 assume !(1 == ~m_pc~0); 6640#L230-17 is_master_triggered_~__retres1~0 := 0; 6641#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6592#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6593#L607-15 assume !(0 != activate_threads_~tmp~1); 6740#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6645#L249-15 assume !(1 == ~t1_pc~0); 6646#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 6852#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6835#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6602#L615-15 assume !(0 != activate_threads_~tmp___0~0); 6603#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7339#L268-15 assume 1 == ~t2_pc~0; 7337#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7336#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7335#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6788#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6789#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6681#L287-15 assume !(1 == ~t3_pc~0); 6662#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 6577#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6555#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6556#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6758#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6759#L306-15 assume !(1 == ~t4_pc~0); 6800#L306-17 is_transmit4_triggered_~__retres1~4 := 0; 6675#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6676#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6850#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6820#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6663#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6578#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6579#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6690#L562-3 assume !(1 == ~T4_E~0); 6851#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6855#L572-3 assume !(1 == ~E_2~0); 6785#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6582#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6583#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6801#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 6492#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6770#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 6827#L787 assume !(0 == start_simulation_~tmp~3); 6660#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6661#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 6522#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6748#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 6584#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6585#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 6783#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 6796#L800 assume !(0 != start_simulation_~tmp___0~1); 6566#L768-1 [2021-10-28 23:45:46,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,855 INFO L85 PathProgramCache]: Analyzing trace with hash 395506184, now seen corresponding path program 1 times [2021-10-28 23:45:46,856 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,856 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387875093] [2021-10-28 23:45:46,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,856 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,894 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,895 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387875093] [2021-10-28 23:45:46,895 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387875093] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,895 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,895 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849651410] [2021-10-28 23:45:46,896 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:46,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:46,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1834467045, now seen corresponding path program 1 times [2021-10-28 23:45:46,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:46,910 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518261544] [2021-10-28 23:45:46,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:46,911 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:46,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:46,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:46,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:46,943 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518261544] [2021-10-28 23:45:46,943 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518261544] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:46,943 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:46,944 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:46,944 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203809291] [2021-10-28 23:45:46,944 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:46,945 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:46,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:45:46,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:45:46,946 INFO L87 Difference]: Start difference. First operand 886 states and 1287 transitions. cyclomatic complexity: 403 Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:47,096 INFO L93 Difference]: Finished difference Result 2293 states and 3293 transitions. [2021-10-28 23:45:47,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:45:47,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2293 states and 3293 transitions. [2021-10-28 23:45:47,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2131 [2021-10-28 23:45:47,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2293 states to 2293 states and 3293 transitions. [2021-10-28 23:45:47,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2293 [2021-10-28 23:45:47,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2293 [2021-10-28 23:45:47,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2293 states and 3293 transitions. [2021-10-28 23:45:47,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:47,156 INFO L681 BuchiCegarLoop]: Abstraction has 2293 states and 3293 transitions. [2021-10-28 23:45:47,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2293 states and 3293 transitions. [2021-10-28 23:45:47,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2293 to 2162. [2021-10-28 23:45:47,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.446345975948196) internal successors, (3127), 2161 states have internal predecessors, (3127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3127 transitions. [2021-10-28 23:45:47,217 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2021-10-28 23:45:47,217 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2021-10-28 23:45:47,217 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 23:45:47,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3127 transitions. [2021-10-28 23:45:47,239 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-10-28 23:45:47,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:47,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:47,240 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,240 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,241 INFO L791 eck$LassoCheckResult]: Stem: 10150#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 10060#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9916#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9917#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 10043#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9918#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9804#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9805#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9977#L353-1 assume !(0 == ~M_E~0); 9960#L494-1 assume !(0 == ~T1_E~0); 9797#L499-1 assume !(0 == ~T2_E~0); 9798#L504-1 assume !(0 == ~T3_E~0); 9908#L509-1 assume !(0 == ~T4_E~0); 9772#L514-1 assume !(0 == ~E_1~0); 9773#L519-1 assume !(0 == ~E_2~0); 9784#L524-1 assume !(0 == ~E_3~0); 9785#L529-1 assume !(0 == ~E_4~0); 9993#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10001#L230 assume !(1 == ~m_pc~0); 10089#L230-2 is_master_triggered_~__retres1~0 := 0; 9742#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9743#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9754#L607 assume !(0 != activate_threads_~tmp~1); 9755#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9671#L249 assume !(1 == ~t1_pc~0); 9672#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 9734#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9997#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9998#L615 assume !(0 != activate_threads_~tmp___0~0); 9695#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9696#L268 assume !(1 == ~t2_pc~0); 9849#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 9831#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9832#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9663#L623 assume !(0 != activate_threads_~tmp___1~0); 9664#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9744#L287 assume !(1 == ~t3_pc~0); 10081#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 10048#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9774#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9775#L631 assume !(0 != activate_threads_~tmp___2~0); 10085#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9988#L306 assume !(1 == ~t4_pc~0); 9801#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 9802#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10007#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10055#L639 assume !(0 != activate_threads_~tmp___3~0); 10041#L639-2 assume !(1 == ~M_E~0); 10042#L547-1 assume !(1 == ~T1_E~0); 10090#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9889#L557-1 assume !(1 == ~T3_E~0); 9890#L562-1 assume !(1 == ~T4_E~0); 9894#L567-1 assume !(1 == ~E_1~0); 9888#L572-1 assume !(1 == ~E_2~0); 9812#L577-1 assume !(1 == ~E_3~0); 9752#L582-1 assume !(1 == ~E_4~0); 9753#L768-1 [2021-10-28 23:45:47,241 INFO L793 eck$LassoCheckResult]: Loop: 9753#L768-1 assume !false; 11716#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11715#L469 assume !false; 11714#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9945#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9674#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 10018#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 10019#L408 assume !(0 != eval_~tmp~0); 9975#L484 start_simulation_~kernel_st~0 := 2; 9976#L326-1 start_simulation_~kernel_st~0 := 3; 10143#L494-2 assume !(0 == ~M_E~0); 10144#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10139#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10140#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9699#L509-3 assume !(0 == ~T4_E~0); 9700#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9980#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9981#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9939#L529-3 assume !(0 == ~E_4~0); 9940#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10131#L230-15 assume !(1 == ~m_pc~0); 10132#L230-17 is_master_triggered_~__retres1~0 := 0; 10039#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10040#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10141#L607-15 assume !(0 != activate_threads_~tmp~1); 10142#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9833#L249-15 assume !(1 == ~t1_pc~0); 9834#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 10124#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10092#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10093#L615-15 assume !(0 != activate_threads_~tmp___0~0); 10101#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10102#L268-15 assume !(1 == ~t2_pc~0); 9738#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 9739#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9909#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10010#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10011#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9872#L287-15 assume !(1 == ~t3_pc~0); 9873#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 9762#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9763#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10156#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10157#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10023#L306-15 assume 1 == ~t4_pc~0; 10024#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10098#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10133#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10134#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10056#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 10057#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9764#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9765#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11764#L562-3 assume !(1 == ~T4_E~0); 10154#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10155#L572-3 assume !(1 == ~E_2~0); 10005#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10006#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10075#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 10076#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9986#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9987#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11726#L787 assume !(0 == start_simulation_~tmp~3); 9850#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9851#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9958#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9959#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 9770#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9771#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 10125#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10126#L800 assume !(0 != start_simulation_~tmp___0~1); 9753#L768-1 [2021-10-28 23:45:47,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1056839975, now seen corresponding path program 1 times [2021-10-28 23:45:47,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,242 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788326875] [2021-10-28 23:45:47,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,242 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:47,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:47,278 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:47,278 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788326875] [2021-10-28 23:45:47,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788326875] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:47,278 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:47,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:45:47,279 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279553432] [2021-10-28 23:45:47,279 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:47,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1744911003, now seen corresponding path program 1 times [2021-10-28 23:45:47,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,280 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347238170] [2021-10-28 23:45:47,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,280 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:47,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:47,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:47,309 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347238170] [2021-10-28 23:45:47,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347238170] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:47,309 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:47,309 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:47,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160948395] [2021-10-28 23:45:47,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:47,310 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:47,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:47,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:47,311 INFO L87 Difference]: Start difference. First operand 2162 states and 3127 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:47,338 INFO L93 Difference]: Finished difference Result 2162 states and 3098 transitions. [2021-10-28 23:45:47,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:47,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3098 transitions. [2021-10-28 23:45:47,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-10-28 23:45:47,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3098 transitions. [2021-10-28 23:45:47,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2021-10-28 23:45:47,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2021-10-28 23:45:47,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3098 transitions. [2021-10-28 23:45:47,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:47,384 INFO L681 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-10-28 23:45:47,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3098 transitions. [2021-10-28 23:45:47,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2021-10-28 23:45:47,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.432932469935245) internal successors, (3098), 2161 states have internal predecessors, (3098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3098 transitions. [2021-10-28 23:45:47,431 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-10-28 23:45:47,431 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-10-28 23:45:47,431 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 23:45:47,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3098 transitions. [2021-10-28 23:45:47,445 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-10-28 23:45:47,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:47,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:47,446 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,447 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,447 INFO L791 eck$LassoCheckResult]: Stem: 14411#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 14358#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14239#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14240#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 14345#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14241#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14137#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14138#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14290#L353-1 assume !(0 == ~M_E~0); 14276#L494-1 assume !(0 == ~T1_E~0); 14129#L499-1 assume !(0 == ~T2_E~0); 14130#L504-1 assume !(0 == ~T3_E~0); 14230#L509-1 assume !(0 == ~T4_E~0); 14104#L514-1 assume !(0 == ~E_1~0); 14105#L519-1 assume !(0 == ~E_2~0); 14116#L524-1 assume !(0 == ~E_3~0); 14117#L529-1 assume !(0 == ~E_4~0); 14304#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14310#L230 assume !(1 == ~m_pc~0); 14380#L230-2 is_master_triggered_~__retres1~0 := 0; 14074#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14075#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14087#L607 assume !(0 != activate_threads_~tmp~1); 14088#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14003#L249 assume !(1 == ~t1_pc~0); 14004#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 14066#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14306#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14307#L615 assume !(0 != activate_threads_~tmp___0~0); 14027#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14028#L268 assume !(1 == ~t2_pc~0); 14178#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 14162#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14163#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13995#L623 assume !(0 != activate_threads_~tmp___1~0); 13996#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14076#L287 assume !(1 == ~t3_pc~0); 14374#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 14348#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14106#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14107#L631 assume !(0 != activate_threads_~tmp___2~0); 14379#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14299#L306 assume !(1 == ~t4_pc~0); 14133#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 14134#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14315#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14353#L639 assume !(0 != activate_threads_~tmp___3~0); 14343#L639-2 assume !(1 == ~M_E~0); 14344#L547-1 assume !(1 == ~T1_E~0); 14381#L552-1 assume !(1 == ~T2_E~0); 14210#L557-1 assume !(1 == ~T3_E~0); 14211#L562-1 assume !(1 == ~T4_E~0); 14216#L567-1 assume !(1 == ~E_1~0); 14209#L572-1 assume !(1 == ~E_2~0); 14144#L577-1 assume !(1 == ~E_3~0); 14085#L582-1 assume !(1 == ~E_4~0); 14086#L768-1 [2021-10-28 23:45:47,447 INFO L793 eck$LassoCheckResult]: Loop: 14086#L768-1 assume !false; 15710#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15708#L469 assume !false; 15706#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15704#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15698#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15696#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15694#L408 assume !(0 != eval_~tmp~0); 14289#L484 start_simulation_~kernel_st~0 := 2; 14062#L326-1 start_simulation_~kernel_st~0 := 3; 14063#L494-2 assume !(0 == ~M_E~0); 13988#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13989#L499-3 assume !(0 == ~T2_E~0); 14207#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14031#L509-3 assume !(0 == ~T4_E~0); 14032#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14293#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14081#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14082#L529-3 assume !(0 == ~E_4~0); 14260#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14392#L230-15 assume !(1 == ~m_pc~0); 14404#L230-17 is_master_triggered_~__retres1~0 := 0; 15934#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15933#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15932#L607-15 assume !(0 != activate_threads_~tmp~1); 15931#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14164#L249-15 assume !(1 == ~t1_pc~0); 14165#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 14077#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14078#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14118#L615-15 assume !(0 != activate_threads_~tmp___0~0); 14119#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14185#L268-15 assume !(1 == ~t2_pc~0); 14070#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 14071#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14232#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14317#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14318#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14197#L287-15 assume !(1 == ~t3_pc~0); 14181#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 14095#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14072#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14073#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16005#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16004#L306-15 assume 1 == ~t4_pc~0; 16002#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16001#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15999#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15996#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15993#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 15989#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15986#L552-3 assume !(1 == ~T2_E~0); 15983#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15980#L562-3 assume !(1 == ~T4_E~0); 15977#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15974#L572-3 assume !(1 == ~E_2~0); 15972#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15965#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14368#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 14333#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 14013#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 14298#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 14363#L787 assume !(0 == start_simulation_~tmp~3); 14179#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 14180#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 14042#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15739#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 15738#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 15737#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 15736#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15735#L800 assume !(0 != start_simulation_~tmp___0~1); 14086#L768-1 [2021-10-28 23:45:47,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,448 INFO L85 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 1 times [2021-10-28 23:45:47,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,448 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834592626] [2021-10-28 23:45:47,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,448 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:47,458 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:47,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:47,498 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:47,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,498 INFO L85 PathProgramCache]: Analyzing trace with hash -2001859675, now seen corresponding path program 1 times [2021-10-28 23:45:47,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,499 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648458484] [2021-10-28 23:45:47,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,499 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:47,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:47,522 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:47,522 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648458484] [2021-10-28 23:45:47,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648458484] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:47,522 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:47,522 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:47,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860351160] [2021-10-28 23:45:47,523 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:47,523 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:47,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:47,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:47,524 INFO L87 Difference]: Start difference. First operand 2162 states and 3098 transitions. cyclomatic complexity: 940 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:47,613 INFO L93 Difference]: Finished difference Result 3793 states and 5373 transitions. [2021-10-28 23:45:47,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:47,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3793 states and 5373 transitions. [2021-10-28 23:45:47,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3664 [2021-10-28 23:45:47,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3793 states to 3793 states and 5373 transitions. [2021-10-28 23:45:47,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3793 [2021-10-28 23:45:47,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3793 [2021-10-28 23:45:47,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3793 states and 5373 transitions. [2021-10-28 23:45:47,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:47,689 INFO L681 BuchiCegarLoop]: Abstraction has 3793 states and 5373 transitions. [2021-10-28 23:45:47,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3793 states and 5373 transitions. [2021-10-28 23:45:47,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3793 to 3790. [2021-10-28 23:45:47,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3790 states, 3790 states have (on average 1.4168865435356202) internal successors, (5370), 3789 states have internal predecessors, (5370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3790 states to 3790 states and 5370 transitions. [2021-10-28 23:45:47,773 INFO L704 BuchiCegarLoop]: Abstraction has 3790 states and 5370 transitions. [2021-10-28 23:45:47,773 INFO L587 BuchiCegarLoop]: Abstraction has 3790 states and 5370 transitions. [2021-10-28 23:45:47,776 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 23:45:47,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3790 states and 5370 transitions. [2021-10-28 23:45:47,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3661 [2021-10-28 23:45:47,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:47,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:47,798 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,798 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:47,799 INFO L791 eck$LassoCheckResult]: Stem: 20380#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 20326#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20201#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20202#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 20312#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20203#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20099#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20100#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20251#L353-1 assume !(0 == ~M_E~0); 20236#L494-1 assume !(0 == ~T1_E~0); 20090#L499-1 assume !(0 == ~T2_E~0); 20091#L504-1 assume !(0 == ~T3_E~0); 20192#L509-1 assume !(0 == ~T4_E~0); 20065#L514-1 assume !(0 == ~E_1~0); 20066#L519-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20077#L524-1 assume !(0 == ~E_3~0); 20078#L529-1 assume !(0 == ~E_4~0); 20267#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20274#L230 assume !(1 == ~m_pc~0); 20448#L230-2 is_master_triggered_~__retres1~0 := 0; 20036#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20037#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20048#L607 assume !(0 != activate_threads_~tmp~1); 20049#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20131#L249 assume !(1 == ~t1_pc~0); 20027#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 20028#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20440#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20438#L615 assume !(0 != activate_threads_~tmp___0~0); 20437#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20436#L268 assume !(1 == ~t2_pc~0); 20434#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 20140#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20433#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20432#L623 assume !(0 != activate_threads_~tmp___1~0); 20430#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20426#L287 assume !(1 == ~t3_pc~0); 20424#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 20422#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20420#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20417#L631 assume !(0 != activate_threads_~tmp___2~0); 20415#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20413#L306 assume !(1 == ~t4_pc~0); 20409#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 20407#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20405#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20403#L639 assume !(0 != activate_threads_~tmp___3~0); 20401#L639-2 assume !(1 == ~M_E~0); 20399#L547-1 assume !(1 == ~T1_E~0); 20396#L552-1 assume !(1 == ~T2_E~0); 20394#L557-1 assume !(1 == ~T3_E~0); 20392#L562-1 assume !(1 == ~T4_E~0); 20178#L567-1 assume !(1 == ~E_1~0); 20172#L572-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20104#L577-1 assume !(1 == ~E_3~0); 20046#L582-1 assume !(1 == ~E_4~0); 20047#L768-1 [2021-10-28 23:45:47,799 INFO L793 eck$LassoCheckResult]: Loop: 20047#L768-1 assume !false; 23148#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 22543#L469 assume !false; 22544#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23145#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23139#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23137#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 23134#L408 assume !(0 != eval_~tmp~0); 23135#L484 start_simulation_~kernel_st~0 := 2; 23327#L326-1 start_simulation_~kernel_st~0 := 3; 23325#L494-2 assume !(0 == ~M_E~0); 23323#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23321#L499-3 assume !(0 == ~T2_E~0); 23319#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23317#L509-3 assume !(0 == ~T4_E~0); 23315#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23293#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23291#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23289#L529-3 assume !(0 == ~E_4~0); 23288#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23287#L230-15 assume !(1 == ~m_pc~0); 23286#L230-17 is_master_triggered_~__retres1~0 := 0; 23285#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23284#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23283#L607-15 assume !(0 != activate_threads_~tmp~1); 23281#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23280#L249-15 assume !(1 == ~t1_pc~0); 23279#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 23277#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23275#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23273#L615-15 assume !(0 != activate_threads_~tmp___0~0); 23271#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23269#L268-15 assume 1 == ~t2_pc~0; 23266#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23264#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23262#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23260#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23258#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23256#L287-15 assume !(1 == ~t3_pc~0); 23254#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 23250#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23248#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23246#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23244#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23242#L306-15 assume 1 == ~t4_pc~0; 23239#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23237#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23235#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23233#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23231#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 23229#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23227#L552-3 assume !(1 == ~T2_E~0); 23225#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23222#L562-3 assume !(1 == ~T4_E~0); 23220#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23218#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23215#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23213#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23211#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23204#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23199#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23197#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 23195#L787 assume !(0 == start_simulation_~tmp~3); 23193#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23182#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23178#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23176#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 23174#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 23172#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 23156#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 23155#L800 assume !(0 != start_simulation_~tmp___0~1); 20047#L768-1 [2021-10-28 23:45:47,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1711268375, now seen corresponding path program 1 times [2021-10-28 23:45:47,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,804 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541809024] [2021-10-28 23:45:47,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,804 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:47,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:47,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:47,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541809024] [2021-10-28 23:45:47,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541809024] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:47,837 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:47,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:45:47,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972915146] [2021-10-28 23:45:47,838 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:47,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:47,839 INFO L85 PathProgramCache]: Analyzing trace with hash -23862938, now seen corresponding path program 1 times [2021-10-28 23:45:47,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:47,839 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133556981] [2021-10-28 23:45:47,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:47,840 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:47,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:47,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:47,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:47,876 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133556981] [2021-10-28 23:45:47,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133556981] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:47,876 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:47,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:45:47,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567256275] [2021-10-28 23:45:47,877 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:47,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:47,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:47,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:47,878 INFO L87 Difference]: Start difference. First operand 3790 states and 5370 transitions. cyclomatic complexity: 1584 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:47,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:47,924 INFO L93 Difference]: Finished difference Result 2162 states and 3031 transitions. [2021-10-28 23:45:47,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:47,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3031 transitions. [2021-10-28 23:45:47,939 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-10-28 23:45:47,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3031 transitions. [2021-10-28 23:45:47,958 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2021-10-28 23:45:47,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2021-10-28 23:45:47,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3031 transitions. [2021-10-28 23:45:47,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:47,965 INFO L681 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-10-28 23:45:47,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3031 transitions. [2021-10-28 23:45:48,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2021-10-28 23:45:48,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.4019426456984274) internal successors, (3031), 2161 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:48,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3031 transitions. [2021-10-28 23:45:48,017 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-10-28 23:45:48,017 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-10-28 23:45:48,017 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 23:45:48,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3031 transitions. [2021-10-28 23:45:48,027 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-10-28 23:45:48,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:48,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:48,032 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,032 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,032 INFO L791 eck$LassoCheckResult]: Stem: 26312#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 26269#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 26153#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26154#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 26255#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26155#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26055#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26056#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26202#L353-1 assume !(0 == ~M_E~0); 26187#L494-1 assume !(0 == ~T1_E~0); 26049#L499-1 assume !(0 == ~T2_E~0); 26050#L504-1 assume !(0 == ~T3_E~0); 26145#L509-1 assume !(0 == ~T4_E~0); 26024#L514-1 assume !(0 == ~E_1~0); 26025#L519-1 assume !(0 == ~E_2~0); 26036#L524-1 assume !(0 == ~E_3~0); 26037#L529-1 assume !(0 == ~E_4~0); 26217#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26223#L230 assume !(1 == ~m_pc~0); 26286#L230-2 is_master_triggered_~__retres1~0 := 0; 25995#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25996#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26007#L607 assume !(0 != activate_threads_~tmp~1); 26008#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25924#L249 assume !(1 == ~t1_pc~0); 25925#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 25987#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26219#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26220#L615 assume !(0 != activate_threads_~tmp___0~0); 25948#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25949#L268 assume !(1 == ~t2_pc~0); 26098#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 26081#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26082#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25916#L623 assume !(0 != activate_threads_~tmp___1~0); 25917#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25997#L287 assume !(1 == ~t3_pc~0); 26281#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 26259#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26026#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26027#L631 assume !(0 != activate_threads_~tmp___2~0); 26285#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26212#L306 assume !(1 == ~t4_pc~0); 26053#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 26054#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26229#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26265#L639 assume !(0 != activate_threads_~tmp___3~0); 26253#L639-2 assume !(1 == ~M_E~0); 26254#L547-1 assume !(1 == ~T1_E~0); 26287#L552-1 assume !(1 == ~T2_E~0); 26129#L557-1 assume !(1 == ~T3_E~0); 26130#L562-1 assume !(1 == ~T4_E~0); 26134#L567-1 assume !(1 == ~E_1~0); 26128#L572-1 assume !(1 == ~E_2~0); 26063#L577-1 assume !(1 == ~E_3~0); 26005#L582-1 assume !(1 == ~E_4~0); 26006#L768-1 [2021-10-28 23:45:48,033 INFO L793 eck$LassoCheckResult]: Loop: 26006#L768-1 assume !false; 27824#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 27821#L469 assume !false; 27819#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27733#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27727#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27725#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 27723#L408 assume !(0 != eval_~tmp~0); 27724#L484 start_simulation_~kernel_st~0 := 2; 27984#L326-1 start_simulation_~kernel_st~0 := 3; 27982#L494-2 assume !(0 == ~M_E~0); 27980#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27978#L499-3 assume !(0 == ~T2_E~0); 27976#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27974#L509-3 assume !(0 == ~T4_E~0); 27972#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27970#L519-3 assume !(0 == ~E_2~0); 27968#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27967#L529-3 assume !(0 == ~E_4~0); 27966#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27965#L230-15 assume !(1 == ~m_pc~0); 27964#L230-17 is_master_triggered_~__retres1~0 := 0; 27963#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27962#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27961#L607-15 assume !(0 != activate_threads_~tmp~1); 27960#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27959#L249-15 assume !(1 == ~t1_pc~0); 27958#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 27956#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27954#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 27952#L615-15 assume !(0 != activate_threads_~tmp___0~0); 27950#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27948#L268-15 assume !(1 == ~t2_pc~0); 27945#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 27943#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27941#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27939#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27937#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27935#L287-15 assume !(1 == ~t3_pc~0); 27933#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 27930#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27928#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27926#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27924#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27922#L306-15 assume !(1 == ~t4_pc~0); 27920#L306-17 is_transmit4_triggered_~__retres1~4 := 0; 27917#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27915#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27913#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27911#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 27909#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27907#L552-3 assume !(1 == ~T2_E~0); 27905#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27902#L562-3 assume !(1 == ~T4_E~0); 27900#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27898#L572-3 assume !(1 == ~E_2~0); 27896#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27894#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27892#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27885#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27881#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27879#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 27877#L787 assume !(0 == start_simulation_~tmp~3); 27875#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27872#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27869#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27868#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 27866#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 27864#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 27862#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 27860#L800 assume !(0 != start_simulation_~tmp___0~1); 26006#L768-1 [2021-10-28 23:45:48,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 2 times [2021-10-28 23:45:48,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,034 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230706576] [2021-10-28 23:45:48,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,034 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,048 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:48,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,084 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:48,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2007375400, now seen corresponding path program 1 times [2021-10-28 23:45:48,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,086 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567497510] [2021-10-28 23:45:48,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,086 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:48,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:48,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:48,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567497510] [2021-10-28 23:45:48,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567497510] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:48,125 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:48,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-10-28 23:45:48,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278064653] [2021-10-28 23:45:48,126 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:48,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:48,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:45:48,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:45:48,127 INFO L87 Difference]: Start difference. First operand 2162 states and 3031 transitions. cyclomatic complexity: 873 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:48,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:48,254 INFO L93 Difference]: Finished difference Result 3731 states and 5155 transitions. [2021-10-28 23:45:48,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 23:45:48,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3731 states and 5155 transitions. [2021-10-28 23:45:48,283 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3643 [2021-10-28 23:45:48,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3731 states to 3731 states and 5155 transitions. [2021-10-28 23:45:48,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3731 [2021-10-28 23:45:48,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3731 [2021-10-28 23:45:48,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3731 states and 5155 transitions. [2021-10-28 23:45:48,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:48,325 INFO L681 BuchiCegarLoop]: Abstraction has 3731 states and 5155 transitions. [2021-10-28 23:45:48,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3731 states and 5155 transitions. [2021-10-28 23:45:48,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3731 to 2189. [2021-10-28 23:45:48,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2189 states, 2189 states have (on average 1.3969849246231156) internal successors, (3058), 2188 states have internal predecessors, (3058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:48,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2189 states to 2189 states and 3058 transitions. [2021-10-28 23:45:48,382 INFO L704 BuchiCegarLoop]: Abstraction has 2189 states and 3058 transitions. [2021-10-28 23:45:48,382 INFO L587 BuchiCegarLoop]: Abstraction has 2189 states and 3058 transitions. [2021-10-28 23:45:48,382 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 23:45:48,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2189 states and 3058 transitions. [2021-10-28 23:45:48,392 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2116 [2021-10-28 23:45:48,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:48,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:48,393 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,394 INFO L791 eck$LassoCheckResult]: Stem: 32252#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 32189#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32066#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32067#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 32175#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32068#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31964#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31965#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32118#L353-1 assume !(0 == ~M_E~0); 32101#L494-1 assume !(0 == ~T1_E~0); 31956#L499-1 assume !(0 == ~T2_E~0); 31957#L504-1 assume !(0 == ~T3_E~0); 32055#L509-1 assume !(0 == ~T4_E~0); 31931#L514-1 assume !(0 == ~E_1~0); 31932#L519-1 assume !(0 == ~E_2~0); 31943#L524-1 assume !(0 == ~E_3~0); 31944#L529-1 assume !(0 == ~E_4~0); 32135#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32140#L230 assume !(1 == ~m_pc~0); 32209#L230-2 is_master_triggered_~__retres1~0 := 0; 31902#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31903#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 31916#L607 assume !(0 != activate_threads_~tmp~1); 31917#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31827#L249 assume !(1 == ~t1_pc~0); 31828#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 31894#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32137#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32138#L615 assume !(0 != activate_threads_~tmp___0~0); 31852#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31853#L268 assume !(1 == ~t2_pc~0); 32005#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 31989#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31990#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 31820#L623 assume !(0 != activate_threads_~tmp___1~0); 31821#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31906#L287 assume !(1 == ~t3_pc~0); 32204#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 32179#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31933#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31934#L631 assume !(0 != activate_threads_~tmp___2~0); 32208#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32129#L306 assume !(1 == ~t4_pc~0); 31960#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 31961#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32146#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 32185#L639 assume !(0 != activate_threads_~tmp___3~0); 32173#L639-2 assume !(1 == ~M_E~0); 32174#L547-1 assume !(1 == ~T1_E~0); 32212#L552-1 assume !(1 == ~T2_E~0); 32041#L557-1 assume !(1 == ~T3_E~0); 32042#L562-1 assume !(1 == ~T4_E~0); 32046#L567-1 assume !(1 == ~E_1~0); 32039#L572-1 assume !(1 == ~E_2~0); 31969#L577-1 assume !(1 == ~E_3~0); 31912#L582-1 assume !(1 == ~E_4~0); 31913#L768-1 [2021-10-28 23:45:48,400 INFO L793 eck$LassoCheckResult]: Loop: 31913#L768-1 assume !false; 31970#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 31859#L469 assume !false; 31860#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33587#L366 assume !(0 == ~m_st~0); 33584#L370 assume !(0 == ~t1_st~0); 33585#L374 assume !(0 == ~t2_st~0); 33586#L378 assume !(0 == ~t3_st~0); 32107#L382 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 32109#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33332#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 33333#L408 assume !(0 != eval_~tmp~0); 32119#L484 start_simulation_~kernel_st~0 := 2; 32120#L326-1 start_simulation_~kernel_st~0 := 3; 32248#L494-2 assume !(0 == ~M_E~0); 32249#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32244#L499-3 assume !(0 == ~T2_E~0); 32245#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31861#L509-3 assume !(0 == ~T4_E~0); 31862#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32123#L519-3 assume !(0 == ~E_2~0); 32124#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32087#L529-3 assume !(0 == ~E_4~0); 32088#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32238#L230-15 assume !(1 == ~m_pc~0); 32239#L230-17 is_master_triggered_~__retres1~0 := 0; 32171#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32172#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32246#L607-15 assume !(0 != activate_threads_~tmp~1); 32247#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31992#L249-15 assume !(1 == ~t1_pc~0); 31993#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 31908#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31909#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31949#L615-15 assume !(0 != activate_threads_~tmp___0~0); 31950#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32014#L268-15 assume !(1 == ~t2_pc~0); 31900#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 31901#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32063#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32148#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32149#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32031#L287-15 assume !(1 == ~t3_pc~0); 32010#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 31924#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31904#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31905#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32115#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32116#L306-15 assume 1 == ~t4_pc~0; 32160#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32025#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32026#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 32232#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32186#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 32013#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31925#L552-3 assume !(1 == ~T2_E~0); 31926#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32040#L562-3 assume !(1 == ~T4_E~0); 32233#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32250#L572-3 assume !(1 == ~E_2~0); 32147#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31929#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31930#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 32199#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33903#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33901#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 33899#L787 assume !(0 == start_simulation_~tmp~3); 33896#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 32077#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31872#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 32102#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 31935#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 31936#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 32145#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 32159#L800 assume !(0 != start_simulation_~tmp___0~1); 31913#L768-1 [2021-10-28 23:45:48,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 3 times [2021-10-28 23:45:48,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,401 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821976003] [2021-10-28 23:45:48,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,401 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,413 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:48,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,443 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:48,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,445 INFO L85 PathProgramCache]: Analyzing trace with hash 370582195, now seen corresponding path program 1 times [2021-10-28 23:45:48,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96292317] [2021-10-28 23:45:48,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,451 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:48,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:48,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:48,479 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96292317] [2021-10-28 23:45:48,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96292317] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:48,480 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:48,480 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:48,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133070741] [2021-10-28 23:45:48,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-10-28 23:45:48,481 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:48,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:48,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:48,481 INFO L87 Difference]: Start difference. First operand 2189 states and 3058 transitions. cyclomatic complexity: 873 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:48,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:48,530 INFO L93 Difference]: Finished difference Result 3483 states and 4792 transitions. [2021-10-28 23:45:48,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:48,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3483 states and 4792 transitions. [2021-10-28 23:45:48,554 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3408 [2021-10-28 23:45:48,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3483 states to 3483 states and 4792 transitions. [2021-10-28 23:45:48,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3483 [2021-10-28 23:45:48,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3483 [2021-10-28 23:45:48,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3483 states and 4792 transitions. [2021-10-28 23:45:48,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:48,595 INFO L681 BuchiCegarLoop]: Abstraction has 3483 states and 4792 transitions. [2021-10-28 23:45:48,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3483 states and 4792 transitions. [2021-10-28 23:45:48,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3483 to 3363. [2021-10-28 23:45:48,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3363 states, 3363 states have (on average 1.3785310734463276) internal successors, (4636), 3362 states have internal predecessors, (4636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:48,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3363 states to 3363 states and 4636 transitions. [2021-10-28 23:45:48,669 INFO L704 BuchiCegarLoop]: Abstraction has 3363 states and 4636 transitions. [2021-10-28 23:45:48,669 INFO L587 BuchiCegarLoop]: Abstraction has 3363 states and 4636 transitions. [2021-10-28 23:45:48,670 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 23:45:48,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3363 states and 4636 transitions. [2021-10-28 23:45:48,685 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3288 [2021-10-28 23:45:48,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:48,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:48,686 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,686 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:48,687 INFO L791 eck$LassoCheckResult]: Stem: 37932#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 37877#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37750#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37751#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 37862#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37752#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37644#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37645#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37802#L353-1 assume !(0 == ~M_E~0); 37786#L494-1 assume !(0 == ~T1_E~0); 37636#L499-1 assume !(0 == ~T2_E~0); 37637#L504-1 assume !(0 == ~T3_E~0); 37739#L509-1 assume !(0 == ~T4_E~0); 37611#L514-1 assume !(0 == ~E_1~0); 37612#L519-1 assume !(0 == ~E_2~0); 37623#L524-1 assume !(0 == ~E_3~0); 37624#L529-1 assume !(0 == ~E_4~0); 37818#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37823#L230 assume !(1 == ~m_pc~0); 37899#L230-2 is_master_triggered_~__retres1~0 := 0; 37581#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37582#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 37596#L607 assume !(0 != activate_threads_~tmp~1); 37597#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37505#L249 assume !(1 == ~t1_pc~0); 37506#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 37573#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37820#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 37821#L615 assume !(0 != activate_threads_~tmp___0~0); 37530#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37531#L268 assume !(1 == ~t2_pc~0); 37686#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 37670#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37671#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37498#L623 assume !(0 != activate_threads_~tmp___1~0); 37499#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37585#L287 assume !(1 == ~t3_pc~0); 37894#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 37867#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37613#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37614#L631 assume !(0 != activate_threads_~tmp___2~0); 37898#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37811#L306 assume !(1 == ~t4_pc~0); 37640#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 37641#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37829#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37872#L639 assume !(0 != activate_threads_~tmp___3~0); 37860#L639-2 assume !(1 == ~M_E~0); 37861#L547-1 assume !(1 == ~T1_E~0); 37901#L552-1 assume !(1 == ~T2_E~0); 37725#L557-1 assume !(1 == ~T3_E~0); 37726#L562-1 assume !(1 == ~T4_E~0); 37730#L567-1 assume !(1 == ~E_1~0); 37722#L572-1 assume !(1 == ~E_2~0); 37649#L577-1 assume !(1 == ~E_3~0); 37592#L582-1 assume !(1 == ~E_4~0); 37593#L768-1 assume !false; 39566#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 39563#L469 [2021-10-28 23:45:48,687 INFO L793 eck$LassoCheckResult]: Loop: 39563#L469 assume !false; 39560#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 39557#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 39554#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 39550#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 39546#L408 assume 0 != eval_~tmp~0; 39529#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 39526#L416 assume !(0 != eval_~tmp_ndt_1~0); 39525#L413 assume !(0 == ~t1_st~0); 39380#L427 assume !(0 == ~t2_st~0); 39187#L441 assume !(0 == ~t3_st~0); 38611#L455 assume !(0 == ~t4_st~0); 39563#L469 [2021-10-28 23:45:48,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 1 times [2021-10-28 23:45:48,689 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,689 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569843372] [2021-10-28 23:45:48,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,689 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,698 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:48,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,717 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:48,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,717 INFO L85 PathProgramCache]: Analyzing trace with hash 590384517, now seen corresponding path program 1 times [2021-10-28 23:45:48,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243755657] [2021-10-28 23:45:48,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,718 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,721 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:48,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:48,725 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:48,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:48,726 INFO L85 PathProgramCache]: Analyzing trace with hash 162355663, now seen corresponding path program 1 times [2021-10-28 23:45:48,726 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:48,726 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455966041] [2021-10-28 23:45:48,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:48,726 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:48,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:48,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:48,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:48,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455966041] [2021-10-28 23:45:48,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455966041] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:48,753 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:48,753 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:48,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067981200] [2021-10-28 23:45:48,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:48,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:48,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:48,875 INFO L87 Difference]: Start difference. First operand 3363 states and 4636 transitions. cyclomatic complexity: 1280 Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:49,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:49,013 INFO L93 Difference]: Finished difference Result 6225 states and 8480 transitions. [2021-10-28 23:45:49,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:49,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6225 states and 8480 transitions. [2021-10-28 23:45:49,067 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5817 [2021-10-28 23:45:49,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6225 states to 6225 states and 8480 transitions. [2021-10-28 23:45:49,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6225 [2021-10-28 23:45:49,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6225 [2021-10-28 23:45:49,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6225 states and 8480 transitions. [2021-10-28 23:45:49,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:49,127 INFO L681 BuchiCegarLoop]: Abstraction has 6225 states and 8480 transitions. [2021-10-28 23:45:49,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6225 states and 8480 transitions. [2021-10-28 23:45:49,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6225 to 6085. [2021-10-28 23:45:49,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6085 states, 6085 states have (on average 1.3640098603122432) internal successors, (8300), 6084 states have internal predecessors, (8300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:49,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6085 states to 6085 states and 8300 transitions. [2021-10-28 23:45:49,274 INFO L704 BuchiCegarLoop]: Abstraction has 6085 states and 8300 transitions. [2021-10-28 23:45:49,274 INFO L587 BuchiCegarLoop]: Abstraction has 6085 states and 8300 transitions. [2021-10-28 23:45:49,274 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 23:45:49,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6085 states and 8300 transitions. [2021-10-28 23:45:49,301 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5677 [2021-10-28 23:45:49,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:49,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:49,302 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:49,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:49,303 INFO L791 eck$LassoCheckResult]: Stem: 47585#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 47501#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 47352#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 47353#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 47484#L333-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 47575#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47243#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47244#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47414#L353-1 assume !(0 == ~M_E~0); 47415#L494-1 assume !(0 == ~T1_E~0); 47235#L499-1 assume !(0 == ~T2_E~0); 47236#L504-1 assume !(0 == ~T3_E~0); 47535#L509-1 assume !(0 == ~T4_E~0); 47536#L514-1 assume !(0 == ~E_1~0); 47434#L519-1 assume !(0 == ~E_2~0); 47435#L524-1 assume !(0 == ~E_3~0); 47432#L529-1 assume !(0 == ~E_4~0); 47433#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47527#L230 assume !(1 == ~m_pc~0); 47528#L230-2 is_master_triggered_~__retres1~0 := 0; 47178#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47179#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 47193#L607 assume !(0 != activate_threads_~tmp~1); 47194#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47102#L249 assume !(1 == ~t1_pc~0); 47103#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 47521#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47522#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 47453#L615 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 47126#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47127#L268 assume !(1 == ~t2_pc~0); 47563#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 47564#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47553#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 47554#L623 assume !(0 != activate_threads_~tmp___1~0); 47182#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47183#L287 assume !(1 == ~t3_pc~0); 47548#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 47549#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47211#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 47212#L631 assume !(0 != activate_threads_~tmp___2~0); 50114#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50113#L306 assume !(1 == ~t4_pc~0); 50111#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 50110#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50109#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 50108#L639 assume !(0 != activate_threads_~tmp___3~0); 50107#L639-2 assume !(1 == ~M_E~0); 50106#L547-1 assume !(1 == ~T1_E~0); 50105#L552-1 assume !(1 == ~T2_E~0); 50104#L557-1 assume !(1 == ~T3_E~0); 50103#L562-1 assume !(1 == ~T4_E~0); 50102#L567-1 assume !(1 == ~E_1~0); 50101#L572-1 assume !(1 == ~E_2~0); 50100#L577-1 assume !(1 == ~E_3~0); 47189#L582-1 assume !(1 == ~E_4~0); 47190#L768-1 assume !false; 50341#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 50338#L469 [2021-10-28 23:45:49,303 INFO L793 eck$LassoCheckResult]: Loop: 50338#L469 assume !false; 50339#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51467#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51465#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 50331#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 50329#L408 assume 0 != eval_~tmp~0; 50327#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 50312#L416 assume !(0 != eval_~tmp_ndt_1~0); 47773#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 47770#L430 assume !(0 != eval_~tmp_ndt_2~0); 47771#L427 assume !(0 == ~t2_st~0); 51485#L441 assume !(0 == ~t3_st~0); 50344#L455 assume !(0 == ~t4_st~0); 50338#L469 [2021-10-28 23:45:49,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:49,304 INFO L85 PathProgramCache]: Analyzing trace with hash -750579381, now seen corresponding path program 1 times [2021-10-28 23:45:49,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:49,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134052798] [2021-10-28 23:45:49,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:49,304 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:49,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:49,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:49,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:49,324 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134052798] [2021-10-28 23:45:49,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134052798] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:49,324 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:49,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:49,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365243692] [2021-10-28 23:45:49,325 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:45:49,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:49,325 INFO L85 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 1 times [2021-10-28 23:45:49,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:49,325 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822836334] [2021-10-28 23:45:49,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:49,326 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:49,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,332 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:49,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,336 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:49,470 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:49,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:49,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:49,471 INFO L87 Difference]: Start difference. First operand 6085 states and 8300 transitions. cyclomatic complexity: 2226 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:49,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:49,497 INFO L93 Difference]: Finished difference Result 4976 states and 6801 transitions. [2021-10-28 23:45:49,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:49,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4976 states and 6801 transitions. [2021-10-28 23:45:49,587 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2021-10-28 23:45:49,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4976 states to 4976 states and 6801 transitions. [2021-10-28 23:45:49,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4976 [2021-10-28 23:45:49,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4976 [2021-10-28 23:45:49,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4976 states and 6801 transitions. [2021-10-28 23:45:49,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:49,626 INFO L681 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-10-28 23:45:49,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4976 states and 6801 transitions. [2021-10-28 23:45:49,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4976 to 4976. [2021-10-28 23:45:49,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4976 states, 4976 states have (on average 1.3667604501607717) internal successors, (6801), 4975 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:49,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4976 states to 4976 states and 6801 transitions. [2021-10-28 23:45:49,735 INFO L704 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-10-28 23:45:49,735 INFO L587 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-10-28 23:45:49,735 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 23:45:49,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4976 states and 6801 transitions. [2021-10-28 23:45:49,762 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2021-10-28 23:45:49,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:49,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:49,763 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:49,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:49,763 INFO L791 eck$LassoCheckResult]: Stem: 58589#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 58532#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 58410#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58411#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 58519#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58412#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58306#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58307#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58460#L353-1 assume !(0 == ~M_E~0); 58444#L494-1 assume !(0 == ~T1_E~0); 58300#L499-1 assume !(0 == ~T2_E~0); 58301#L504-1 assume !(0 == ~T3_E~0); 58400#L509-1 assume !(0 == ~T4_E~0); 58272#L514-1 assume !(0 == ~E_1~0); 58273#L519-1 assume !(0 == ~E_2~0); 58284#L524-1 assume !(0 == ~E_3~0); 58285#L529-1 assume !(0 == ~E_4~0); 58475#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58484#L230 assume !(1 == ~m_pc~0); 58553#L230-2 is_master_triggered_~__retres1~0 := 0; 58242#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58243#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58257#L607 assume !(0 != activate_threads_~tmp~1); 58258#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58174#L249 assume !(1 == ~t1_pc~0); 58175#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 58233#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58478#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58479#L615 assume !(0 != activate_threads_~tmp___0~0); 58193#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58194#L268 assume !(1 == ~t2_pc~0); 58349#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 58335#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58336#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58163#L623 assume !(0 != activate_threads_~tmp___1~0); 58164#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58246#L287 assume !(1 == ~t3_pc~0); 58546#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 58523#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58274#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58275#L631 assume !(0 != activate_threads_~tmp___2~0); 58551#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58468#L306 assume !(1 == ~t4_pc~0); 58302#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 58303#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58487#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58527#L639 assume !(0 != activate_threads_~tmp___3~0); 58517#L639-2 assume !(1 == ~M_E~0); 58518#L547-1 assume !(1 == ~T1_E~0); 58554#L552-1 assume !(1 == ~T2_E~0); 58385#L557-1 assume !(1 == ~T3_E~0); 58386#L562-1 assume !(1 == ~T4_E~0); 58390#L567-1 assume !(1 == ~E_1~0); 58383#L572-1 assume !(1 == ~E_2~0); 58316#L577-1 assume !(1 == ~E_3~0); 58253#L582-1 assume !(1 == ~E_4~0); 58254#L768-1 assume !false; 62617#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 62615#L469 [2021-10-28 23:45:49,764 INFO L793 eck$LassoCheckResult]: Loop: 62615#L469 assume !false; 62613#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 62611#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 62610#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 62609#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 62607#L408 assume 0 != eval_~tmp~0; 62605#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 58216#L416 assume !(0 != eval_~tmp_ndt_1~0); 58217#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 58462#L430 assume !(0 != eval_~tmp_ndt_2~0); 58502#L427 assume !(0 == ~t2_st~0); 62633#L441 assume !(0 == ~t3_st~0); 62620#L455 assume !(0 == ~t4_st~0); 62615#L469 [2021-10-28 23:45:49,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:49,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 2 times [2021-10-28 23:45:49,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:49,765 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455609861] [2021-10-28 23:45:49,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:49,765 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:49,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,775 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:49,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,808 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:49,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:49,809 INFO L85 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 2 times [2021-10-28 23:45:49,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:49,810 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948450528] [2021-10-28 23:45:49,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:49,810 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:49,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,813 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:49,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:49,824 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:49,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:49,825 INFO L85 PathProgramCache]: Analyzing trace with hash 592796105, now seen corresponding path program 1 times [2021-10-28 23:45:49,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:49,825 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763893988] [2021-10-28 23:45:49,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:49,826 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:49,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:49,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:49,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:49,855 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763893988] [2021-10-28 23:45:49,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763893988] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:49,860 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:49,860 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:49,861 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878255569] [2021-10-28 23:45:49,984 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:49,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:49,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:49,985 INFO L87 Difference]: Start difference. First operand 4976 states and 6801 transitions. cyclomatic complexity: 1832 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:50,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:50,056 INFO L93 Difference]: Finished difference Result 8779 states and 11960 transitions. [2021-10-28 23:45:50,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:50,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8779 states and 11960 transitions. [2021-10-28 23:45:50,105 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8669 [2021-10-28 23:45:50,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8779 states to 8779 states and 11960 transitions. [2021-10-28 23:45:50,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8779 [2021-10-28 23:45:50,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8779 [2021-10-28 23:45:50,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8779 states and 11960 transitions. [2021-10-28 23:45:50,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:50,157 INFO L681 BuchiCegarLoop]: Abstraction has 8779 states and 11960 transitions. [2021-10-28 23:45:50,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8779 states and 11960 transitions. [2021-10-28 23:45:50,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8779 to 8289. [2021-10-28 23:45:50,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8289 states, 8289 states have (on average 1.3668717577512366) internal successors, (11330), 8288 states have internal predecessors, (11330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:50,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8289 states to 8289 states and 11330 transitions. [2021-10-28 23:45:50,394 INFO L704 BuchiCegarLoop]: Abstraction has 8289 states and 11330 transitions. [2021-10-28 23:45:50,394 INFO L587 BuchiCegarLoop]: Abstraction has 8289 states and 11330 transitions. [2021-10-28 23:45:50,394 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 23:45:50,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8289 states and 11330 transitions. [2021-10-28 23:45:50,428 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8179 [2021-10-28 23:45:50,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:50,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:50,429 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:50,429 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:50,430 INFO L791 eck$LassoCheckResult]: Stem: 72383#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 72313#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 72178#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 72179#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 72298#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72180#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72074#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72075#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72235#L353-1 assume !(0 == ~M_E~0); 72216#L494-1 assume !(0 == ~T1_E~0); 72064#L499-1 assume !(0 == ~T2_E~0); 72065#L504-1 assume !(0 == ~T3_E~0); 72172#L509-1 assume !(0 == ~T4_E~0); 72038#L514-1 assume !(0 == ~E_1~0); 72039#L519-1 assume !(0 == ~E_2~0); 72050#L524-1 assume !(0 == ~E_3~0); 72051#L529-1 assume !(0 == ~E_4~0); 72248#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 72255#L230 assume !(1 == ~m_pc~0); 72333#L230-2 is_master_triggered_~__retres1~0 := 0; 72008#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 72009#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72021#L607 assume !(0 != activate_threads_~tmp~1); 72022#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71938#L249 assume !(1 == ~t1_pc~0); 71939#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 71999#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 72251#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 72252#L615 assume !(0 != activate_threads_~tmp___0~0); 71960#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 71961#L268 assume !(1 == ~t2_pc~0); 72116#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 72098#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 72099#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 71930#L623 assume !(0 != activate_threads_~tmp___1~0); 71931#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72010#L287 assume !(1 == ~t3_pc~0); 72330#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 72301#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 72040#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 72041#L631 assume !(0 != activate_threads_~tmp___2~0); 72332#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 72243#L306 assume !(1 == ~t4_pc~0); 72068#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 72069#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 72260#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 72308#L639 assume !(0 != activate_threads_~tmp___3~0); 72296#L639-2 assume !(1 == ~M_E~0); 72297#L547-1 assume !(1 == ~T1_E~0); 72334#L552-1 assume !(1 == ~T2_E~0); 72152#L557-1 assume !(1 == ~T3_E~0); 72153#L562-1 assume !(1 == ~T4_E~0); 72157#L567-1 assume !(1 == ~E_1~0); 72151#L572-1 assume !(1 == ~E_2~0); 72079#L577-1 assume !(1 == ~E_3~0); 72019#L582-1 assume !(1 == ~E_4~0); 72020#L768-1 assume !false; 73275#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 73272#L469 [2021-10-28 23:45:50,432 INFO L793 eck$LassoCheckResult]: Loop: 73272#L469 assume !false; 73270#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 73268#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 73266#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 73262#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 73260#L408 assume 0 != eval_~tmp~0; 73257#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 73254#L416 assume !(0 != eval_~tmp_ndt_1~0); 73251#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 73252#L430 assume !(0 != eval_~tmp_ndt_2~0); 77745#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 77742#L444 assume !(0 != eval_~tmp_ndt_3~0); 73292#L441 assume !(0 == ~t3_st~0); 73278#L455 assume !(0 == ~t4_st~0); 73272#L469 [2021-10-28 23:45:50,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:50,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 3 times [2021-10-28 23:45:50,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:50,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948234932] [2021-10-28 23:45:50,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:50,433 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:50,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:50,442 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:50,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:50,461 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:50,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:50,461 INFO L85 PathProgramCache]: Analyzing trace with hash 210997043, now seen corresponding path program 1 times [2021-10-28 23:45:50,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:50,462 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424697144] [2021-10-28 23:45:50,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:50,462 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:50,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:50,465 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:50,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:50,470 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:50,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:50,471 INFO L85 PathProgramCache]: Analyzing trace with hash 1192128765, now seen corresponding path program 1 times [2021-10-28 23:45:50,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:50,471 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636681987] [2021-10-28 23:45:50,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:50,471 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:50,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:50,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:50,498 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:50,498 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636681987] [2021-10-28 23:45:50,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636681987] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:50,499 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:50,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:45:50,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304115495] [2021-10-28 23:45:50,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:50,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:50,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:50,612 INFO L87 Difference]: Start difference. First operand 8289 states and 11330 transitions. cyclomatic complexity: 3048 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:50,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:50,703 INFO L93 Difference]: Finished difference Result 12888 states and 17587 transitions. [2021-10-28 23:45:50,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:50,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12888 states and 17587 transitions. [2021-10-28 23:45:50,772 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12758 [2021-10-28 23:45:50,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12888 states to 12888 states and 17587 transitions. [2021-10-28 23:45:50,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12888 [2021-10-28 23:45:50,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12888 [2021-10-28 23:45:50,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12888 states and 17587 transitions. [2021-10-28 23:45:50,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:50,965 INFO L681 BuchiCegarLoop]: Abstraction has 12888 states and 17587 transitions. [2021-10-28 23:45:50,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12888 states and 17587 transitions. [2021-10-28 23:45:51,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12888 to 12688. [2021-10-28 23:45:51,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12688 states, 12688 states have (on average 1.3656210592686002) internal successors, (17327), 12687 states have internal predecessors, (17327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:51,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12688 states to 12688 states and 17327 transitions. [2021-10-28 23:45:51,255 INFO L704 BuchiCegarLoop]: Abstraction has 12688 states and 17327 transitions. [2021-10-28 23:45:51,255 INFO L587 BuchiCegarLoop]: Abstraction has 12688 states and 17327 transitions. [2021-10-28 23:45:51,255 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-28 23:45:51,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12688 states and 17327 transitions. [2021-10-28 23:45:51,304 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12558 [2021-10-28 23:45:51,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:51,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:51,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:51,306 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:51,306 INFO L791 eck$LassoCheckResult]: Stem: 93587#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 93506#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93364#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 93365#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 93490#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93366#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93255#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93256#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93422#L353-1 assume !(0 == ~M_E~0); 93405#L494-1 assume !(0 == ~T1_E~0); 93247#L499-1 assume !(0 == ~T2_E~0); 93248#L504-1 assume !(0 == ~T3_E~0); 93354#L509-1 assume !(0 == ~T4_E~0); 93220#L514-1 assume !(0 == ~E_1~0); 93221#L519-1 assume !(0 == ~E_2~0); 93232#L524-1 assume !(0 == ~E_3~0); 93233#L529-1 assume !(0 == ~E_4~0); 93441#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93446#L230 assume !(1 == ~m_pc~0); 93533#L230-2 is_master_triggered_~__retres1~0 := 0; 93190#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93191#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 93205#L607 assume !(0 != activate_threads_~tmp~1); 93206#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93116#L249 assume !(1 == ~t1_pc~0); 93117#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 93181#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93442#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 93443#L615 assume !(0 != activate_threads_~tmp___0~0); 93140#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93141#L268 assume !(1 == ~t2_pc~0); 93296#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 93281#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93282#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 93109#L623 assume !(0 != activate_threads_~tmp___1~0); 93110#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93194#L287 assume !(1 == ~t3_pc~0); 93527#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 93495#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93222#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 93223#L631 assume !(0 != activate_threads_~tmp___2~0); 93532#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93434#L306 assume !(1 == ~t4_pc~0); 93251#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 93252#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93451#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 93502#L639 assume !(0 != activate_threads_~tmp___3~0); 93488#L639-2 assume !(1 == ~M_E~0); 93489#L547-1 assume !(1 == ~T1_E~0); 93534#L552-1 assume !(1 == ~T2_E~0); 93338#L557-1 assume !(1 == ~T3_E~0); 93339#L562-1 assume !(1 == ~T4_E~0); 93344#L567-1 assume !(1 == ~E_1~0); 93335#L572-1 assume !(1 == ~E_2~0); 93260#L577-1 assume !(1 == ~E_3~0); 93201#L582-1 assume !(1 == ~E_4~0); 93202#L768-1 assume !false; 104711#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 104709#L469 [2021-10-28 23:45:51,306 INFO L793 eck$LassoCheckResult]: Loop: 104709#L469 assume !false; 104708#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 104705#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 104703#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 104701#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 104699#L408 assume 0 != eval_~tmp~0; 104690#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 104688#L416 assume !(0 != eval_~tmp_ndt_1~0); 104677#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 103881#L430 assume !(0 != eval_~tmp_ndt_2~0); 103880#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 103693#L444 assume !(0 != eval_~tmp_ndt_3~0); 103877#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 104181#L458 assume !(0 != eval_~tmp_ndt_4~0); 104182#L455 assume !(0 == ~t4_st~0); 104709#L469 [2021-10-28 23:45:51,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:51,307 INFO L85 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 4 times [2021-10-28 23:45:51,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:51,307 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636731428] [2021-10-28 23:45:51,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:51,307 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:51,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:51,315 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:51,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:51,334 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:51,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:51,334 INFO L85 PathProgramCache]: Analyzing trace with hash -2049172699, now seen corresponding path program 1 times [2021-10-28 23:45:51,334 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:51,335 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387931161] [2021-10-28 23:45:51,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:51,335 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:51,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:51,338 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:51,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:51,342 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:51,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:51,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1698860389, now seen corresponding path program 1 times [2021-10-28 23:45:51,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:51,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390944473] [2021-10-28 23:45:51,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:51,344 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:51,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:45:51,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:45:51,369 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:45:51,369 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390944473] [2021-10-28 23:45:51,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390944473] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:45:51,369 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:45:51,370 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-10-28 23:45:51,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856823398] [2021-10-28 23:45:51,528 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:45:51,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:45:51,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:45:51,529 INFO L87 Difference]: Start difference. First operand 12688 states and 17327 transitions. cyclomatic complexity: 4646 Second operand has 3 states, 2 states have (on average 36.5) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:51,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:45:51,850 INFO L93 Difference]: Finished difference Result 23888 states and 32491 transitions. [2021-10-28 23:45:51,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:45:51,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23888 states and 32491 transitions. [2021-10-28 23:45:51,986 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2021-10-28 23:45:52,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23888 states to 23888 states and 32491 transitions. [2021-10-28 23:45:52,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23888 [2021-10-28 23:45:52,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23888 [2021-10-28 23:45:52,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23888 states and 32491 transitions. [2021-10-28 23:45:52,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:45:52,127 INFO L681 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-10-28 23:45:52,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23888 states and 32491 transitions. [2021-10-28 23:45:52,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23888 to 23888. [2021-10-28 23:45:52,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23888 states, 23888 states have (on average 1.3601389819156062) internal successors, (32491), 23887 states have internal predecessors, (32491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:45:52,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23888 states to 23888 states and 32491 transitions. [2021-10-28 23:45:52,635 INFO L704 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-10-28 23:45:52,635 INFO L587 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-10-28 23:45:52,636 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-28 23:45:52,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23888 states and 32491 transitions. [2021-10-28 23:45:52,728 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2021-10-28 23:45:52,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:45:52,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:45:52,729 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:52,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-10-28 23:45:52,729 INFO L791 eck$LassoCheckResult]: Stem: 130148#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 130081#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 129944#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 129945#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 130067#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129946#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129837#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129838#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130001#L353-1 assume !(0 == ~M_E~0); 129983#L494-1 assume !(0 == ~T1_E~0); 129829#L499-1 assume !(0 == ~T2_E~0); 129830#L504-1 assume !(0 == ~T3_E~0); 129935#L509-1 assume !(0 == ~T4_E~0); 129803#L514-1 assume !(0 == ~E_1~0); 129804#L519-1 assume !(0 == ~E_2~0); 129815#L524-1 assume !(0 == ~E_3~0); 129816#L529-1 assume !(0 == ~E_4~0); 130016#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 130022#L230 assume !(1 == ~m_pc~0); 130103#L230-2 is_master_triggered_~__retres1~0 := 0; 129774#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129775#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 129788#L607 assume !(0 != activate_threads_~tmp~1); 129789#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129701#L249 assume !(1 == ~t1_pc~0); 129702#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 129765#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130018#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 130019#L615 assume !(0 != activate_threads_~tmp___0~0); 129724#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129725#L268 assume !(1 == ~t2_pc~0); 129880#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 129863#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129864#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129694#L623 assume !(0 != activate_threads_~tmp___1~0); 129695#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 129778#L287 assume !(1 == ~t3_pc~0); 130098#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 130070#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129805#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129806#L631 assume !(0 != activate_threads_~tmp___2~0); 130102#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130010#L306 assume !(1 == ~t4_pc~0); 129833#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 129834#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 130028#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 130077#L639 assume !(0 != activate_threads_~tmp___3~0); 130065#L639-2 assume !(1 == ~M_E~0); 130066#L547-1 assume !(1 == ~T1_E~0); 130104#L552-1 assume !(1 == ~T2_E~0); 129917#L557-1 assume !(1 == ~T3_E~0); 129918#L562-1 assume !(1 == ~T4_E~0); 129924#L567-1 assume !(1 == ~E_1~0); 129915#L572-1 assume !(1 == ~E_2~0); 129843#L577-1 assume !(1 == ~E_3~0); 129784#L582-1 assume !(1 == ~E_4~0); 129785#L768-1 assume !false; 151464#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 151329#L469 [2021-10-28 23:45:52,730 INFO L793 eck$LassoCheckResult]: Loop: 151329#L469 assume !false; 151460#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 151457#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 151458#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 152846#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 151449#L408 assume 0 != eval_~tmp~0; 151450#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 152842#L416 assume !(0 != eval_~tmp_ndt_1~0); 152840#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 151721#L430 assume !(0 != eval_~tmp_ndt_2~0); 151339#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 151336#L444 assume !(0 != eval_~tmp_ndt_3~0); 151334#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 151332#L458 assume !(0 != eval_~tmp_ndt_4~0); 151330#L455 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 151320#L472 assume !(0 != eval_~tmp_ndt_5~0); 151329#L469 [2021-10-28 23:45:52,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:52,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 5 times [2021-10-28 23:45:52,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:52,731 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995399207] [2021-10-28 23:45:52,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:52,731 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:52,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,739 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:52,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,757 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:52,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:52,757 INFO L85 PathProgramCache]: Analyzing trace with hash 900155617, now seen corresponding path program 1 times [2021-10-28 23:45:52,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:52,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006152890] [2021-10-28 23:45:52,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:52,758 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:52,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,761 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:52,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,766 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:52,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:45:52,766 INFO L85 PathProgramCache]: Analyzing trace with hash -1125064661, now seen corresponding path program 1 times [2021-10-28 23:45:52,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:45:52,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184937997] [2021-10-28 23:45:52,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:45:52,767 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:45:52,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,776 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:45:52,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:45:52,798 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:45:54,959 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 11:45:54 BoogieIcfgContainer [2021-10-28 23:45:54,961 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 23:45:54,962 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 23:45:54,962 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 23:45:54,962 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 23:45:54,963 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:45:44" (3/4) ... [2021-10-28 23:45:54,966 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 23:45:55,051 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/witness.graphml [2021-10-28 23:45:55,052 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 23:45:55,058 INFO L168 Benchmark]: Toolchain (without parser) took 12051.18 ms. Allocated memory was 96.5 MB in the beginning and 1.0 GB in the end (delta: 952.1 MB). Free memory was 55.6 MB in the beginning and 808.8 MB in the end (delta: -753.2 MB). Peak memory consumption was 198.3 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,058 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 96.5 MB. Free memory is still 72.0 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 23:45:55,059 INFO L168 Benchmark]: CACSL2BoogieTranslator took 502.84 ms. Allocated memory is still 96.5 MB. Free memory was 55.4 MB in the beginning and 67.8 MB in the end (delta: -12.4 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,060 INFO L168 Benchmark]: Boogie Procedure Inliner took 110.55 ms. Allocated memory is still 96.5 MB. Free memory was 67.8 MB in the beginning and 63.7 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,060 INFO L168 Benchmark]: Boogie Preprocessor took 84.84 ms. Allocated memory is still 96.5 MB. Free memory was 63.7 MB in the beginning and 60.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,060 INFO L168 Benchmark]: RCFGBuilder took 1114.69 ms. Allocated memory was 96.5 MB in the beginning and 130.0 MB in the end (delta: 33.6 MB). Free memory was 60.2 MB in the beginning and 94.3 MB in the end (delta: -34.1 MB). Peak memory consumption was 37.4 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,063 INFO L168 Benchmark]: BuchiAutomizer took 10141.56 ms. Allocated memory was 130.0 MB in the beginning and 1.0 GB in the end (delta: 918.6 MB). Free memory was 94.3 MB in the beginning and 813.0 MB in the end (delta: -718.6 MB). Peak memory consumption was 295.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,064 INFO L168 Benchmark]: Witness Printer took 89.70 ms. Allocated memory is still 1.0 GB. Free memory was 813.0 MB in the beginning and 808.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-10-28 23:45:55,069 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 96.5 MB. Free memory is still 72.0 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 502.84 ms. Allocated memory is still 96.5 MB. Free memory was 55.4 MB in the beginning and 67.8 MB in the end (delta: -12.4 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 110.55 ms. Allocated memory is still 96.5 MB. Free memory was 67.8 MB in the beginning and 63.7 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 84.84 ms. Allocated memory is still 96.5 MB. Free memory was 63.7 MB in the beginning and 60.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1114.69 ms. Allocated memory was 96.5 MB in the beginning and 130.0 MB in the end (delta: 33.6 MB). Free memory was 60.2 MB in the beginning and 94.3 MB in the end (delta: -34.1 MB). Peak memory consumption was 37.4 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 10141.56 ms. Allocated memory was 130.0 MB in the beginning and 1.0 GB in the end (delta: 918.6 MB). Free memory was 94.3 MB in the beginning and 813.0 MB in the end (delta: -718.6 MB). Peak memory consumption was 295.1 MB. Max. memory is 16.1 GB. * Witness Printer took 89.70 ms. Allocated memory is still 1.0 GB. Free memory was 813.0 MB in the beginning and 808.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 23888 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.0s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 4.7s. Construction of modules took 0.4s. Büchi inclusion checks took 1.1s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1.7s AutomataMinimizationTime, 18 MinimizatonAttempts, 3308 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 1.0s Buchi closure took 0.2s. Biggest automaton had 23888 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 10632 SDtfs, 11500 SDslu, 8611 SDs, 0 SdLazy, 423 SolverSat, 222 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 403]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=28472} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=28472, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16340f1f=0, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5be6ba99=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3173679c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@66306085=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40cdb732=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@666a4dbc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1bc283a5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60172487=0, NULL=28473, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@341d39b1=0, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=28474, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=28475, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e94305a=0, t1_st=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1bb985a2=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@130bf2df=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f43cbc8=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 403]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L813] int __retres1 ; [L725] m_i = 1 [L726] t1_i = 1 [L727] t2_i = 1 [L728] t3_i = 1 [L729] t4_i = 1 [L754] int kernel_st ; [L755] int tmp ; [L756] int tmp___0 ; [L760] kernel_st = 0 [L333] COND TRUE m_i == 1 [L334] m_st = 0 [L338] COND TRUE t1_i == 1 [L339] t1_st = 0 [L343] COND TRUE t2_i == 1 [L344] t2_st = 0 [L348] COND TRUE t3_i == 1 [L349] t3_st = 0 [L353] COND TRUE t4_i == 1 [L354] t4_st = 0 [L494] COND FALSE !(M_E == 0) [L499] COND FALSE !(T1_E == 0) [L504] COND FALSE !(T2_E == 0) [L509] COND FALSE !(T3_E == 0) [L514] COND FALSE !(T4_E == 0) [L519] COND FALSE !(E_1 == 0) [L524] COND FALSE !(E_2 == 0) [L529] COND FALSE !(E_3 == 0) [L534] COND FALSE !(E_4 == 0) [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; [L230] COND FALSE !(m_pc == 1) [L240] __retres1 = 0 [L242] return (__retres1); [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) [L246] int __retres1 ; [L249] COND FALSE !(t1_pc == 1) [L259] __retres1 = 0 [L261] return (__retres1); [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) [L265] int __retres1 ; [L268] COND FALSE !(t2_pc == 1) [L278] __retres1 = 0 [L280] return (__retres1); [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) [L284] int __retres1 ; [L287] COND FALSE !(t3_pc == 1) [L297] __retres1 = 0 [L299] return (__retres1); [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) [L303] int __retres1 ; [L306] COND FALSE !(t4_pc == 1) [L316] __retres1 = 0 [L318] return (__retres1); [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) [L547] COND FALSE !(M_E == 1) [L552] COND FALSE !(T1_E == 1) [L557] COND FALSE !(T2_E == 1) [L562] COND FALSE !(T3_E == 1) [L567] COND FALSE !(T4_E == 1) [L572] COND FALSE !(E_1 == 1) [L577] COND FALSE !(E_2 == 1) [L582] COND FALSE !(E_3 == 1) [L587] COND FALSE !(E_4 == 1) [L768] COND TRUE 1 [L771] kernel_st = 1 [L399] int tmp ; Loop: [L403] COND TRUE 1 [L363] int __retres1 ; [L366] COND TRUE m_st == 0 [L367] __retres1 = 1 [L394] return (__retres1); [L406] tmp = exists_runnable_thread() [L408] COND TRUE \read(tmp) [L413] COND TRUE m_st == 0 [L414] int tmp_ndt_1; [L415] tmp_ndt_1 = __VERIFIER_nondet_int() [L416] COND FALSE !(\read(tmp_ndt_1)) [L427] COND TRUE t1_st == 0 [L428] int tmp_ndt_2; [L429] tmp_ndt_2 = __VERIFIER_nondet_int() [L430] COND FALSE !(\read(tmp_ndt_2)) [L441] COND TRUE t2_st == 0 [L442] int tmp_ndt_3; [L443] tmp_ndt_3 = __VERIFIER_nondet_int() [L444] COND FALSE !(\read(tmp_ndt_3)) [L455] COND TRUE t3_st == 0 [L456] int tmp_ndt_4; [L457] tmp_ndt_4 = __VERIFIER_nondet_int() [L458] COND FALSE !(\read(tmp_ndt_4)) [L469] COND TRUE t4_st == 0 [L470] int tmp_ndt_5; [L471] tmp_ndt_5 = __VERIFIER_nondet_int() [L472] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 23:45:55,142 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d7cc8e10-fd25-4397-8169-40bcd6b8a008/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...