./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 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............................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-28 23:40:57,346 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-28 23:40:57,348 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-28 23:40:57,391 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-28 23:40:57,392 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-28 23:40:57,394 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-28 23:40:57,396 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-28 23:40:57,400 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-28 23:40:57,403 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-28 23:40:57,406 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-28 23:40:57,408 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-28 23:40:57,410 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-28 23:40:57,411 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-28 23:40:57,412 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-28 23:40:57,415 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-28 23:40:57,417 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-28 23:40:57,418 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-28 23:40:57,420 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-28 23:40:57,423 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-28 23:40:57,427 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-28 23:40:57,429 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-28 23:40:57,439 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-28 23:40:57,442 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-28 23:40:57,445 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-28 23:40:57,450 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-28 23:40:57,457 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-28 23:40:57,458 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-28 23:40:57,460 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-28 23:40:57,462 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-28 23:40:57,463 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-28 23:40:57,464 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-28 23:40:57,466 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-28 23:40:57,467 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-28 23:40:57,468 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-28 23:40:57,469 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-28 23:40:57,470 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-28 23:40:57,471 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-28 23:40:57,471 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-28 23:40:57,472 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-28 23:40:57,473 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-28 23:40:57,474 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-28 23:40:57,475 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-10-28 23:40:57,505 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-28 23:40:57,507 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-28 23:40:57,510 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-10-28 23:40:57,511 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-10-28 23:40:57,512 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-28 23:40:57,513 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-28 23:40:57,513 INFO L138 SettingsManager]: * Use SBE=true [2021-10-28 23:40:57,513 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-10-28 23:40:57,514 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-10-28 23:40:57,514 INFO L138 SettingsManager]: * Use old map elimination=false [2021-10-28 23:40:57,515 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-10-28 23:40:57,516 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-10-28 23:40:57,516 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-10-28 23:40:57,516 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-28 23:40:57,516 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-10-28 23:40:57,517 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-28 23:40:57,517 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-28 23:40:57,517 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-10-28 23:40:57,518 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-10-28 23:40:57,518 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-10-28 23:40:57,518 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-28 23:40:57,518 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-10-28 23:40:57,519 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-28 23:40:57,519 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-10-28 23:40:57,519 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-28 23:40:57,520 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-10-28 23:40:57,520 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-28 23:40:57,520 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-10-28 23:40:57,521 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-10-28 23:40:57,522 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-10-28 23:40:57,522 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2021-10-28 23:40:57,826 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-28 23:40:57,864 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-28 23:40:57,868 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-28 23:40:57,870 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-28 23:40:57,870 INFO L275 PluginConnector]: CDTParser initialized [2021-10-28 23:40:57,872 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2021-10-28 23:40:57,992 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/data/8b6d241d9/98b1f1e13ef3450b8b51f32c3dbbbfee/FLAGa1bc3ddef [2021-10-28 23:40:58,506 INFO L306 CDTParser]: Found 1 translation units. [2021-10-28 23:40:58,507 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2021-10-28 23:40:58,515 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/data/8b6d241d9/98b1f1e13ef3450b8b51f32c3dbbbfee/FLAGa1bc3ddef [2021-10-28 23:40:58,906 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/data/8b6d241d9/98b1f1e13ef3450b8b51f32c3dbbbfee [2021-10-28 23:40:58,909 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-28 23:40:58,918 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-28 23:40:58,923 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-28 23:40:58,924 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-28 23:40:58,928 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-28 23:40:58,929 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:40:58" (1/1) ... [2021-10-28 23:40:58,930 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@797f64a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:58, skipping insertion in model container [2021-10-28 23:40:58,931 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.10 11:40:58" (1/1) ... [2021-10-28 23:40:58,940 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-28 23:40:58,952 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-28 23:40:59,092 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:40:59,097 INFO L203 MainTranslator]: Completed pre-run [2021-10-28 23:40:59,135 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-28 23:40:59,155 INFO L208 MainTranslator]: Completed translation [2021-10-28 23:40:59,156 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59 WrapperNode [2021-10-28 23:40:59,156 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-28 23:40:59,158 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-28 23:40:59,158 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-28 23:40:59,159 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-28 23:40:59,168 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,174 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,194 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-28 23:40:59,195 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-28 23:40:59,196 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-28 23:40:59,196 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-28 23:40:59,206 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,207 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,207 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,208 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,210 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,214 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,215 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,217 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-28 23:40:59,218 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-28 23:40:59,218 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-28 23:40:59,218 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-28 23:40:59,220 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (1/1) ... [2021-10-28 23:40:59,229 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:40:59,243 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:40:59,261 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:40:59,282 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-10-28 23:40:59,320 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-28 23:40:59,321 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-28 23:40:59,503 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-28 23:40:59,503 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2021-10-28 23:40:59,507 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:40:59 BoogieIcfgContainer [2021-10-28 23:40:59,507 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-28 23:40:59,510 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-10-28 23:40:59,511 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-10-28 23:40:59,515 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-10-28 23:40:59,516 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:40:59,516 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.10 11:40:58" (1/3) ... [2021-10-28 23:40:59,519 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@473a111c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:40:59, skipping insertion in model container [2021-10-28 23:40:59,519 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:40:59,519 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.10 11:40:59" (2/3) ... [2021-10-28 23:40:59,522 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@473a111c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.10 11:40:59, skipping insertion in model container [2021-10-28 23:40:59,522 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-10-28 23:40:59,522 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:40:59" (3/3) ... [2021-10-28 23:40:59,524 INFO L389 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2021-10-28 23:40:59,600 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-10-28 23:40:59,600 INFO L360 BuchiCegarLoop]: Hoare is false [2021-10-28 23:40:59,601 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-10-28 23:40:59,601 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-10-28 23:40:59,601 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-10-28 23:40:59,601 INFO L364 BuchiCegarLoop]: Difference is false [2021-10-28 23:40:59,601 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-10-28 23:40:59,602 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-10-28 23:40:59,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:40:59,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:40:59,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:40:59,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:40:59,650 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-28 23:40:59,650 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:40:59,651 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-10-28 23:40:59,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:40:59,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:40:59,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:40:59,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:40:59,653 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-28 23:40:59,654 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:40:59,662 INFO L791 eck$LassoCheckResult]: Stem: 6#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 4#L12-1true [2021-10-28 23:40:59,662 INFO L793 eck$LassoCheckResult]: Loop: 4#L12-1true assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9#L12true assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4#L12-1true [2021-10-28 23:40:59,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:40:59,670 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2021-10-28 23:40:59,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:40:59,682 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070505313] [2021-10-28 23:40:59,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:40:59,684 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:40:59,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:40:59,770 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:40:59,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:40:59,792 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:40:59,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:40:59,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 1 times [2021-10-28 23:40:59,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:40:59,797 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113064145] [2021-10-28 23:40:59,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:40:59,798 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:40:59,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:40:59,808 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:40:59,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:40:59,814 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:40:59,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:40:59,817 INFO L85 PathProgramCache]: Analyzing trace with hash 31083, now seen corresponding path program 1 times [2021-10-28 23:40:59,817 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:40:59,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193325934] [2021-10-28 23:40:59,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:40:59,818 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:40:59,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:40:59,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:40:59,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:40:59,895 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193325934] [2021-10-28 23:40:59,896 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193325934] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:40:59,896 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:40:59,897 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2021-10-28 23:40:59,897 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296668316] [2021-10-28 23:40:59,985 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:00,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-10-28 23:41:00,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-10-28 23:41:00,017 INFO L87 Difference]: Start difference. First operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:00,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:00,074 INFO L93 Difference]: Finished difference Result 15 states and 18 transitions. [2021-10-28 23:41:00,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-10-28 23:41:00,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 18 transitions. [2021-10-28 23:41:00,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-10-28 23:41:00,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 7 states and 10 transitions. [2021-10-28 23:41:00,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-10-28 23:41:00,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 23:41:00,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 10 transitions. [2021-10-28 23:41:00,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-10-28 23:41:00,093 INFO L681 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 23:41:00,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 10 transitions. [2021-10-28 23:41:00,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2021-10-28 23:41:00,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 6 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:00,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 10 transitions. [2021-10-28 23:41:00,144 INFO L704 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 23:41:00,145 INFO L587 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2021-10-28 23:41:00,145 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-10-28 23:41:00,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 10 transitions. [2021-10-28 23:41:00,146 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-10-28 23:41:00,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:00,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:00,147 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-10-28 23:41:00,147 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-10-28 23:41:00,147 INFO L791 eck$LassoCheckResult]: Stem: 36#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 37#L12-1 [2021-10-28 23:41:00,147 INFO L793 eck$LassoCheckResult]: Loop: 37#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 40#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 37#L12-1 [2021-10-28 23:41:00,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:00,148 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 2 times [2021-10-28 23:41:00,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:00,149 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129983911] [2021-10-28 23:41:00,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:00,150 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:00,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,161 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:00,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,165 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:00,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:00,167 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 1 times [2021-10-28 23:41:00,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:00,167 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591040575] [2021-10-28 23:41:00,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:00,168 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:00,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,177 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:00,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,184 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:00,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:00,185 INFO L85 PathProgramCache]: Analyzing trace with hash 963343, now seen corresponding path program 1 times [2021-10-28 23:41:00,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:00,194 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883399008] [2021-10-28 23:41:00,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:00,195 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:00,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,203 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:00,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:00,220 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:00,307 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:00,308 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:00,308 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:00,308 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:00,308 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 23:41:00,308 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,309 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:00,309 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:00,309 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2021-10-28 23:41:00,309 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:00,309 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:00,332 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,341 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,348 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,479 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:00,480 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 23:41:00,482 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:00,490 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:00,498 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:00,498 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:00,510 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-10-28 23:41:00,533 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 23:41:00,533 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 23:41:00,557 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:00,557 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:00,558 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:00,568 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:00,568 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:00,568 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-10-28 23:41:00,589 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 23:41:00,590 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 23:41:00,630 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:00,630 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:00,634 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:00,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-10-28 23:41:00,638 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:00,639 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:00,688 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2021-10-28 23:41:00,689 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,689 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:00,690 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:00,703 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 23:41:00,704 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:00,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-10-28 23:41:00,798 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 23:41:00,805 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:00,805 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:00,805 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:00,805 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:00,805 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:00,805 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 23:41:00,806 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,806 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:00,806 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:00,806 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2021-10-28 23:41:00,806 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:00,806 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:00,808 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:00,910 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:00,915 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 23:41:00,917 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:00,917 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:00,922 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:00,930 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-10-28 23:41:00,931 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:00,940 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:00,941 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:00,941 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:00,941 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:00,948 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 23:41:00,948 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 23:41:00,964 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 23:41:01,009 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:01,009 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:01,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:01,011 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:01,019 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:01,030 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:01,030 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:01,030 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:01,030 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:01,035 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 23:41:01,035 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 23:41:01,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-10-28 23:41:01,058 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 23:41:01,097 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:01,097 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:01,097 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:01,102 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:01,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-10-28 23:41:01,106 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:01,117 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:01,118 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 23:41:01,118 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:01,118 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:01,119 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:01,124 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 23:41:01,124 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 23:41:01,142 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 23:41:01,147 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 23:41:01,147 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 23:41:01,149 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:01,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:01,151 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:01,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-10-28 23:41:01,182 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 23:41:01,183 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 23:41:01,183 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 23:41:01,184 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, ULTIMATE.start_main_~range~0) = -1*ULTIMATE.start_main_~i~0 + 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2021-10-28 23:41:01,220 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:01,223 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 23:41:01,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:01,266 INFO L263 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:01,268 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:01,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:01,288 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:01,289 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:01,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:01,363 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 23:41:01,364 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:01,411 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 10 states and 14 transitions. Complement of second has 5 states. [2021-10-28 23:41:01,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:01,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:01,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 4 transitions. [2021-10-28 23:41:01,414 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 1 letters. Loop has 3 letters. [2021-10-28 23:41:01,415 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:01,415 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 4 letters. Loop has 3 letters. [2021-10-28 23:41:01,415 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:01,416 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 1 letters. Loop has 6 letters. [2021-10-28 23:41:01,417 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:01,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 14 transitions. [2021-10-28 23:41:01,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:41:01,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 10 states and 14 transitions. [2021-10-28 23:41:01,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-10-28 23:41:01,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 23:41:01,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 14 transitions. [2021-10-28 23:41:01,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:01,422 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-10-28 23:41:01,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 14 transitions. [2021-10-28 23:41:01,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-10-28 23:41:01,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.4) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:01,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 14 transitions. [2021-10-28 23:41:01,425 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-10-28 23:41:01,426 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-10-28 23:41:01,426 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-10-28 23:41:01,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 14 transitions. [2021-10-28 23:41:01,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:41:01,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:01,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:01,429 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-10-28 23:41:01,430 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:01,430 INFO L791 eck$LassoCheckResult]: Stem: 89#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 90#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 91#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84#L12-1 [2021-10-28 23:41:01,430 INFO L793 eck$LassoCheckResult]: Loop: 84#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 85#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 84#L12-1 [2021-10-28 23:41:01,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,431 INFO L85 PathProgramCache]: Analyzing trace with hash 963341, now seen corresponding path program 1 times [2021-10-28 23:41:01,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,432 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036252115] [2021-10-28 23:41:01,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,433 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,455 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:01,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,466 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:01,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 2 times [2021-10-28 23:41:01,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448375382] [2021-10-28 23:41:01,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,469 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,480 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:01,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,492 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:01,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,493 INFO L85 PathProgramCache]: Analyzing trace with hash 925771032, now seen corresponding path program 1 times [2021-10-28 23:41:01,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,494 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272081940] [2021-10-28 23:41:01,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,494 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:01,555 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:01,555 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:01,556 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272081940] [2021-10-28 23:41:01,556 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272081940] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:01,557 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1251738395] [2021-10-28 23:41:01,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,558 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:01,558 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:01,562 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:01,582 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-10-28 23:41:01,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:01,601 INFO L263 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 4 conjunts are in the unsatisfiable core [2021-10-28 23:41:01,602 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:01,703 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:01,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1251738395] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:01,710 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:01,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2] total 3 [2021-10-28 23:41:01,711 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998317105] [2021-10-28 23:41:01,743 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:01,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-10-28 23:41:01,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2021-10-28 23:41:01,745 INFO L87 Difference]: Start difference. First operand 10 states and 14 transitions. cyclomatic complexity: 6 Second operand has 5 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:01,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:01,787 INFO L93 Difference]: Finished difference Result 13 states and 17 transitions. [2021-10-28 23:41:01,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:41:01,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 17 transitions. [2021-10-28 23:41:01,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:41:01,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 17 transitions. [2021-10-28 23:41:01,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-10-28 23:41:01,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2021-10-28 23:41:01,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 17 transitions. [2021-10-28 23:41:01,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:01,794 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2021-10-28 23:41:01,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 17 transitions. [2021-10-28 23:41:01,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2021-10-28 23:41:01,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 12 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:01,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 17 transitions. [2021-10-28 23:41:01,800 INFO L704 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2021-10-28 23:41:01,800 INFO L587 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2021-10-28 23:41:01,800 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-10-28 23:41:01,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 17 transitions. [2021-10-28 23:41:01,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-10-28 23:41:01,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:01,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:01,803 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1] [2021-10-28 23:41:01,803 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:01,804 INFO L791 eck$LassoCheckResult]: Stem: 140#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 136#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 142#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 132#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 133#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 138#L12-1 [2021-10-28 23:41:01,804 INFO L793 eck$LassoCheckResult]: Loop: 138#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 144#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 138#L12-1 [2021-10-28 23:41:01,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1365869310, now seen corresponding path program 1 times [2021-10-28 23:41:01,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,805 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751509191] [2021-10-28 23:41:01,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,806 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,831 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:01,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,850 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:01,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 3 times [2021-10-28 23:41:01,851 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,851 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167550641] [2021-10-28 23:41:01,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,851 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,855 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:01,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:01,875 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:01,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:01,876 INFO L85 PathProgramCache]: Analyzing trace with hash 1659585997, now seen corresponding path program 1 times [2021-10-28 23:41:01,906 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:01,906 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008160693] [2021-10-28 23:41:01,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:01,906 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:01,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:01,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,001 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:02,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:02,002 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008160693] [2021-10-28 23:41:02,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008160693] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:41:02,003 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:41:02,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-10-28 23:41:02,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312636895] [2021-10-28 23:41:02,023 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:02,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:41:02,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:41:02,025 INFO L87 Difference]: Start difference. First operand 13 states and 17 transitions. cyclomatic complexity: 6 Second operand has 4 states, 3 states have (on average 3.0) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:02,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:02,058 INFO L93 Difference]: Finished difference Result 20 states and 25 transitions. [2021-10-28 23:41:02,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:41:02,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 25 transitions. [2021-10-28 23:41:02,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2021-10-28 23:41:02,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 20 states and 25 transitions. [2021-10-28 23:41:02,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-10-28 23:41:02,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-10-28 23:41:02,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 25 transitions. [2021-10-28 23:41:02,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:02,069 INFO L681 BuchiCegarLoop]: Abstraction has 20 states and 25 transitions. [2021-10-28 23:41:02,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 25 transitions. [2021-10-28 23:41:02,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 15. [2021-10-28 23:41:02,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:02,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 19 transitions. [2021-10-28 23:41:02,074 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2021-10-28 23:41:02,074 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2021-10-28 23:41:02,075 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-10-28 23:41:02,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 19 transitions. [2021-10-28 23:41:02,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:02,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:02,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:02,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1] [2021-10-28 23:41:02,077 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-10-28 23:41:02,077 INFO L791 eck$LassoCheckResult]: Stem: 181#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 178#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 183#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 188#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 174#L12-1 [2021-10-28 23:41:02,077 INFO L793 eck$LassoCheckResult]: Loop: 174#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 175#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 174#L12-1 [2021-10-28 23:41:02,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:02,078 INFO L85 PathProgramCache]: Analyzing trace with hash -1365869310, now seen corresponding path program 2 times [2021-10-28 23:41:02,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:02,078 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965151680] [2021-10-28 23:41:02,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:02,079 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:02,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,101 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:02,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,107 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:02,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:02,108 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 2 times [2021-10-28 23:41:02,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:02,109 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009998465] [2021-10-28 23:41:02,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:02,109 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:02,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,125 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:02,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,137 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:02,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:02,138 INFO L85 PathProgramCache]: Analyzing trace with hash -92441875, now seen corresponding path program 3 times [2021-10-28 23:41:02,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:02,139 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061176974] [2021-10-28 23:41:02,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:02,139 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:02,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,151 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:02,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:02,171 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:02,209 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:02,210 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:02,210 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:02,210 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:02,210 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 23:41:02,210 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,210 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:02,210 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:02,211 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2021-10-28 23:41:02,211 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:02,211 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:02,212 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,215 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,218 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,279 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:02,279 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 23:41:02,279 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,280 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,281 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,291 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:02,292 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:02,311 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-10-28 23:41:02,326 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 23:41:02,327 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 23:41:02,370 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,371 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,372 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-10-28 23:41:02,376 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:02,376 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:02,410 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 23:41:02,410 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 23:41:02,444 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,445 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,446 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,447 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-10-28 23:41:02,448 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:02,448 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:02,483 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,483 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,484 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-10-28 23:41:02,497 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 23:41:02,497 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:02,597 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 23:41:02,606 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,606 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:02,606 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:02,607 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:02,607 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:02,607 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 23:41:02,607 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,607 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:02,607 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:02,607 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2021-10-28 23:41:02,607 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:02,607 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:02,609 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,624 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,628 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:02,711 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:02,712 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 23:41:02,712 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,713 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,723 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:02,734 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:02,735 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:02,735 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:02,735 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:02,738 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 23:41:02,739 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 23:41:02,743 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-10-28 23:41:02,762 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 23:41:02,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,805 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,810 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,817 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:02,828 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:02,829 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:02,829 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:02,829 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:02,832 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 23:41:02,833 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 23:41:02,837 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-10-28 23:41:02,847 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 23:41:02,891 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,892 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,892 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,893 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,900 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:02,911 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:02,912 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 23:41:02,912 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:02,912 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:02,912 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:02,914 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 23:41:02,914 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 23:41:02,917 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2021-10-28 23:41:02,938 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 23:41:02,943 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2021-10-28 23:41:02,943 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2021-10-28 23:41:02,943 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:02,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:02,945 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:02,951 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 23:41:02,952 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 23:41:02,952 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 23:41:02,952 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, ULTIMATE.start_main_~range~0) = -1*ULTIMATE.start_main_~i~0 + 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2021-10-28 23:41:02,967 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2021-10-28 23:41:02,996 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:02,997 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 23:41:03,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:03,030 INFO L263 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:03,031 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:03,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:03,083 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:03,084 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:03,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:03,129 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 23:41:03,130 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 15 states and 19 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,155 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 15 states and 19 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 32 states and 38 transitions. Complement of second has 5 states. [2021-10-28 23:41:03,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:03,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2021-10-28 23:41:03,160 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 7 letters. Loop has 3 letters. [2021-10-28 23:41:03,162 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:03,162 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 10 letters. Loop has 3 letters. [2021-10-28 23:41:03,162 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:03,162 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 7 letters. Loop has 6 letters. [2021-10-28 23:41:03,163 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:03,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 38 transitions. [2021-10-28 23:41:03,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 28 states and 34 transitions. [2021-10-28 23:41:03,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-10-28 23:41:03,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-10-28 23:41:03,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2021-10-28 23:41:03,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:03,170 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 34 transitions. [2021-10-28 23:41:03,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2021-10-28 23:41:03,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2021-10-28 23:41:03,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 32 transitions. [2021-10-28 23:41:03,178 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 32 transitions. [2021-10-28 23:41:03,179 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 32 transitions. [2021-10-28 23:41:03,179 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-10-28 23:41:03,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 32 transitions. [2021-10-28 23:41:03,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:03,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:03,185 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1] [2021-10-28 23:41:03,185 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:03,186 INFO L791 eck$LassoCheckResult]: Stem: 279#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 288#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 285#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 284#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 276#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 281#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 290#L12-1 [2021-10-28 23:41:03,186 INFO L793 eck$LassoCheckResult]: Loop: 290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 292#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 290#L12-1 [2021-10-28 23:41:03,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,187 INFO L85 PathProgramCache]: Analyzing trace with hash -92441877, now seen corresponding path program 4 times [2021-10-28 23:41:03,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:03,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316042811] [2021-10-28 23:41:03,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:03,188 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:03,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:03,233 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:03,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:03,234 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316042811] [2021-10-28 23:41:03,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316042811] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:03,235 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [222736582] [2021-10-28 23:41:03,235 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:41:03,235 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:03,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:03,237 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:03,239 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-10-28 23:41:03,287 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:41:03,287 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:03,288 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:03,289 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:03,420 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:03,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [222736582] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:03,421 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:03,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 5 [2021-10-28 23:41:03,425 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29263914] [2021-10-28 23:41:03,426 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:03,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 4 times [2021-10-28 23:41:03,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:03,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094332709] [2021-10-28 23:41:03,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:03,431 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:03,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:03,438 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:03,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:03,441 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:03,469 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:03,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-10-28 23:41:03,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2021-10-28 23:41:03,470 INFO L87 Difference]: Start difference. First operand 26 states and 32 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:03,516 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2021-10-28 23:41:03,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-10-28 23:41:03,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 38 transitions. [2021-10-28 23:41:03,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 31 states and 36 transitions. [2021-10-28 23:41:03,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-10-28 23:41:03,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-10-28 23:41:03,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 36 transitions. [2021-10-28 23:41:03,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:03,523 INFO L681 BuchiCegarLoop]: Abstraction has 31 states and 36 transitions. [2021-10-28 23:41:03,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 36 transitions. [2021-10-28 23:41:03,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 29. [2021-10-28 23:41:03,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.1724137931034482) internal successors, (34), 28 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 34 transitions. [2021-10-28 23:41:03,533 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 34 transitions. [2021-10-28 23:41:03,533 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 34 transitions. [2021-10-28 23:41:03,534 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-10-28 23:41:03,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 34 transitions. [2021-10-28 23:41:03,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:03,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:03,538 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 2, 2, 1] [2021-10-28 23:41:03,539 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:03,539 INFO L791 eck$LassoCheckResult]: Stem: 373#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 386#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 385#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 383#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 382#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 381#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 392#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 388#L12-1 [2021-10-28 23:41:03,539 INFO L793 eck$LassoCheckResult]: Loop: 388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 390#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 388#L12-1 [2021-10-28 23:41:03,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,540 INFO L85 PathProgramCache]: Analyzing trace with hash -861851360, now seen corresponding path program 5 times [2021-10-28 23:41:03,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:03,545 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498804757] [2021-10-28 23:41:03,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:03,546 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:03,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:03,609 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:03,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:03,611 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498804757] [2021-10-28 23:41:03,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498804757] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:03,612 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [215654068] [2021-10-28 23:41:03,612 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:03,612 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:03,612 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:03,622 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:03,642 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-10-28 23:41:03,677 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-10-28 23:41:03,677 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:03,678 INFO L263 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-28 23:41:03,679 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:03,830 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:03,831 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [215654068] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:03,831 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:03,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2021-10-28 23:41:03,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550301160] [2021-10-28 23:41:03,832 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:03,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,833 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 5 times [2021-10-28 23:41:03,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:03,833 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127658040] [2021-10-28 23:41:03,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:03,834 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:03,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:03,840 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:03,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:03,848 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:03,867 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:03,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-10-28 23:41:03,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2021-10-28 23:41:03,869 INFO L87 Difference]: Start difference. First operand 29 states and 34 transitions. cyclomatic complexity: 8 Second operand has 9 states, 8 states have (on average 2.875) internal successors, (23), 8 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:03,928 INFO L93 Difference]: Finished difference Result 39 states and 44 transitions. [2021-10-28 23:41:03,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-10-28 23:41:03,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 44 transitions. [2021-10-28 23:41:03,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 37 states and 42 transitions. [2021-10-28 23:41:03,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2021-10-28 23:41:03,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2021-10-28 23:41:03,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 42 transitions. [2021-10-28 23:41:03,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:03,945 INFO L681 BuchiCegarLoop]: Abstraction has 37 states and 42 transitions. [2021-10-28 23:41:03,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 42 transitions. [2021-10-28 23:41:03,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 35. [2021-10-28 23:41:03,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.1428571428571428) internal successors, (40), 34 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:03,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 40 transitions. [2021-10-28 23:41:03,951 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 40 transitions. [2021-10-28 23:41:03,951 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 40 transitions. [2021-10-28 23:41:03,952 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-10-28 23:41:03,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 40 transitions. [2021-10-28 23:41:03,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:03,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:03,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:03,954 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1] [2021-10-28 23:41:03,954 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:03,955 INFO L791 eck$LassoCheckResult]: Stem: 491#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 502#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 501#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 499#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 498#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 496#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 490#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 486#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 487#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 495#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 510#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 509#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 505#L12-1 [2021-10-28 23:41:03,955 INFO L793 eck$LassoCheckResult]: Loop: 505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 507#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 505#L12-1 [2021-10-28 23:41:03,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:03,955 INFO L85 PathProgramCache]: Analyzing trace with hash -99300661, now seen corresponding path program 6 times [2021-10-28 23:41:03,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:03,956 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071808578] [2021-10-28 23:41:03,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:03,956 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:03,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:04,059 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:04,059 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:04,059 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071808578] [2021-10-28 23:41:04,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071808578] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:04,060 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [880852694] [2021-10-28 23:41:04,060 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:04,060 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:04,060 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:04,076 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:04,077 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:04,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-10-28 23:41:04,132 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2021-10-28 23:41:04,133 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:04,134 INFO L263 TraceCheckSpWp]: Trace formula consists of 42 conjuncts, 7 conjunts are in the unsatisfiable core [2021-10-28 23:41:04,135 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:04,298 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:04,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [880852694] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:04,298 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:04,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 9 [2021-10-28 23:41:04,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236119007] [2021-10-28 23:41:04,299 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:04,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:04,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 6 times [2021-10-28 23:41:04,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:04,300 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068123541] [2021-10-28 23:41:04,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:04,301 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:04,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:04,304 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:04,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:04,307 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:04,323 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:04,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-10-28 23:41:04,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2021-10-28 23:41:04,324 INFO L87 Difference]: Start difference. First operand 35 states and 40 transitions. cyclomatic complexity: 8 Second operand has 11 states, 10 states have (on average 2.9) internal successors, (29), 10 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:04,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:04,363 INFO L93 Difference]: Finished difference Result 45 states and 50 transitions. [2021-10-28 23:41:04,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-10-28 23:41:04,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 50 transitions. [2021-10-28 23:41:04,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:04,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 43 states and 48 transitions. [2021-10-28 23:41:04,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-10-28 23:41:04,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-10-28 23:41:04,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 48 transitions. [2021-10-28 23:41:04,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:04,367 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 48 transitions. [2021-10-28 23:41:04,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 48 transitions. [2021-10-28 23:41:04,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 41. [2021-10-28 23:41:04,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.1219512195121952) internal successors, (46), 40 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:04,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2021-10-28 23:41:04,372 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 46 transitions. [2021-10-28 23:41:04,372 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 46 transitions. [2021-10-28 23:41:04,372 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-10-28 23:41:04,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 46 transitions. [2021-10-28 23:41:04,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:04,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:04,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:04,374 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 4, 2, 1] [2021-10-28 23:41:04,374 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:04,375 INFO L791 eck$LassoCheckResult]: Stem: 627#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 639#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 662#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 633#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 660#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 648#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 644#L12-1 [2021-10-28 23:41:04,375 INFO L793 eck$LassoCheckResult]: Loop: 644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 646#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 644#L12-1 [2021-10-28 23:41:04,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash 966544704, now seen corresponding path program 7 times [2021-10-28 23:41:04,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:04,376 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849640459] [2021-10-28 23:41:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:04,376 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:04,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:04,442 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:04,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:04,443 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849640459] [2021-10-28 23:41:04,443 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849640459] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:04,443 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1363989283] [2021-10-28 23:41:04,443 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:41:04,444 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:04,444 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:04,450 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:04,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-10-28 23:41:04,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:04,524 INFO L263 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 8 conjunts are in the unsatisfiable core [2021-10-28 23:41:04,525 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:04,737 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:04,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1363989283] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:04,738 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:04,738 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 11 [2021-10-28 23:41:04,739 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720793811] [2021-10-28 23:41:04,740 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:04,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:04,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 7 times [2021-10-28 23:41:04,740 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:04,741 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143293029] [2021-10-28 23:41:04,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:04,741 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:04,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:04,757 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:04,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:04,764 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:04,780 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:04,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-10-28 23:41:04,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2021-10-28 23:41:04,785 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.9166666666666665) internal successors, (35), 12 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:04,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:04,858 INFO L93 Difference]: Finished difference Result 51 states and 56 transitions. [2021-10-28 23:41:04,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-10-28 23:41:04,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 56 transitions. [2021-10-28 23:41:04,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:04,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 49 states and 54 transitions. [2021-10-28 23:41:04,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2021-10-28 23:41:04,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2021-10-28 23:41:04,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 54 transitions. [2021-10-28 23:41:04,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:04,867 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 54 transitions. [2021-10-28 23:41:04,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 54 transitions. [2021-10-28 23:41:04,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 47. [2021-10-28 23:41:04,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.1063829787234043) internal successors, (52), 46 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:04,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2021-10-28 23:41:04,883 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 52 transitions. [2021-10-28 23:41:04,883 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 52 transitions. [2021-10-28 23:41:04,883 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-10-28 23:41:04,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 52 transitions. [2021-10-28 23:41:04,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:04,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:04,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:04,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 5, 2, 1] [2021-10-28 23:41:04,886 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:04,887 INFO L791 eck$LassoCheckResult]: Stem: 792#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 802#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 801#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 800#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 799#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 798#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 797#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 796#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 791#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 831#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 830#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 829#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 828#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 827#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 823#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 825#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 810#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 806#L12-1 [2021-10-28 23:41:04,887 INFO L793 eck$LassoCheckResult]: Loop: 806#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 808#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 806#L12-1 [2021-10-28 23:41:04,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:04,887 INFO L85 PathProgramCache]: Analyzing trace with hash 872594091, now seen corresponding path program 8 times [2021-10-28 23:41:04,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:04,888 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223376300] [2021-10-28 23:41:04,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:04,888 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:04,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:04,996 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:04,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:04,997 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223376300] [2021-10-28 23:41:04,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223376300] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:04,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [18609364] [2021-10-28 23:41:04,998 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:41:04,998 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:04,998 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:05,001 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:05,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-10-28 23:41:05,094 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:41:05,094 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:05,095 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 9 conjunts are in the unsatisfiable core [2021-10-28 23:41:05,096 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:05,357 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:05,357 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [18609364] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:05,358 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:05,358 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 13 [2021-10-28 23:41:05,358 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2197806] [2021-10-28 23:41:05,359 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:05,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:05,359 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 8 times [2021-10-28 23:41:05,359 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:05,360 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969257081] [2021-10-28 23:41:05,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:05,360 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:05,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:05,364 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:05,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:05,367 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:05,385 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:05,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-10-28 23:41:05,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=132, Unknown=0, NotChecked=0, Total=210 [2021-10-28 23:41:05,387 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. cyclomatic complexity: 8 Second operand has 15 states, 14 states have (on average 2.9285714285714284) internal successors, (41), 14 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:05,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:05,483 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2021-10-28 23:41:05,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-10-28 23:41:05,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 62 transitions. [2021-10-28 23:41:05,485 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:05,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 55 states and 60 transitions. [2021-10-28 23:41:05,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2021-10-28 23:41:05,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2021-10-28 23:41:05,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 60 transitions. [2021-10-28 23:41:05,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:05,487 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 60 transitions. [2021-10-28 23:41:05,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 60 transitions. [2021-10-28 23:41:05,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 53. [2021-10-28 23:41:05,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.0943396226415094) internal successors, (58), 52 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:05,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2021-10-28 23:41:05,491 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 58 transitions. [2021-10-28 23:41:05,491 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 58 transitions. [2021-10-28 23:41:05,491 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-10-28 23:41:05,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 58 transitions. [2021-10-28 23:41:05,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:05,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:05,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:05,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 6, 2, 1] [2021-10-28 23:41:05,494 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:05,494 INFO L791 eck$LassoCheckResult]: Stem: 974#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 985#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 982#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1020#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1016#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1006#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 994#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 990#L12-1 [2021-10-28 23:41:05,494 INFO L793 eck$LassoCheckResult]: Loop: 990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 992#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 990#L12-1 [2021-10-28 23:41:05,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:05,495 INFO L85 PathProgramCache]: Analyzing trace with hash -1986408096, now seen corresponding path program 9 times [2021-10-28 23:41:05,495 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:05,495 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414797722] [2021-10-28 23:41:05,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:05,496 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:05,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:05,583 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 0 proven. 84 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:05,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:05,583 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414797722] [2021-10-28 23:41:05,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414797722] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:05,584 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [554498673] [2021-10-28 23:41:05,584 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:41:05,584 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:05,585 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:05,586 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:05,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-10-28 23:41:05,694 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-10-28 23:41:05,694 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:05,695 INFO L263 TraceCheckSpWp]: Trace formula consists of 60 conjuncts, 10 conjunts are in the unsatisfiable core [2021-10-28 23:41:05,696 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:05,958 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 0 proven. 84 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:05,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [554498673] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:05,958 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:05,959 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 15 [2021-10-28 23:41:05,959 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14306104] [2021-10-28 23:41:05,959 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:05,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:05,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 9 times [2021-10-28 23:41:05,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:05,960 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772940570] [2021-10-28 23:41:05,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:05,961 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:05,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:05,965 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:05,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:05,967 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:05,983 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:05,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-10-28 23:41:05,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=171, Unknown=0, NotChecked=0, Total=272 [2021-10-28 23:41:05,984 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. cyclomatic complexity: 8 Second operand has 17 states, 16 states have (on average 2.9375) internal successors, (47), 16 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:06,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:06,058 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2021-10-28 23:41:06,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-10-28 23:41:06,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 68 transitions. [2021-10-28 23:41:06,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:06,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 61 states and 66 transitions. [2021-10-28 23:41:06,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38 [2021-10-28 23:41:06,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38 [2021-10-28 23:41:06,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 66 transitions. [2021-10-28 23:41:06,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:06,065 INFO L681 BuchiCegarLoop]: Abstraction has 61 states and 66 transitions. [2021-10-28 23:41:06,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 66 transitions. [2021-10-28 23:41:06,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 59. [2021-10-28 23:41:06,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.0847457627118644) internal successors, (64), 58 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:06,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions. [2021-10-28 23:41:06,074 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 64 transitions. [2021-10-28 23:41:06,074 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 64 transitions. [2021-10-28 23:41:06,074 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-10-28 23:41:06,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 64 transitions. [2021-10-28 23:41:06,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:06,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:06,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:06,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 7, 2, 1] [2021-10-28 23:41:06,077 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:06,077 INFO L791 eck$LassoCheckResult]: Stem: 1184#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1193#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1192#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1191#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1190#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1189#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1188#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1187#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1183#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1180#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1181#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1235#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1234#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1231#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1229#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1228#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1215#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1217#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1212#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1202#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1198#L12-1 [2021-10-28 23:41:06,079 INFO L793 eck$LassoCheckResult]: Loop: 1198#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1200#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1198#L12-1 [2021-10-28 23:41:06,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:06,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1024114037, now seen corresponding path program 10 times [2021-10-28 23:41:06,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:06,080 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306156185] [2021-10-28 23:41:06,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:06,080 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:06,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:06,188 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:06,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:06,188 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306156185] [2021-10-28 23:41:06,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306156185] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:06,189 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2033359419] [2021-10-28 23:41:06,189 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:41:06,189 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:06,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:06,191 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:06,206 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-10-28 23:41:06,302 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:41:06,302 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:06,303 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 11 conjunts are in the unsatisfiable core [2021-10-28 23:41:06,305 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:06,578 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:06,579 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2033359419] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:06,579 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:06,579 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 17 [2021-10-28 23:41:06,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253693375] [2021-10-28 23:41:06,581 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:06,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:06,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 10 times [2021-10-28 23:41:06,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:06,582 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692188743] [2021-10-28 23:41:06,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:06,583 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:06,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:06,593 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:06,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:06,595 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:06,640 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:06,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-10-28 23:41:06,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=215, Unknown=0, NotChecked=0, Total=342 [2021-10-28 23:41:06,641 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. cyclomatic complexity: 8 Second operand has 19 states, 18 states have (on average 2.9444444444444446) internal successors, (53), 18 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:06,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:06,714 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2021-10-28 23:41:06,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 23:41:06,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 74 transitions. [2021-10-28 23:41:06,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:06,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 67 states and 72 transitions. [2021-10-28 23:41:06,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-10-28 23:41:06,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-10-28 23:41:06,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 72 transitions. [2021-10-28 23:41:06,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:06,720 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 72 transitions. [2021-10-28 23:41:06,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 72 transitions. [2021-10-28 23:41:06,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2021-10-28 23:41:06,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.0769230769230769) internal successors, (70), 64 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:06,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 70 transitions. [2021-10-28 23:41:06,738 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 70 transitions. [2021-10-28 23:41:06,740 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 70 transitions. [2021-10-28 23:41:06,741 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-10-28 23:41:06,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 70 transitions. [2021-10-28 23:41:06,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:06,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:06,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:06,744 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 8, 2, 1] [2021-10-28 23:41:06,745 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:06,745 INFO L791 eck$LassoCheckResult]: Stem: 1415#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1416#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1424#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1423#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1422#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1420#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1418#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1414#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1412#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1473#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1472#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1471#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1470#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1469#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1468#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1467#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1466#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1465#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1464#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1463#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1462#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1461#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1460#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1445#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1433#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1429#L12-1 [2021-10-28 23:41:06,746 INFO L793 eck$LassoCheckResult]: Loop: 1429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1431#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1429#L12-1 [2021-10-28 23:41:06,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:06,746 INFO L85 PathProgramCache]: Analyzing trace with hash 2066464128, now seen corresponding path program 11 times [2021-10-28 23:41:06,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:06,747 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235719149] [2021-10-28 23:41:06,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:06,747 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:06,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:06,896 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 0 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:06,896 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:06,896 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235719149] [2021-10-28 23:41:06,897 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235719149] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:06,897 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1813384203] [2021-10-28 23:41:06,897 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:06,897 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:06,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:06,899 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:06,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-10-28 23:41:07,043 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-10-28 23:41:07,043 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:07,044 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 12 conjunts are in the unsatisfiable core [2021-10-28 23:41:07,046 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:07,343 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 0 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:07,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1813384203] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:07,344 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:07,344 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 19 [2021-10-28 23:41:07,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712359951] [2021-10-28 23:41:07,346 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:07,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:07,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 11 times [2021-10-28 23:41:07,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:07,348 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277433738] [2021-10-28 23:41:07,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:07,348 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:07,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:07,352 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:07,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:07,354 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:07,367 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:07,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-28 23:41:07,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=156, Invalid=264, Unknown=0, NotChecked=0, Total=420 [2021-10-28 23:41:07,369 INFO L87 Difference]: Start difference. First operand 65 states and 70 transitions. cyclomatic complexity: 8 Second operand has 21 states, 20 states have (on average 2.95) internal successors, (59), 20 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:07,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:07,444 INFO L93 Difference]: Finished difference Result 75 states and 80 transitions. [2021-10-28 23:41:07,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-10-28 23:41:07,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 80 transitions. [2021-10-28 23:41:07,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:07,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 73 states and 78 transitions. [2021-10-28 23:41:07,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2021-10-28 23:41:07,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2021-10-28 23:41:07,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 78 transitions. [2021-10-28 23:41:07,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:07,448 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 78 transitions. [2021-10-28 23:41:07,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 78 transitions. [2021-10-28 23:41:07,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 71. [2021-10-28 23:41:07,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.0704225352112675) internal successors, (76), 70 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:07,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 76 transitions. [2021-10-28 23:41:07,451 INFO L704 BuchiCegarLoop]: Abstraction has 71 states and 76 transitions. [2021-10-28 23:41:07,451 INFO L587 BuchiCegarLoop]: Abstraction has 71 states and 76 transitions. [2021-10-28 23:41:07,451 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-10-28 23:41:07,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 76 transitions. [2021-10-28 23:41:07,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:07,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:07,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:07,454 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 9, 2, 1] [2021-10-28 23:41:07,454 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:07,454 INFO L791 eck$LassoCheckResult]: Stem: 1667#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1677#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1670#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1733#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1732#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1729#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1728#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1727#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1726#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1725#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1723#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1722#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1721#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1720#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1719#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1718#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1717#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1699#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1687#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1683#L12-1 [2021-10-28 23:41:07,454 INFO L793 eck$LassoCheckResult]: Loop: 1683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1685#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1683#L12-1 [2021-10-28 23:41:07,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:07,455 INFO L85 PathProgramCache]: Analyzing trace with hash -2028314005, now seen corresponding path program 12 times [2021-10-28 23:41:07,455 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:07,455 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340394322] [2021-10-28 23:41:07,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:07,456 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:07,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:07,579 INFO L134 CoverageAnalysis]: Checked inductivity of 165 backedges. 0 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:07,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:07,580 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340394322] [2021-10-28 23:41:07,580 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340394322] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:07,580 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1054495075] [2021-10-28 23:41:07,581 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:07,581 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:07,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:07,586 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:07,590 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-10-28 23:41:07,724 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2021-10-28 23:41:07,724 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:07,725 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 13 conjunts are in the unsatisfiable core [2021-10-28 23:41:07,726 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:08,133 INFO L134 CoverageAnalysis]: Checked inductivity of 165 backedges. 0 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:08,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1054495075] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:08,134 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:08,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 21 [2021-10-28 23:41:08,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282056544] [2021-10-28 23:41:08,135 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:08,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:08,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 12 times [2021-10-28 23:41:08,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:08,137 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051032656] [2021-10-28 23:41:08,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:08,139 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:08,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:08,143 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:08,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:08,147 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:08,173 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:08,174 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-10-28 23:41:08,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=318, Unknown=0, NotChecked=0, Total=506 [2021-10-28 23:41:08,175 INFO L87 Difference]: Start difference. First operand 71 states and 76 transitions. cyclomatic complexity: 8 Second operand has 23 states, 22 states have (on average 2.9545454545454546) internal successors, (65), 22 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:08,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:08,268 INFO L93 Difference]: Finished difference Result 81 states and 86 transitions. [2021-10-28 23:41:08,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-10-28 23:41:08,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 86 transitions. [2021-10-28 23:41:08,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:08,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 79 states and 84 transitions. [2021-10-28 23:41:08,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47 [2021-10-28 23:41:08,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2021-10-28 23:41:08,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 84 transitions. [2021-10-28 23:41:08,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:08,272 INFO L681 BuchiCegarLoop]: Abstraction has 79 states and 84 transitions. [2021-10-28 23:41:08,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 84 transitions. [2021-10-28 23:41:08,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 77. [2021-10-28 23:41:08,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.0649350649350648) internal successors, (82), 76 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:08,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2021-10-28 23:41:08,276 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 82 transitions. [2021-10-28 23:41:08,276 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 82 transitions. [2021-10-28 23:41:08,276 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-10-28 23:41:08,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 82 transitions. [2021-10-28 23:41:08,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:08,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:08,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:08,279 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 10, 2, 1] [2021-10-28 23:41:08,279 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:08,279 INFO L791 eck$LassoCheckResult]: Stem: 1946#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1954#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2013#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2012#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2009#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2008#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2007#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2006#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2004#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2003#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2002#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2001#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2000#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1997#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1976#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1964#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1960#L12-1 [2021-10-28 23:41:08,280 INFO L793 eck$LassoCheckResult]: Loop: 1960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1962#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1960#L12-1 [2021-10-28 23:41:08,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:08,280 INFO L85 PathProgramCache]: Analyzing trace with hash 392434080, now seen corresponding path program 13 times [2021-10-28 23:41:08,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:08,281 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197433713] [2021-10-28 23:41:08,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:08,281 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:08,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:08,429 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:08,429 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:08,430 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197433713] [2021-10-28 23:41:08,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197433713] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:08,430 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1174701129] [2021-10-28 23:41:08,430 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:41:08,430 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:08,430 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:08,435 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:08,439 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-10-28 23:41:08,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:08,630 INFO L263 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 23:41:08,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:09,049 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:09,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1174701129] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:09,049 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:09,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 23 [2021-10-28 23:41:09,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984821796] [2021-10-28 23:41:09,050 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:09,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:09,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 13 times [2021-10-28 23:41:09,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:09,051 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531638135] [2021-10-28 23:41:09,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:09,051 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:09,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,055 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:09,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,056 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:09,071 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:09,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-10-28 23:41:09,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=377, Unknown=0, NotChecked=0, Total=600 [2021-10-28 23:41:09,073 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. cyclomatic complexity: 8 Second operand has 25 states, 24 states have (on average 2.9583333333333335) internal successors, (71), 24 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:09,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:09,169 INFO L93 Difference]: Finished difference Result 87 states and 92 transitions. [2021-10-28 23:41:09,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-10-28 23:41:09,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 92 transitions. [2021-10-28 23:41:09,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:09,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 85 states and 90 transitions. [2021-10-28 23:41:09,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50 [2021-10-28 23:41:09,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50 [2021-10-28 23:41:09,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 90 transitions. [2021-10-28 23:41:09,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:09,173 INFO L681 BuchiCegarLoop]: Abstraction has 85 states and 90 transitions. [2021-10-28 23:41:09,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 90 transitions. [2021-10-28 23:41:09,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 83. [2021-10-28 23:41:09,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.0602409638554218) internal successors, (88), 82 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:09,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 88 transitions. [2021-10-28 23:41:09,177 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 88 transitions. [2021-10-28 23:41:09,177 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 88 transitions. [2021-10-28 23:41:09,177 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-10-28 23:41:09,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 88 transitions. [2021-10-28 23:41:09,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-10-28 23:41:09,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:09,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:09,179 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 12, 1, 1] [2021-10-28 23:41:09,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-10-28 23:41:09,179 INFO L791 eck$LassoCheckResult]: Stem: 2246#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 2247#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2256#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2270#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2266#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2257#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2258#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2244#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2240#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2241#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2296#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2293#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2292#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2290#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2288#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2286#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2284#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2278#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2273#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2272#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2271#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2269#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2265#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2261#L12-1 [2021-10-28 23:41:09,179 INFO L793 eck$LassoCheckResult]: Loop: 2261#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2263#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2259#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2261#L12-1 [2021-10-28 23:41:09,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:09,179 INFO L85 PathProgramCache]: Analyzing trace with hash -1288685295, now seen corresponding path program 14 times [2021-10-28 23:41:09,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:09,180 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990031939] [2021-10-28 23:41:09,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:09,180 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:09,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,192 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:09,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,206 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:09,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:09,206 INFO L85 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 3 times [2021-10-28 23:41:09,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:09,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008047163] [2021-10-28 23:41:09,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:09,207 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:09,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,212 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:09,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,215 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:09,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:09,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1489045630, now seen corresponding path program 15 times [2021-10-28 23:41:09,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:09,216 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339346982] [2021-10-28 23:41:09,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:09,217 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:09,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,234 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:09,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:09,286 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:09,314 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:09,314 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:09,314 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:09,314 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:09,314 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 23:41:09,314 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,315 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:09,315 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:09,315 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration16_Loop [2021-10-28 23:41:09,315 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:09,315 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:09,316 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,319 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,328 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,369 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:09,369 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 23:41:09,369 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,371 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,379 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:09,379 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:09,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2021-10-28 23:41:09,410 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2021-10-28 23:41:09,410 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2021-10-28 23:41:09,444 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:09,445 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,446 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,448 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:09,448 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:09,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2021-10-28 23:41:09,491 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:09,492 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,493 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,493 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2021-10-28 23:41:09,494 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 23:41:09,494 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:09,570 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 23:41:09,578 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:09,579 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:09,579 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:09,579 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:09,579 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:09,579 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 23:41:09,579 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,579 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:09,579 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:09,579 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration16_Loop [2021-10-28 23:41:09,579 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:09,579 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:09,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,583 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:09,636 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:09,636 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 23:41:09,636 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,637 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,638 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,648 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:09,661 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:09,661 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:09,662 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:09,662 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:09,667 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-10-28 23:41:09,667 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-10-28 23:41:09,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2021-10-28 23:41:09,686 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-10-28 23:41:09,727 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:09,727 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,729 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,731 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:09,741 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:09,741 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 23:41:09,741 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:09,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:09,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:09,744 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 23:41:09,744 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 23:41:09,747 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2021-10-28 23:41:09,749 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 23:41:09,752 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 23:41:09,752 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2021-10-28 23:41:09,752 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:09,752 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:09,753 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:09,754 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 23:41:09,755 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 23:41:09,755 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 23:41:09,755 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0, ULTIMATE.start_main_~i~0) = 1*ULTIMATE.start_main_~range~0 - 1*ULTIMATE.start_main_~i~0 Supporting invariants [] [2021-10-28 23:41:09,755 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2021-10-28 23:41:09,776 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2021-10-28 23:41:09,777 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 23:41:09,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:09,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:09,819 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:09,827 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:09,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:09,964 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:09,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:09,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:09,988 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 23:41:09,988 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,005 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 111 states and 117 transitions. Complement of second has 5 states. [2021-10-28 23:41:10,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:10,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2021-10-28 23:41:10,006 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 40 letters. Loop has 3 letters. [2021-10-28 23:41:10,007 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:10,007 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 23:41:10,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:10,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:10,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:10,037 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:10,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:10,157 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:10,158 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:10,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:10,184 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 23:41:10,185 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,198 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 111 states and 117 transitions. Complement of second has 5 states. [2021-10-28 23:41:10,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:10,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2021-10-28 23:41:10,200 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 40 letters. Loop has 3 letters. [2021-10-28 23:41:10,201 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:10,201 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2021-10-28 23:41:10,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:10,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:10,225 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:10,226 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:10,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:10,345 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2021-10-28 23:41:10,345 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:10,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:10,369 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-10-28 23:41:10,369 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,385 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 83 states and 88 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 135 states and 143 transitions. Complement of second has 4 states. [2021-10-28 23:41:10,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:10,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 10 transitions. [2021-10-28 23:41:10,386 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 40 letters. Loop has 3 letters. [2021-10-28 23:41:10,388 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:10,388 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 43 letters. Loop has 3 letters. [2021-10-28 23:41:10,389 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:10,389 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 40 letters. Loop has 6 letters. [2021-10-28 23:41:10,390 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:10,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135 states and 143 transitions. [2021-10-28 23:41:10,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2021-10-28 23:41:10,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135 states to 89 states and 96 transitions. [2021-10-28 23:41:10,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-10-28 23:41:10,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-10-28 23:41:10,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 96 transitions. [2021-10-28 23:41:10,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:10,395 INFO L681 BuchiCegarLoop]: Abstraction has 89 states and 96 transitions. [2021-10-28 23:41:10,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 96 transitions. [2021-10-28 23:41:10,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 47. [2021-10-28 23:41:10,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.127659574468085) internal successors, (53), 46 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:10,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 53 transitions. [2021-10-28 23:41:10,397 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 53 transitions. [2021-10-28 23:41:10,397 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 53 transitions. [2021-10-28 23:41:10,397 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-10-28 23:41:10,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 53 transitions. [2021-10-28 23:41:10,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2021-10-28 23:41:10,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:10,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:10,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 11, 1, 1] [2021-10-28 23:41:10,399 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2021-10-28 23:41:10,399 INFO L791 eck$LassoCheckResult]: Stem: 3106#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 3107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3109#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3110#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3116#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3103#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3099#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3145#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3105#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3129#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3128#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3127#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3125#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3119#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3120#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3117#L12 [2021-10-28 23:41:10,399 INFO L793 eck$LassoCheckResult]: Loop: 3117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3115#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3111#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3113#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3117#L12 [2021-10-28 23:41:10,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:10,400 INFO L85 PathProgramCache]: Analyzing trace with hash -719445336, now seen corresponding path program 16 times [2021-10-28 23:41:10,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:10,400 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556178355] [2021-10-28 23:41:10,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:10,401 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:10,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:10,410 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:10,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:10,419 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:10,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:10,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1274769951, now seen corresponding path program 1 times [2021-10-28 23:41:10,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:10,421 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989097200] [2021-10-28 23:41:10,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:10,421 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:10,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:10,426 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:10,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:10,429 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:10,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:10,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1755888518, now seen corresponding path program 17 times [2021-10-28 23:41:10,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:10,430 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953997479] [2021-10-28 23:41:10,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:10,431 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:10,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:10,568 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:10,648 INFO L134 CoverageAnalysis]: Checked inductivity of 287 backedges. 52 proven. 234 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 23:41:10,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:10,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953997479] [2021-10-28 23:41:10,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953997479] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:10,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1095786060] [2021-10-28 23:41:10,648 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:10,648 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:10,649 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:10,651 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:10,652 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-10-28 23:41:10,867 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 15 check-sat command(s) [2021-10-28 23:41:10,867 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:10,868 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 23:41:10,869 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:11,314 INFO L134 CoverageAnalysis]: Checked inductivity of 287 backedges. 52 proven. 234 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-10-28 23:41:11,315 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1095786060] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:11,315 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:11,315 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 26 [2021-10-28 23:41:11,315 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558603373] [2021-10-28 23:41:11,366 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:11,367 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:11,367 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:11,367 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:11,367 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2021-10-28 23:41:11,367 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,367 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:11,367 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:11,367 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration17_Loop [2021-10-28 23:41:11,367 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:11,367 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:11,368 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,378 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,424 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:11,424 INFO L404 LassoAnalysis]: Checking for nontermination... [2021-10-28 23:41:11,424 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:11,426 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:11,431 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2021-10-28 23:41:11,432 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:11,445 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2021-10-28 23:41:11,494 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:11,495 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,495 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:11,496 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:11,499 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2021-10-28 23:41:11,500 INFO L160 nArgumentSynthesizer]: Using integer mode. [2021-10-28 23:41:11,519 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2021-10-28 23:41:11,666 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2021-10-28 23:41:11,669 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:11,669 INFO L210 LassoAnalysis]: Preferences: [2021-10-28 23:41:11,669 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-10-28 23:41:11,669 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-10-28 23:41:11,669 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-10-28 23:41:11,669 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-10-28 23:41:11,669 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,669 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-10-28 23:41:11,670 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-10-28 23:41:11,670 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration17_Loop [2021-10-28 23:41:11,670 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-10-28 23:41:11,670 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-10-28 23:41:11,671 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-10-28 23:41:11,728 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-10-28 23:41:11,728 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-10-28 23:41:11,728 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:11,729 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:11,731 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2021-10-28 23:41:11,732 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-10-28 23:41:11,739 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-10-28 23:41:11,739 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-10-28 23:41:11,740 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-10-28 23:41:11,740 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-10-28 23:41:11,740 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-10-28 23:41:11,741 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-10-28 23:41:11,742 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-10-28 23:41:11,755 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-10-28 23:41:11,759 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2021-10-28 23:41:11,759 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2021-10-28 23:41:11,759 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-10-28 23:41:11,759 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:11,765 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-10-28 23:41:11,766 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-10-28 23:41:11,766 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2021-10-28 23:41:11,767 INFO L513 LassoAnalysis]: Proved termination. [2021-10-28 23:41:11,767 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0) = 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2021-10-28 23:41:11,782 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2021-10-28 23:41:11,803 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2021-10-28 23:41:11,804 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2021-10-28 23:41:11,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:11,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:11,863 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 2 conjunts are in the unsatisfiable core [2021-10-28 23:41:11,864 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:11,874 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2021-10-28 23:41:11,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:11,975 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-28 23:41:11,975 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:12,063 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:12,063 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 4 loop predicates [2021-10-28 23:41:12,063 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 47 states and 53 transitions. cyclomatic complexity: 8 Second operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 6 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:12,085 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 47 states and 53 transitions. cyclomatic complexity: 8. Second operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 6 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 99 states and 115 transitions. Complement of second has 6 states. [2021-10-28 23:41:12,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-10-28 23:41:12,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 6 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:12,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 10 transitions. [2021-10-28 23:41:12,086 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 38 letters. Loop has 6 letters. [2021-10-28 23:41:12,086 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:12,087 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 44 letters. Loop has 6 letters. [2021-10-28 23:41:12,087 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:12,087 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 10 transitions. Stem has 38 letters. Loop has 12 letters. [2021-10-28 23:41:12,088 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-10-28 23:41:12,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 115 transitions. [2021-10-28 23:41:12,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:12,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 54 states and 62 transitions. [2021-10-28 23:41:12,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-10-28 23:41:12,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 23:41:12,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 62 transitions. [2021-10-28 23:41:12,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:12,091 INFO L681 BuchiCegarLoop]: Abstraction has 54 states and 62 transitions. [2021-10-28 23:41:12,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 62 transitions. [2021-10-28 23:41:12,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 50. [2021-10-28 23:41:12,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.14) internal successors, (57), 49 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:12,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 57 transitions. [2021-10-28 23:41:12,093 INFO L704 BuchiCegarLoop]: Abstraction has 50 states and 57 transitions. [2021-10-28 23:41:12,093 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:12,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-10-28 23:41:12,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=441, Unknown=0, NotChecked=0, Total=702 [2021-10-28 23:41:12,094 INFO L87 Difference]: Start difference. First operand 50 states and 57 transitions. Second operand has 27 states, 27 states have (on average 2.962962962962963) internal successors, (80), 26 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:12,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:12,180 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2021-10-28 23:41:12,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-10-28 23:41:12,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 64 transitions. [2021-10-28 23:41:12,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:12,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 55 states and 62 transitions. [2021-10-28 23:41:12,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:12,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:12,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 62 transitions. [2021-10-28 23:41:12,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:12,184 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 62 transitions. [2021-10-28 23:41:12,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 62 transitions. [2021-10-28 23:41:12,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 53. [2021-10-28 23:41:12,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.1320754716981132) internal successors, (60), 52 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:12,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 60 transitions. [2021-10-28 23:41:12,186 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 60 transitions. [2021-10-28 23:41:12,186 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 60 transitions. [2021-10-28 23:41:12,186 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-10-28 23:41:12,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 60 transitions. [2021-10-28 23:41:12,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:12,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:12,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:12,188 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 14, 12, 2, 1, 1] [2021-10-28 23:41:12,188 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:12,188 INFO L791 eck$LassoCheckResult]: Stem: 3667#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 3668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3671#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3715#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3706#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3705#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3703#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3701#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3699#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3698#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3696#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3693#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3683#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3680#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3676#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 3663#L12-1 [2021-10-28 23:41:12,189 INFO L793 eck$LassoCheckResult]: Loop: 3663#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3664#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 3663#L12-1 [2021-10-28 23:41:12,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:12,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1344774389, now seen corresponding path program 2 times [2021-10-28 23:41:12,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:12,189 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558467658] [2021-10-28 23:41:12,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:12,190 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:12,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:12,334 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 217 proven. 82 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-10-28 23:41:12,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:12,335 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558467658] [2021-10-28 23:41:12,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558467658] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:12,335 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1901920214] [2021-10-28 23:41:12,335 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:41:12,335 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:12,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:12,336 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:12,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-10-28 23:41:12,584 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:41:12,584 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:12,585 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 16 conjunts are in the unsatisfiable core [2021-10-28 23:41:12,586 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:13,154 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 28 proven. 273 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-10-28 23:41:13,154 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1901920214] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:13,154 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:13,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 30 [2021-10-28 23:41:13,155 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879742152] [2021-10-28 23:41:13,155 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:13,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:13,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 14 times [2021-10-28 23:41:13,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:13,156 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817895409] [2021-10-28 23:41:13,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:13,156 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:13,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:13,161 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:13,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:13,162 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:13,177 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:13,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-10-28 23:41:13,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=225, Invalid=645, Unknown=0, NotChecked=0, Total=870 [2021-10-28 23:41:13,179 INFO L87 Difference]: Start difference. First operand 53 states and 60 transitions. cyclomatic complexity: 10 Second operand has 30 states, 30 states have (on average 2.966666666666667) internal successors, (89), 30 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:14,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:14,072 INFO L93 Difference]: Finished difference Result 168 states and 196 transitions. [2021-10-28 23:41:14,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-10-28 23:41:14,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168 states and 196 transitions. [2021-10-28 23:41:14,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:14,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168 states to 166 states and 194 transitions. [2021-10-28 23:41:14,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-10-28 23:41:14,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-10-28 23:41:14,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166 states and 194 transitions. [2021-10-28 23:41:14,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:14,078 INFO L681 BuchiCegarLoop]: Abstraction has 166 states and 194 transitions. [2021-10-28 23:41:14,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states and 194 transitions. [2021-10-28 23:41:14,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 89. [2021-10-28 23:41:14,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 88 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:14,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 106 transitions. [2021-10-28 23:41:14,082 INFO L704 BuchiCegarLoop]: Abstraction has 89 states and 106 transitions. [2021-10-28 23:41:14,082 INFO L587 BuchiCegarLoop]: Abstraction has 89 states and 106 transitions. [2021-10-28 23:41:14,082 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-10-28 23:41:14,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 106 transitions. [2021-10-28 23:41:14,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:14,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:14,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:14,089 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 17, 14, 3, 1, 1] [2021-10-28 23:41:14,089 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:14,090 INFO L791 eck$LassoCheckResult]: Stem: 4134#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 4129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4130#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4135#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4145#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4155#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4153#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4147#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4143#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4142#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4138#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4137#L12-1 [2021-10-28 23:41:14,090 INFO L793 eck$LassoCheckResult]: Loop: 4137#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4136#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4137#L12-1 [2021-10-28 23:41:14,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:14,090 INFO L85 PathProgramCache]: Analyzing trace with hash -227533164, now seen corresponding path program 3 times [2021-10-28 23:41:14,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:14,091 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423480515] [2021-10-28 23:41:14,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:14,091 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:14,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:14,166 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 34 proven. 135 refuted. 0 times theorem prover too weak. 273 trivial. 0 not checked. [2021-10-28 23:41:14,166 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:14,167 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423480515] [2021-10-28 23:41:14,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423480515] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:14,167 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1453329530] [2021-10-28 23:41:14,168 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:41:14,168 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:14,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:14,173 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:14,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-10-28 23:41:14,497 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-10-28 23:41:14,498 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:14,498 INFO L263 TraceCheckSpWp]: Trace formula consists of 45 conjuncts, 6 conjunts are in the unsatisfiable core [2021-10-28 23:41:14,500 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:14,691 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 166 refuted. 0 times theorem prover too weak. 276 trivial. 0 not checked. [2021-10-28 23:41:14,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1453329530] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:14,692 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:14,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 7 [2021-10-28 23:41:14,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227670474] [2021-10-28 23:41:14,694 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:14,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:14,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 15 times [2021-10-28 23:41:14,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:14,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341033906] [2021-10-28 23:41:14,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:14,696 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:14,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:14,701 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:14,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:14,703 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:14,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:14,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-10-28 23:41:14,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2021-10-28 23:41:14,721 INFO L87 Difference]: Start difference. First operand 89 states and 106 transitions. cyclomatic complexity: 20 Second operand has 8 states, 8 states have (on average 2.875) internal successors, (23), 7 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:14,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:14,813 INFO L93 Difference]: Finished difference Result 175 states and 214 transitions. [2021-10-28 23:41:14,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-10-28 23:41:14,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 214 transitions. [2021-10-28 23:41:14,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:14,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 173 states and 212 transitions. [2021-10-28 23:41:14,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:14,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:14,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173 states and 212 transitions. [2021-10-28 23:41:14,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:14,819 INFO L681 BuchiCegarLoop]: Abstraction has 173 states and 212 transitions. [2021-10-28 23:41:14,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states and 212 transitions. [2021-10-28 23:41:14,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 98. [2021-10-28 23:41:14,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.183673469387755) internal successors, (116), 97 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:14,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 116 transitions. [2021-10-28 23:41:14,824 INFO L704 BuchiCegarLoop]: Abstraction has 98 states and 116 transitions. [2021-10-28 23:41:14,824 INFO L587 BuchiCegarLoop]: Abstraction has 98 states and 116 transitions. [2021-10-28 23:41:14,824 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-10-28 23:41:14,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 116 transitions. [2021-10-28 23:41:14,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:14,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:14,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:14,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 20, 16, 4, 1, 1] [2021-10-28 23:41:14,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:14,827 INFO L791 eck$LassoCheckResult]: Stem: 4577#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 4578#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4580#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4581#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4579#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4575#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4634#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4633#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4630#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4625#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4590#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4586#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4573#L12-1 [2021-10-28 23:41:14,827 INFO L793 eck$LassoCheckResult]: Loop: 4573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4574#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4573#L12-1 [2021-10-28 23:41:14,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:14,828 INFO L85 PathProgramCache]: Analyzing trace with hash 812435755, now seen corresponding path program 4 times [2021-10-28 23:41:14,828 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:14,828 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511638306] [2021-10-28 23:41:14,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:14,829 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:14,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:14,913 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 144 proven. 186 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2021-10-28 23:41:14,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:14,913 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511638306] [2021-10-28 23:41:14,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511638306] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:14,914 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1139366693] [2021-10-28 23:41:14,914 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:41:14,914 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:14,914 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:14,916 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:14,936 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-10-28 23:41:15,268 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:41:15,268 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:15,269 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 23:41:15,271 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:15,793 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 429 proven. 174 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2021-10-28 23:41:15,794 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1139366693] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:15,794 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:15,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 20] total 25 [2021-10-28 23:41:15,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844737266] [2021-10-28 23:41:15,795 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:15,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:15,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 16 times [2021-10-28 23:41:15,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:15,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315756758] [2021-10-28 23:41:15,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:15,796 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:15,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:15,801 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:15,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:15,809 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:15,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:15,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-10-28 23:41:15,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=453, Unknown=0, NotChecked=0, Total=600 [2021-10-28 23:41:15,827 INFO L87 Difference]: Start difference. First operand 98 states and 116 transitions. cyclomatic complexity: 22 Second operand has 25 states, 25 states have (on average 3.08) internal successors, (77), 25 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:16,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:16,957 INFO L93 Difference]: Finished difference Result 254 states and 296 transitions. [2021-10-28 23:41:16,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2021-10-28 23:41:16,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 254 states and 296 transitions. [2021-10-28 23:41:16,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:16,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 254 states to 248 states and 290 transitions. [2021-10-28 23:41:16,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-10-28 23:41:16,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-10-28 23:41:16,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 248 states and 290 transitions. [2021-10-28 23:41:16,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:16,964 INFO L681 BuchiCegarLoop]: Abstraction has 248 states and 290 transitions. [2021-10-28 23:41:16,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states and 290 transitions. [2021-10-28 23:41:16,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 116. [2021-10-28 23:41:16,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1724137931034482) internal successors, (136), 115 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:16,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 136 transitions. [2021-10-28 23:41:16,968 INFO L704 BuchiCegarLoop]: Abstraction has 116 states and 136 transitions. [2021-10-28 23:41:16,968 INFO L587 BuchiCegarLoop]: Abstraction has 116 states and 136 transitions. [2021-10-28 23:41:16,968 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-10-28 23:41:16,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 136 transitions. [2021-10-28 23:41:16,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:16,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:16,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:16,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 19, 4, 1, 1] [2021-10-28 23:41:16,971 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:16,971 INFO L791 eck$LassoCheckResult]: Stem: 5275#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 5270#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5271#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5276#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5382#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5374#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5373#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5370#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5369#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5368#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5361#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5358#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5357#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5356#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5355#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5354#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5352#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5351#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5350#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5347#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5348#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5344#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5329#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5336#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5324#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5323#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5322#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5319#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5318#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5292#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5315#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5284#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5283#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5282#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5279#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 5278#L12-1 [2021-10-28 23:41:16,971 INFO L793 eck$LassoCheckResult]: Loop: 5278#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5277#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 5278#L12-1 [2021-10-28 23:41:16,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:16,972 INFO L85 PathProgramCache]: Analyzing trace with hash -933829070, now seen corresponding path program 5 times [2021-10-28 23:41:16,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:16,972 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600559950] [2021-10-28 23:41:16,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:16,973 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:16,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:17,045 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 266 proven. 240 refuted. 0 times theorem prover too weak. 299 trivial. 0 not checked. [2021-10-28 23:41:17,045 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:17,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600559950] [2021-10-28 23:41:17,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600559950] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:17,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1060080142] [2021-10-28 23:41:17,046 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:17,046 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:17,047 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:17,048 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:17,066 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-10-28 23:41:17,403 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 17 check-sat command(s) [2021-10-28 23:41:17,403 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:17,404 INFO L263 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 23:41:17,406 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:17,891 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 579 proven. 130 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2021-10-28 23:41:17,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1060080142] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:17,892 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:17,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 15] total 21 [2021-10-28 23:41:17,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226747036] [2021-10-28 23:41:17,892 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:17,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:17,893 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 17 times [2021-10-28 23:41:17,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:17,893 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119484938] [2021-10-28 23:41:17,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:17,893 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:17,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:17,899 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:17,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:17,902 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:17,931 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:17,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-28 23:41:17,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=338, Unknown=0, NotChecked=0, Total=420 [2021-10-28 23:41:17,933 INFO L87 Difference]: Start difference. First operand 116 states and 136 transitions. cyclomatic complexity: 24 Second operand has 21 states, 21 states have (on average 3.142857142857143) internal successors, (66), 21 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:18,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:18,807 INFO L93 Difference]: Finished difference Result 194 states and 223 transitions. [2021-10-28 23:41:18,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-10-28 23:41:18,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 223 transitions. [2021-10-28 23:41:18,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:18,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 186 states and 215 transitions. [2021-10-28 23:41:18,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 23:41:18,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 23:41:18,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 215 transitions. [2021-10-28 23:41:18,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:18,813 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 215 transitions. [2021-10-28 23:41:18,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 215 transitions. [2021-10-28 23:41:18,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 99. [2021-10-28 23:41:18,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.1414141414141414) internal successors, (113), 98 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:18,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 113 transitions. [2021-10-28 23:41:18,816 INFO L704 BuchiCegarLoop]: Abstraction has 99 states and 113 transitions. [2021-10-28 23:41:18,816 INFO L587 BuchiCegarLoop]: Abstraction has 99 states and 113 transitions. [2021-10-28 23:41:18,816 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-10-28 23:41:18,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 113 transitions. [2021-10-28 23:41:18,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:18,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:18,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:18,819 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 25, 21, 4, 1, 1] [2021-10-28 23:41:18,819 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:18,819 INFO L791 eck$LassoCheckResult]: Stem: 5879#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 5873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5880#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5970#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5967#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5965#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5964#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5963#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5962#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5961#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5958#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5952#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5947#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5946#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5945#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5943#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5941#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5940#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5939#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5936#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5934#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5933#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5931#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5930#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5928#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5925#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5923#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5920#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5912#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5900#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 5910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 5888#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 5887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5882#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 5884#L12-1 [2021-10-28 23:41:18,819 INFO L793 eck$LassoCheckResult]: Loop: 5884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 5886#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 5884#L12-1 [2021-10-28 23:41:18,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:18,820 INFO L85 PathProgramCache]: Analyzing trace with hash 247033814, now seen corresponding path program 6 times [2021-10-28 23:41:18,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:18,821 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580498795] [2021-10-28 23:41:18,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:18,821 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:18,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:18,971 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 340 proven. 297 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2021-10-28 23:41:18,971 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:18,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580498795] [2021-10-28 23:41:18,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580498795] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:18,974 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2052094383] [2021-10-28 23:41:18,974 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:18,974 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:18,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:18,983 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:18,984 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-10-28 23:41:19,347 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2021-10-28 23:41:19,347 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:19,348 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 7 conjunts are in the unsatisfiable core [2021-10-28 23:41:19,350 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:19,556 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 230 proven. 5 refuted. 0 times theorem prover too weak. 715 trivial. 0 not checked. [2021-10-28 23:41:19,556 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2052094383] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:19,556 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:19,557 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 5] total 13 [2021-10-28 23:41:19,557 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530577589] [2021-10-28 23:41:19,557 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:19,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:19,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 18 times [2021-10-28 23:41:19,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:19,559 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035482567] [2021-10-28 23:41:19,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:19,559 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:19,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:19,568 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:19,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:19,571 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:19,587 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:19,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-10-28 23:41:19,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2021-10-28 23:41:19,589 INFO L87 Difference]: Start difference. First operand 99 states and 113 transitions. cyclomatic complexity: 18 Second operand has 13 states, 13 states have (on average 3.3846153846153846) internal successors, (44), 13 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:19,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:19,862 INFO L93 Difference]: Finished difference Result 121 states and 138 transitions. [2021-10-28 23:41:19,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-10-28 23:41:19,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 138 transitions. [2021-10-28 23:41:19,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:19,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 119 states and 136 transitions. [2021-10-28 23:41:19,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-10-28 23:41:19,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-10-28 23:41:19,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 136 transitions. [2021-10-28 23:41:19,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:19,870 INFO L681 BuchiCegarLoop]: Abstraction has 119 states and 136 transitions. [2021-10-28 23:41:19,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 136 transitions. [2021-10-28 23:41:19,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 106. [2021-10-28 23:41:19,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 106 states have (on average 1.1320754716981132) internal successors, (120), 105 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:19,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 120 transitions. [2021-10-28 23:41:19,873 INFO L704 BuchiCegarLoop]: Abstraction has 106 states and 120 transitions. [2021-10-28 23:41:19,874 INFO L587 BuchiCegarLoop]: Abstraction has 106 states and 120 transitions. [2021-10-28 23:41:19,874 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-10-28 23:41:19,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106 states and 120 transitions. [2021-10-28 23:41:19,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:19,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:19,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:19,876 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 22, 5, 1, 1] [2021-10-28 23:41:19,876 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:19,876 INFO L791 eck$LassoCheckResult]: Stem: 6379#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 6374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6381#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6478#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6477#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6476#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6475#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6445#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6446#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6442#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6400#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6425#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6422#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6421#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6415#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6413#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6407#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6420#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6397#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6394#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6387#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6385#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 6384#L12-1 [2021-10-28 23:41:19,877 INFO L793 eck$LassoCheckResult]: Loop: 6384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6383#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 6384#L12-1 [2021-10-28 23:41:19,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:19,877 INFO L85 PathProgramCache]: Analyzing trace with hash -399996620, now seen corresponding path program 7 times [2021-10-28 23:41:19,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:19,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440619870] [2021-10-28 23:41:19,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:19,878 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:19,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:19,918 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 132 proven. 0 refuted. 0 times theorem prover too weak. 975 trivial. 0 not checked. [2021-10-28 23:41:19,919 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:19,919 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440619870] [2021-10-28 23:41:19,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440619870] provided 1 perfect and 0 imperfect interpolant sequences [2021-10-28 23:41:19,919 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-10-28 23:41:19,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-10-28 23:41:19,919 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889298609] [2021-10-28 23:41:19,920 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:19,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:19,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 19 times [2021-10-28 23:41:19,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:19,921 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994155768] [2021-10-28 23:41:19,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:19,921 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:19,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:19,971 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:19,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:19,973 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:19,988 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:19,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-10-28 23:41:19,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-10-28 23:41:19,989 INFO L87 Difference]: Start difference. First operand 106 states and 120 transitions. cyclomatic complexity: 18 Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:20,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:20,017 INFO L93 Difference]: Finished difference Result 106 states and 119 transitions. [2021-10-28 23:41:20,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-10-28 23:41:20,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 119 transitions. [2021-10-28 23:41:20,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:20,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 106 states and 119 transitions. [2021-10-28 23:41:20,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:20,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:20,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 119 transitions. [2021-10-28 23:41:20,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:20,020 INFO L681 BuchiCegarLoop]: Abstraction has 106 states and 119 transitions. [2021-10-28 23:41:20,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 119 transitions. [2021-10-28 23:41:20,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2021-10-28 23:41:20,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 106 states have (on average 1.1226415094339623) internal successors, (119), 105 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:20,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 119 transitions. [2021-10-28 23:41:20,023 INFO L704 BuchiCegarLoop]: Abstraction has 106 states and 119 transitions. [2021-10-28 23:41:20,024 INFO L587 BuchiCegarLoop]: Abstraction has 106 states and 119 transitions. [2021-10-28 23:41:20,024 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-10-28 23:41:20,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106 states and 119 transitions. [2021-10-28 23:41:20,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:20,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:20,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:20,026 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 28, 23, 5, 1, 1] [2021-10-28 23:41:20,026 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:20,026 INFO L791 eck$LassoCheckResult]: Stem: 6599#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 6600#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6602#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6601#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6597#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6603#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6686#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6683#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6665#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6662#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6645#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6641#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6640#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6619#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6617#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6609#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6611#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6607#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 6595#L12-1 [2021-10-28 23:41:20,026 INFO L793 eck$LassoCheckResult]: Loop: 6595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6596#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 6595#L12-1 [2021-10-28 23:41:20,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:20,027 INFO L85 PathProgramCache]: Analyzing trace with hash -2002991635, now seen corresponding path program 8 times [2021-10-28 23:41:20,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:20,027 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94988701] [2021-10-28 23:41:20,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:20,028 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:20,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:20,154 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 483 proven. 357 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2021-10-28 23:41:20,154 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:20,155 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94988701] [2021-10-28 23:41:20,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94988701] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:20,155 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [972261241] [2021-10-28 23:41:20,155 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:41:20,155 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:20,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:20,163 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:20,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-10-28 23:41:20,592 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:41:20,592 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:20,594 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 17 conjunts are in the unsatisfiable core [2021-10-28 23:41:20,596 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:21,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 615 proven. 315 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2021-10-28 23:41:21,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [972261241] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:21,260 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:21,260 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 16] total 23 [2021-10-28 23:41:21,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661351184] [2021-10-28 23:41:21,261 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:21,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:21,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 20 times [2021-10-28 23:41:21,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:21,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104492970] [2021-10-28 23:41:21,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:21,262 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:21,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:21,268 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:21,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:21,270 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:21,286 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:21,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-10-28 23:41:21,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=359, Unknown=0, NotChecked=0, Total=552 [2021-10-28 23:41:21,288 INFO L87 Difference]: Start difference. First operand 106 states and 119 transitions. cyclomatic complexity: 17 Second operand has 24 states, 24 states have (on average 3.0833333333333335) internal successors, (74), 23 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:21,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:21,402 INFO L93 Difference]: Finished difference Result 120 states and 133 transitions. [2021-10-28 23:41:21,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-10-28 23:41:21,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 133 transitions. [2021-10-28 23:41:21,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:21,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 116 states and 129 transitions. [2021-10-28 23:41:21,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:21,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:21,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 129 transitions. [2021-10-28 23:41:21,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:21,405 INFO L681 BuchiCegarLoop]: Abstraction has 116 states and 129 transitions. [2021-10-28 23:41:21,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 129 transitions. [2021-10-28 23:41:21,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 112. [2021-10-28 23:41:21,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 112 states have (on average 1.1160714285714286) internal successors, (125), 111 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:21,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 125 transitions. [2021-10-28 23:41:21,409 INFO L704 BuchiCegarLoop]: Abstraction has 112 states and 125 transitions. [2021-10-28 23:41:21,409 INFO L587 BuchiCegarLoop]: Abstraction has 112 states and 125 transitions. [2021-10-28 23:41:21,409 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-10-28 23:41:21,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112 states and 125 transitions. [2021-10-28 23:41:21,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:21,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:21,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:21,411 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 30, 25, 5, 1, 1] [2021-10-28 23:41:21,411 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:21,411 INFO L791 eck$LassoCheckResult]: Stem: 7110#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 7111#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7113#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7112#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7108#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7109#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7114#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7176#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7162#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7161#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7159#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7158#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7157#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7156#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7150#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7148#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7144#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7137#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7151#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7149#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7130#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7128#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7119#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7123#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7122#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7117#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 7106#L12-1 [2021-10-28 23:41:21,411 INFO L793 eck$LassoCheckResult]: Loop: 7106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7107#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 7106#L12-1 [2021-10-28 23:41:21,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:21,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1003691849, now seen corresponding path program 9 times [2021-10-28 23:41:21,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:21,412 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539325417] [2021-10-28 23:41:21,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:21,412 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:21,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:21,662 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 755 proven. 448 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2021-10-28 23:41:21,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:21,662 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539325417] [2021-10-28 23:41:21,663 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539325417] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:21,663 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2032723164] [2021-10-28 23:41:21,663 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:41:21,663 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:21,663 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:21,666 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:21,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-10-28 23:41:22,272 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-10-28 23:41:22,273 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:22,274 INFO L263 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 9 conjunts are in the unsatisfiable core [2021-10-28 23:41:22,276 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:22,528 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 477 proven. 33 refuted. 0 times theorem prover too weak. 855 trivial. 0 not checked. [2021-10-28 23:41:22,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2032723164] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:22,528 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:22,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 7] total 19 [2021-10-28 23:41:22,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062505456] [2021-10-28 23:41:22,530 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:22,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:22,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 21 times [2021-10-28 23:41:22,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:22,532 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544557097] [2021-10-28 23:41:22,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:22,532 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:22,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:22,543 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:22,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:22,545 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:22,560 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:22,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-10-28 23:41:22,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2021-10-28 23:41:22,561 INFO L87 Difference]: Start difference. First operand 112 states and 125 transitions. cyclomatic complexity: 17 Second operand has 19 states, 19 states have (on average 3.1578947368421053) internal successors, (60), 19 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:23,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:23,528 INFO L93 Difference]: Finished difference Result 288 states and 318 transitions. [2021-10-28 23:41:23,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-10-28 23:41:23,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 318 transitions. [2021-10-28 23:41:23,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:23,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 260 states and 290 transitions. [2021-10-28 23:41:23,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-10-28 23:41:23,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-10-28 23:41:23,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 260 states and 290 transitions. [2021-10-28 23:41:23,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:23,533 INFO L681 BuchiCegarLoop]: Abstraction has 260 states and 290 transitions. [2021-10-28 23:41:23,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states and 290 transitions. [2021-10-28 23:41:23,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 163. [2021-10-28 23:41:23,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.0920245398773005) internal successors, (178), 162 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:23,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 178 transitions. [2021-10-28 23:41:23,537 INFO L704 BuchiCegarLoop]: Abstraction has 163 states and 178 transitions. [2021-10-28 23:41:23,538 INFO L587 BuchiCegarLoop]: Abstraction has 163 states and 178 transitions. [2021-10-28 23:41:23,538 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-10-28 23:41:23,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 178 transitions. [2021-10-28 23:41:23,539 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:23,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:23,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:23,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [44, 43, 35, 8, 1, 1] [2021-10-28 23:41:23,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:23,541 INFO L791 eck$LassoCheckResult]: Stem: 7894#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 7887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7895#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 8037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8034#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8032#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8029#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8028#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8027#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8026#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8025#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8023#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8022#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8020#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8016#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8015#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8014#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8012#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8011#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8010#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8009#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8008#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8005#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8004#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8002#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7999#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7993#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7985#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7984#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7981#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7969#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7968#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7966#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7965#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7960#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7959#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7958#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7956#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7954#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7953#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7945#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7934#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7930#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7926#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7924#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7923#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7918#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7906#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7913#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7911#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7909#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 7905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 7903#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 7902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7900#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 7899#L12-1 [2021-10-28 23:41:23,542 INFO L793 eck$LassoCheckResult]: Loop: 7899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 7898#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 7899#L12-1 [2021-10-28 23:41:23,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:23,542 INFO L85 PathProgramCache]: Analyzing trace with hash -20877514, now seen corresponding path program 10 times [2021-10-28 23:41:23,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:23,543 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603296531] [2021-10-28 23:41:23,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:23,543 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:23,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:23,674 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 1426 proven. 444 refuted. 0 times theorem prover too weak. 925 trivial. 0 not checked. [2021-10-28 23:41:23,674 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:23,674 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603296531] [2021-10-28 23:41:23,675 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1603296531] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:23,675 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [729189123] [2021-10-28 23:41:23,675 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:41:23,676 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:23,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:23,679 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:23,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-10-28 23:41:24,210 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:41:24,211 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:24,213 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 25 conjunts are in the unsatisfiable core [2021-10-28 23:41:24,215 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:25,140 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 1765 proven. 420 refuted. 0 times theorem prover too weak. 610 trivial. 0 not checked. [2021-10-28 23:41:25,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [729189123] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:25,141 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:25,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 25] total 34 [2021-10-28 23:41:25,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878743675] [2021-10-28 23:41:25,142 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:25,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:25,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 22 times [2021-10-28 23:41:25,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:25,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660257488] [2021-10-28 23:41:25,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:25,143 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:25,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:25,149 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:25,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:25,151 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:25,168 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:25,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-10-28 23:41:25,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=218, Invalid=904, Unknown=0, NotChecked=0, Total=1122 [2021-10-28 23:41:25,170 INFO L87 Difference]: Start difference. First operand 163 states and 178 transitions. cyclomatic complexity: 19 Second operand has 34 states, 34 states have (on average 3.0588235294117645) internal successors, (104), 34 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:26,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:26,577 INFO L93 Difference]: Finished difference Result 364 states and 412 transitions. [2021-10-28 23:41:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2021-10-28 23:41:26,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 364 states and 412 transitions. [2021-10-28 23:41:26,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:26,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 364 states to 358 states and 406 transitions. [2021-10-28 23:41:26,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-10-28 23:41:26,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-10-28 23:41:26,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 358 states and 406 transitions. [2021-10-28 23:41:26,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:26,585 INFO L681 BuchiCegarLoop]: Abstraction has 358 states and 406 transitions. [2021-10-28 23:41:26,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 358 states and 406 transitions. [2021-10-28 23:41:26,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 358 to 225. [2021-10-28 23:41:26,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.1244444444444444) internal successors, (253), 224 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:26,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 253 transitions. [2021-10-28 23:41:26,593 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 253 transitions. [2021-10-28 23:41:26,593 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 253 transitions. [2021-10-28 23:41:26,593 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-10-28 23:41:26,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 253 transitions. [2021-10-28 23:41:26,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:26,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:26,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:26,598 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [59, 58, 48, 10, 1, 1] [2021-10-28 23:41:26,599 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:26,599 INFO L791 eck$LassoCheckResult]: Stem: 9006#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 8999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9007#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9004#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9223#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9222#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9221#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9220#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9219#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9218#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9217#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9216#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9215#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9214#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9213#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9212#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9211#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9210#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9209#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9208#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9206#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9205#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9204#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9203#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9202#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9201#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9199#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9198#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9197#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9196#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9195#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9194#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9193#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9192#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9191#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9190#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9189#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9188#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9187#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9184#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9183#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9181#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9179#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9178#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9177#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9176#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9175#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9174#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9173#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9172#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9171#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9170#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9169#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9168#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9167#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9166#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9165#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9164#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9163#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9162#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9149#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9147#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9130#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9110#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9060#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9129#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9128#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9099#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9094#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9093#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9092#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9091#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9090#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9087#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9079#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9078#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9076#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9073#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9070#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9069#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9067#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9057#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9052#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9042#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9040#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9036#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9030#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9021#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9015#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9009#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 9011#L12-1 [2021-10-28 23:41:26,600 INFO L793 eck$LassoCheckResult]: Loop: 9011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9013#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 9011#L12-1 [2021-10-28 23:41:26,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:26,600 INFO L85 PathProgramCache]: Analyzing trace with hash 1405044931, now seen corresponding path program 11 times [2021-10-28 23:41:26,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:26,601 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990666730] [2021-10-28 23:41:26,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:26,601 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:26,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:26,769 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2496 proven. 513 refuted. 0 times theorem prover too weak. 2066 trivial. 0 not checked. [2021-10-28 23:41:26,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:26,770 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990666730] [2021-10-28 23:41:26,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990666730] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:26,770 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2027685662] [2021-10-28 23:41:26,770 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:26,770 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:26,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:26,772 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:26,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-10-28 23:41:27,266 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2021-10-28 23:41:27,266 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:27,267 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 23:41:27,269 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:28,125 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 3360 proven. 248 refuted. 0 times theorem prover too weak. 1467 trivial. 0 not checked. [2021-10-28 23:41:28,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2027685662] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:28,125 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:28,126 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 18] total 28 [2021-10-28 23:41:28,126 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941062938] [2021-10-28 23:41:28,126 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:28,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:28,127 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 23 times [2021-10-28 23:41:28,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:28,127 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435771468] [2021-10-28 23:41:28,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:28,128 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:28,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:28,136 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:28,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:28,137 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:28,157 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:28,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-10-28 23:41:28,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=616, Unknown=0, NotChecked=0, Total=756 [2021-10-28 23:41:28,159 INFO L87 Difference]: Start difference. First operand 225 states and 253 transitions. cyclomatic complexity: 32 Second operand has 28 states, 28 states have (on average 3.142857142857143) internal successors, (88), 28 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:28,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:28,738 INFO L93 Difference]: Finished difference Result 275 states and 304 transitions. [2021-10-28 23:41:28,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-10-28 23:41:28,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 275 states and 304 transitions. [2021-10-28 23:41:28,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:28,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 275 states to 271 states and 298 transitions. [2021-10-28 23:41:28,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:28,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:28,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 298 transitions. [2021-10-28 23:41:28,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:28,744 INFO L681 BuchiCegarLoop]: Abstraction has 271 states and 298 transitions. [2021-10-28 23:41:28,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 298 transitions. [2021-10-28 23:41:28,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 249. [2021-10-28 23:41:28,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 249 states have (on average 1.108433734939759) internal successors, (276), 248 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:28,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 276 transitions. [2021-10-28 23:41:28,750 INFO L704 BuchiCegarLoop]: Abstraction has 249 states and 276 transitions. [2021-10-28 23:41:28,750 INFO L587 BuchiCegarLoop]: Abstraction has 249 states and 276 transitions. [2021-10-28 23:41:28,750 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-10-28 23:41:28,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 249 states and 276 transitions. [2021-10-28 23:41:28,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:28,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:28,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:28,755 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [60, 59, 49, 10, 1, 1] [2021-10-28 23:41:28,755 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:28,756 INFO L791 eck$LassoCheckResult]: Stem: 10112#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 10107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10114#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10355#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10115#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10110#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10354#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10353#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10351#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10348#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10347#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10346#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10345#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10342#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10341#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10340#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10339#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10336#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10333#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10332#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10330#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10329#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10328#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10327#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10326#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10325#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10324#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10323#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10322#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10319#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10317#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10316#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10315#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10312#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10310#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10300#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10239#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10292#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10291#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10290#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10289#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10288#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10287#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10286#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10285#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10284#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10283#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10282#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10281#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10280#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10279#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10278#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10277#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10276#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10275#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10274#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10273#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10272#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10268#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10234#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10232#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10231#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10227#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10228#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10224#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10219#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10215#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10216#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10212#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10203#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10204#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10195#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10196#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10189#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10187#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10186#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10184#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10183#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10181#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10179#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10178#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10177#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10176#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10175#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10171#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10154#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10169#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10170#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10167#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10166#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10165#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10164#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10163#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10162#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10160#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10159#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10158#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10157#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10156#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10155#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10153#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10151#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10150#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10148#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10147#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10146#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10145#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10144#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10133#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10140#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10139#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10138#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10137#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10136#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10135#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10127#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10132#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10131#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10130#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10128#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10120#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10126#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10125#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10124#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10123#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10117#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 10119#L12-1 [2021-10-28 23:41:28,756 INFO L793 eck$LassoCheckResult]: Loop: 10119#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10121#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 10119#L12-1 [2021-10-28 23:41:28,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:28,757 INFO L85 PathProgramCache]: Analyzing trace with hash -1282551758, now seen corresponding path program 12 times [2021-10-28 23:41:28,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:28,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035266371] [2021-10-28 23:41:28,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:28,757 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:28,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:28,918 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 2418 proven. 1716 refuted. 0 times theorem prover too weak. 1117 trivial. 0 not checked. [2021-10-28 23:41:28,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:28,919 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1035266371] [2021-10-28 23:41:28,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1035266371] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:28,919 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1957412186] [2021-10-28 23:41:28,919 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:28,919 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:28,920 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:28,923 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:28,924 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-10-28 23:41:29,473 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 24 check-sat command(s) [2021-10-28 23:41:29,474 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:29,475 INFO L263 TraceCheckSpWp]: Trace formula consists of 168 conjuncts, 13 conjunts are in the unsatisfiable core [2021-10-28 23:41:29,477 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:30,188 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 2600 proven. 585 refuted. 0 times theorem prover too weak. 2066 trivial. 0 not checked. [2021-10-28 23:41:30,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1957412186] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:30,188 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:30,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 20 [2021-10-28 23:41:30,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885255453] [2021-10-28 23:41:30,190 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:30,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:30,190 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 24 times [2021-10-28 23:41:30,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:30,190 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117434517] [2021-10-28 23:41:30,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:30,191 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:30,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:30,198 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:30,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:30,200 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:30,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:30,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-10-28 23:41:30,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=273, Unknown=0, NotChecked=0, Total=420 [2021-10-28 23:41:30,217 INFO L87 Difference]: Start difference. First operand 249 states and 276 transitions. cyclomatic complexity: 32 Second operand has 21 states, 21 states have (on average 3.1904761904761907) internal successors, (67), 20 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:30,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:30,513 INFO L93 Difference]: Finished difference Result 366 states and 403 transitions. [2021-10-28 23:41:30,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-10-28 23:41:30,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 403 transitions. [2021-10-28 23:41:30,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:30,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 362 states and 398 transitions. [2021-10-28 23:41:30,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:30,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:30,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 398 transitions. [2021-10-28 23:41:30,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:30,524 INFO L681 BuchiCegarLoop]: Abstraction has 362 states and 398 transitions. [2021-10-28 23:41:30,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 398 transitions. [2021-10-28 23:41:30,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 333. [2021-10-28 23:41:30,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 333 states, 333 states have (on average 1.105105105105105) internal successors, (368), 332 states have internal predecessors, (368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:30,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 333 states to 333 states and 368 transitions. [2021-10-28 23:41:30,533 INFO L704 BuchiCegarLoop]: Abstraction has 333 states and 368 transitions. [2021-10-28 23:41:30,533 INFO L587 BuchiCegarLoop]: Abstraction has 333 states and 368 transitions. [2021-10-28 23:41:30,535 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-10-28 23:41:30,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 333 states and 368 transitions. [2021-10-28 23:41:30,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:30,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:30,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:30,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [62, 61, 51, 10, 1, 1] [2021-10-28 23:41:30,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:30,542 INFO L791 eck$LassoCheckResult]: Stem: 11320#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 11321#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11322#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11323#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11570#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11556#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11554#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11550#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11548#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11545#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11544#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11543#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11542#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11540#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11539#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11538#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11537#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11536#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11535#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11534#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11533#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11532#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11531#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11528#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11527#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11526#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11525#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11524#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11523#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11522#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11521#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11520#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11519#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11518#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11517#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11516#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11515#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11514#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11513#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11512#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11511#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11510#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11509#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11508#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11507#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11506#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11504#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11503#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11502#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11499#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11497#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11496#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11495#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11494#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11488#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11486#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11482#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11480#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11476#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11470#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11464#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11459#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11458#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11460#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11595#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11592#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11591#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11589#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11586#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11583#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11398#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11399#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11395#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11393#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11391#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11390#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11387#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11381#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11374#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11373#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11371#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11368#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11366#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11365#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11360#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11359#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11358#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11356#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11355#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11354#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11353#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11352#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11351#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11340#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11350#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11348#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11347#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11346#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11345#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11344#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11343#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11342#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11339#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11338#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11337#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11336#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11335#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11326#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 11333#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11332#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 11331#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 11329#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11324#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 11313#L12-1 [2021-10-28 23:41:30,542 INFO L793 eck$LassoCheckResult]: Loop: 11313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 11314#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 11313#L12-1 [2021-10-28 23:41:30,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:30,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1433360102, now seen corresponding path program 13 times [2021-10-28 23:41:30,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:30,543 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911969571] [2021-10-28 23:41:30,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:30,544 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:30,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:30,761 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2822 proven. 1233 refuted. 0 times theorem prover too weak. 1557 trivial. 0 not checked. [2021-10-28 23:41:30,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:30,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911969571] [2021-10-28 23:41:30,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911969571] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:30,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1091790314] [2021-10-28 23:41:30,762 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:41:30,763 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:30,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:30,767 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:30,786 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-10-28 23:41:31,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:31,699 INFO L263 TraceCheckSpWp]: Trace formula consists of 408 conjuncts, 18 conjunts are in the unsatisfiable core [2021-10-28 23:41:31,703 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:32,599 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2192 proven. 360 refuted. 0 times theorem prover too weak. 3060 trivial. 0 not checked. [2021-10-28 23:41:32,599 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1091790314] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:32,599 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:32,600 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 17] total 27 [2021-10-28 23:41:32,600 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429166075] [2021-10-28 23:41:32,600 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:32,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:32,601 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 25 times [2021-10-28 23:41:32,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:32,601 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876752577] [2021-10-28 23:41:32,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:32,601 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:32,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:32,606 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:32,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:32,607 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:32,630 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:32,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-10-28 23:41:32,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=485, Unknown=0, NotChecked=0, Total=756 [2021-10-28 23:41:32,631 INFO L87 Difference]: Start difference. First operand 333 states and 368 transitions. cyclomatic complexity: 41 Second operand has 28 states, 28 states have (on average 3.107142857142857) internal successors, (87), 27 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:32,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:32,819 INFO L93 Difference]: Finished difference Result 324 states and 358 transitions. [2021-10-28 23:41:32,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-10-28 23:41:32,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 324 states and 358 transitions. [2021-10-28 23:41:32,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:32,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 324 states to 320 states and 354 transitions. [2021-10-28 23:41:32,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:32,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:32,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 320 states and 354 transitions. [2021-10-28 23:41:32,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:32,825 INFO L681 BuchiCegarLoop]: Abstraction has 320 states and 354 transitions. [2021-10-28 23:41:32,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states and 354 transitions. [2021-10-28 23:41:32,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 318. [2021-10-28 23:41:32,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.1069182389937107) internal successors, (352), 317 states have internal predecessors, (352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:32,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 352 transitions. [2021-10-28 23:41:32,833 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 352 transitions. [2021-10-28 23:41:32,833 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 352 transitions. [2021-10-28 23:41:32,833 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-10-28 23:41:32,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 352 transitions. [2021-10-28 23:41:32,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:32,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:32,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:32,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [64, 63, 53, 10, 1, 1] [2021-10-28 23:41:32,839 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:32,839 INFO L791 eck$LassoCheckResult]: Stem: 12578#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 12579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12580#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12581#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12808#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12789#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12787#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12784#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12785#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12783#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12782#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12781#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12780#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12778#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12777#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12776#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12774#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12773#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12772#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12771#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12770#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12768#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12767#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12766#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12765#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12764#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12762#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12761#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12760#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12759#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12758#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12756#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12755#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12753#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12752#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12751#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12750#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12749#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12748#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12747#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12746#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12745#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12740#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12736#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12734#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12722#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12718#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12714#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12712#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12683#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12665#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12653#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12647#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12641#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12634#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12633#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12630#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12628#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12627#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12625#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12624#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12623#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12620#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12619#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12618#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12616#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12615#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12613#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12612#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12611#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12608#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12607#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12606#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12603#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12601#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12597#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12586#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 12593#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12592#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 12591#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 12589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12584#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 12572#L12-1 [2021-10-28 23:41:32,840 INFO L793 eck$LassoCheckResult]: Loop: 12572#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 12573#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 12572#L12-1 [2021-10-28 23:41:32,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:32,840 INFO L85 PathProgramCache]: Analyzing trace with hash -2129101710, now seen corresponding path program 14 times [2021-10-28 23:41:32,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:32,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535982612] [2021-10-28 23:41:32,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:32,841 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:32,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:33,041 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2666 proven. 2106 refuted. 0 times theorem prover too weak. 1213 trivial. 0 not checked. [2021-10-28 23:41:33,042 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:33,042 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535982612] [2021-10-28 23:41:33,042 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535982612] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:33,043 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1252644624] [2021-10-28 23:41:33,043 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:41:33,043 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:33,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:33,054 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:33,070 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-10-28 23:41:34,132 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:41:34,132 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:34,135 INFO L263 TraceCheckSpWp]: Trace formula consists of 420 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 23:41:34,138 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:34,970 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2380 proven. 408 refuted. 0 times theorem prover too weak. 3197 trivial. 0 not checked. [2021-10-28 23:41:34,971 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1252644624] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:34,971 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:34,971 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 18] total 28 [2021-10-28 23:41:34,971 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044061142] [2021-10-28 23:41:34,971 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:34,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:34,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 26 times [2021-10-28 23:41:34,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:34,972 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266825359] [2021-10-28 23:41:34,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:34,973 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:34,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:34,981 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:34,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:34,982 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:35,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:35,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-10-28 23:41:35,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=513, Unknown=0, NotChecked=0, Total=812 [2021-10-28 23:41:35,012 INFO L87 Difference]: Start difference. First operand 318 states and 352 transitions. cyclomatic complexity: 40 Second operand has 29 states, 29 states have (on average 3.1379310344827585) internal successors, (91), 28 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:35,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:35,282 INFO L93 Difference]: Finished difference Result 356 states and 391 transitions. [2021-10-28 23:41:35,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-10-28 23:41:35,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 356 states and 391 transitions. [2021-10-28 23:41:35,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:35,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 356 states to 352 states and 387 transitions. [2021-10-28 23:41:35,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-10-28 23:41:35,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-10-28 23:41:35,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 352 states and 387 transitions. [2021-10-28 23:41:35,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:35,289 INFO L681 BuchiCegarLoop]: Abstraction has 352 states and 387 transitions. [2021-10-28 23:41:35,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 352 states and 387 transitions. [2021-10-28 23:41:35,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 352 to 285. [2021-10-28 23:41:35,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 285 states, 285 states have (on average 1.0982456140350878) internal successors, (313), 284 states have internal predecessors, (313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:35,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285 states to 285 states and 313 transitions. [2021-10-28 23:41:35,296 INFO L704 BuchiCegarLoop]: Abstraction has 285 states and 313 transitions. [2021-10-28 23:41:35,296 INFO L587 BuchiCegarLoop]: Abstraction has 285 states and 313 transitions. [2021-10-28 23:41:35,296 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-10-28 23:41:35,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 285 states and 313 transitions. [2021-10-28 23:41:35,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:35,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:35,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:35,301 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [72, 71, 60, 11, 1, 1] [2021-10-28 23:41:35,302 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:35,302 INFO L791 eck$LassoCheckResult]: Stem: 13884#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 13885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13887#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13882#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14161#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14160#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14159#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14158#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14157#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14156#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14155#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14154#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14153#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14152#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14151#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14150#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14149#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14148#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14147#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14146#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14145#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14144#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14143#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14141#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14140#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14139#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14138#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14137#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14136#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14135#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14134#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14133#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14132#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14131#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14130#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14129#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14128#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14127#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14126#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14125#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14124#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14123#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14122#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14121#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14119#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14118#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14117#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14116#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14115#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14114#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14113#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14112#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14111#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14110#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14109#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14108#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14106#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14105#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14104#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14103#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14102#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14099#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14094#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14093#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14092#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14091#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14087#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14086#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14085#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14084#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14082#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14081#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14079#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14078#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14076#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14073#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14070#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14069#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14067#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14064#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14063#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14061#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14058#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14054#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14048#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14008#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14010#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14000#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13991#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13987#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13988#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13984#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13974#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13966#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13961#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13958#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13952#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13947#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13941#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13938#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13932#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13929#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13914#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13924#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13923#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13920#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13911#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13904#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13903#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13902#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13900#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 13898#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13897#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 13896#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 13894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13889#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 13879#L12-1 [2021-10-28 23:41:35,303 INFO L793 eck$LassoCheckResult]: Loop: 13879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 13880#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 13879#L12-1 [2021-10-28 23:41:35,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:35,303 INFO L85 PathProgramCache]: Analyzing trace with hash 2068451124, now seen corresponding path program 15 times [2021-10-28 23:41:35,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:35,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726136227] [2021-10-28 23:41:35,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:35,304 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:35,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:35,653 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 4222 proven. 2368 refuted. 0 times theorem prover too weak. 1007 trivial. 0 not checked. [2021-10-28 23:41:35,653 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:35,654 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726136227] [2021-10-28 23:41:35,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726136227] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:35,656 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1088353099] [2021-10-28 23:41:35,656 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:41:35,656 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:35,657 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:35,659 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:35,674 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-10-28 23:41:36,449 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 41 check-sat command(s) [2021-10-28 23:41:36,449 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:36,451 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 15 conjunts are in the unsatisfiable core [2021-10-28 23:41:36,454 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:37,137 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 4111 proven. 411 refuted. 0 times theorem prover too weak. 3075 trivial. 0 not checked. [2021-10-28 23:41:37,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1088353099] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:37,137 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:37,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 14] total 35 [2021-10-28 23:41:37,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051468727] [2021-10-28 23:41:37,141 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:37,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:37,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 27 times [2021-10-28 23:41:37,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:37,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409021234] [2021-10-28 23:41:37,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:37,142 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:37,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:37,180 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:37,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:37,182 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:37,194 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:37,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-10-28 23:41:37,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=1035, Unknown=0, NotChecked=0, Total=1190 [2021-10-28 23:41:37,199 INFO L87 Difference]: Start difference. First operand 285 states and 313 transitions. cyclomatic complexity: 34 Second operand has 35 states, 35 states have (on average 3.2285714285714286) internal successors, (113), 35 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:39,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:39,174 INFO L93 Difference]: Finished difference Result 510 states and 539 transitions. [2021-10-28 23:41:39,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2021-10-28 23:41:39,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 539 transitions. [2021-10-28 23:41:39,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:39,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 476 states and 504 transitions. [2021-10-28 23:41:39,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-10-28 23:41:39,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60 [2021-10-28 23:41:39,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 476 states and 504 transitions. [2021-10-28 23:41:39,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:39,190 INFO L681 BuchiCegarLoop]: Abstraction has 476 states and 504 transitions. [2021-10-28 23:41:39,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 476 states and 504 transitions. [2021-10-28 23:41:39,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 476 to 225. [2021-10-28 23:41:39,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.0355555555555556) internal successors, (233), 224 states have internal predecessors, (233), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:39,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 233 transitions. [2021-10-28 23:41:39,196 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 233 transitions. [2021-10-28 23:41:39,196 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 233 transitions. [2021-10-28 23:41:39,196 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-10-28 23:41:39,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 233 transitions. [2021-10-28 23:41:39,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:39,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:39,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:39,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [72, 72, 61, 11, 1] [2021-10-28 23:41:39,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:39,201 INFO L791 eck$LassoCheckResult]: Stem: 15502#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 15494#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15496#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15503#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15504#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15497#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15706#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15705#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15703#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15701#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15699#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15698#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15696#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15693#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15682#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15677#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15671#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15647#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15641#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15626#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15615#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15611#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15586#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15583#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15574#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15572#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15571#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15541#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15566#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15556#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15554#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15543#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15538#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15506#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15507#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15505#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15553#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15552#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15551#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15550#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15549#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15548#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15542#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15537#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15536#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15535#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15534#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15533#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15532#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15531#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15530#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15529#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15528#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15527#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15526#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15525#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15524#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15523#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15522#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15521#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15520#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15519#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15517#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15516#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 15512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 15510#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 15509#L12-1 [2021-10-28 23:41:39,201 INFO L793 eck$LassoCheckResult]: Loop: 15509#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 15508#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 15509#L12-1 [2021-10-28 23:41:39,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:39,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1117603618, now seen corresponding path program 18 times [2021-10-28 23:41:39,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:39,202 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803150010] [2021-10-28 23:41:39,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:39,203 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:39,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:39,391 INFO L134 CoverageAnalysis]: Checked inductivity of 7668 backedges. 3696 proven. 726 refuted. 0 times theorem prover too weak. 3246 trivial. 0 not checked. [2021-10-28 23:41:39,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:39,391 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803150010] [2021-10-28 23:41:39,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803150010] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:39,392 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1145196259] [2021-10-28 23:41:39,392 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:39,392 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:39,392 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:39,398 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:39,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-10-28 23:41:40,155 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 36 check-sat command(s) [2021-10-28 23:41:40,155 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:40,157 INFO L263 TraceCheckSpWp]: Trace formula consists of 243 conjuncts, 14 conjunts are in the unsatisfiable core [2021-10-28 23:41:40,160 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:40,919 INFO L134 CoverageAnalysis]: Checked inductivity of 7668 backedges. 3696 proven. 726 refuted. 0 times theorem prover too weak. 3246 trivial. 0 not checked. [2021-10-28 23:41:40,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1145196259] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:40,920 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:40,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 23 [2021-10-28 23:41:40,920 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061737602] [2021-10-28 23:41:40,921 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:40,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:40,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 28 times [2021-10-28 23:41:40,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:40,922 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507215701] [2021-10-28 23:41:40,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:40,922 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:40,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:40,930 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:40,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:40,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:40,947 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:40,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-10-28 23:41:40,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=191, Invalid=361, Unknown=0, NotChecked=0, Total=552 [2021-10-28 23:41:40,948 INFO L87 Difference]: Start difference. First operand 225 states and 233 transitions. cyclomatic complexity: 12 Second operand has 24 states, 24 states have (on average 3.0416666666666665) internal successors, (73), 23 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:41,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:41,197 INFO L93 Difference]: Finished difference Result 262 states and 271 transitions. [2021-10-28 23:41:41,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-10-28 23:41:41,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 262 states and 271 transitions. [2021-10-28 23:41:41,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:41,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 262 states to 260 states and 269 transitions. [2021-10-28 23:41:41,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:41:41,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:41:41,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 260 states and 269 transitions. [2021-10-28 23:41:41,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:41,200 INFO L681 BuchiCegarLoop]: Abstraction has 260 states and 269 transitions. [2021-10-28 23:41:41,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states and 269 transitions. [2021-10-28 23:41:41,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 258. [2021-10-28 23:41:41,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 258 states, 258 states have (on average 1.0348837209302326) internal successors, (267), 257 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:41,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 267 transitions. [2021-10-28 23:41:41,204 INFO L704 BuchiCegarLoop]: Abstraction has 258 states and 267 transitions. [2021-10-28 23:41:41,204 INFO L587 BuchiCegarLoop]: Abstraction has 258 states and 267 transitions. [2021-10-28 23:41:41,205 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-10-28 23:41:41,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 258 states and 267 transitions. [2021-10-28 23:41:41,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:41,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:41,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:41,210 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [83, 83, 71, 12, 1] [2021-10-28 23:41:41,210 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:41,211 INFO L791 eck$LassoCheckResult]: Stem: 16682#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 16683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16686#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16688#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16934#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16926#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16924#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16923#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16918#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16912#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16911#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16900#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16891#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16889#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16888#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16882#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16879#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16878#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16876#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16873#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16871#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16870#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16869#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16867#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16864#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16863#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16861#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16799#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16859#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16857#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16856#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16854#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16853#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16851#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16849#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16848#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16847#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16845#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16843#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16842#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16841#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16839#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16837#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16835#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16833#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16830#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16829#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16826#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16808#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16804#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16802#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16774#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16800#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16796#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16789#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16787#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16785#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16784#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16783#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16782#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16781#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16780#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16778#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16777#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16776#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16772#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16771#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16770#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16769#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16766#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16764#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16763#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16762#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16760#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16759#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16758#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16757#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16756#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16754#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16753#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16752#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16751#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16750#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16749#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16748#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16747#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16746#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16745#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16742#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16738#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16736#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16734#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16732#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16730#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16728#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16689#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16678#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16741#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16737#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16735#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16729#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16724#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16722#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16721#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16717#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16716#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16715#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16714#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16713#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16712#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16711#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16710#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16709#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16708#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16707#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16704#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16701#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 16697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 16695#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 16691#L12-1 [2021-10-28 23:41:41,211 INFO L793 eck$LassoCheckResult]: Loop: 16691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 16690#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 16691#L12-1 [2021-10-28 23:41:41,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:41,212 INFO L85 PathProgramCache]: Analyzing trace with hash 127539371, now seen corresponding path program 19 times [2021-10-28 23:41:41,212 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:41,212 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947907088] [2021-10-28 23:41:41,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:41,212 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:41,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:41,446 INFO L134 CoverageAnalysis]: Checked inductivity of 10209 backedges. 4698 proven. 810 refuted. 0 times theorem prover too weak. 4701 trivial. 0 not checked. [2021-10-28 23:41:41,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:41,446 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947907088] [2021-10-28 23:41:41,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947907088] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:41,447 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1940960658] [2021-10-28 23:41:41,447 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:41:41,447 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:41,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:41,458 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:41,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-10-28 23:41:42,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:42,495 INFO L263 TraceCheckSpWp]: Trace formula consists of 540 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 23:41:42,499 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:43,407 INFO L134 CoverageAnalysis]: Checked inductivity of 10209 backedges. 3510 proven. 459 refuted. 0 times theorem prover too weak. 6240 trivial. 0 not checked. [2021-10-28 23:41:43,407 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1940960658] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:43,407 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:43,407 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 19] total 31 [2021-10-28 23:41:43,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879965261] [2021-10-28 23:41:43,408 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:43,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:43,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 29 times [2021-10-28 23:41:43,409 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:43,409 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683978108] [2021-10-28 23:41:43,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:43,409 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:43,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:43,419 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:43,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:43,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:43,441 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:43,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-10-28 23:41:43,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=347, Invalid=645, Unknown=0, NotChecked=0, Total=992 [2021-10-28 23:41:43,442 INFO L87 Difference]: Start difference. First operand 258 states and 267 transitions. cyclomatic complexity: 14 Second operand has 32 states, 32 states have (on average 3.03125) internal successors, (97), 31 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:43,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:43,569 INFO L93 Difference]: Finished difference Result 272 states and 281 transitions. [2021-10-28 23:41:43,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-10-28 23:41:43,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 272 states and 281 transitions. [2021-10-28 23:41:43,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:43,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 272 states to 268 states and 277 transitions. [2021-10-28 23:41:43,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:41:43,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:41:43,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 268 states and 277 transitions. [2021-10-28 23:41:43,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:43,575 INFO L681 BuchiCegarLoop]: Abstraction has 268 states and 277 transitions. [2021-10-28 23:41:43,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states and 277 transitions. [2021-10-28 23:41:43,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 264. [2021-10-28 23:41:43,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 264 states, 264 states have (on average 1.0340909090909092) internal successors, (273), 263 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:43,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 273 transitions. [2021-10-28 23:41:43,580 INFO L704 BuchiCegarLoop]: Abstraction has 264 states and 273 transitions. [2021-10-28 23:41:43,580 INFO L587 BuchiCegarLoop]: Abstraction has 264 states and 273 transitions. [2021-10-28 23:41:43,580 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-10-28 23:41:43,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 264 states and 273 transitions. [2021-10-28 23:41:43,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:43,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:43,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:43,587 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [85, 85, 73, 12, 1] [2021-10-28 23:41:43,587 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:43,587 INFO L791 eck$LassoCheckResult]: Stem: 17997#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 17998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 17999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 17996#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 17992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 17993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18253#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18252#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18251#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18249#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18247#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18246#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18245#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18243#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18242#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18241#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18238#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18237#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18235#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18234#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18231#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18229#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18228#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18225#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18224#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18219#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18218#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18206#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18203#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18171#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18170#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18169#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18168#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18167#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18166#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18165#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18164#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18163#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18161#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18160#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18159#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18158#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18157#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18156#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18155#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18154#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18153#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18152#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18151#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18150#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18149#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18148#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18147#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18146#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18145#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18144#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18143#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18141#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18140#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18139#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18138#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18137#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18136#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18135#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18134#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18133#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18132#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18131#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18130#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18129#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18128#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18127#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18126#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18125#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18124#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18123#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18122#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18121#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18120#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18119#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18118#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18114#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18086#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18112#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18113#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18109#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18108#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18106#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18105#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18104#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18103#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18102#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18099#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18094#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18093#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18092#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18091#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18090#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18087#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18083#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18068#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18064#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18063#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18057#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18054#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18042#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18001#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 17990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 17991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 17994#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 17995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18034#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18030#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18026#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18024#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18022#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18018#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18013#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18012#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 18009#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18008#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 18007#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 18003#L12-1 [2021-10-28 23:41:43,588 INFO L793 eck$LassoCheckResult]: Loop: 18003#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 18002#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 18003#L12-1 [2021-10-28 23:41:43,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:43,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1795556039, now seen corresponding path program 20 times [2021-10-28 23:41:43,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:43,589 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256100741] [2021-10-28 23:41:43,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:43,589 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:43,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:43,819 INFO L134 CoverageAnalysis]: Checked inductivity of 10710 backedges. 5412 proven. 1803 refuted. 0 times theorem prover too weak. 3495 trivial. 0 not checked. [2021-10-28 23:41:43,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:43,819 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256100741] [2021-10-28 23:41:43,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256100741] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:43,820 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1254530804] [2021-10-28 23:41:43,820 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:41:43,820 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:43,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:43,823 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:43,837 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-10-28 23:41:44,951 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:41:44,951 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:44,953 INFO L263 TraceCheckSpWp]: Trace formula consists of 552 conjuncts, 21 conjunts are in the unsatisfiable core [2021-10-28 23:41:44,956 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:45,884 INFO L134 CoverageAnalysis]: Checked inductivity of 10710 backedges. 3762 proven. 513 refuted. 0 times theorem prover too weak. 6435 trivial. 0 not checked. [2021-10-28 23:41:45,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1254530804] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:45,884 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:45,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 20] total 32 [2021-10-28 23:41:45,885 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369478919] [2021-10-28 23:41:45,885 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:45,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:45,886 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 30 times [2021-10-28 23:41:45,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:45,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111066087] [2021-10-28 23:41:45,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:45,886 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:45,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:45,897 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:45,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:45,899 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:45,915 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:45,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-10-28 23:41:45,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=375, Invalid=681, Unknown=0, NotChecked=0, Total=1056 [2021-10-28 23:41:45,916 INFO L87 Difference]: Start difference. First operand 264 states and 273 transitions. cyclomatic complexity: 14 Second operand has 33 states, 33 states have (on average 3.0606060606060606) internal successors, (101), 32 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:46,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:46,248 INFO L93 Difference]: Finished difference Result 308 states and 318 transitions. [2021-10-28 23:41:46,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-10-28 23:41:46,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 318 transitions. [2021-10-28 23:41:46,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:46,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 304 states and 314 transitions. [2021-10-28 23:41:46,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:41:46,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:41:46,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 314 transitions. [2021-10-28 23:41:46,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:46,256 INFO L681 BuchiCegarLoop]: Abstraction has 304 states and 314 transitions. [2021-10-28 23:41:46,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 314 transitions. [2021-10-28 23:41:46,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 300. [2021-10-28 23:41:46,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 300 states, 300 states have (on average 1.0333333333333334) internal successors, (310), 299 states have internal predecessors, (310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:46,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 310 transitions. [2021-10-28 23:41:46,263 INFO L704 BuchiCegarLoop]: Abstraction has 300 states and 310 transitions. [2021-10-28 23:41:46,263 INFO L587 BuchiCegarLoop]: Abstraction has 300 states and 310 transitions. [2021-10-28 23:41:46,263 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-10-28 23:41:46,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 300 states and 310 transitions. [2021-10-28 23:41:46,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:46,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:46,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:46,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [97, 97, 84, 13, 1] [2021-10-28 23:41:46,270 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:46,271 INFO L791 eck$LassoCheckResult]: Stem: 19387#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 19388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19393#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19386#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19677#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19676#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19675#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19674#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19673#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19672#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19671#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19630#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19628#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19627#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19625#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19624#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19623#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19622#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19621#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19620#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19619#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19618#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19616#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19615#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19613#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19612#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19611#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19610#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19609#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19608#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19607#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19606#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19603#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19601#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19600#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19598#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19594#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19593#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19592#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19591#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19590#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19587#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19586#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19585#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19584#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19583#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19582#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19581#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19580#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19579#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19578#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19577#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19576#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19575#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19574#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19573#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19572#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19571#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19570#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19569#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19568#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19567#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19566#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19505#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19562#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19532#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19516#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19515#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19514#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19513#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19512#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19510#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19508#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19480#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19506#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19507#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19503#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19502#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19498#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19495#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19494#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19493#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19491#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19490#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19489#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19487#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19486#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19485#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19483#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19482#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19481#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19477#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19474#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19473#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19471#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19469#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19468#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19467#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19463#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19462#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19461#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19457#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19446#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19442#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19440#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19436#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19431#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19429#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19395#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19390#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19447#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19445#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19441#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19439#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19435#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19433#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19430#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19428#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19416#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19407#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19401#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19397#L12-1 [2021-10-28 23:41:46,271 INFO L793 eck$LassoCheckResult]: Loop: 19397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19396#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 19397#L12-1 [2021-10-28 23:41:46,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:46,272 INFO L85 PathProgramCache]: Analyzing trace with hash 342566413, now seen corresponding path program 21 times [2021-10-28 23:41:46,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:46,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995723869] [2021-10-28 23:41:46,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:46,273 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:46,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:46,495 INFO L134 CoverageAnalysis]: Checked inductivity of 13968 backedges. 6240 proven. 975 refuted. 0 times theorem prover too weak. 6753 trivial. 0 not checked. [2021-10-28 23:41:46,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:46,496 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995723869] [2021-10-28 23:41:46,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995723869] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:46,496 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1691823546] [2021-10-28 23:41:46,496 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:41:46,496 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:46,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:46,503 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:46,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-10-28 23:41:47,576 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 61 check-sat command(s) [2021-10-28 23:41:47,576 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:47,578 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 23:41:47,582 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:48,716 INFO L134 CoverageAnalysis]: Checked inductivity of 13968 backedges. 4620 proven. 570 refuted. 0 times theorem prover too weak. 8778 trivial. 0 not checked. [2021-10-28 23:41:48,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1691823546] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:48,717 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:48,717 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 21] total 34 [2021-10-28 23:41:48,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874219258] [2021-10-28 23:41:48,718 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:48,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:48,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 31 times [2021-10-28 23:41:48,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:48,720 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336945140] [2021-10-28 23:41:48,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:48,720 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:48,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:48,742 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:48,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:48,744 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:48,764 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:48,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-10-28 23:41:48,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=414, Invalid=776, Unknown=0, NotChecked=0, Total=1190 [2021-10-28 23:41:48,766 INFO L87 Difference]: Start difference. First operand 300 states and 310 transitions. cyclomatic complexity: 16 Second operand has 35 states, 35 states have (on average 3.0285714285714285) internal successors, (106), 34 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:48,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:48,939 INFO L93 Difference]: Finished difference Result 314 states and 324 transitions. [2021-10-28 23:41:48,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-10-28 23:41:48,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 324 transitions. [2021-10-28 23:41:48,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:48,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 310 states and 320 transitions. [2021-10-28 23:41:48,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:41:48,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:41:48,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 310 states and 320 transitions. [2021-10-28 23:41:48,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:48,944 INFO L681 BuchiCegarLoop]: Abstraction has 310 states and 320 transitions. [2021-10-28 23:41:48,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states and 320 transitions. [2021-10-28 23:41:48,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 306. [2021-10-28 23:41:48,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306 states, 306 states have (on average 1.0326797385620916) internal successors, (316), 305 states have internal predecessors, (316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:48,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 316 transitions. [2021-10-28 23:41:48,951 INFO L704 BuchiCegarLoop]: Abstraction has 306 states and 316 transitions. [2021-10-28 23:41:48,952 INFO L587 BuchiCegarLoop]: Abstraction has 306 states and 316 transitions. [2021-10-28 23:41:48,952 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-10-28 23:41:48,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306 states and 316 transitions. [2021-10-28 23:41:48,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:48,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:48,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:48,959 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [99, 99, 86, 13, 1] [2021-10-28 23:41:48,959 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:48,960 INFO L791 eck$LassoCheckResult]: Stem: 20912#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 20913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20918#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21213#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21158#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21156#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21155#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21150#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21149#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21147#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21129#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21128#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21127#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21125#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21122#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21123#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21119#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21107#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21101#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21098#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21097#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21096#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21095#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21092#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21090#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21087#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21086#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21085#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21084#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21082#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21081#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21079#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21078#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21076#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21073#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21070#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21069#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21067#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21064#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21063#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21057#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21052#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21040#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21027#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21024#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21004#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21002#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20999#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20997#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20996#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20993#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20982#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20981#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20976#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20971#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20965#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20963#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20959#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20954#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20920#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20970#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20966#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20962#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20958#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20953#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20948#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20947#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20944#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20942#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20941#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20932#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20929#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20927#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20926#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20922#L12-1 [2021-10-28 23:41:48,960 INFO L793 eck$LassoCheckResult]: Loop: 20922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20921#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 20922#L12-1 [2021-10-28 23:41:48,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:48,961 INFO L85 PathProgramCache]: Analyzing trace with hash -299906519, now seen corresponding path program 22 times [2021-10-28 23:41:48,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:48,961 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473624533] [2021-10-28 23:41:48,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:48,961 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:49,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:49,185 INFO L134 CoverageAnalysis]: Checked inductivity of 14553 backedges. 7290 proven. 2166 refuted. 0 times theorem prover too weak. 5097 trivial. 0 not checked. [2021-10-28 23:41:49,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:49,186 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473624533] [2021-10-28 23:41:49,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473624533] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:49,186 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1477761813] [2021-10-28 23:41:49,186 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:41:49,186 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:49,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:49,189 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:49,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-10-28 23:41:50,251 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:41:50,251 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:50,254 INFO L263 TraceCheckSpWp]: Trace formula consists of 635 conjuncts, 36 conjunts are in the unsatisfiable core [2021-10-28 23:41:50,257 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:51,622 INFO L134 CoverageAnalysis]: Checked inductivity of 14553 backedges. 7242 proven. 1071 refuted. 0 times theorem prover too weak. 6240 trivial. 0 not checked. [2021-10-28 23:41:51,623 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1477761813] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:51,623 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:51,623 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 36] total 49 [2021-10-28 23:41:51,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964409530] [2021-10-28 23:41:51,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:51,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:51,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 32 times [2021-10-28 23:41:51,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:51,624 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299100400] [2021-10-28 23:41:51,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:51,624 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:51,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:51,636 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:51,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:51,637 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:51,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:51,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-10-28 23:41:51,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=512, Invalid=1840, Unknown=0, NotChecked=0, Total=2352 [2021-10-28 23:41:51,663 INFO L87 Difference]: Start difference. First operand 306 states and 316 transitions. cyclomatic complexity: 16 Second operand has 49 states, 49 states have (on average 3.061224489795918) internal successors, (150), 49 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:54,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:54,532 INFO L93 Difference]: Finished difference Result 775 states and 824 transitions. [2021-10-28 23:41:54,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 148 states. [2021-10-28 23:41:54,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 775 states and 824 transitions. [2021-10-28 23:41:54,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:54,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 775 states to 759 states and 808 transitions. [2021-10-28 23:41:54,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2021-10-28 23:41:54,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2021-10-28 23:41:54,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 759 states and 808 transitions. [2021-10-28 23:41:54,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:54,543 INFO L681 BuchiCegarLoop]: Abstraction has 759 states and 808 transitions. [2021-10-28 23:41:54,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 759 states and 808 transitions. [2021-10-28 23:41:54,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 759 to 378. [2021-10-28 23:41:54,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 378 states, 378 states have (on average 1.0582010582010581) internal successors, (400), 377 states have internal predecessors, (400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:54,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 378 states to 378 states and 400 transitions. [2021-10-28 23:41:54,554 INFO L704 BuchiCegarLoop]: Abstraction has 378 states and 400 transitions. [2021-10-28 23:41:54,554 INFO L587 BuchiCegarLoop]: Abstraction has 378 states and 400 transitions. [2021-10-28 23:41:54,554 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-10-28 23:41:54,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 378 states and 400 transitions. [2021-10-28 23:41:54,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:54,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:54,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:54,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [101, 101, 88, 13, 1] [2021-10-28 23:41:54,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:54,560 INFO L791 eck$LassoCheckResult]: Stem: 23310#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 23303#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23311#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23677#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23676#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23675#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23674#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23673#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23672#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23671#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23634#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23633#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23630#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23628#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23627#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23568#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23622#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23609#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23608#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23607#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23606#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23605#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23604#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23603#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23602#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23601#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23600#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23599#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23598#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23597#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23584#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23574#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23571#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23566#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23565#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23562#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23508#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23504#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23505#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23479#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23478#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23477#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23476#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23475#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23448#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23445#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23428#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23426#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23354#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23427#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23425#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23419#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23418#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23416#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23415#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23368#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23366#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23365#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23362#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23361#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23360#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23359#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23358#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23356#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23355#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23353#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23351#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23348#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23347#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23346#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23345#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23342#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23341#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23340#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23339#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23336#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23334#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23333#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23332#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23331#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23330#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23329#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23328#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23327#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23326#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23325#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23324#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23323#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23322#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23321#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23320#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23319#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23318#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23317#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23316#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23307#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23410#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23408#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23407#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23406#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23405#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23404#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23403#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23402#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23401#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23400#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23399#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23398#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23397#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23395#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23394#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23390#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23389#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23388#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23386#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23385#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23383#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23382#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23381#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23380#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23379#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23378#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23377#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 23375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23374#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 23371#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 23372#L12-1 [2021-10-28 23:41:54,560 INFO L793 eck$LassoCheckResult]: Loop: 23372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 23373#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 23372#L12-1 [2021-10-28 23:41:54,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:54,561 INFO L85 PathProgramCache]: Analyzing trace with hash -770433595, now seen corresponding path program 23 times [2021-10-28 23:41:54,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:54,561 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853887162] [2021-10-28 23:41:54,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:54,562 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:54,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:54,822 INFO L134 CoverageAnalysis]: Checked inductivity of 15150 backedges. 7524 proven. 3747 refuted. 0 times theorem prover too weak. 3879 trivial. 0 not checked. [2021-10-28 23:41:54,822 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:54,822 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853887162] [2021-10-28 23:41:54,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853887162] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:54,822 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1643734174] [2021-10-28 23:41:54,822 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:41:54,823 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:54,823 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:54,825 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:54,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-10-28 23:41:56,043 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2021-10-28 23:41:56,043 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:41:56,044 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 25 conjunts are in the unsatisfiable core [2021-10-28 23:41:56,047 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:41:57,048 INFO L134 CoverageAnalysis]: Checked inductivity of 15150 backedges. 10010 proven. 517 refuted. 0 times theorem prover too weak. 4623 trivial. 0 not checked. [2021-10-28 23:41:57,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1643734174] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:57,048 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:41:57,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 25] total 39 [2021-10-28 23:41:57,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636089897] [2021-10-28 23:41:57,049 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:41:57,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:57,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 33 times [2021-10-28 23:41:57,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:57,050 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570829088] [2021-10-28 23:41:57,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:57,050 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:57,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:57,060 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:41:57,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:41:57,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:41:57,076 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:41:57,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-10-28 23:41:57,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=1231, Unknown=0, NotChecked=0, Total=1482 [2021-10-28 23:41:57,080 INFO L87 Difference]: Start difference. First operand 378 states and 400 transitions. cyclomatic complexity: 26 Second operand has 39 states, 39 states have (on average 3.128205128205128) internal successors, (122), 39 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:58,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:41:58,996 INFO L93 Difference]: Finished difference Result 790 states and 846 transitions. [2021-10-28 23:41:58,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2021-10-28 23:41:58,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 790 states and 846 transitions. [2021-10-28 23:41:59,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:59,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 790 states to 786 states and 842 transitions. [2021-10-28 23:41:59,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60 [2021-10-28 23:41:59,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60 [2021-10-28 23:41:59,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 786 states and 842 transitions. [2021-10-28 23:41:59,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:41:59,006 INFO L681 BuchiCegarLoop]: Abstraction has 786 states and 842 transitions. [2021-10-28 23:41:59,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states and 842 transitions. [2021-10-28 23:41:59,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 525. [2021-10-28 23:41:59,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 525 states, 525 states have (on average 1.0704761904761906) internal successors, (562), 524 states have internal predecessors, (562), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:41:59,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 562 transitions. [2021-10-28 23:41:59,017 INFO L704 BuchiCegarLoop]: Abstraction has 525 states and 562 transitions. [2021-10-28 23:41:59,017 INFO L587 BuchiCegarLoop]: Abstraction has 525 states and 562 transitions. [2021-10-28 23:41:59,017 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-10-28 23:41:59,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 525 states and 562 transitions. [2021-10-28 23:41:59,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:41:59,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:41:59,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:41:59,023 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [123, 123, 108, 15, 1] [2021-10-28 23:41:59,023 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:41:59,024 INFO L791 eck$LassoCheckResult]: Stem: 25586#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 25580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25591#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 26050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26040#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26036#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26034#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26033#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26030#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26024#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25998#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25995#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25993#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25992#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25991#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25988#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25987#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25982#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25981#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25976#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25973#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25971#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25970#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25966#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25961#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25943#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25941#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25967#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25934#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25933#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25931#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25930#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25928#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25925#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25921#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25920#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25919#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25902#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25896#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25890#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25876#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25874#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25868#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25864#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25862#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25858#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25856#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25854#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25852#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25848#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25846#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25842#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25840#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25834#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25830#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25828#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25824#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25822#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25793#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25792#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25791#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25790#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25789#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25788#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25787#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25786#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25785#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25784#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25783#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25782#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25781#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25780#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25778#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25777#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25776#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25775#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25774#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25772#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25771#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25770#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25769#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25766#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25764#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25760#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25759#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25758#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25757#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25756#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25753#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25752#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25751#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25750#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25749#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25748#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25747#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25746#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25745#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25744#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25743#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25742#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25741#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25740#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25739#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25738#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25737#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25736#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25735#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25734#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25733#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25732#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25730#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25729#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25727#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25726#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25724#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25723#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25722#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25721#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25720#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25719#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25718#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25677#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25703#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25699#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25698#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25696#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25693#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25682#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25674#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25654#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25643#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25594#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25587#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25642#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25634#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25625#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25613#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25609#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25608#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25607#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25606#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25605#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25604#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25603#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25602#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25601#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25600#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25599#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25598#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25597#L12-1 [2021-10-28 23:41:59,024 INFO L793 eck$LassoCheckResult]: Loop: 25597#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25596#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 25597#L12-1 [2021-10-28 23:41:59,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:41:59,025 INFO L85 PathProgramCache]: Analyzing trace with hash 1624880549, now seen corresponding path program 24 times [2021-10-28 23:41:59,025 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:41:59,025 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851859739] [2021-10-28 23:41:59,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:41:59,026 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:41:59,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:41:59,292 INFO L134 CoverageAnalysis]: Checked inductivity of 22509 backedges. 10716 proven. 2400 refuted. 0 times theorem prover too weak. 9393 trivial. 0 not checked. [2021-10-28 23:41:59,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:41:59,292 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851859739] [2021-10-28 23:41:59,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851859739] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:41:59,293 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1004259383] [2021-10-28 23:41:59,293 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:41:59,293 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:41:59,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:41:59,299 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:41:59,318 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-10-28 23:42:00,888 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 82 check-sat command(s) [2021-10-28 23:42:00,888 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:00,890 INFO L263 TraceCheckSpWp]: Trace formula consists of 531 conjuncts, 27 conjunts are in the unsatisfiable core [2021-10-28 23:42:00,893 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:02,035 INFO L134 CoverageAnalysis]: Checked inductivity of 22509 backedges. 15156 proven. 948 refuted. 0 times theorem prover too weak. 6405 trivial. 0 not checked. [2021-10-28 23:42:02,035 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1004259383] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:02,035 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:02,035 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 26] total 41 [2021-10-28 23:42:02,036 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280962932] [2021-10-28 23:42:02,036 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:02,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:02,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 34 times [2021-10-28 23:42:02,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:02,037 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250649775] [2021-10-28 23:42:02,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:02,037 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:02,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:02,047 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:02,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:02,048 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:02,110 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:02,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-10-28 23:42:02,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=283, Invalid=1357, Unknown=0, NotChecked=0, Total=1640 [2021-10-28 23:42:02,112 INFO L87 Difference]: Start difference. First operand 525 states and 562 transitions. cyclomatic complexity: 42 Second operand has 41 states, 41 states have (on average 3.1219512195121952) internal successors, (128), 41 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:03,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:03,520 INFO L93 Difference]: Finished difference Result 739 states and 783 transitions. [2021-10-28 23:42:03,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2021-10-28 23:42:03,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739 states and 783 transitions. [2021-10-28 23:42:03,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:03,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739 states to 612 states and 646 transitions. [2021-10-28 23:42:03,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:03,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:03,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 612 states and 646 transitions. [2021-10-28 23:42:03,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:03,530 INFO L681 BuchiCegarLoop]: Abstraction has 612 states and 646 transitions. [2021-10-28 23:42:03,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 612 states and 646 transitions. [2021-10-28 23:42:03,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 612 to 510. [2021-10-28 23:42:03,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.0549019607843138) internal successors, (538), 509 states have internal predecessors, (538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:03,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 538 transitions. [2021-10-28 23:42:03,542 INFO L704 BuchiCegarLoop]: Abstraction has 510 states and 538 transitions. [2021-10-28 23:42:03,542 INFO L587 BuchiCegarLoop]: Abstraction has 510 states and 538 transitions. [2021-10-28 23:42:03,543 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-10-28 23:42:03,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 538 transitions. [2021-10-28 23:42:03,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:03,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:03,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:03,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [125, 125, 110, 15, 1] [2021-10-28 23:42:03,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:03,551 INFO L791 eck$LassoCheckResult]: Stem: 28137#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 28138#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28139#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28140#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28136#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28132#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28133#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28626#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28617#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28611#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28584#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28581#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28579#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28578#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28577#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28573#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28572#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28570#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28556#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28554#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28550#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28548#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28489#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28488#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28487#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28486#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28483#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28481#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28480#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28477#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28474#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28473#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28471#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28469#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28468#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28467#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28463#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28462#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28461#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28460#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28459#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28458#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28457#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28440#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28456#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28455#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28430#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28429#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28428#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28427#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28426#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28425#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28424#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28423#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28422#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28420#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28418#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28417#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28416#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28415#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28414#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28413#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28412#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28411#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28410#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28409#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28408#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28407#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28406#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28405#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28403#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28402#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28401#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28400#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28399#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28358#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28356#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28398#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28395#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28394#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28393#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28386#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28337#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28332#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28327#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28328#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28324#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28376#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28374#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28317#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28316#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28308#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28304#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28303#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28302#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28301#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28300#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28299#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28296#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28293#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28292#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28290#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28288#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28286#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28284#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28279#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28278#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28276#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28274#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28272#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28270#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28269#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28266#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28265#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28263#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28261#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28260#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28259#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28258#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28256#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28254#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28227#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28252#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28253#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28250#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28249#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28248#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28247#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28246#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28245#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28244#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28243#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28242#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28241#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28240#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28239#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28238#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28237#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28236#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28234#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28233#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28232#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28231#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28230#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28229#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28228#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28225#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28224#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28219#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28218#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28206#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28205#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28204#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28203#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28202#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28201#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28199#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28198#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28197#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28193#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28191#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28187#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28181#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28176#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28142#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28131#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28135#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28196#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28192#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28190#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28186#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28184#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28180#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28175#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28174#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28173#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28172#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28171#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28170#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28169#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28168#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28167#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28166#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28165#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28164#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28163#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28162#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28160#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28159#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28158#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28157#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28156#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28155#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28154#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28153#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28151#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 28150#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 28148#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 28144#L12-1 [2021-10-28 23:42:03,552 INFO L793 eck$LassoCheckResult]: Loop: 28144#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 28143#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 28144#L12-1 [2021-10-28 23:42:03,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:03,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1730656823, now seen corresponding path program 25 times [2021-10-28 23:42:03,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:03,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406196652] [2021-10-28 23:42:03,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:03,553 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:03,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:03,867 INFO L134 CoverageAnalysis]: Checked inductivity of 23250 backedges. 9450 proven. 1215 refuted. 0 times theorem prover too weak. 12585 trivial. 0 not checked. [2021-10-28 23:42:03,868 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:03,868 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406196652] [2021-10-28 23:42:03,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406196652] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:03,868 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [129892338] [2021-10-28 23:42:03,868 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:42:03,869 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:03,869 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:03,875 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:03,898 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-10-28 23:42:05,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:05,357 INFO L263 TraceCheckSpWp]: Trace formula consists of 801 conjuncts, 18 conjunts are in the unsatisfiable core [2021-10-28 23:42:05,360 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:06,475 INFO L134 CoverageAnalysis]: Checked inductivity of 23250 backedges. 9450 proven. 1215 refuted. 0 times theorem prover too weak. 12585 trivial. 0 not checked. [2021-10-28 23:42:06,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [129892338] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:06,476 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:06,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 31 [2021-10-28 23:42:06,476 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785336683] [2021-10-28 23:42:06,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:06,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:06,477 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 35 times [2021-10-28 23:42:06,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:06,478 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235501694] [2021-10-28 23:42:06,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:06,478 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:06,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:06,490 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:06,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:06,492 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:06,506 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:06,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-10-28 23:42:06,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=349, Invalid=643, Unknown=0, NotChecked=0, Total=992 [2021-10-28 23:42:06,507 INFO L87 Difference]: Start difference. First operand 510 states and 538 transitions. cyclomatic complexity: 34 Second operand has 32 states, 32 states have (on average 3.03125) internal successors, (97), 31 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:06,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:06,824 INFO L93 Difference]: Finished difference Result 512 states and 539 transitions. [2021-10-28 23:42:06,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-10-28 23:42:06,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 539 transitions. [2021-10-28 23:42:06,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:06,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 510 states and 537 transitions. [2021-10-28 23:42:06,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:06,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:06,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 510 states and 537 transitions. [2021-10-28 23:42:06,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:06,830 INFO L681 BuchiCegarLoop]: Abstraction has 510 states and 537 transitions. [2021-10-28 23:42:06,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states and 537 transitions. [2021-10-28 23:42:06,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 510. [2021-10-28 23:42:06,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 510 states have (on average 1.0529411764705883) internal successors, (537), 509 states have internal predecessors, (537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:06,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 537 transitions. [2021-10-28 23:42:06,841 INFO L704 BuchiCegarLoop]: Abstraction has 510 states and 537 transitions. [2021-10-28 23:42:06,841 INFO L587 BuchiCegarLoop]: Abstraction has 510 states and 537 transitions. [2021-10-28 23:42:06,841 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-10-28 23:42:06,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 537 transitions. [2021-10-28 23:42:06,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:06,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:06,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:06,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [126, 126, 111, 15, 1] [2021-10-28 23:42:06,848 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:06,849 INFO L791 eck$LassoCheckResult]: Stem: 30346#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 30347#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30351#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30350#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30352#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30851#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30849#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30848#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30847#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30846#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30845#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30843#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30842#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30841#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30840#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30839#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30838#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30837#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30835#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30834#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30833#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30832#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30831#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30830#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30829#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30828#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30827#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30826#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30825#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30824#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30823#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30822#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30821#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30819#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30818#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30817#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30816#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30815#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30814#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30813#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30812#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30811#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30810#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30809#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30808#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30807#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30806#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30805#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30804#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30803#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30802#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30801#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30800#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30798#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30797#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30796#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30795#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30794#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30793#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30792#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30791#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30790#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30789#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30788#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30787#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30786#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30785#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30784#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30783#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30782#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30781#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30780#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30778#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30777#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30776#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30775#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30774#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30772#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30771#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30770#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30769#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30766#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30764#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30763#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30762#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30760#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30759#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30758#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30757#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30756#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30735#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30733#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30731#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30729#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30727#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30725#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30723#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30721#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30717#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30713#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30711#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30707#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30705#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30703#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30699#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30693#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30687#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30683#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30681#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30675#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30673#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30669#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30645#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30640#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30569#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30566#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30560#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30556#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30554#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30550#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30548#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30547#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30543#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30591#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30535#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30536#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30531#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30530#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30528#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30527#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30526#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30522#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30521#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30520#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30519#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30517#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30516#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30510#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30509#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30508#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30507#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30506#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30505#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30504#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30503#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30502#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30499#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30498#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30497#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30496#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30495#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30494#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30493#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30492#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30489#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30488#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30487#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30486#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30483#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30481#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30480#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30477#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30474#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30473#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30471#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30469#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30467#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30460#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30445#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30437#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30436#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30435#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30434#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30433#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30432#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30431#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30430#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30429#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30428#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30427#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30426#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30425#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30424#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30423#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30422#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30420#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30418#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30416#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30415#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30410#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30408#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30406#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30402#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30400#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30353#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30342#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30348#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30407#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30405#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30401#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30399#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30395#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30393#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30386#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30382#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30374#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30373#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30370#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30369#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30368#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30365#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30361#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30359#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30355#L12-1 [2021-10-28 23:42:06,849 INFO L793 eck$LassoCheckResult]: Loop: 30355#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30354#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 30355#L12-1 [2021-10-28 23:42:06,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:06,850 INFO L85 PathProgramCache]: Analyzing trace with hash 632988290, now seen corresponding path program 26 times [2021-10-28 23:42:06,850 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:06,850 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071910019] [2021-10-28 23:42:06,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:06,850 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:06,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:07,212 INFO L134 CoverageAnalysis]: Checked inductivity of 23625 backedges. 11319 proven. 2643 refuted. 0 times theorem prover too weak. 9663 trivial. 0 not checked. [2021-10-28 23:42:07,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:07,212 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071910019] [2021-10-28 23:42:07,213 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071910019] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:07,213 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1765276250] [2021-10-28 23:42:07,213 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:42:07,213 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:07,213 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:07,220 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:07,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-10-28 23:42:08,720 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:42:08,720 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:08,723 INFO L263 TraceCheckSpWp]: Trace formula consists of 807 conjuncts, 19 conjunts are in the unsatisfiable core [2021-10-28 23:42:08,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:09,882 INFO L134 CoverageAnalysis]: Checked inductivity of 23625 backedges. 9720 proven. 1320 refuted. 0 times theorem prover too weak. 12585 trivial. 0 not checked. [2021-10-28 23:42:09,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1765276250] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:09,882 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:09,883 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18] total 32 [2021-10-28 23:42:09,883 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392446818] [2021-10-28 23:42:09,883 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:09,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:09,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 36 times [2021-10-28 23:42:09,884 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:09,884 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329743085] [2021-10-28 23:42:09,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:09,885 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:09,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:09,939 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:09,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:09,940 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:09,954 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:09,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-10-28 23:42:09,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=368, Invalid=688, Unknown=0, NotChecked=0, Total=1056 [2021-10-28 23:42:09,955 INFO L87 Difference]: Start difference. First operand 510 states and 537 transitions. cyclomatic complexity: 33 Second operand has 33 states, 33 states have (on average 3.0606060606060606) internal successors, (101), 32 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:10,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:10,280 INFO L93 Difference]: Finished difference Result 558 states and 584 transitions. [2021-10-28 23:42:10,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-10-28 23:42:10,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 558 states and 584 transitions. [2021-10-28 23:42:10,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:10,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 558 states to 554 states and 580 transitions. [2021-10-28 23:42:10,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:10,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:10,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 554 states and 580 transitions. [2021-10-28 23:42:10,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:10,285 INFO L681 BuchiCegarLoop]: Abstraction has 554 states and 580 transitions. [2021-10-28 23:42:10,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states and 580 transitions. [2021-10-28 23:42:10,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 459. [2021-10-28 23:42:10,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 459 states, 459 states have (on average 1.0457516339869282) internal successors, (480), 458 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:10,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 480 transitions. [2021-10-28 23:42:10,294 INFO L704 BuchiCegarLoop]: Abstraction has 459 states and 480 transitions. [2021-10-28 23:42:10,294 INFO L587 BuchiCegarLoop]: Abstraction has 459 states and 480 transitions. [2021-10-28 23:42:10,294 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-10-28 23:42:10,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 459 states and 480 transitions. [2021-10-28 23:42:10,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:10,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:10,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:10,300 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [128, 128, 113, 15, 1] [2021-10-28 23:42:10,300 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:10,301 INFO L791 eck$LassoCheckResult]: Stem: 32614#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 32615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32619#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32620#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 33068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32618#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32613#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33066#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33064#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33063#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33058#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33054#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33048#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33042#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33036#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33030#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33026#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33024#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33018#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33013#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 33012#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33009#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33008#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33007#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33006#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33004#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33003#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 33002#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 33001#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 33000#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32997#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32995#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32994#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32992#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32991#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32990#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32989#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32988#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32987#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32986#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32985#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32984#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32983#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32980#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32978#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32977#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32976#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32975#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32974#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32973#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32972#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32971#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32970#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32966#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32934#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32915#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32909#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32900#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32889#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32888#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32882#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32879#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32838#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32834#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32835#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32830#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32829#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32815#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32816#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32812#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32811#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32806#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32804#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32854#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32794#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32795#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32791#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32790#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32789#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32788#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32786#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32785#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32784#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32782#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32781#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32780#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32779#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32778#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32776#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32775#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32774#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32773#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32772#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32770#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32769#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32768#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32767#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32766#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32764#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32763#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32762#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32761#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32760#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32759#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32758#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32757#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32756#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32755#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32754#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32751#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32750#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32749#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32748#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32746#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32745#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32744#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32743#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32742#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32737#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32735#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32707#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32732#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32730#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32729#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32727#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32726#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32724#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32723#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32722#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32721#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32720#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32719#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32718#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32704#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32659#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32684#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32682#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32677#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32673#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32671#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32667#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32661#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32656#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32622#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32676#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32672#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32666#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32660#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32655#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32654#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32653#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32652#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32651#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32650#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32649#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32648#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32647#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32646#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32645#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32644#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32643#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32642#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32640#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32634#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 32630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 32628#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 32624#L12-1 [2021-10-28 23:42:10,301 INFO L793 eck$LassoCheckResult]: Loop: 32624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 32623#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 32624#L12-1 [2021-10-28 23:42:10,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:10,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1020239206, now seen corresponding path program 27 times [2021-10-28 23:42:10,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:10,302 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121037958] [2021-10-28 23:42:10,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:10,303 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:10,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:10,597 INFO L134 CoverageAnalysis]: Checked inductivity of 24384 backedges. 12285 proven. 4656 refuted. 0 times theorem prover too weak. 7443 trivial. 0 not checked. [2021-10-28 23:42:10,598 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:10,598 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121037958] [2021-10-28 23:42:10,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121037958] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:10,598 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [579210744] [2021-10-28 23:42:10,598 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:42:10,599 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:10,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:10,603 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:10,622 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-10-28 23:42:12,958 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 112 check-sat command(s) [2021-10-28 23:42:12,958 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:12,962 INFO L263 TraceCheckSpWp]: Trace formula consists of 720 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 23:42:12,972 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:14,118 INFO L134 CoverageAnalysis]: Checked inductivity of 24384 backedges. 10101 proven. 1428 refuted. 0 times theorem prover too weak. 12855 trivial. 0 not checked. [2021-10-28 23:42:14,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [579210744] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:14,118 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:14,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19] total 33 [2021-10-28 23:42:14,119 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451888867] [2021-10-28 23:42:14,120 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:14,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:14,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 37 times [2021-10-28 23:42:14,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:14,121 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584928478] [2021-10-28 23:42:14,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:14,121 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:14,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:14,149 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:14,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:14,151 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:14,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:14,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-10-28 23:42:14,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=391, Invalid=731, Unknown=0, NotChecked=0, Total=1122 [2021-10-28 23:42:14,166 INFO L87 Difference]: Start difference. First operand 459 states and 480 transitions. cyclomatic complexity: 27 Second operand has 34 states, 34 states have (on average 3.088235294117647) internal successors, (105), 33 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:14,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:14,720 INFO L93 Difference]: Finished difference Result 607 states and 636 transitions. [2021-10-28 23:42:14,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2021-10-28 23:42:14,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 607 states and 636 transitions. [2021-10-28 23:42:14,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:14,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 607 states to 603 states and 632 transitions. [2021-10-28 23:42:14,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:14,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:14,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 603 states and 632 transitions. [2021-10-28 23:42:14,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:14,732 INFO L681 BuchiCegarLoop]: Abstraction has 603 states and 632 transitions. [2021-10-28 23:42:14,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 603 states and 632 transitions. [2021-10-28 23:42:14,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 603 to 558. [2021-10-28 23:42:14,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 558 states, 558 states have (on average 1.050179211469534) internal successors, (586), 557 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:14,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 558 states to 558 states and 586 transitions. [2021-10-28 23:42:14,742 INFO L704 BuchiCegarLoop]: Abstraction has 558 states and 586 transitions. [2021-10-28 23:42:14,742 INFO L587 BuchiCegarLoop]: Abstraction has 558 states and 586 transitions. [2021-10-28 23:42:14,742 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-10-28 23:42:14,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 558 states and 586 transitions. [2021-10-28 23:42:14,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:14,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:14,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:14,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [130, 130, 115, 15, 1] [2021-10-28 23:42:14,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:14,750 INFO L791 eck$LassoCheckResult]: Stem: 34929#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 34930#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34932#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35416#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35401#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35400#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35395#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35394#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35393#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35386#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35382#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35374#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35373#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35371#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35370#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35369#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35368#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35361#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35358#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35357#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35356#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35355#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35354#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35352#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35351#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35350#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35344#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35334#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35333#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35332#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35331#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35328#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35327#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35326#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35325#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35320#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35317#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35316#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35308#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35304#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35303#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35302#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35301#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35300#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35299#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35296#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35293#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35291#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35285#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35283#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35279#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35277#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35273#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35271#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35269#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35267#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35260#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35261#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35258#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35256#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35254#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35252#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35250#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35248#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35246#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35244#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35242#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35238#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35236#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35234#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35232#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35230#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35228#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35226#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35224#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35220#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35218#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35214#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35212#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35208#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35206#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35202#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35196#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35194#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35186#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35155#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35156#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35147#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35143#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35144#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35140#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35135#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35130#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35126#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35125#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35120#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35116#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35117#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35113#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35112#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35111#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35110#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35172#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35170#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35103#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35165#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35099#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35094#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35093#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35092#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35091#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35090#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35087#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35086#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35085#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35084#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35082#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35081#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35079#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35078#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35076#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35073#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35070#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35069#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35067#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35064#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35063#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35057#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35052#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35040#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35036#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35030#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35026#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35024#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35015#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 35014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 35001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 35000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34997#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34995#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34994#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34992#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34991#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34990#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34989#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34988#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34984#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34976#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34933#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34921#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34926#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34987#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34975#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34973#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34966#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34954#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34945#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 34941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 34939#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 34935#L12-1 [2021-10-28 23:42:14,751 INFO L793 eck$LassoCheckResult]: Loop: 34935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 34934#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 34935#L12-1 [2021-10-28 23:42:14,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:14,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1239724674, now seen corresponding path program 28 times [2021-10-28 23:42:14,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:14,752 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143838605] [2021-10-28 23:42:14,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:14,752 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:14,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:15,141 INFO L134 CoverageAnalysis]: Checked inductivity of 25155 backedges. 12312 proven. 7065 refuted. 0 times theorem prover too weak. 5778 trivial. 0 not checked. [2021-10-28 23:42:15,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:15,141 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143838605] [2021-10-28 23:42:15,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143838605] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:15,142 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [333626616] [2021-10-28 23:42:15,142 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:42:15,142 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:15,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:15,147 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:15,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-10-28 23:42:17,035 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:42:17,036 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:17,039 INFO L263 TraceCheckSpWp]: Trace formula consists of 827 conjuncts, 40 conjunts are in the unsatisfiable core [2021-10-28 23:42:17,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:18,717 INFO L134 CoverageAnalysis]: Checked inductivity of 25155 backedges. 11112 proven. 1485 refuted. 0 times theorem prover too weak. 12558 trivial. 0 not checked. [2021-10-28 23:42:18,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [333626616] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:18,718 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:18,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 40] total 55 [2021-10-28 23:42:18,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212367471] [2021-10-28 23:42:18,719 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:18,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:18,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 38 times [2021-10-28 23:42:18,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:18,720 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977530246] [2021-10-28 23:42:18,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:18,720 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:18,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:18,737 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:18,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:18,739 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:18,754 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:18,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2021-10-28 23:42:18,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2319, Unknown=0, NotChecked=0, Total=2970 [2021-10-28 23:42:18,766 INFO L87 Difference]: Start difference. First operand 558 states and 586 transitions. cyclomatic complexity: 35 Second operand has 55 states, 55 states have (on average 3.090909090909091) internal successors, (170), 55 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:22,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:22,535 INFO L93 Difference]: Finished difference Result 1085 states and 1145 transitions. [2021-10-28 23:42:22,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 183 states. [2021-10-28 23:42:22,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1085 states and 1145 transitions. [2021-10-28 23:42:22,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:22,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1085 states to 997 states and 1055 transitions. [2021-10-28 23:42:22,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2021-10-28 23:42:22,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2021-10-28 23:42:22,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 997 states and 1055 transitions. [2021-10-28 23:42:22,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:22,545 INFO L681 BuchiCegarLoop]: Abstraction has 997 states and 1055 transitions. [2021-10-28 23:42:22,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 997 states and 1055 transitions. [2021-10-28 23:42:22,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 997 to 609. [2021-10-28 23:42:22,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 609 states, 609 states have (on average 1.0459770114942528) internal successors, (637), 608 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:22,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 637 transitions. [2021-10-28 23:42:22,558 INFO L704 BuchiCegarLoop]: Abstraction has 609 states and 637 transitions. [2021-10-28 23:42:22,558 INFO L587 BuchiCegarLoop]: Abstraction has 609 states and 637 transitions. [2021-10-28 23:42:22,558 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-10-28 23:42:22,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 609 states and 637 transitions. [2021-10-28 23:42:22,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:22,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:22,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:22,564 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [143, 143, 127, 16, 1] [2021-10-28 23:42:22,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:22,565 INFO L791 eck$LassoCheckResult]: Stem: 38279#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 38272#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38280#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38792#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38791#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38790#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38789#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38788#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38786#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38785#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38784#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38782#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38781#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38780#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38779#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38778#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38776#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38775#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38774#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38773#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38772#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38770#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38769#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38768#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38767#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38766#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38764#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38763#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38762#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38761#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38760#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38759#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38758#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38757#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38756#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38755#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38754#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38751#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38750#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38749#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38748#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38746#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38745#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38744#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38743#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38742#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38737#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38738#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38734#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38731#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38730#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38729#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38728#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38725#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38724#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38722#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38721#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38717#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38716#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38715#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38714#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38713#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38712#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38711#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38710#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38709#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38708#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38707#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38704#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38686#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38684#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38673#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38672#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38671#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38620#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38613#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38612#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38611#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38610#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38609#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38608#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38607#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38606#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38603#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38601#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38600#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38594#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38593#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38592#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38591#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38590#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38587#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38586#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38585#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38584#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38583#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38582#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38581#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38572#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38571#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38569#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38566#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38562#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38561#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38560#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38559#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38558#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38557#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38556#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38555#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38554#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38548#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38542#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38540#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38536#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38534#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38530#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38528#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38524#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38522#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38516#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38504#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38495#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38489#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38486#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38553#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38551#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38545#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38543#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38539#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38537#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38533#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38531#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38527#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38525#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38521#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38519#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38511#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38509#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38507#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38502#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38496#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38493#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38491#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38448#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38447#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38446#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38445#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38444#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38443#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38442#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38441#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38440#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38439#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38437#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38435#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38433#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38431#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38430#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38429#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38416#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38401#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38400#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38394#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38323#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38395#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38387#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38381#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38378#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38376#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38333#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38332#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38330#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38329#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38328#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38327#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38326#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38325#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38324#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38321#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38320#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38316#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38308#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38304#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38284#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38300#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38292#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38291#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38288#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38285#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38281#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38276#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38375#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38370#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38369#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38366#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38365#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38364#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38363#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38360#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38358#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38357#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38355#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38354#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38353#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38351#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38348#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38347#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38346#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38345#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38342#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38341#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38340#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38339#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38334#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38335#L12-1 [2021-10-28 23:42:22,566 INFO L793 eck$LassoCheckResult]: Loop: 38335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38336#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 38335#L12-1 [2021-10-28 23:42:22,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:22,566 INFO L85 PathProgramCache]: Analyzing trace with hash 2062858279, now seen corresponding path program 29 times [2021-10-28 23:42:22,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:22,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413976607] [2021-10-28 23:42:22,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:22,567 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:22,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:22,916 INFO L134 CoverageAnalysis]: Checked inductivity of 30459 backedges. 14310 proven. 3105 refuted. 0 times theorem prover too weak. 13044 trivial. 0 not checked. [2021-10-28 23:42:22,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:22,916 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413976607] [2021-10-28 23:42:22,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413976607] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:22,916 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [611829914] [2021-10-28 23:42:22,916 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:42:22,917 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:22,917 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:22,922 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:22,938 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-10-28 23:42:25,014 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2021-10-28 23:42:25,014 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:25,017 INFO L263 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 33 conjunts are in the unsatisfiable core [2021-10-28 23:42:25,022 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:26,530 INFO L134 CoverageAnalysis]: Checked inductivity of 30459 backedges. 16731 proven. 931 refuted. 0 times theorem prover too weak. 12797 trivial. 0 not checked. [2021-10-28 23:42:26,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [611829914] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:26,530 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:26,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 32] total 49 [2021-10-28 23:42:26,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938346588] [2021-10-28 23:42:26,532 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:26,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:26,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 39 times [2021-10-28 23:42:26,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:26,533 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364263970] [2021-10-28 23:42:26,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:26,533 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:26,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:26,567 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:26,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:26,568 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:26,581 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:26,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-10-28 23:42:26,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=466, Invalid=1886, Unknown=0, NotChecked=0, Total=2352 [2021-10-28 23:42:26,583 INFO L87 Difference]: Start difference. First operand 609 states and 637 transitions. cyclomatic complexity: 34 Second operand has 49 states, 49 states have (on average 3.122448979591837) internal successors, (153), 49 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:29,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:29,913 INFO L93 Difference]: Finished difference Result 1013 states and 1054 transitions. [2021-10-28 23:42:29,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 151 states. [2021-10-28 23:42:29,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1013 states and 1054 transitions. [2021-10-28 23:42:29,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:29,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1013 states to 995 states and 1036 transitions. [2021-10-28 23:42:29,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64 [2021-10-28 23:42:29,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64 [2021-10-28 23:42:29,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1036 transitions. [2021-10-28 23:42:29,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:29,921 INFO L681 BuchiCegarLoop]: Abstraction has 995 states and 1036 transitions. [2021-10-28 23:42:29,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1036 transitions. [2021-10-28 23:42:29,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 591. [2021-10-28 23:42:29,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 591 states, 591 states have (on average 1.0372250423011844) internal successors, (613), 590 states have internal predecessors, (613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:29,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 591 states to 591 states and 613 transitions. [2021-10-28 23:42:29,932 INFO L704 BuchiCegarLoop]: Abstraction has 591 states and 613 transitions. [2021-10-28 23:42:29,933 INFO L587 BuchiCegarLoop]: Abstraction has 591 states and 613 transitions. [2021-10-28 23:42:29,933 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-10-28 23:42:29,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 591 states and 613 transitions. [2021-10-28 23:42:29,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:29,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:29,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:29,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [144, 144, 128, 16, 1] [2021-10-28 23:42:29,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:29,940 INFO L791 eck$LassoCheckResult]: Stem: 41504#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 41497#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41505#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 42087#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42086#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42085#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42084#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42083#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42082#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42081#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42080#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42079#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42078#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42077#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42076#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42075#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42074#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42073#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42072#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42071#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42070#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42069#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42068#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42066#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42064#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42063#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42058#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42054#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42048#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42042#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42036#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41969#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42032#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42029#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 42028#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42027#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42026#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42025#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42023#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42022#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42020#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42016#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42015#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42014#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42012#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42011#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42010#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42009#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42008#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42005#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42004#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 42002#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 42001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 42000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41999#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41997#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41996#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41993#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41985#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41984#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41980#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41978#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41981#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41966#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41934#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41926#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41924#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41887#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41875#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41871#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41867#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41863#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41859#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41851#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41847#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41848#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41843#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41839#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41835#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41836#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41832#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41827#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41823#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41824#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41815#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41805#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41920#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41915#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41906#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41905#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41904#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41903#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41902#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41900#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41899#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41898#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41897#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41896#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41895#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41894#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41766#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41762#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41751#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41714#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41750#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41748#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41746#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41745#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41744#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41743#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41742#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41737#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41734#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41731#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41730#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41729#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41728#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41725#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41724#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41722#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41721#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41717#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41716#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41671#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41647#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41641#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41626#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41613#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41612#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41611#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41610#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41609#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41608#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41607#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41606#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41603#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41601#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41600#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41555#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41554#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41553#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41552#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41551#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41550#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41549#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41545#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41544#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41543#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41542#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41540#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41539#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41538#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41537#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41536#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41535#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41534#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41533#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41532#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41531#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41530#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41509#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41528#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41527#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41526#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41525#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41524#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41523#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41522#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41521#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41520#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41519#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41517#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41516#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41510#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41508#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41506#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41501#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41502#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41507#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41594#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41593#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41592#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41591#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41590#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41587#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41586#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41585#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41584#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41583#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41582#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41581#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41580#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41579#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41578#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41577#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41576#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41575#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41574#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41573#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41572#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41571#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41570#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41569#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41568#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41567#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41566#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41565#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41564#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41563#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41562#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41561#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 41560#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41559#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 41556#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 41557#L12-1 [2021-10-28 23:42:29,940 INFO L793 eck$LassoCheckResult]: Loop: 41557#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 41558#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 41557#L12-1 [2021-10-28 23:42:29,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:29,941 INFO L85 PathProgramCache]: Analyzing trace with hash -233067676, now seen corresponding path program 30 times [2021-10-28 23:42:29,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:29,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277278041] [2021-10-28 23:42:29,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:29,941 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:30,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:30,277 INFO L134 CoverageAnalysis]: Checked inductivity of 30888 backedges. 15477 proven. 5289 refuted. 0 times theorem prover too weak. 10122 trivial. 0 not checked. [2021-10-28 23:42:30,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:30,277 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277278041] [2021-10-28 23:42:30,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277278041] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:30,278 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [998784718] [2021-10-28 23:42:30,278 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:42:30,278 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:30,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:30,287 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:30,304 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-10-28 23:42:32,484 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 58 check-sat command(s) [2021-10-28 23:42:32,484 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:32,491 INFO L263 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 31 conjunts are in the unsatisfiable core [2021-10-28 23:42:32,494 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:33,999 INFO L134 CoverageAnalysis]: Checked inductivity of 30888 backedges. 19014 proven. 834 refuted. 0 times theorem prover too weak. 11040 trivial. 0 not checked. [2021-10-28 23:42:33,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [998784718] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:33,999 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:34,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 31] total 48 [2021-10-28 23:42:34,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064718164] [2021-10-28 23:42:34,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:34,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:34,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 40 times [2021-10-28 23:42:34,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:34,001 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019883337] [2021-10-28 23:42:34,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:34,001 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:34,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:34,015 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:34,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:34,016 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:34,028 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:34,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-10-28 23:42:34,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=419, Invalid=1837, Unknown=0, NotChecked=0, Total=2256 [2021-10-28 23:42:34,029 INFO L87 Difference]: Start difference. First operand 591 states and 613 transitions. cyclomatic complexity: 27 Second operand has 48 states, 48 states have (on average 3.0833333333333335) internal successors, (148), 48 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:37,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:37,811 INFO L93 Difference]: Finished difference Result 1146 states and 1194 transitions. [2021-10-28 23:42:37,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 154 states. [2021-10-28 23:42:37,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1146 states and 1194 transitions. [2021-10-28 23:42:37,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:37,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1146 states to 1136 states and 1184 transitions. [2021-10-28 23:42:37,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2021-10-28 23:42:37,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2021-10-28 23:42:37,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1136 states and 1184 transitions. [2021-10-28 23:42:37,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:37,822 INFO L681 BuchiCegarLoop]: Abstraction has 1136 states and 1184 transitions. [2021-10-28 23:42:37,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states and 1184 transitions. [2021-10-28 23:42:37,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 726. [2021-10-28 23:42:37,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 726 states, 726 states have (on average 1.0316804407713498) internal successors, (749), 725 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:37,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 726 states to 726 states and 749 transitions. [2021-10-28 23:42:37,834 INFO L704 BuchiCegarLoop]: Abstraction has 726 states and 749 transitions. [2021-10-28 23:42:37,834 INFO L587 BuchiCegarLoop]: Abstraction has 726 states and 749 transitions. [2021-10-28 23:42:37,834 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-10-28 23:42:37,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 726 states and 749 transitions. [2021-10-28 23:42:37,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:37,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:37,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:37,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [147, 147, 131, 16, 1] [2021-10-28 23:42:37,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:37,841 INFO L791 eck$LassoCheckResult]: Stem: 44857#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 44853#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44854#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44861#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45496#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45495#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45494#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45493#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45491#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45490#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45489#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45488#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45487#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45486#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45485#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45484#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45483#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45482#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45481#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45480#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45479#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45478#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45477#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45476#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45475#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45474#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45473#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45472#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45471#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45470#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45469#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45468#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45467#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45466#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45465#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45464#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45463#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45462#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45461#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45460#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45459#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45458#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45457#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45456#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45455#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45454#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45453#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45452#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45451#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45450#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45449#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45448#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45447#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45446#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45445#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45444#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45443#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45442#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45441#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45439#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45437#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45435#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45433#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45431#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45430#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45429#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45416#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45401#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45400#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45395#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45394#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45393#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45380#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45355#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45351#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45345#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45339#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45333#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45327#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45325#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45321#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45319#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45315#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45309#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45303#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45299#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45376#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45358#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45354#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45352#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45346#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45340#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45334#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45332#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45328#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45326#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45322#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45316#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45310#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45304#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45300#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45298#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45267#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45266#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45265#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45264#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45263#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45262#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45261#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45260#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45257#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45255#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45253#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45251#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45249#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45247#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45245#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45243#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45241#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45237#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45231#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45229#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45225#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45223#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45219#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45217#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45213#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45211#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45071#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45065#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45062#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45061#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45060#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45059#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45058#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45056#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45055#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45054#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45050#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45049#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45046#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45044#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45042#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45040#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45034#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45030#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45027#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 45026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45024#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 45002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 45001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 45000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44998#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44997#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44995#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44994#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44993#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44992#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44991#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44988#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44987#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44982#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44981#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44973#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44976#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44974#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44969#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44968#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44966#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44965#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44960#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44959#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44958#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44956#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44954#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44906#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44905#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44901#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44883#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44882#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44881#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44880#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44879#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44877#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44876#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44875#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44874#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44873#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44871#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44869#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44868#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44867#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44866#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44858#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44859#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44863#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44953#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44948#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44947#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44944#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44942#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44941#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44932#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44929#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44927#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44926#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44924#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44923#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44920#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 44916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44915#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 44912#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 44913#L12-1 [2021-10-28 23:42:37,841 INFO L793 eck$LassoCheckResult]: Loop: 44913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 44914#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 44913#L12-1 [2021-10-28 23:42:37,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:37,842 INFO L85 PathProgramCache]: Analyzing trace with hash -817446101, now seen corresponding path program 31 times [2021-10-28 23:42:37,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:37,842 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215162124] [2021-10-28 23:42:37,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:37,843 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:37,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:38,149 INFO L134 CoverageAnalysis]: Checked inductivity of 32193 backedges. 15066 proven. 10944 refuted. 0 times theorem prover too weak. 6183 trivial. 0 not checked. [2021-10-28 23:42:38,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:38,150 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215162124] [2021-10-28 23:42:38,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215162124] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:38,150 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1277150413] [2021-10-28 23:42:38,150 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:42:38,151 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:38,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:38,166 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:38,167 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-10-28 23:42:40,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:40,283 INFO L263 TraceCheckSpWp]: Trace formula consists of 936 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 23:42:40,287 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:41,664 INFO L134 CoverageAnalysis]: Checked inductivity of 32193 backedges. 12636 proven. 1653 refuted. 0 times theorem prover too weak. 17904 trivial. 0 not checked. [2021-10-28 23:42:41,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1277150413] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:41,664 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:41,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 21] total 36 [2021-10-28 23:42:41,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132793461] [2021-10-28 23:42:41,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:41,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:41,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 41 times [2021-10-28 23:42:41,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:41,671 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51597159] [2021-10-28 23:42:41,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:41,671 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:41,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:41,711 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:41,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:41,713 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:41,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:41,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-10-28 23:42:41,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=476, Invalid=856, Unknown=0, NotChecked=0, Total=1332 [2021-10-28 23:42:41,730 INFO L87 Difference]: Start difference. First operand 726 states and 749 transitions. cyclomatic complexity: 29 Second operand has 37 states, 37 states have (on average 3.135135135135135) internal successors, (116), 36 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:42,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:42,782 INFO L93 Difference]: Finished difference Result 1447 states and 1494 transitions. [2021-10-28 23:42:42,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2021-10-28 23:42:42,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1447 states and 1494 transitions. [2021-10-28 23:42:42,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:42,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1447 states to 1443 states and 1490 transitions. [2021-10-28 23:42:42,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:42,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:42,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1443 states and 1490 transitions. [2021-10-28 23:42:42,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:42,801 INFO L681 BuchiCegarLoop]: Abstraction has 1443 states and 1490 transitions. [2021-10-28 23:42:42,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1443 states and 1490 transitions. [2021-10-28 23:42:42,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1443 to 732. [2021-10-28 23:42:42,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 732 states, 732 states have (on average 1.0327868852459017) internal successors, (756), 731 states have internal predecessors, (756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:42,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 732 states to 732 states and 756 transitions. [2021-10-28 23:42:42,824 INFO L704 BuchiCegarLoop]: Abstraction has 732 states and 756 transitions. [2021-10-28 23:42:42,824 INFO L587 BuchiCegarLoop]: Abstraction has 732 states and 756 transitions. [2021-10-28 23:42:42,825 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-10-28 23:42:42,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 732 states and 756 transitions. [2021-10-28 23:42:42,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:42,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:42,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:42,834 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [160, 160, 143, 17, 1] [2021-10-28 23:42:42,834 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:42,836 INFO L791 eck$LassoCheckResult]: Stem: 48500#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 48501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48502#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48503#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 49115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49107#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49101#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49098#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49097#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49096#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49095#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49092#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49089#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49088#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49068#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49065#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49062#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49061#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49058#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49056#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 49055#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49054#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49050#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49049#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49046#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49044#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49042#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49040#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49039#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49038#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49034#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49032#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49029#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49028#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49027#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49026#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49025#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49023#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49022#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49020#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49016#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49015#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49014#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49012#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49011#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49010#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49009#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49008#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49005#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49004#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49002#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48999#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48997#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48996#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48993#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48985#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48984#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48981#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48979#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48976#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48974#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48966#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48954#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48953#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48948#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48947#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48944#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48942#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48941#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48932#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48929#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48927#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48926#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48924#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48923#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48920#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48915#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48908#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48907#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48884#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48880#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48878#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48877#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48875#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48842#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48840#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48834#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48824#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48823#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48822#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48821#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48819#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48818#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48817#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48816#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48815#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48814#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48813#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48812#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48811#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48810#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48809#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48808#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48807#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48806#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48805#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48804#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48803#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48802#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48801#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48800#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48799#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48798#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48797#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48796#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48795#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48794#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48793#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48792#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48743#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48746#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48736#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48727#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48719#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48715#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48711#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48712#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48708#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48703#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48700#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48691#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48688#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48679#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48676#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48672#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48671#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48670#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48669#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48668#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48667#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48666#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48665#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48664#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48663#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48662#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48661#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48660#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48659#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48658#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48657#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48656#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48655#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48654#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48653#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48652#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48651#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48650#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48649#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48648#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48647#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48646#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48645#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48644#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48643#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48642#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48640#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48618#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48611#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48586#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48583#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48574#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48572#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48571#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48541#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48566#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48555#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48549#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48543#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48538#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48504#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48497#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48554#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48548#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48542#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48537#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48536#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48535#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48534#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48533#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48532#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48531#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48530#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48529#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48528#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48527#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48526#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48525#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48524#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48523#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48522#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48521#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48520#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48519#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48517#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48516#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48510#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48506#L12-1 [2021-10-28 23:42:42,836 INFO L793 eck$LassoCheckResult]: Loop: 48506#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48505#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 48506#L12-1 [2021-10-28 23:42:42,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:42,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1439192410, now seen corresponding path program 32 times [2021-10-28 23:42:42,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:42,837 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292592190] [2021-10-28 23:42:42,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:42,838 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:43,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:43,342 INFO L134 CoverageAnalysis]: Checked inductivity of 38160 backedges. 17325 proven. 3372 refuted. 0 times theorem prover too weak. 17463 trivial. 0 not checked. [2021-10-28 23:42:43,342 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:43,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292592190] [2021-10-28 23:42:43,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292592190] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:43,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [783945371] [2021-10-28 23:42:43,343 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:42:43,343 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:43,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:43,351 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:43,371 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-10-28 23:42:45,699 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:42:45,699 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:45,704 INFO L263 TraceCheckSpWp]: Trace formula consists of 1017 conjuncts, 20 conjunts are in the unsatisfiable core [2021-10-28 23:42:45,709 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:47,359 INFO L134 CoverageAnalysis]: Checked inductivity of 38160 backedges. 17325 proven. 3372 refuted. 0 times theorem prover too weak. 17463 trivial. 0 not checked. [2021-10-28 23:42:47,359 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [783945371] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:47,359 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:47,359 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 34 [2021-10-28 23:42:47,359 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47230626] [2021-10-28 23:42:47,360 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:47,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:47,360 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 42 times [2021-10-28 23:42:47,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:47,360 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609002682] [2021-10-28 23:42:47,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:47,361 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:47,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:47,379 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:47,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:47,380 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:47,400 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:47,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-10-28 23:42:47,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=400, Invalid=790, Unknown=0, NotChecked=0, Total=1190 [2021-10-28 23:42:47,401 INFO L87 Difference]: Start difference. First operand 732 states and 756 transitions. cyclomatic complexity: 30 Second operand has 35 states, 35 states have (on average 3.057142857142857) internal successors, (107), 34 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:48,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:48,282 INFO L93 Difference]: Finished difference Result 742 states and 765 transitions. [2021-10-28 23:42:48,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2021-10-28 23:42:48,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 742 states and 765 transitions. [2021-10-28 23:42:48,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:48,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 742 states to 740 states and 763 transitions. [2021-10-28 23:42:48,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:42:48,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-10-28 23:42:48,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 740 states and 763 transitions. [2021-10-28 23:42:48,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:48,289 INFO L681 BuchiCegarLoop]: Abstraction has 740 states and 763 transitions. [2021-10-28 23:42:48,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 740 states and 763 transitions. [2021-10-28 23:42:48,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 740 to 690. [2021-10-28 23:42:48,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690 states, 690 states have (on average 1.0318840579710145) internal successors, (712), 689 states have internal predecessors, (712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:48,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 712 transitions. [2021-10-28 23:42:48,301 INFO L704 BuchiCegarLoop]: Abstraction has 690 states and 712 transitions. [2021-10-28 23:42:48,301 INFO L587 BuchiCegarLoop]: Abstraction has 690 states and 712 transitions. [2021-10-28 23:42:48,301 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-10-28 23:42:48,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 712 transitions. [2021-10-28 23:42:48,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:48,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:48,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:48,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [162, 162, 145, 17, 1] [2021-10-28 23:42:48,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:48,309 INFO L791 eck$LassoCheckResult]: Stem: 51517#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 51518#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51519#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51520#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 52153#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52151#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52150#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52148#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52147#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52146#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52145#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52144#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52143#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52142#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52140#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52139#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52138#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52137#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52136#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52135#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52134#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52133#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52132#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52131#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52130#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52128#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52127#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52126#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52125#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52124#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52123#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52122#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52121#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52120#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52119#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52118#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52117#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52116#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52115#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52114#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52113#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52112#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52111#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52110#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52109#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52108#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52107#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52106#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52105#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52104#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52103#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52102#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52101#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52100#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52099#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52098#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52096#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52095#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52094#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 52093#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52092#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52091#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52090#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52089#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52088#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52087#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52086#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52085#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52084#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52083#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52082#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52081#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52080#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52079#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52078#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52077#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52076#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52075#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52074#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52073#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52072#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52071#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52070#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52069#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52068#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52066#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52064#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52063#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52058#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52054#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52048#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52046#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52042#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52037#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 52036#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52030#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52026#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52024#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52018#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52013#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52012#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52009#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52008#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52007#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52006#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52004#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52003#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 52002#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 52001#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 52000#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51969#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51966#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51934#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51920#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51902#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51896#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51890#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51866#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51854#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51848#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51842#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51841#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51839#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51838#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51833#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51831#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51829#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51825#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51823#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51819#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51817#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51813#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51811#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51807#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51805#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51801#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51799#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51795#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51789#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51785#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51783#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51781#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51777#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51734#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51729#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51730#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51733#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51774#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51772#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51771#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51770#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51769#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51766#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51764#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51763#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51762#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51760#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51759#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51758#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51757#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51756#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51750#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51693#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51687#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51682#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51677#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51676#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51675#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51674#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51673#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51672#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51671#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51670#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51669#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51657#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51628#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51609#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51608#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51607#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51603#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51601#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51600#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51594#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51593#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51592#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51591#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51590#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51587#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51586#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51583#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51574#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51572#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51568#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51562#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51557#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51521#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51509#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51510#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51514#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51573#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51569#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51567#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51561#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51556#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51554#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51550#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51548#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51545#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51544#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51543#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51542#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51540#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51539#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51538#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51537#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51536#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51535#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51534#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51533#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51532#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51531#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51530#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 51529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51528#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 51527#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 51523#L12-1 [2021-10-28 23:42:48,310 INFO L793 eck$LassoCheckResult]: Loop: 51523#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 51522#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 51523#L12-1 [2021-10-28 23:42:48,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:48,310 INFO L85 PathProgramCache]: Analyzing trace with hash 2107192578, now seen corresponding path program 33 times [2021-10-28 23:42:48,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:48,311 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395903824] [2021-10-28 23:42:48,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:48,311 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:48,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:48,715 INFO L134 CoverageAnalysis]: Checked inductivity of 39123 backedges. 18915 proven. 11937 refuted. 0 times theorem prover too weak. 8271 trivial. 0 not checked. [2021-10-28 23:42:48,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:48,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395903824] [2021-10-28 23:42:48,716 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395903824] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:48,716 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [431820665] [2021-10-28 23:42:48,716 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:42:48,716 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:48,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:48,723 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:48,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-10-28 23:42:51,303 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 136 check-sat command(s) [2021-10-28 23:42:51,303 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:42:51,307 INFO L263 TraceCheckSpWp]: Trace formula consists of 867 conjuncts, 29 conjunts are in the unsatisfiable core [2021-10-28 23:42:51,310 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:42:52,842 INFO L134 CoverageAnalysis]: Checked inductivity of 39123 backedges. 19662 proven. 11080 refuted. 0 times theorem prover too weak. 8381 trivial. 0 not checked. [2021-10-28 23:42:52,842 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [431820665] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:52,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:42:52,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 27] total 46 [2021-10-28 23:42:52,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992476893] [2021-10-28 23:42:52,844 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:42:52,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:52,844 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 43 times [2021-10-28 23:42:52,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:52,844 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146697489] [2021-10-28 23:42:52,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:52,845 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:52,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:52,862 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:42:52,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:42:52,863 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:42:52,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:42:52,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-10-28 23:42:52,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=367, Invalid=1703, Unknown=0, NotChecked=0, Total=2070 [2021-10-28 23:42:52,883 INFO L87 Difference]: Start difference. First operand 690 states and 712 transitions. cyclomatic complexity: 28 Second operand has 46 states, 46 states have (on average 3.4130434782608696) internal successors, (157), 46 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:58,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:42:58,111 INFO L93 Difference]: Finished difference Result 1778 states and 1840 transitions. [2021-10-28 23:42:58,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 198 states. [2021-10-28 23:42:58,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1778 states and 1840 transitions. [2021-10-28 23:42:58,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:58,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1778 states to 1688 states and 1750 transitions. [2021-10-28 23:42:58,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2021-10-28 23:42:58,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2021-10-28 23:42:58,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 1750 transitions. [2021-10-28 23:42:58,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:42:58,128 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 1750 transitions. [2021-10-28 23:42:58,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 1750 transitions. [2021-10-28 23:42:58,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1149. [2021-10-28 23:42:58,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1149 states, 1149 states have (on average 1.0287206266318538) internal successors, (1182), 1148 states have internal predecessors, (1182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:42:58,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1149 states to 1149 states and 1182 transitions. [2021-10-28 23:42:58,151 INFO L704 BuchiCegarLoop]: Abstraction has 1149 states and 1182 transitions. [2021-10-28 23:42:58,151 INFO L587 BuchiCegarLoop]: Abstraction has 1149 states and 1182 transitions. [2021-10-28 23:42:58,151 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-10-28 23:42:58,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1149 states and 1182 transitions. [2021-10-28 23:42:58,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:42:58,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:42:58,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:42:58,162 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [170, 170, 152, 18, 1] [2021-10-28 23:42:58,162 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:42:58,164 INFO L791 eck$LassoCheckResult]: Stem: 55872#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 55868#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55876#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56948#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56947#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56944#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56942#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56941#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56932#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56929#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56927#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56926#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56924#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56923#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56922#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56920#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56917#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56916#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56915#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56914#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56906#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56905#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56904#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56903#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56902#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56900#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56899#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56898#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56895#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56894#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56893#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56892#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56891#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56890#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56889#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56887#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56886#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56885#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56883#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56882#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56881#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56880#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56879#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56877#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56876#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56875#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56874#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56873#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56871#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56869#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56868#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56867#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56866#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56865#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56864#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56863#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56862#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56861#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56859#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56858#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56857#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56856#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56855#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56854#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56853#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56852#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56851#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56850#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56849#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56848#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56842#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56838#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56836#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56832#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56830#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56827#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56825#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56823#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56821#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56819#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56815#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56813#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56809#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56807#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56803#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56801#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56797#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56795#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56791#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56789#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56787#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56785#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56781#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56759#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56751#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56749#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56745#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56732#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56730#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56731#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56599#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56598#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56597#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56596#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56595#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56592#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56591#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56589#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56586#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56583#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56574#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56572#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56571#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56569#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56568#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56567#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56566#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56562#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56553#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56513#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56511#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56415#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56416#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56407#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56403#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56395#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56388#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56379#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56355#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56204#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56200#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56168#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56169#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56475#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56445#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56428#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56427#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56426#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56425#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56424#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56422#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56109#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56423#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56206#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56040#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 56038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56012#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56004#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 56002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55990#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55981#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55979#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55976#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55974#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55965#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 56043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 56042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55958#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55952#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55947#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55946#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55945#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55943#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55941#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55938#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55932#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55878#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55873#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55874#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55930#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55928#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55926#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55924#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55918#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55909#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55900#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55897#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55889#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55888#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 55884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 55882#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 55881#L12-1 [2021-10-28 23:42:58,164 INFO L793 eck$LassoCheckResult]: Loop: 55881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 55880#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 55881#L12-1 [2021-10-28 23:42:58,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:42:58,165 INFO L85 PathProgramCache]: Analyzing trace with hash -50297856, now seen corresponding path program 34 times [2021-10-28 23:42:58,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:42:58,165 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688414240] [2021-10-28 23:42:58,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:42:58,166 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:42:58,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:42:58,606 INFO L134 CoverageAnalysis]: Checked inductivity of 43095 backedges. 19947 proven. 15393 refuted. 0 times theorem prover too weak. 7755 trivial. 0 not checked. [2021-10-28 23:42:58,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:42:58,607 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688414240] [2021-10-28 23:42:58,607 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688414240] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:42:58,607 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1156214932] [2021-10-28 23:42:58,607 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:42:58,607 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:42:58,607 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:42:58,610 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:42:58,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-10-28 23:43:01,558 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:43:01,559 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:01,563 INFO L263 TraceCheckSpWp]: Trace formula consists of 1076 conjuncts, 40 conjunts are in the unsatisfiable core [2021-10-28 23:43:01,566 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:03,377 INFO L134 CoverageAnalysis]: Checked inductivity of 43095 backedges. 19830 proven. 3429 refuted. 0 times theorem prover too weak. 19836 trivial. 0 not checked. [2021-10-28 23:43:03,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1156214932] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:03,378 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:03,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 40] total 56 [2021-10-28 23:43:03,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747210461] [2021-10-28 23:43:03,379 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:03,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:03,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 44 times [2021-10-28 23:43:03,379 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:03,379 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074602185] [2021-10-28 23:43:03,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:03,379 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:03,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:03,396 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:03,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:03,397 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:03,408 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:03,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2021-10-28 23:43:03,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=674, Invalid=2406, Unknown=0, NotChecked=0, Total=3080 [2021-10-28 23:43:03,409 INFO L87 Difference]: Start difference. First operand 1149 states and 1182 transitions. cyclomatic complexity: 40 Second operand has 56 states, 56 states have (on average 3.125) internal successors, (175), 56 states have internal predecessors, (175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:08,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:08,191 INFO L93 Difference]: Finished difference Result 1651 states and 1714 transitions. [2021-10-28 23:43:08,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 214 states. [2021-10-28 23:43:08,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1651 states and 1714 transitions. [2021-10-28 23:43:08,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:08,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1651 states to 1604 states and 1666 transitions. [2021-10-28 23:43:08,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2021-10-28 23:43:08,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2021-10-28 23:43:08,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1604 states and 1666 transitions. [2021-10-28 23:43:08,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:08,207 INFO L681 BuchiCegarLoop]: Abstraction has 1604 states and 1666 transitions. [2021-10-28 23:43:08,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states and 1666 transitions. [2021-10-28 23:43:08,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1125. [2021-10-28 23:43:08,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1125 states, 1125 states have (on average 1.0266666666666666) internal successors, (1155), 1124 states have internal predecessors, (1155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:08,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1125 states to 1125 states and 1155 transitions. [2021-10-28 23:43:08,226 INFO L704 BuchiCegarLoop]: Abstraction has 1125 states and 1155 transitions. [2021-10-28 23:43:08,226 INFO L587 BuchiCegarLoop]: Abstraction has 1125 states and 1155 transitions. [2021-10-28 23:43:08,227 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-10-28 23:43:08,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1125 states and 1155 transitions. [2021-10-28 23:43:08,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:08,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:08,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:08,235 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [176, 176, 158, 18, 1] [2021-10-28 23:43:08,235 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:08,236 INFO L791 eck$LassoCheckResult]: Stem: 60838#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 60834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60842#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61884#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61880#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61878#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61877#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61875#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61874#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61872#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61871#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61869#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61868#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61867#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61866#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61865#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61863#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61862#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61861#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61860#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61859#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61857#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61856#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61854#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61853#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61851#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61849#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61848#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61847#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61845#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61843#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61842#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61841#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61839#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61837#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61835#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61833#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61830#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61829#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61808#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61791#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61788#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61787#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61786#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61785#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61784#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61783#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61782#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61781#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61780#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61778#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61777#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61776#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61775#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61774#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61772#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61771#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61770#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61769#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61768#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61766#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61764#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61763#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61762#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61760#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61759#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61758#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61757#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61756#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61753#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61752#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61751#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61750#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61749#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61748#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61747#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61746#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61745#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61744#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61743#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61742#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61737#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61741#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61733#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61729#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61727#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61726#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61724#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61723#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61722#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61721#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61720#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61719#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61718#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61706#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61705#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61703#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61701#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61699#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61698#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61696#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61693#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61683#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61647#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61641#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61600#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61599#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61598#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61597#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61596#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61595#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61592#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61591#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61589#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61588#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61586#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61583#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61578#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61577#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61576#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61574#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61572#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61571#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61568#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61520#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61307#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61275#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61274#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61272#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61266#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61264#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61260#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61258#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61256#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61254#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61252#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61248#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61246#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61181#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61171#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61172#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61163#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61164#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61155#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61156#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61147#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61148#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61139#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61140#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61131#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61132#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61123#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61124#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61115#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61116#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61102#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61092#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61089#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61088#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61068#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61065#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61062#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61061#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61060#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61059#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61058#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61056#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61055#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61054#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61050#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61049#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61046#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61044#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61042#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61040#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61039#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61038#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61034#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61032#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61028#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 61026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 61005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 61003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 61001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60991#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60978#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60958#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60973#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60971#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60970#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60967#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60965#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60928#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60924#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60923#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60918#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60870#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60869#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60867#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60846#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60865#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60863#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60862#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60861#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60860#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60859#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60857#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60856#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60854#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60853#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60851#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60849#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60848#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60847#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60845#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60843#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60839#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60912#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60911#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60900#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60889#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60888#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60882#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60879#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60878#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60876#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 60875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 60871#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 60872#L12-1 [2021-10-28 23:43:08,237 INFO L793 eck$LassoCheckResult]: Loop: 60872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 60873#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 60872#L12-1 [2021-10-28 23:43:08,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:08,237 INFO L85 PathProgramCache]: Analyzing trace with hash -419178784, now seen corresponding path program 35 times [2021-10-28 23:43:08,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:08,238 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815692384] [2021-10-28 23:43:08,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:08,238 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:08,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:08,676 INFO L134 CoverageAnalysis]: Checked inductivity of 46200 backedges. 22464 proven. 6177 refuted. 0 times theorem prover too weak. 17559 trivial. 0 not checked. [2021-10-28 23:43:08,676 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:08,676 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815692384] [2021-10-28 23:43:08,676 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815692384] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:08,677 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [181746385] [2021-10-28 23:43:08,677 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-10-28 23:43:08,677 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:08,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:08,683 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:08,698 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-10-28 23:43:11,467 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2021-10-28 23:43:11,467 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:11,469 INFO L263 TraceCheckSpWp]: Trace formula consists of 341 conjuncts, 35 conjunts are in the unsatisfiable core [2021-10-28 23:43:11,562 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:13,212 INFO L134 CoverageAnalysis]: Checked inductivity of 46200 backedges. 26687 proven. 1065 refuted. 0 times theorem prover too weak. 18448 trivial. 0 not checked. [2021-10-28 23:43:13,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [181746385] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:13,212 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:13,213 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 34] total 53 [2021-10-28 23:43:13,213 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559256714] [2021-10-28 23:43:13,213 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:13,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:13,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 45 times [2021-10-28 23:43:13,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:13,214 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852527534] [2021-10-28 23:43:13,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:13,214 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:13,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:13,233 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:13,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:13,233 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:13,246 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:13,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2021-10-28 23:43:13,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=560, Invalid=2196, Unknown=0, NotChecked=0, Total=2756 [2021-10-28 23:43:13,248 INFO L87 Difference]: Start difference. First operand 1125 states and 1155 transitions. cyclomatic complexity: 36 Second operand has 53 states, 53 states have (on average 3.1320754716981134) internal successors, (166), 53 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:18,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:18,752 INFO L93 Difference]: Finished difference Result 1341 states and 1387 transitions. [2021-10-28 23:43:18,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 212 states. [2021-10-28 23:43:18,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1341 states and 1387 transitions. [2021-10-28 23:43:18,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:18,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1341 states to 1333 states and 1379 transitions. [2021-10-28 23:43:18,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2021-10-28 23:43:18,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2021-10-28 23:43:18,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1333 states and 1379 transitions. [2021-10-28 23:43:18,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:18,764 INFO L681 BuchiCegarLoop]: Abstraction has 1333 states and 1379 transitions. [2021-10-28 23:43:18,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1333 states and 1379 transitions. [2021-10-28 23:43:18,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1333 to 780. [2021-10-28 23:43:18,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 780 states, 780 states have (on average 1.0256410256410255) internal successors, (800), 779 states have internal predecessors, (800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:18,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 800 transitions. [2021-10-28 23:43:18,778 INFO L704 BuchiCegarLoop]: Abstraction has 780 states and 800 transitions. [2021-10-28 23:43:18,778 INFO L587 BuchiCegarLoop]: Abstraction has 780 states and 800 transitions. [2021-10-28 23:43:18,778 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-10-28 23:43:18,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 780 states and 800 transitions. [2021-10-28 23:43:18,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:18,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:18,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:18,789 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [186, 186, 167, 19, 1] [2021-10-28 23:43:18,789 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:18,790 INFO L791 eck$LassoCheckResult]: Stem: 65328#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 65324#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65326#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65332#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 66052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66050#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66049#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66046#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66044#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66042#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66040#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66039#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66038#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66036#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66034#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66032#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66030#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66029#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66028#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66027#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66026#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66025#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66024#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66023#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66022#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66020#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66018#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66016#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66015#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66014#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66012#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66011#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66010#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66009#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66008#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66005#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66004#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 66002#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 66001#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 66000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65999#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65993#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65985#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65984#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65983#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65981#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65979#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65976#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65974#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65967#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65966#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65965#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65962#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65961#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65960#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65959#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65956#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65955#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65950#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65949#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65944#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65943#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65936#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65933#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65931#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65930#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65928#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65925#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65921#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65920#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65919#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65914#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65913#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65910#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65909#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65908#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65907#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65832#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65881#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65878#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65877#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65875#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65874#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65872#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65871#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65869#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65868#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65867#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65866#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65865#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65863#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65862#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65861#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65860#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65859#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65857#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65856#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65854#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65853#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65851#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65849#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65848#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65847#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65845#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65843#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65842#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65841#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65839#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65837#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65835#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65787#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65833#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65830#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65829#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65808#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65789#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65745#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65788#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65785#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65784#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65783#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65782#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65781#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65780#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65778#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65777#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65776#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65774#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65773#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65772#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65771#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65770#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65768#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65767#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65766#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65765#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65764#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65762#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65761#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65760#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65759#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65758#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65756#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65755#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65754#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65753#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65752#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65751#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65750#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65749#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65748#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65747#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65746#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65742#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65741#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65740#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65739#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65738#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65737#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65650#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65648#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65643#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65623#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65611#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65607#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65601#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65598#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65596#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65736#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65735#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65734#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65733#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65732#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65729#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65728#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65727#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65726#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65725#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65723#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65722#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65721#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65720#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65719#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65718#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65717#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65716#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65715#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65714#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65713#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65712#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65711#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65710#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65709#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65708#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65707#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65706#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65705#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65559#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65704#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65686#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65683#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65674#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65651#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65646#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65640#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65620#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65608#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65604#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65602#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65457#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65452#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65449#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65445#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65440#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65436#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65437#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65433#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65424#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65420#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65417#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65416#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65415#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65414#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65413#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65412#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65411#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65410#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65409#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65408#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65407#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65406#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65405#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65403#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65402#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65401#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65400#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65357#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65355#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65354#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65353#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65352#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65351#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65350#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65349#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65348#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65347#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65346#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65345#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65344#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65343#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65342#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65341#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65340#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65339#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65338#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65337#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65333#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65329#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65330#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65399#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65398#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65397#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65396#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65395#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65393#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65391#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65390#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65387#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65381#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65378#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65376#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65375#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65370#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65369#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65366#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65365#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65364#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65363#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 65362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 65358#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 65359#L12-1 [2021-10-28 23:43:18,791 INFO L793 eck$LassoCheckResult]: Loop: 65359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 65360#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 65359#L12-1 [2021-10-28 23:43:18,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:18,792 INFO L85 PathProgramCache]: Analyzing trace with hash -875576194, now seen corresponding path program 36 times [2021-10-28 23:43:18,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:18,792 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150066894] [2021-10-28 23:43:18,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:18,793 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:18,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:19,354 INFO L134 CoverageAnalysis]: Checked inductivity of 51615 backedges. 24624 proven. 16884 refuted. 0 times theorem prover too weak. 10107 trivial. 0 not checked. [2021-10-28 23:43:19,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:19,355 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150066894] [2021-10-28 23:43:19,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150066894] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:19,355 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [495640581] [2021-10-28 23:43:19,356 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-10-28 23:43:19,356 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:19,357 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:19,359 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:19,380 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-10-28 23:43:22,266 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 101 check-sat command(s) [2021-10-28 23:43:22,266 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:22,269 INFO L263 TraceCheckSpWp]: Trace formula consists of 648 conjuncts, 21 conjunts are in the unsatisfiable core [2021-10-28 23:43:22,272 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:23,509 INFO L134 CoverageAnalysis]: Checked inductivity of 51615 backedges. 16440 proven. 588 refuted. 0 times theorem prover too weak. 34587 trivial. 0 not checked. [2021-10-28 23:43:23,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [495640581] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:23,509 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:23,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 17] total 36 [2021-10-28 23:43:23,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296140861] [2021-10-28 23:43:23,510 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:23,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:23,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 46 times [2021-10-28 23:43:23,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:23,511 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706424172] [2021-10-28 23:43:23,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:23,511 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:23,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:23,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:23,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:23,532 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:23,555 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:23,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-10-28 23:43:23,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=205, Invalid=1055, Unknown=0, NotChecked=0, Total=1260 [2021-10-28 23:43:23,556 INFO L87 Difference]: Start difference. First operand 780 states and 800 transitions. cyclomatic complexity: 26 Second operand has 36 states, 36 states have (on average 3.3333333333333335) internal successors, (120), 36 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:26,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:26,494 INFO L93 Difference]: Finished difference Result 1910 states and 1957 transitions. [2021-10-28 23:43:26,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2021-10-28 23:43:26,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1910 states and 1957 transitions. [2021-10-28 23:43:26,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:26,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1910 states to 1725 states and 1771 transitions. [2021-10-28 23:43:26,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-10-28 23:43:26,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2021-10-28 23:43:26,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1725 states and 1771 transitions. [2021-10-28 23:43:26,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:26,513 INFO L681 BuchiCegarLoop]: Abstraction has 1725 states and 1771 transitions. [2021-10-28 23:43:26,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1725 states and 1771 transitions. [2021-10-28 23:43:26,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1725 to 960. [2021-10-28 23:43:26,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 960 states, 960 states have (on average 1.025) internal successors, (984), 959 states have internal predecessors, (984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:26,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 960 states to 960 states and 984 transitions. [2021-10-28 23:43:26,532 INFO L704 BuchiCegarLoop]: Abstraction has 960 states and 984 transitions. [2021-10-28 23:43:26,532 INFO L587 BuchiCegarLoop]: Abstraction has 960 states and 984 transitions. [2021-10-28 23:43:26,533 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-10-28 23:43:26,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 960 states and 984 transitions. [2021-10-28 23:43:26,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:26,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:26,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:26,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [189, 189, 170, 19, 1] [2021-10-28 23:43:26,542 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:26,543 INFO L791 eck$LassoCheckResult]: Stem: 69987#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 69988#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 69989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 69990#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70704#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70686#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70683#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70657#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70656#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70655#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70650#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70647#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70641#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70626#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70617#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70611#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70590#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70588#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70587#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70584#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70581#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70579#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70578#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70577#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70573#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70572#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70570#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70556#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70554#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70553#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70552#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70550#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70549#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70548#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70547#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70546#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70542#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70540#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70537#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70538#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70532#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70516#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70515#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70514#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70513#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70512#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70511#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70510#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70509#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70508#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70507#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70506#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70505#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70504#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70503#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70502#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70498#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70495#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70494#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70493#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70491#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70490#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70489#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70487#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70483#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70481#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70480#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70477#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70474#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70473#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70471#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70469#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70468#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70467#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70463#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70462#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70461#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70460#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70459#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70458#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70457#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70456#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70455#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70454#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70453#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70452#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70451#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70450#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70449#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70447#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70445#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70444#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70443#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70442#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70441#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70439#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70437#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70435#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70433#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70431#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70430#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70429#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70416#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70404#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70401#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70400#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70395#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70394#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70393#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70386#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70382#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70374#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70373#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70370#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70369#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70368#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70361#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70248#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70320#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70317#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70313#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70307#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70303#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70301#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70295#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70289#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70283#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70281#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70279#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70277#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70275#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70271#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70269#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70265#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70263#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70261#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70259#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70257#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70255#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70253#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70251#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70239#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70237#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70235#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70233#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70231#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70229#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70227#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70225#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70221#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70219#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70215#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70213#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70209#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70203#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70201#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70197#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70195#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70191#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70189#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70185#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70183#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70177#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70173#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70171#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70167#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70165#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70159#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70155#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70153#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70147#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70143#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70141#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70137#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70135#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70125#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70123#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70122#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70119#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70107#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70102#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70098#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70097#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70096#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70095#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70092#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70089#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70087#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70083#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70081#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70077#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70071#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70069#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70063#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 69991#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 69978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 69979#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 69983#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 69984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70088#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70086#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70082#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70076#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70070#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70064#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70057#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70052#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70040#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70039#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70036#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70034#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70033#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70030#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70024#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70012#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 70005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70003#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 70002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 70001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 70000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 69999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 69998#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 69997#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 69993#L12-1 [2021-10-28 23:43:26,543 INFO L793 eck$LassoCheckResult]: Loop: 69993#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 69992#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 69993#L12-1 [2021-10-28 23:43:26,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:26,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1617752563, now seen corresponding path program 37 times [2021-10-28 23:43:26,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:26,544 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815673927] [2021-10-28 23:43:26,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:26,545 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:26,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:27,032 INFO L134 CoverageAnalysis]: Checked inductivity of 53298 backedges. 23814 proven. 20952 refuted. 0 times theorem prover too weak. 8532 trivial. 0 not checked. [2021-10-28 23:43:27,032 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:27,033 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815673927] [2021-10-28 23:43:27,033 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815673927] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:27,033 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [874257898] [2021-10-28 23:43:27,033 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-10-28 23:43:27,033 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:27,034 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:27,051 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:27,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2021-10-28 23:43:29,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:29,896 INFO L263 TraceCheckSpWp]: Trace formula consists of 1197 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 23:43:29,900 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:31,341 INFO L134 CoverageAnalysis]: Checked inductivity of 53298 backedges. 22572 proven. 3705 refuted. 0 times theorem prover too weak. 27021 trivial. 0 not checked. [2021-10-28 23:43:31,341 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [874257898] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:31,341 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:31,341 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21] total 37 [2021-10-28 23:43:31,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182118098] [2021-10-28 23:43:31,342 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:31,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:31,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 47 times [2021-10-28 23:43:31,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:31,342 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718624926] [2021-10-28 23:43:31,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:31,343 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:31,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:31,362 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:31,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:31,362 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:31,373 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:31,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-10-28 23:43:31,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=908, Unknown=0, NotChecked=0, Total=1406 [2021-10-28 23:43:31,374 INFO L87 Difference]: Start difference. First operand 960 states and 984 transitions. cyclomatic complexity: 29 Second operand has 38 states, 38 states have (on average 3.1842105263157894) internal successors, (121), 37 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:32,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:32,886 INFO L93 Difference]: Finished difference Result 2007 states and 2061 transitions. [2021-10-28 23:43:32,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 117 states. [2021-10-28 23:43:32,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2007 states and 2061 transitions. [2021-10-28 23:43:32,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:32,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2007 states to 2003 states and 2057 transitions. [2021-10-28 23:43:32,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2021-10-28 23:43:32,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2021-10-28 23:43:32,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2003 states and 2057 transitions. [2021-10-28 23:43:32,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:32,910 INFO L681 BuchiCegarLoop]: Abstraction has 2003 states and 2057 transitions. [2021-10-28 23:43:32,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2003 states and 2057 transitions. [2021-10-28 23:43:32,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2003 to 996. [2021-10-28 23:43:32,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 996 states, 996 states have (on average 1.0240963855421688) internal successors, (1020), 995 states have internal predecessors, (1020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:32,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 996 states to 996 states and 1020 transitions. [2021-10-28 23:43:32,927 INFO L704 BuchiCegarLoop]: Abstraction has 996 states and 1020 transitions. [2021-10-28 23:43:32,927 INFO L587 BuchiCegarLoop]: Abstraction has 996 states and 1020 transitions. [2021-10-28 23:43:32,927 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-10-28 23:43:32,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 996 states and 1020 transitions. [2021-10-28 23:43:32,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:32,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:32,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:32,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [193, 193, 174, 19, 1] [2021-10-28 23:43:32,935 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:32,935 INFO L791 eck$LassoCheckResult]: Stem: 74854#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 74855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74857#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75567#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75566#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75562#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75516#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75515#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75514#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75513#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75512#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75510#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75509#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75508#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75507#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75506#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75505#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75504#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75503#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75502#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75498#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75495#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75494#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75493#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75491#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75490#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75489#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75487#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75486#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75485#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75483#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75482#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75481#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75480#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75479#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75478#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75477#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75476#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75475#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75451#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75445#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75428#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75427#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75426#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75425#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75424#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75422#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75421#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75420#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75419#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75418#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75416#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75415#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75410#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75408#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75407#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75406#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75405#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75404#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75403#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75402#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75401#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75398#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75397#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75396#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75395#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75393#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75391#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75390#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75387#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75381#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75378#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75376#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75375#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75370#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75369#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75366#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75365#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75364#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75363#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75360#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75358#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75357#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75355#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75354#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75353#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75351#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75347#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75344#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75334#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75333#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75332#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75331#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75328#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75327#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75326#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75325#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75321#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75320#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75316#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75308#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75303#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75302#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75301#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75300#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75298#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75297#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75296#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75295#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75294#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75293#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75292#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75291#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75290#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75289#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75288#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75287#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75286#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75285#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75284#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75283#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75282#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75281#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75280#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75279#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75278#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75277#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75276#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75275#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75274#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75273#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75272#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75271#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75270#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75269#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75268#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75267#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75266#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75265#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75264#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75263#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75262#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75260#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75259#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75258#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75257#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75256#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75255#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75254#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75253#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75252#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75251#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75250#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75249#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75248#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75247#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75246#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75245#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75244#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75243#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75242#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75241#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75240#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75239#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75238#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75237#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75236#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75234#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75233#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75232#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75231#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75230#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75229#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75228#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75227#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75226#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75225#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75224#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75223#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75222#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75219#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75215#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75212#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75209#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75206#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75197#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75191#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75188#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75173#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75170#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75164#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75155#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75149#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75146#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75143#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75137#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75134#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75128#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75125#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75123#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75119#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75114#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75113#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75112#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75111#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75110#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75109#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75103#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75097#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75091#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75085#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75079#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75073#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75049#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 75047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75039#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75033#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75027#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75021#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75015#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75013#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75009#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75007#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 75003#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 75001#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 75000#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74999#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74994#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74992#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74991#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74990#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74989#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74988#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74987#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74986#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74985#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74984#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74983#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74980#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74978#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74977#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74976#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74975#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74974#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74973#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74972#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74971#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74970#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74966#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74965#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74960#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74959#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74958#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74954#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74948#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74942#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74938#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74934#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74858#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74845#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74846#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74851#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74953#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74947#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74943#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74941#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74939#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74937#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74933#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74931#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74924#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74923#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74918#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74912#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74911#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74906#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74900#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74891#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74889#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74888#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74887#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74882#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74879#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74878#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74876#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74873#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74871#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74870#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74869#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74867#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 74866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 74864#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 74860#L12-1 [2021-10-28 23:43:32,936 INFO L793 eck$LassoCheckResult]: Loop: 74860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 74859#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 74860#L12-1 [2021-10-28 23:43:32,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:32,936 INFO L85 PathProgramCache]: Analyzing trace with hash 109818189, now seen corresponding path program 38 times [2021-10-28 23:43:32,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:32,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674795529] [2021-10-28 23:43:32,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:32,937 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:33,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:33,394 INFO L134 CoverageAnalysis]: Checked inductivity of 55584 backedges. 26418 proven. 6561 refuted. 0 times theorem prover too weak. 22605 trivial. 0 not checked. [2021-10-28 23:43:33,395 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:33,395 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674795529] [2021-10-28 23:43:33,395 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674795529] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:33,395 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [444597433] [2021-10-28 23:43:33,395 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-10-28 23:43:33,395 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:33,395 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:33,399 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:33,414 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2021-10-28 23:43:36,419 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-10-28 23:43:36,419 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:36,423 INFO L263 TraceCheckSpWp]: Trace formula consists of 1221 conjuncts, 22 conjunts are in the unsatisfiable core [2021-10-28 23:43:36,426 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:37,870 INFO L134 CoverageAnalysis]: Checked inductivity of 55584 backedges. 26418 proven. 6561 refuted. 0 times theorem prover too weak. 22605 trivial. 0 not checked. [2021-10-28 23:43:37,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [444597433] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:37,871 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:37,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 37 [2021-10-28 23:43:37,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656381431] [2021-10-28 23:43:37,872 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:37,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:37,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 48 times [2021-10-28 23:43:37,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:37,873 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334585355] [2021-10-28 23:43:37,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:37,873 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:37,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:37,920 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:37,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:37,921 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:37,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:37,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-10-28 23:43:37,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=951, Unknown=0, NotChecked=0, Total=1406 [2021-10-28 23:43:37,933 INFO L87 Difference]: Start difference. First operand 996 states and 1020 transitions. cyclomatic complexity: 29 Second operand has 38 states, 38 states have (on average 3.0789473684210527) internal successors, (117), 37 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:39,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:39,120 INFO L93 Difference]: Finished difference Result 1004 states and 1028 transitions. [2021-10-28 23:43:39,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2021-10-28 23:43:39,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1028 transitions. [2021-10-28 23:43:39,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:39,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 1002 states and 1026 transitions. [2021-10-28 23:43:39,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2021-10-28 23:43:39,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2021-10-28 23:43:39,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1026 transitions. [2021-10-28 23:43:39,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:39,128 INFO L681 BuchiCegarLoop]: Abstraction has 1002 states and 1026 transitions. [2021-10-28 23:43:39,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1026 transitions. [2021-10-28 23:43:39,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 732. [2021-10-28 23:43:39,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 732 states, 732 states have (on average 1.0245901639344261) internal successors, (750), 731 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:39,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 732 states to 732 states and 750 transitions. [2021-10-28 23:43:39,139 INFO L704 BuchiCegarLoop]: Abstraction has 732 states and 750 transitions. [2021-10-28 23:43:39,139 INFO L587 BuchiCegarLoop]: Abstraction has 732 states and 750 transitions. [2021-10-28 23:43:39,139 INFO L425 BuchiCegarLoop]: ======== Iteration 53============ [2021-10-28 23:43:39,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 732 states and 750 transitions. [2021-10-28 23:43:39,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:39,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:39,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:39,149 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [206, 206, 186, 20, 1] [2021-10-28 23:43:39,149 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:39,150 INFO L791 eck$LassoCheckResult]: Stem: 78738#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 78739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78740#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78737#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78734#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78741#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79447#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79446#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79445#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79444#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79443#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79439#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79428#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79427#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79426#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79425#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79424#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79422#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79421#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79420#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79419#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79418#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79416#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79415#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79409#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79408#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79407#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79406#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79405#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79404#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79403#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79402#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79401#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79399#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79398#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79397#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79395#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79394#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79390#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79389#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79388#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79386#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79385#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79383#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79382#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79381#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79380#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79379#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79378#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79377#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79374#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79373#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79371#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79368#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79366#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79365#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79362#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79361#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79360#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79359#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79358#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79356#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79355#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79354#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79296#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79352#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79351#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79350#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79344#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79334#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79333#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79332#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79331#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79328#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79327#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79326#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79325#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79321#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79320#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79316#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79308#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79306#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79304#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79303#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79302#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79300#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79293#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79292#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79290#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79288#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79286#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79284#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79279#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79278#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79276#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79274#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79272#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79270#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79269#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79266#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79265#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79263#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79261#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79260#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79259#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79258#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79257#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79256#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79255#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79254#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79253#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79252#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79251#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79249#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79246#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79194#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79243#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79239#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79238#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79237#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79235#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79234#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79231#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79229#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79228#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79225#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79224#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79219#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79218#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79195#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79191#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79162#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79161#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79156#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79155#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79107#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79150#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79147#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79146#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79134#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79129#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79128#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79127#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79125#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79123#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79122#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79119#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79108#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79104#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79101#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79098#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79097#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79096#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79095#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79092#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79089#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79088#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79070#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79063#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 79061#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79057#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79055#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79049#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79037#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79033#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79031#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79025#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79019#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79013#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 79007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 79005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 79003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78991#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78987#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78985#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78981#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78973#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78971#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78965#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78963#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78957#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78951#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78947#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78941#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78927#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78895#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78889#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78885#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78879#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78880#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78876#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78873#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78871#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78870#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78869#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78867#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78864#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78863#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78861#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78859#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78858#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78857#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78855#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78854#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78853#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78851#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78849#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78848#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78847#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78846#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78845#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78843#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78842#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78840#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78834#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78830#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78828#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78824#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78822#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78818#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78816#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78811#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78742#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78735#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78841#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78839#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78837#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78835#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78833#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78829#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78827#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78823#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78821#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78817#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78815#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78810#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78808#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78790#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78789#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78787#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78785#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78784#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78783#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78782#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78781#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78780#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78778#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78777#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78776#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78775#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78774#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78773#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78772#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78771#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78770#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78768#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78767#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78766#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78765#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78764#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78763#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78762#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78761#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78760#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78759#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78758#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78756#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78755#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78754#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78753#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78752#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78751#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 78750#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78749#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 78748#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 78744#L12-1 [2021-10-28 23:43:39,151 INFO L793 eck$LassoCheckResult]: Loop: 78744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 78743#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 78744#L12-1 [2021-10-28 23:43:39,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:39,152 INFO L85 PathProgramCache]: Analyzing trace with hash -109127424, now seen corresponding path program 39 times [2021-10-28 23:43:39,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:39,152 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120501801] [2021-10-28 23:43:39,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:39,152 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:39,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:39,675 INFO L134 CoverageAnalysis]: Checked inductivity of 63345 backedges. 29304 proven. 23040 refuted. 0 times theorem prover too weak. 11001 trivial. 0 not checked. [2021-10-28 23:43:39,675 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:39,676 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120501801] [2021-10-28 23:43:39,676 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120501801] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:39,676 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [419838578] [2021-10-28 23:43:39,676 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-10-28 23:43:39,676 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:39,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:39,678 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:39,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2021-10-28 23:43:42,818 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 80 check-sat command(s) [2021-10-28 23:43:42,818 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:42,821 INFO L263 TraceCheckSpWp]: Trace formula consists of 522 conjuncts, 21 conjunts are in the unsatisfiable core [2021-10-28 23:43:42,823 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:44,295 INFO L134 CoverageAnalysis]: Checked inductivity of 63345 backedges. 26826 proven. 1278 refuted. 0 times theorem prover too weak. 35241 trivial. 0 not checked. [2021-10-28 23:43:44,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [419838578] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:44,296 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:44,296 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20] total 40 [2021-10-28 23:43:44,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884531469] [2021-10-28 23:43:44,297 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:44,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:44,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 49 times [2021-10-28 23:43:44,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:44,298 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290400611] [2021-10-28 23:43:44,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:44,299 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:44,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:44,329 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:44,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:44,331 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:44,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:44,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-10-28 23:43:44,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=243, Invalid=1317, Unknown=0, NotChecked=0, Total=1560 [2021-10-28 23:43:44,351 INFO L87 Difference]: Start difference. First operand 732 states and 750 transitions. cyclomatic complexity: 23 Second operand has 40 states, 40 states have (on average 3.425) internal successors, (137), 40 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:48,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:43:48,197 INFO L93 Difference]: Finished difference Result 2418 states and 2471 transitions. [2021-10-28 23:43:48,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 187 states. [2021-10-28 23:43:48,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2418 states and 2471 transitions. [2021-10-28 23:43:48,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:48,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2418 states to 1759 states and 1805 transitions. [2021-10-28 23:43:48,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2021-10-28 23:43:48,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112 [2021-10-28 23:43:48,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1759 states and 1805 transitions. [2021-10-28 23:43:48,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:43:48,209 INFO L681 BuchiCegarLoop]: Abstraction has 1759 states and 1805 transitions. [2021-10-28 23:43:48,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1759 states and 1805 transitions. [2021-10-28 23:43:48,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1759 to 962. [2021-10-28 23:43:48,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 962 states, 962 states have (on average 1.024948024948025) internal successors, (986), 961 states have internal predecessors, (986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:43:48,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 962 states to 962 states and 986 transitions. [2021-10-28 23:43:48,223 INFO L704 BuchiCegarLoop]: Abstraction has 962 states and 986 transitions. [2021-10-28 23:43:48,223 INFO L587 BuchiCegarLoop]: Abstraction has 962 states and 986 transitions. [2021-10-28 23:43:48,223 INFO L425 BuchiCegarLoop]: ======== Iteration 54============ [2021-10-28 23:43:48,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 962 states and 986 transitions. [2021-10-28 23:43:48,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:43:48,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:43:48,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:43:48,230 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [208, 208, 188, 20, 1] [2021-10-28 23:43:48,230 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:43:48,231 INFO L791 eck$LassoCheckResult]: Stem: 84118#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 84119#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84121#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84845#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84844#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84843#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84842#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84841#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84839#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84838#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84837#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84836#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84835#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84833#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84831#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84830#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84829#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84828#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84824#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84823#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84821#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84820#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84819#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84817#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84815#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84814#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84813#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84811#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84809#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84808#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84806#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84805#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84803#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84789#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84786#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84785#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84784#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84782#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84781#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84780#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84779#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84778#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84776#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84775#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84774#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84773#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84772#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84770#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84769#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84768#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84767#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84766#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84764#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84763#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84762#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84761#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84760#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84759#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84758#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84757#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84756#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84755#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84754#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84751#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84750#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84749#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84748#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84746#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84745#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84744#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84743#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84742#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84737#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84734#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84729#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84728#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84727#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84726#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84724#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84723#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84722#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84721#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84720#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84719#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84718#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84716#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84715#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84712#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84710#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84709#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84706#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84705#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84704#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84703#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84701#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84700#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84699#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84698#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84697#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84696#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84694#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84693#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84692#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84691#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84688#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84687#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84686#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84685#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84684#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84683#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84682#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84681#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84680#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84679#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84674#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84666#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84665#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84664#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84663#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84659#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84657#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84653#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84652#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84651#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84647#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84646#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84645#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84644#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84643#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84641#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84640#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84639#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84638#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84637#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84635#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84634#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84633#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84632#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84631#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84630#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84629#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84628#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84627#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84626#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84625#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84624#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84623#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84622#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84621#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84616#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84608#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84588#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84587#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84584#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84581#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84579#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84578#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84577#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84573#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84572#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84570#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84559#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84515#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84513#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84511#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84510#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84509#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84508#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84507#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84506#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84505#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84504#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84503#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84502#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84499#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84498#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84497#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84496#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84495#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84494#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84493#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84492#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84489#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84488#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84487#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84486#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84484#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84483#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84481#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84480#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84477#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84474#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84473#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84472#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84471#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84469#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84468#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84467#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84463#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84462#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84461#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84460#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84459#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84458#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84457#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84456#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84455#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84454#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84453#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84452#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84451#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84450#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84449#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84447#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84445#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84444#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84443#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84442#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84441#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84440#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84439#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84438#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84437#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84396#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84391#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84389#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84381#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84357#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84355#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84353#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84351#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84345#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84339#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84333#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84327#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84317#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84315#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84312#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84310#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84300#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84292#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84291#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84288#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84285#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84284#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84283#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84282#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84281#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84280#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84279#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84278#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84277#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84276#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84275#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84274#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84273#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84272#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84271#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84270#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84269#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84268#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84267#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84266#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84265#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84264#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84263#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84262#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84261#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84260#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84259#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84258#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84257#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84256#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84255#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84254#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84253#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84252#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84251#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84250#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84249#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84247#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84245#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84243#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84241#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84237#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84231#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84229#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84225#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84223#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84219#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84217#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84215#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84212#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84122#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84110#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84114#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84248#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84246#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84242#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84240#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84238#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84236#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84234#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84230#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84228#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84224#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84222#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84218#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84216#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84211#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84209#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84188#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84180#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84179#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84176#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84170#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84162#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84161#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84156#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84155#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84150#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84149#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84147#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84143#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84141#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84140#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84139#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84137#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84134#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 84130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84129#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 84128#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 84124#L12-1 [2021-10-28 23:43:48,232 INFO L793 eck$LassoCheckResult]: Loop: 84124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 84123#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 84124#L12-1 [2021-10-28 23:43:48,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:48,232 INFO L85 PathProgramCache]: Analyzing trace with hash -2050240932, now seen corresponding path program 40 times [2021-10-28 23:43:48,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:48,232 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119761820] [2021-10-28 23:43:48,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:48,233 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:48,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-28 23:43:48,690 INFO L134 CoverageAnalysis]: Checked inductivity of 64584 backedges. 27648 proven. 27756 refuted. 0 times theorem prover too weak. 9180 trivial. 0 not checked. [2021-10-28 23:43:48,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-10-28 23:43:48,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119761820] [2021-10-28 23:43:48,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119761820] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:48,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2010325407] [2021-10-28 23:43:48,690 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-10-28 23:43:48,690 INFO L170 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-10-28 23:43:48,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 [2021-10-28 23:43:48,696 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-10-28 23:43:48,697 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2021-10-28 23:43:52,005 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-10-28 23:43:52,005 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-10-28 23:43:52,009 INFO L263 TraceCheckSpWp]: Trace formula consists of 1310 conjuncts, 41 conjunts are in the unsatisfiable core [2021-10-28 23:43:52,012 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-10-28 23:43:53,961 INFO L134 CoverageAnalysis]: Checked inductivity of 64584 backedges. 28590 proven. 27384 refuted. 0 times theorem prover too weak. 8610 trivial. 0 not checked. [2021-10-28 23:43:53,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2010325407] provided 0 perfect and 1 imperfect interpolant sequences [2021-10-28 23:43:53,961 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-10-28 23:43:53,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 41] total 53 [2021-10-28 23:43:53,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545594630] [2021-10-28 23:43:53,963 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-10-28 23:43:53,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:43:53,963 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 50 times [2021-10-28 23:43:53,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:43:53,963 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148308852] [2021-10-28 23:43:53,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:43:53,963 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:43:53,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:53,986 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:43:53,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:43:53,988 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:43:53,999 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-10-28 23:43:53,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2021-10-28 23:43:54,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=512, Invalid=2244, Unknown=0, NotChecked=0, Total=2756 [2021-10-28 23:43:54,000 INFO L87 Difference]: Start difference. First operand 962 states and 986 transitions. cyclomatic complexity: 30 Second operand has 53 states, 53 states have (on average 3.169811320754717) internal successors, (168), 53 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:44:00,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-10-28 23:44:00,007 INFO L93 Difference]: Finished difference Result 1275 states and 1324 transitions. [2021-10-28 23:44:00,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 240 states. [2021-10-28 23:44:00,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1275 states and 1324 transitions. [2021-10-28 23:44:00,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:44:00,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1275 states to 1259 states and 1308 transitions. [2021-10-28 23:44:00,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 130 [2021-10-28 23:44:00,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 130 [2021-10-28 23:44:00,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1259 states and 1308 transitions. [2021-10-28 23:44:00,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2021-10-28 23:44:00,016 INFO L681 BuchiCegarLoop]: Abstraction has 1259 states and 1308 transitions. [2021-10-28 23:44:00,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1259 states and 1308 transitions. [2021-10-28 23:44:00,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1259 to 636. [2021-10-28 23:44:00,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 636 states, 636 states have (on average 1.0188679245283019) internal successors, (648), 635 states have internal predecessors, (648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-10-28 23:44:00,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 648 transitions. [2021-10-28 23:44:00,025 INFO L704 BuchiCegarLoop]: Abstraction has 636 states and 648 transitions. [2021-10-28 23:44:00,025 INFO L587 BuchiCegarLoop]: Abstraction has 636 states and 648 transitions. [2021-10-28 23:44:00,026 INFO L425 BuchiCegarLoop]: ======== Iteration 55============ [2021-10-28 23:44:00,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 648 transitions. [2021-10-28 23:44:00,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-10-28 23:44:00,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-10-28 23:44:00,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-10-28 23:44:00,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [210, 210, 190, 20, 1] [2021-10-28 23:44:00,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-10-28 23:44:00,034 INFO L791 eck$LassoCheckResult]: Stem: 88942#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 88935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88936#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88943#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89570#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89569#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89568#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89567#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89566#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89565#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89564#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89563#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89562#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89560#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89516#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89515#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89514#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89513#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89512#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89511#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89510#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89509#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89508#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89507#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89506#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89504#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89503#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89502#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89501#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89500#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89499#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89497#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89496#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89495#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89494#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89493#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89491#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89490#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89489#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89488#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89487#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89486#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89485#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89484#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89483#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89482#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89481#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89480#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89479#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89478#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89477#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89476#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89475#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89474#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89473#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89472#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89471#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89470#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89469#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89468#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89467#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89466#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89465#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89464#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89463#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89462#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89461#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89460#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89404#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89459#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89457#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89456#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89455#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89454#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89453#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89452#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89451#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89450#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89449#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89448#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89447#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89446#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89445#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89444#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89443#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89442#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89441#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89440#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89439#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89437#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89435#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89433#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89431#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89430#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89429#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89428#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89427#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89426#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89423#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89422#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89421#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89416#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89414#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89412#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89411#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89406#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89353#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89405#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89403#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89401#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89400#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89399#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89395#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89394#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89393#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89392#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89391#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89389#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89388#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89387#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89386#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89385#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89383#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89382#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89381#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89377#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89375#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89374#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89373#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89371#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89370#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89369#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89368#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89361#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89358#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89357#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89356#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89355#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89305#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89354#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89352#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89351#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89350#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89345#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89344#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89334#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89333#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89332#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89331#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89329#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89328#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89327#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89326#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89325#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89324#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89323#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89321#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89320#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89316#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89315#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89312#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89311#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89310#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89308#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89260#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89304#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89303#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89302#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89301#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89300#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89299#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89296#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89293#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89292#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89290#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89288#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89286#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89284#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89279#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89278#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89276#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89274#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89272#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89270#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89269#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89266#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89265#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89263#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89218#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89261#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89259#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89258#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89257#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89256#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89255#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89254#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89253#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89252#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89251#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89249#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89247#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89246#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89245#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89243#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89242#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89241#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89238#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89237#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89235#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89234#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89233#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89231#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89229#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89228#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89227#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89226#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89225#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89224#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89223#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89221#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89220#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89219#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89216#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89215#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89211#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89210#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89209#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89208#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89207#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89204#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89203#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89201#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89199#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89198#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89197#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89196#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89195#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89194#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89193#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89192#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89191#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89190#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89189#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89188#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89187#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89186#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89185#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89184#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89183#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89182#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89177#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89176#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89175#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89162#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89161#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89156#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89155#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89150#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89149#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89148#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89147#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89146#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89144#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89143#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89140#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89139#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89138#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89137#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89136#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89135#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89134#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89133#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89132#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89131#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89130#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89129#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89128#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89127#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89126#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89125#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89124#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89123#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89122#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89121#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89120#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89119#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89118#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89117#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89116#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89115#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89114#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89113#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89112#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89111#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89110#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89109#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89108#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89107#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89106#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89105#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89104#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89103#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89102#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89101#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89100#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89099#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89098#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89097#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89096#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89095#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89094#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89093#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89092#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89091#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89090#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89089#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89088#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89087#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89086#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89085#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89084#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89083#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89082#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89081#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89034#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89077#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89068#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89058#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89046#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89040#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89036#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88945#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88940#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89061#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89045#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89039#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89030#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89024#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89009#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 89008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 89002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 89001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 89000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88998#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88995#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88994#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88993#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88992#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88991#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88988#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88987#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88982#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88981#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88976#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88973#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88971#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88970#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88967#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88965#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88964#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88963#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88962#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88961#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88958#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88955#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88952#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 88951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 88949#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 88948#L12-1 [2021-10-28 23:44:00,034 INFO L793 eck$LassoCheckResult]: Loop: 88948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 88947#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 88948#L12-1 [2021-10-28 23:44:00,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:44:00,035 INFO L85 PathProgramCache]: Analyzing trace with hash -397192768, now seen corresponding path program 41 times [2021-10-28 23:44:00,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:44:00,035 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381024294] [2021-10-28 23:44:00,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:44:00,036 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:44:00,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,233 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:44:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,353 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:44:00,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:44:00,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 51 times [2021-10-28 23:44:00,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:44:00,354 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003638066] [2021-10-28 23:44:00,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:44:00,355 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:44:00,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,446 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:44:00,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,448 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:44:00,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-28 23:44:00,448 INFO L85 PathProgramCache]: Analyzing trace with hash 549839627, now seen corresponding path program 16 times [2021-10-28 23:44:00,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-10-28 23:44:00,449 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111759430] [2021-10-28 23:44:00,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-10-28 23:44:00,449 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-28 23:44:00,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,708 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-28 23:44:00,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-28 23:44:00,818 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-10-28 23:44:45,065 WARN L207 SmtUtils]: Spent 43.83 s on a formula simplification. DAG size of input: 2131 DAG size of output: 679 [2021-10-28 23:44:45,431 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.10 11:44:45 BoogieIcfgContainer [2021-10-28 23:44:45,432 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-10-28 23:44:45,432 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-28 23:44:45,432 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-28 23:44:45,433 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-28 23:44:45,433 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.10 11:40:59" (3/4) ... [2021-10-28 23:44:45,436 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-10-28 23:44:45,596 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/witness.graphml [2021-10-28 23:44:45,596 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-28 23:44:45,597 INFO L168 Benchmark]: Toolchain (without parser) took 226678.56 ms. Allocated memory was 100.7 MB in the beginning and 3.3 GB in the end (delta: 3.1 GB). Free memory was 67.4 MB in the beginning and 798.5 MB in the end (delta: -731.1 MB). Peak memory consumption was 2.4 GB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,597 INFO L168 Benchmark]: CDTParser took 0.31 ms. Allocated memory is still 100.7 MB. Free memory is still 54.0 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 23:44:45,598 INFO L168 Benchmark]: CACSL2BoogieTranslator took 233.58 ms. Allocated memory is still 100.7 MB. Free memory was 67.2 MB in the beginning and 77.4 MB in the end (delta: -10.3 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,598 INFO L168 Benchmark]: Boogie Procedure Inliner took 36.71 ms. Allocated memory is still 100.7 MB. Free memory was 77.4 MB in the beginning and 76.2 MB in the end (delta: 1.2 MB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-28 23:44:45,599 INFO L168 Benchmark]: Boogie Preprocessor took 21.78 ms. Allocated memory is still 100.7 MB. Free memory was 76.2 MB in the beginning and 75.4 MB in the end (delta: 827.0 kB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,599 INFO L168 Benchmark]: RCFGBuilder took 289.07 ms. Allocated memory is still 100.7 MB. Free memory was 75.0 MB in the beginning and 67.5 MB in the end (delta: 7.5 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,600 INFO L168 Benchmark]: BuchiAutomizer took 225921.34 ms. Allocated memory was 100.7 MB in the beginning and 3.3 GB in the end (delta: 3.1 GB). Free memory was 67.5 MB in the beginning and 815.6 MB in the end (delta: -748.1 MB). Peak memory consumption was 2.8 GB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,600 INFO L168 Benchmark]: Witness Printer took 163.72 ms. Allocated memory is still 3.3 GB. Free memory was 815.6 MB in the beginning and 798.5 MB in the end (delta: 17.1 MB). Peak memory consumption was 18.9 MB. Max. memory is 16.1 GB. [2021-10-28 23:44:45,606 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31 ms. Allocated memory is still 100.7 MB. Free memory is still 54.0 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 233.58 ms. Allocated memory is still 100.7 MB. Free memory was 67.2 MB in the beginning and 77.4 MB in the end (delta: -10.3 MB). Peak memory consumption was 8.4 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 36.71 ms. Allocated memory is still 100.7 MB. Free memory was 77.4 MB in the beginning and 76.2 MB in the end (delta: 1.2 MB). There was no memory consumed. Max. memory is 16.1 GB. * Boogie Preprocessor took 21.78 ms. Allocated memory is still 100.7 MB. Free memory was 76.2 MB in the beginning and 75.4 MB in the end (delta: 827.0 kB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 289.07 ms. Allocated memory is still 100.7 MB. Free memory was 75.0 MB in the beginning and 67.5 MB in the end (delta: 7.5 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 225921.34 ms. Allocated memory was 100.7 MB in the beginning and 3.3 GB in the end (delta: 3.1 GB). Free memory was 67.5 MB in the beginning and 815.6 MB in the end (delta: -748.1 MB). Peak memory consumption was 2.8 GB. Max. memory is 16.1 GB. * Witness Printer took 163.72 ms. Allocated memory is still 3.3 GB. Free memory was 815.6 MB in the beginning and 798.5 MB in the end (delta: 17.1 MB). Peak memory consumption was 18.9 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 55 terminating modules (51 trivial, 3 deterministic, 1 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function range + -1 * i and consists of 3 locations. One deterministic module has affine ranking function range + -1 * i and consists of 3 locations. One deterministic module has affine ranking function range and consists of 4 locations. One nondeterministic module has affine ranking function range + -1 * i and consists of 3 locations. 51 modules have a trivial ranking function, the largest among these consists of 56 locations. The remainder module has 636 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 225.7s and 55 iterations. TraceHistogramMax:210. Analysis of lassos took 160.8s. Construction of modules took 11.7s. Büchi inclusion checks took 51.7s. Highest rank in rank-based complementation 3. Minimization of det autom 1. Minimization of nondet autom 54. Automata minimization 0.4s AutomataMinimizationTime, 55 MinimizatonAttempts, 8958 StatesRemovedByMinimization, 50 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 1149 states and ocurred in iteration 47. Nontrivial modules had stage [3, 0, 1, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 2/3 HoareTripleCheckerStatistics: 112 SDtfs, 403 SDslu, 3 SDs, 0 SdLazy, 22025 SolverSat, 2869 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.7s Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT3 conc3 concLT1 SILN47 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital16 mio100 ax171 hnf100 lsp58 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq165 hnf94 smp79 dnf100 smp100 tf109 neg96 sie107 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 47ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 5 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.8s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 11]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {range=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@85acc1c=0, \result=0, i=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 11]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 Loop: [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-10-28 23:44:45,733 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:45,940 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Ended with exit code 0 [2021-10-28 23:44:46,138 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:46,336 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Ended with exit code 0 [2021-10-28 23:44:46,535 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:46,736 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Ended with exit code 0 [2021-10-28 23:44:46,940 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Ended with exit code 0 [2021-10-28 23:44:47,139 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2021-10-28 23:44:47,337 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Ended with exit code 0 [2021-10-28 23:44:47,536 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2021-10-28 23:44:47,735 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2021-10-28 23:44:47,934 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2021-10-28 23:44:48,133 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Ended with exit code 0 [2021-10-28 23:44:48,334 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Ended with exit code 0 [2021-10-28 23:44:48,538 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2021-10-28 23:44:48,736 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Ended with exit code 0 [2021-10-28 23:44:48,933 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2021-10-28 23:44:49,131 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2021-10-28 23:44:49,335 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Ended with exit code 0 [2021-10-28 23:44:49,535 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2021-10-28 23:44:49,734 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:49,934 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2021-10-28 23:44:50,133 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Ended with exit code 0 [2021-10-28 23:44:50,332 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2021-10-28 23:44:50,532 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2021-10-28 23:44:50,734 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:50,932 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2021-10-28 23:44:51,132 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Ended with exit code 0 [2021-10-28 23:44:51,335 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2021-10-28 23:44:51,533 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2021-10-28 23:44:51,733 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2021-10-28 23:44:51,935 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Ended with exit code 0 [2021-10-28 23:44:52,135 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2021-10-28 23:44:52,337 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:52,536 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2021-10-28 23:44:52,736 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2021-10-28 23:44:52,934 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:53,137 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2021-10-28 23:44:53,333 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2021-10-28 23:44:53,536 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2021-10-28 23:44:53,733 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2021-10-28 23:44:53,934 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2021-10-28 23:44:54,137 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2021-10-28 23:44:54,338 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:54,537 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2021-10-28 23:44:54,735 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2021-10-28 23:44:54,935 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2021-10-28 23:44:55,136 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2021-10-28 23:44:55,353 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2264eb13-30dc-4be1-90c2-f85c58d848ab/bin/uautomizer-GMMbpWq8iD/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...