./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9ad7fb26 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f0c25c4595bcff85f43364ad0fa5f5ab2969e78914fb12550c2b3a9f3c584b71 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-9ad7fb2 [2021-11-02 22:59:16,968 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-02 22:59:16,972 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-02 22:59:17,029 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-02 22:59:17,030 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-02 22:59:17,035 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-02 22:59:17,041 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-02 22:59:17,044 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-02 22:59:17,047 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-02 22:59:17,049 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-02 22:59:17,051 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-02 22:59:17,053 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-02 22:59:17,053 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-02 22:59:17,055 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-02 22:59:17,057 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-02 22:59:17,059 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-02 22:59:17,061 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-02 22:59:17,063 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-02 22:59:17,065 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-02 22:59:17,069 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-02 22:59:17,071 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-02 22:59:17,073 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-02 22:59:17,075 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-02 22:59:17,077 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-02 22:59:17,081 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-02 22:59:17,082 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-02 22:59:17,083 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-02 22:59:17,084 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-02 22:59:17,085 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-02 22:59:17,087 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-02 22:59:17,087 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-02 22:59:17,088 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-02 22:59:17,090 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-02 22:59:17,091 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-02 22:59:17,093 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-02 22:59:17,094 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-02 22:59:17,095 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-02 22:59:17,095 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-02 22:59:17,096 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-02 22:59:17,098 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-02 22:59:17,099 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-02 22:59:17,100 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-02 22:59:17,134 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-02 22:59:17,135 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-02 22:59:17,135 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-02 22:59:17,136 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-02 22:59:17,137 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-02 22:59:17,138 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-02 22:59:17,138 INFO L138 SettingsManager]: * Use SBE=true [2021-11-02 22:59:17,138 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-02 22:59:17,139 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-02 22:59:17,139 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-02 22:59:17,139 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-02 22:59:17,140 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-02 22:59:17,140 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-02 22:59:17,140 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-02 22:59:17,141 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-02 22:59:17,141 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-02 22:59:17,141 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-02 22:59:17,142 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-02 22:59:17,142 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-02 22:59:17,142 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-02 22:59:17,142 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-02 22:59:17,143 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-02 22:59:17,143 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-02 22:59:17,143 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-02 22:59:17,144 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-02 22:59:17,144 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-02 22:59:17,144 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-02 22:59:17,145 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-02 22:59:17,145 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-02 22:59:17,145 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-02 22:59:17,146 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-02 22:59:17,146 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-02 22:59:17,147 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-02 22:59:17,148 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f0c25c4595bcff85f43364ad0fa5f5ab2969e78914fb12550c2b3a9f3c584b71 [2021-11-02 22:59:17,486 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-02 22:59:17,529 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-02 22:59:17,534 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-02 22:59:17,535 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-02 22:59:17,537 INFO L275 PluginConnector]: CDTParser initialized [2021-11-02 22:59:17,538 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2021-11-02 22:59:17,655 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/data/9ac94345f/75334c523ccb45c19f6037a855b3be6c/FLAGe5ffb42d3 [2021-11-02 22:59:18,302 INFO L306 CDTParser]: Found 1 translation units. [2021-11-02 22:59:18,303 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2021-11-02 22:59:18,316 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/data/9ac94345f/75334c523ccb45c19f6037a855b3be6c/FLAGe5ffb42d3 [2021-11-02 22:59:18,569 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/data/9ac94345f/75334c523ccb45c19f6037a855b3be6c [2021-11-02 22:59:18,572 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-02 22:59:18,574 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-02 22:59:18,575 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-02 22:59:18,576 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-02 22:59:18,584 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-02 22:59:18,586 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 10:59:18" (1/1) ... [2021-11-02 22:59:18,588 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c4f0ba5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:18, skipping insertion in model container [2021-11-02 22:59:18,588 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 10:59:18" (1/1) ... [2021-11-02 22:59:18,609 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-02 22:59:18,661 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-02 22:59:18,863 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[366,379] [2021-11-02 22:59:18,982 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 22:59:18,995 INFO L203 MainTranslator]: Completed pre-run [2021-11-02 22:59:19,010 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[366,379] [2021-11-02 22:59:19,085 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 22:59:19,112 INFO L208 MainTranslator]: Completed translation [2021-11-02 22:59:19,113 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19 WrapperNode [2021-11-02 22:59:19,113 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-02 22:59:19,115 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-02 22:59:19,115 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-02 22:59:19,115 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-02 22:59:19,125 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,141 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,277 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-02 22:59:19,279 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-02 22:59:19,279 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-02 22:59:19,279 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-02 22:59:19,294 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,295 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,326 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,326 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,379 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,442 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,449 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,467 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-02 22:59:19,469 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-02 22:59:19,469 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-02 22:59:19,469 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-02 22:59:19,470 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (1/1) ... [2021-11-02 22:59:19,507 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-02 22:59:19,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/z3 [2021-11-02 22:59:19,547 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-02 22:59:19,570 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbc0fc3c-4368-4c62-99e8-39ecded77836/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-02 22:59:19,611 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-02 22:59:19,611 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-02 22:59:19,612 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-02 22:59:19,612 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-02 22:59:21,741 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-02 22:59:21,741 INFO L299 CfgBuilder]: Removed 325 assume(true) statements. [2021-11-02 22:59:21,746 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 10:59:21 BoogieIcfgContainer [2021-11-02 22:59:21,746 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-02 22:59:21,748 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-02 22:59:21,748 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-02 22:59:21,753 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-02 22:59:21,754 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:59:21,755 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 10:59:18" (1/3) ... [2021-11-02 22:59:21,757 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5da391ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 10:59:21, skipping insertion in model container [2021-11-02 22:59:21,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:59:21,758 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:59:19" (2/3) ... [2021-11-02 22:59:21,758 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5da391ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 10:59:21, skipping insertion in model container [2021-11-02 22:59:21,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:59:21,758 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 10:59:21" (3/3) ... [2021-11-02 22:59:21,760 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2021-11-02 22:59:21,823 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-02 22:59:21,823 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-02 22:59:21,824 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-02 22:59:21,824 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-02 22:59:21,824 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-02 22:59:21,825 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-02 22:59:21,825 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-02 22:59:21,825 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-02 22:59:21,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 973 states, 972 states have (on average 1.5277777777777777) internal successors, (1485), 972 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:22,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 858 [2021-11-02 22:59:22,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:22,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:22,032 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,033 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-02 22:59:22,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 973 states, 972 states have (on average 1.5277777777777777) internal successors, (1485), 972 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:22,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 858 [2021-11-02 22:59:22,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:22,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:22,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,088 INFO L791 eck$LassoCheckResult]: Stem: 446#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 890#L-1true havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 878#L1258true havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 456#L582true assume !(1 == ~m_i~0);~m_st~0 := 2; 559#L589-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 262#L594-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 628#L599-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 19#L604-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16#L609-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 72#L614-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 119#L619-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 673#L624-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 930#L629-1true assume 0 == ~M_E~0;~M_E~0 := 1; 118#L846-1true assume !(0 == ~T1_E~0); 906#L851-1true assume !(0 == ~T2_E~0); 131#L856-1true assume !(0 == ~T3_E~0); 478#L861-1true assume !(0 == ~T4_E~0); 517#L866-1true assume !(0 == ~T5_E~0); 411#L871-1true assume !(0 == ~T6_E~0); 806#L876-1true assume !(0 == ~T7_E~0); 794#L881-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 421#L886-1true assume !(0 == ~E_M~0); 265#L891-1true assume !(0 == ~E_1~0); 413#L896-1true assume !(0 == ~E_2~0); 545#L901-1true assume !(0 == ~E_3~0); 436#L906-1true assume !(0 == ~E_4~0); 829#L911-1true assume !(0 == ~E_5~0); 296#L916-1true assume !(0 == ~E_6~0); 550#L921-1true assume 0 == ~E_7~0;~E_7~0 := 1; 704#L926-1true assume !(0 == ~E_8~0); 842#L931-1true havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812#L410true assume !(1 == ~m_pc~0); 228#L410-2true is_master_triggered_~__retres1~0 := 0; 738#L421true is_master_triggered_#res := is_master_triggered_~__retres1~0; 874#L422true activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 518#L1053true assume !(0 != activate_threads_~tmp~1); 587#L1053-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 670#L429true assume 1 == ~t1_pc~0; 873#L430true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 946#L440true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22#L441true activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 575#L1061true assume !(0 != activate_threads_~tmp___0~0); 475#L1061-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 582#L448true assume !(1 == ~t2_pc~0); 76#L448-2true is_transmit2_triggered_~__retres1~2 := 0; 231#L459true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 773#L460true activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 176#L1069true assume !(0 != activate_threads_~tmp___1~0); 787#L1069-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 849#L467true assume 1 == ~t3_pc~0; 337#L468true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 111#L478true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 403#L479true activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 612#L1077true assume !(0 != activate_threads_~tmp___2~0); 314#L1077-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 83#L486true assume !(1 == ~t4_pc~0); 835#L486-2true is_transmit4_triggered_~__retres1~4 := 0; 447#L497true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75#L498true activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 760#L1085true assume !(0 != activate_threads_~tmp___3~0); 177#L1085-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 381#L505true assume 1 == ~t5_pc~0; 334#L506true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 934#L516true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 935#L517true activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 933#L1093true assume !(0 != activate_threads_~tmp___4~0); 412#L1093-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 881#L524true assume 1 == ~t6_pc~0; 223#L525true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 422#L535true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 657#L536true activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 66#L1101true assume !(0 != activate_threads_~tmp___5~0); 862#L1101-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 267#L543true assume !(1 == ~t7_pc~0); 969#L543-2true is_transmit7_triggered_~__retres1~7 := 0; 720#L554true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 454#L555true activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 811#L1109true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 161#L1109-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 416#L562true assume 1 == ~t8_pc~0; 654#L563true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 768#L573true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40#L574true activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 972#L1117true assume !(0 != activate_threads_~tmp___7~0); 917#L1117-2true assume !(1 == ~M_E~0); 610#L944-1true assume !(1 == ~T1_E~0); 284#L949-1true assume !(1 == ~T2_E~0); 283#L954-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 899#L959-1true assume !(1 == ~T4_E~0); 634#L964-1true assume !(1 == ~T5_E~0); 149#L969-1true assume !(1 == ~T6_E~0); 719#L974-1true assume !(1 == ~T7_E~0); 569#L979-1true assume !(1 == ~T8_E~0); 918#L984-1true assume !(1 == ~E_M~0); 229#L989-1true assume !(1 == ~E_1~0); 415#L994-1true assume 1 == ~E_2~0;~E_2~0 := 2; 172#L999-1true assume !(1 == ~E_3~0); 541#L1004-1true assume !(1 == ~E_4~0); 31#L1009-1true assume !(1 == ~E_5~0); 168#L1014-1true assume !(1 == ~E_6~0); 513#L1019-1true assume !(1 == ~E_7~0); 750#L1024-1true assume !(1 == ~E_8~0); 271#L1295-1true [2021-11-02 22:59:22,096 INFO L793 eck$LassoCheckResult]: Loop: 271#L1295-1true assume !false; 709#L1296true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 583#L821true assume !true; 727#L836true start_simulation_~kernel_st~0 := 2; 742#L582-1true start_simulation_~kernel_st~0 := 3; 28#L846-2true assume 0 == ~M_E~0;~M_E~0 := 1; 7#L846-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 350#L851-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 64#L856-3true assume !(0 == ~T3_E~0); 486#L861-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 25#L866-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 180#L871-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 252#L876-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 191#L881-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 630#L886-3true assume 0 == ~E_M~0;~E_M~0 := 1; 319#L891-3true assume 0 == ~E_1~0;~E_1~0 := 1; 417#L896-3true assume !(0 == ~E_2~0); 234#L901-3true assume 0 == ~E_3~0;~E_3~0 := 1; 321#L906-3true assume 0 == ~E_4~0;~E_4~0 := 1; 557#L911-3true assume 0 == ~E_5~0;~E_5~0 := 1; 463#L916-3true assume 0 == ~E_6~0;~E_6~0 := 1; 199#L921-3true assume 0 == ~E_7~0;~E_7~0 := 1; 448#L926-3true assume 0 == ~E_8~0;~E_8~0 := 1; 551#L931-3true havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59#L410-30true assume 1 == ~m_pc~0; 29#L411-10true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 146#L421-10true is_master_triggered_#res := is_master_triggered_~__retres1~0; 277#L422-10true activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 679#L1053-30true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 952#L1053-32true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 780#L429-30true assume 1 == ~t1_pc~0; 279#L430-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 915#L440-10true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 240#L441-10true activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 796#L1061-30true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 128#L1061-32true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 552#L448-30true assume !(1 == ~t2_pc~0); 686#L448-32true is_transmit2_triggered_~__retres1~2 := 0; 651#L459-10true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30#L460-10true activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 876#L1069-30true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 850#L1069-32true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 879#L467-30true assume !(1 == ~t3_pc~0); 717#L467-32true is_transmit3_triggered_~__retres1~3 := 0; 364#L478-10true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 563#L479-10true activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 81#L1077-30true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 258#L1077-32true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 462#L486-30true assume 1 == ~t4_pc~0; 781#L487-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 309#L497-10true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 813#L498-10true activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 865#L1085-30true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 195#L1085-32true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 122#L505-30true assume !(1 == ~t5_pc~0); 923#L505-32true is_transmit5_triggered_~__retres1~5 := 0; 680#L516-10true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 275#L517-10true activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 889#L1093-30true assume !(0 != activate_threads_~tmp___4~0); 659#L1093-32true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 771#L524-30true assume !(1 == ~t6_pc~0); 502#L524-32true is_transmit6_triggered_~__retres1~6 := 0; 792#L535-10true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 885#L536-10true activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 506#L1101-30true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 759#L1101-32true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 140#L543-30true assume 1 == ~t7_pc~0; 67#L544-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 755#L554-10true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 844#L555-10true activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 579#L1109-30true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 90#L1109-32true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 343#L562-30true assume 1 == ~t8_pc~0; 85#L563-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26#L573-10true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 98#L574-10true activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13#L1117-30true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 178#L1117-32true assume 1 == ~M_E~0;~M_E~0 := 2; 112#L944-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 4#L949-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 581#L954-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 291#L959-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 32#L964-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 203#L969-3true assume !(1 == ~T6_E~0); 110#L974-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 886#L979-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 341#L984-3true assume 1 == ~E_M~0;~E_M~0 := 2; 947#L989-3true assume 1 == ~E_1~0;~E_1~0 := 2; 138#L994-3true assume 1 == ~E_2~0;~E_2~0 := 2; 790#L999-3true assume 1 == ~E_3~0;~E_3~0 := 2; 440#L1004-3true assume 1 == ~E_4~0;~E_4~0 := 2; 58#L1009-3true assume !(1 == ~E_5~0); 504#L1014-3true assume 1 == ~E_6~0;~E_6~0 := 2; 329#L1019-3true assume 1 == ~E_7~0;~E_7~0 := 2; 931#L1024-3true assume 1 == ~E_8~0;~E_8~0 := 2; 315#L1029-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 803#L642-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 189#L689-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 725#L690-1true start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 368#L1314true assume !(0 == start_simulation_~tmp~3); 818#L1314-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 749#L642-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 909#L689-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 735#L690-2true stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 427#L1269true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 807#L1276true stop_simulation_#res := stop_simulation_~__retres2~0; 20#L1277true start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 106#L1327true assume !(0 != start_simulation_~tmp___0~1); 271#L1295-1true [2021-11-02 22:59:22,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:22,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1715933315, now seen corresponding path program 1 times [2021-11-02 22:59:22,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:22,119 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079552988] [2021-11-02 22:59:22,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:22,121 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:22,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:22,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:22,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:22,476 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079552988] [2021-11-02 22:59:22,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079552988] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:22,477 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:22,478 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:22,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338806122] [2021-11-02 22:59:22,487 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:22,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:22,488 INFO L85 PathProgramCache]: Analyzing trace with hash 1666094012, now seen corresponding path program 1 times [2021-11-02 22:59:22,488 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:22,489 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324758124] [2021-11-02 22:59:22,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:22,489 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:22,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:22,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:22,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:22,539 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324758124] [2021-11-02 22:59:22,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324758124] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:22,540 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:22,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:59:22,541 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449736771] [2021-11-02 22:59:22,543 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:22,544 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:22,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:22,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:22,574 INFO L87 Difference]: Start difference. First operand has 973 states, 972 states have (on average 1.5277777777777777) internal successors, (1485), 972 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:22,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:22,682 INFO L93 Difference]: Finished difference Result 973 states and 1461 transitions. [2021-11-02 22:59:22,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:22,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1461 transitions. [2021-11-02 22:59:22,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:22,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 968 states and 1456 transitions. [2021-11-02 22:59:22,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:22,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:22,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1456 transitions. [2021-11-02 22:59:22,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:22,756 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1456 transitions. [2021-11-02 22:59:22,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1456 transitions. [2021-11-02 22:59:22,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:22,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.5041322314049588) internal successors, (1456), 967 states have internal predecessors, (1456), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:22,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1456 transitions. [2021-11-02 22:59:22,881 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1456 transitions. [2021-11-02 22:59:22,882 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1456 transitions. [2021-11-02 22:59:22,882 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-02 22:59:22,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1456 transitions. [2021-11-02 22:59:22,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:22,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:22,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:22,904 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,904 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:22,906 INFO L791 eck$LassoCheckResult]: Stem: 2670#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2671#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2910#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2683#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 2684#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2431#L594-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2432#L599-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1991#L604-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1985#L609-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1986#L614-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2103#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2193#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2843#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 2191#L846-1 assume !(0 == ~T1_E~0); 2192#L851-1 assume !(0 == ~T2_E~0); 2221#L856-1 assume !(0 == ~T3_E~0); 2222#L861-1 assume !(0 == ~T4_E~0); 2707#L866-1 assume !(0 == ~T5_E~0); 2633#L871-1 assume !(0 == ~T6_E~0); 2634#L876-1 assume !(0 == ~T7_E~0); 2894#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2644#L886-1 assume !(0 == ~E_M~0); 2435#L891-1 assume !(0 == ~E_1~0); 2436#L896-1 assume !(0 == ~E_2~0); 2637#L901-1 assume !(0 == ~E_3~0); 2660#L906-1 assume !(0 == ~E_4~0); 2661#L911-1 assume !(0 == ~E_5~0); 2476#L916-1 assume !(0 == ~E_6~0); 2477#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 2772#L926-1 assume !(0 == ~E_8~0); 2857#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2898#L410 assume !(1 == ~m_pc~0); 2380#L410-2 is_master_triggered_~__retres1~0 := 0; 2381#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2872#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2748#L1053 assume !(0 != activate_threads_~tmp~1); 2749#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2798#L429 assume 1 == ~t1_pc~0; 2840#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2736#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1996#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1997#L1061 assume !(0 != activate_threads_~tmp___0~0); 2702#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2703#L448 assume !(1 == ~t2_pc~0); 2110#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 2111#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2386#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2295#L1069 assume !(0 != activate_threads_~tmp___1~0); 2296#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2889#L467 assume 1 == ~t3_pc~0; 2539#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2177#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2178#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2622#L1077 assume !(0 != activate_threads_~tmp___2~0); 2501#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2126#L486 assume !(1 == ~t4_pc~0); 2127#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 2672#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2108#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2109#L1085 assume !(0 != activate_threads_~tmp___3~0); 2297#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2298#L505 assume 1 == ~t5_pc~0; 2532#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2533#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2921#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2920#L1093 assume !(0 != activate_threads_~tmp___4~0); 2635#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2636#L524 assume 1 == ~t6_pc~0; 2371#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2372#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2645#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2089#L1101 assume !(0 != activate_threads_~tmp___5~0); 2090#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2438#L543 assume !(1 == ~t7_pc~0); 2439#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 2530#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2680#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2681#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2272#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2273#L562 assume 1 == ~t8_pc~0; 2639#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2826#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2036#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2037#L1117 assume !(0 != activate_threads_~tmp___7~0); 2916#L1117-2 assume !(1 == ~M_E~0); 2813#L944-1 assume !(1 == ~T1_E~0); 2462#L949-1 assume !(1 == ~T2_E~0); 2460#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2461#L959-1 assume !(1 == ~T4_E~0); 2821#L964-1 assume !(1 == ~T5_E~0); 2252#L969-1 assume !(1 == ~T6_E~0); 2253#L974-1 assume !(1 == ~T7_E~0); 2784#L979-1 assume !(1 == ~T8_E~0); 2785#L984-1 assume !(1 == ~E_M~0); 2382#L989-1 assume !(1 == ~E_1~0); 2383#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2289#L999-1 assume !(1 == ~E_3~0); 2290#L1004-1 assume !(1 == ~E_4~0); 2013#L1009-1 assume !(1 == ~E_5~0); 2014#L1014-1 assume !(1 == ~E_6~0); 2280#L1019-1 assume !(1 == ~E_7~0); 2745#L1024-1 assume !(1 == ~E_8~0); 2170#L1295-1 [2021-11-02 22:59:22,908 INFO L793 eck$LassoCheckResult]: Loop: 2170#L1295-1 assume !false; 2444#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2187#L821 assume !false; 2795#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2031#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2033#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2839#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2610#L704 assume !(0 != eval_~tmp~0); 2612#L836 start_simulation_~kernel_st~0 := 2; 2866#L582-1 start_simulation_~kernel_st~0 := 3; 2007#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1964#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1965#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2084#L856-3 assume !(0 == ~T3_E~0); 2085#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2001#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2002#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2300#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2314#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2315#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2510#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2511#L896-3 assume !(0 == ~E_2~0); 2390#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2391#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2514#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2690#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2328#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2329#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2673#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2076#L410-30 assume 1 == ~m_pc~0; 2008#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2010#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2248#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2452#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2844#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2885#L429-30 assume 1 == ~t1_pc~0; 2456#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2430#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2397#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2398#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2215#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2216#L448-30 assume 1 == ~t2_pc~0; 2737#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2738#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2011#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2012#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2905#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2906#L467-30 assume !(1 == ~t3_pc~0); 2864#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 2573#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2574#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2122#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2123#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2423#L486-30 assume 1 == ~t4_pc~0; 2688#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2491#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2492#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2899#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2322#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2202#L505-30 assume !(1 == ~t5_pc~0); 2203#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 2847#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2450#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2451#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 2828#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2829#L524-30 assume 1 == ~t6_pc~0; 2883#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2728#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2892#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2730#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2731#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2240#L543-30 assume 1 == ~t7_pc~0; 2093#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2095#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2879#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2793#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2142#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2143#L562-30 assume 1 == ~t8_pc~0; 2130#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2003#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2004#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1978#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1979#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 2179#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1957#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1958#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2470#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2015#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2016#L969-3 assume !(1 == ~T6_E~0); 2175#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2176#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2546#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2547#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2235#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2236#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2663#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2074#L1009-3 assume !(1 == ~E_5~0); 2075#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2528#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2529#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2502#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2503#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2195#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2313#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 2579#L1314 assume !(0 == start_simulation_~tmp~3); 2581#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2877#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2072#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2870#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 2650#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2651#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 1992#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 1993#L1327 assume !(0 != start_simulation_~tmp___0~1); 2170#L1295-1 [2021-11-02 22:59:22,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:22,910 INFO L85 PathProgramCache]: Analyzing trace with hash 684892417, now seen corresponding path program 1 times [2021-11-02 22:59:22,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:22,911 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357680956] [2021-11-02 22:59:22,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:22,913 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:22,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,060 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,061 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357680956] [2021-11-02 22:59:23,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [357680956] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,061 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119760007] [2021-11-02 22:59:23,063 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:23,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,064 INFO L85 PathProgramCache]: Analyzing trace with hash -173652646, now seen corresponding path program 1 times [2021-11-02 22:59:23,064 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,064 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103737654] [2021-11-02 22:59:23,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,065 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,178 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,179 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103737654] [2021-11-02 22:59:23,181 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103737654] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,182 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,182 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,182 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394498502] [2021-11-02 22:59:23,182 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:23,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:23,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:23,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:23,184 INFO L87 Difference]: Start difference. First operand 968 states and 1456 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:23,223 INFO L93 Difference]: Finished difference Result 968 states and 1455 transitions. [2021-11-02 22:59:23,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:23,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1455 transitions. [2021-11-02 22:59:23,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1455 transitions. [2021-11-02 22:59:23,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:23,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:23,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1455 transitions. [2021-11-02 22:59:23,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:23,251 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1455 transitions. [2021-11-02 22:59:23,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1455 transitions. [2021-11-02 22:59:23,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:23,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.503099173553719) internal successors, (1455), 967 states have internal predecessors, (1455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1455 transitions. [2021-11-02 22:59:23,281 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1455 transitions. [2021-11-02 22:59:23,281 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1455 transitions. [2021-11-02 22:59:23,282 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-02 22:59:23,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1455 transitions. [2021-11-02 22:59:23,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:23,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:23,293 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,293 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,294 INFO L791 eck$LassoCheckResult]: Stem: 4613#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4614#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4853#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4626#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 4627#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4374#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4375#L599-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3934#L604-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3928#L609-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3929#L614-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4046#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4136#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4786#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 4134#L846-1 assume !(0 == ~T1_E~0); 4135#L851-1 assume !(0 == ~T2_E~0); 4164#L856-1 assume !(0 == ~T3_E~0); 4165#L861-1 assume !(0 == ~T4_E~0); 4650#L866-1 assume !(0 == ~T5_E~0); 4576#L871-1 assume !(0 == ~T6_E~0); 4577#L876-1 assume !(0 == ~T7_E~0); 4837#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4587#L886-1 assume !(0 == ~E_M~0); 4378#L891-1 assume !(0 == ~E_1~0); 4379#L896-1 assume !(0 == ~E_2~0); 4580#L901-1 assume !(0 == ~E_3~0); 4603#L906-1 assume !(0 == ~E_4~0); 4604#L911-1 assume !(0 == ~E_5~0); 4419#L916-1 assume !(0 == ~E_6~0); 4420#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4715#L926-1 assume !(0 == ~E_8~0); 4800#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4841#L410 assume !(1 == ~m_pc~0); 4323#L410-2 is_master_triggered_~__retres1~0 := 0; 4324#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4815#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4691#L1053 assume !(0 != activate_threads_~tmp~1); 4692#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4741#L429 assume 1 == ~t1_pc~0; 4783#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4679#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3939#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3940#L1061 assume !(0 != activate_threads_~tmp___0~0); 4645#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4646#L448 assume !(1 == ~t2_pc~0); 4053#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 4054#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4329#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4238#L1069 assume !(0 != activate_threads_~tmp___1~0); 4239#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4832#L467 assume 1 == ~t3_pc~0; 4482#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4120#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4121#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4565#L1077 assume !(0 != activate_threads_~tmp___2~0); 4444#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4069#L486 assume !(1 == ~t4_pc~0); 4070#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 4615#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4051#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4052#L1085 assume !(0 != activate_threads_~tmp___3~0); 4240#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4241#L505 assume 1 == ~t5_pc~0; 4475#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4476#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4864#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4863#L1093 assume !(0 != activate_threads_~tmp___4~0); 4578#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4579#L524 assume 1 == ~t6_pc~0; 4314#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4315#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4588#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4032#L1101 assume !(0 != activate_threads_~tmp___5~0); 4033#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4381#L543 assume !(1 == ~t7_pc~0); 4382#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 4473#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4623#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4624#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4215#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4216#L562 assume 1 == ~t8_pc~0; 4582#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4769#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3979#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3980#L1117 assume !(0 != activate_threads_~tmp___7~0); 4859#L1117-2 assume !(1 == ~M_E~0); 4756#L944-1 assume !(1 == ~T1_E~0); 4405#L949-1 assume !(1 == ~T2_E~0); 4403#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4404#L959-1 assume !(1 == ~T4_E~0); 4764#L964-1 assume !(1 == ~T5_E~0); 4195#L969-1 assume !(1 == ~T6_E~0); 4196#L974-1 assume !(1 == ~T7_E~0); 4727#L979-1 assume !(1 == ~T8_E~0); 4728#L984-1 assume !(1 == ~E_M~0); 4325#L989-1 assume !(1 == ~E_1~0); 4326#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4232#L999-1 assume !(1 == ~E_3~0); 4233#L1004-1 assume !(1 == ~E_4~0); 3956#L1009-1 assume !(1 == ~E_5~0); 3957#L1014-1 assume !(1 == ~E_6~0); 4223#L1019-1 assume !(1 == ~E_7~0); 4688#L1024-1 assume !(1 == ~E_8~0); 4113#L1295-1 [2021-11-02 22:59:23,295 INFO L793 eck$LassoCheckResult]: Loop: 4113#L1295-1 assume !false; 4387#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4130#L821 assume !false; 4738#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3974#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3976#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4782#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4553#L704 assume !(0 != eval_~tmp~0); 4555#L836 start_simulation_~kernel_st~0 := 2; 4809#L582-1 start_simulation_~kernel_st~0 := 3; 3950#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3907#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3908#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4027#L856-3 assume !(0 == ~T3_E~0); 4028#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3944#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3945#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4243#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4257#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4258#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4453#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4454#L896-3 assume !(0 == ~E_2~0); 4333#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4334#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4457#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4633#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4271#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4272#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4616#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4019#L410-30 assume !(1 == ~m_pc~0); 3952#L410-32 is_master_triggered_~__retres1~0 := 0; 3953#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4191#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4395#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4787#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4828#L429-30 assume !(1 == ~t1_pc~0); 4372#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 4373#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4340#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4341#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4158#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4159#L448-30 assume 1 == ~t2_pc~0; 4680#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4681#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3954#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3955#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4848#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4849#L467-30 assume 1 == ~t3_pc~0; 4851#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4516#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4517#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4065#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4066#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4366#L486-30 assume 1 == ~t4_pc~0; 4631#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4434#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4435#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4842#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4265#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4145#L505-30 assume !(1 == ~t5_pc~0); 4146#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 4790#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4393#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4394#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 4771#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4772#L524-30 assume 1 == ~t6_pc~0; 4826#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4671#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4835#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4673#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4674#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4183#L543-30 assume 1 == ~t7_pc~0; 4036#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4038#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4822#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4736#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4085#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4086#L562-30 assume 1 == ~t8_pc~0; 4073#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3946#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3947#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3921#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 3922#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 4122#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3900#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3901#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4413#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3958#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3959#L969-3 assume !(1 == ~T6_E~0); 4118#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4119#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4489#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4490#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4178#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4179#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4606#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4017#L1009-3 assume !(1 == ~E_5~0); 4018#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4471#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4472#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4445#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4446#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4138#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4256#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 4522#L1314 assume !(0 == start_simulation_~tmp~3); 4524#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4820#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4015#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4813#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 4593#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4594#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 3935#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 3936#L1327 assume !(0 != start_simulation_~tmp___0~1); 4113#L1295-1 [2021-11-02 22:59:23,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,296 INFO L85 PathProgramCache]: Analyzing trace with hash -916178689, now seen corresponding path program 1 times [2021-11-02 22:59:23,296 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,296 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079514116] [2021-11-02 22:59:23,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,297 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,349 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,350 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079514116] [2021-11-02 22:59:23,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079514116] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,350 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888200256] [2021-11-02 22:59:23,352 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:23,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,353 INFO L85 PathProgramCache]: Analyzing trace with hash -727736839, now seen corresponding path program 1 times [2021-11-02 22:59:23,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,353 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253014001] [2021-11-02 22:59:23,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,478 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,478 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253014001] [2021-11-02 22:59:23,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253014001] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,479 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787352934] [2021-11-02 22:59:23,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:23,480 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:23,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:23,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:23,481 INFO L87 Difference]: Start difference. First operand 968 states and 1455 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:23,508 INFO L93 Difference]: Finished difference Result 968 states and 1454 transitions. [2021-11-02 22:59:23,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:23,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1454 transitions. [2021-11-02 22:59:23,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1454 transitions. [2021-11-02 22:59:23,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:23,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:23,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1454 transitions. [2021-11-02 22:59:23,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:23,539 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1454 transitions. [2021-11-02 22:59:23,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1454 transitions. [2021-11-02 22:59:23,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:23,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.5020661157024793) internal successors, (1454), 967 states have internal predecessors, (1454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1454 transitions. [2021-11-02 22:59:23,568 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1454 transitions. [2021-11-02 22:59:23,568 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1454 transitions. [2021-11-02 22:59:23,568 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-02 22:59:23,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1454 transitions. [2021-11-02 22:59:23,612 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:23,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:23,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,616 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,616 INFO L791 eck$LassoCheckResult]: Stem: 6556#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6557#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6796#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6569#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 6570#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6317#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6318#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5877#L604-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5871#L609-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5872#L614-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5989#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6079#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6729#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6077#L846-1 assume !(0 == ~T1_E~0); 6078#L851-1 assume !(0 == ~T2_E~0); 6107#L856-1 assume !(0 == ~T3_E~0); 6108#L861-1 assume !(0 == ~T4_E~0); 6593#L866-1 assume !(0 == ~T5_E~0); 6519#L871-1 assume !(0 == ~T6_E~0); 6520#L876-1 assume !(0 == ~T7_E~0); 6780#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6530#L886-1 assume !(0 == ~E_M~0); 6321#L891-1 assume !(0 == ~E_1~0); 6322#L896-1 assume !(0 == ~E_2~0); 6523#L901-1 assume !(0 == ~E_3~0); 6546#L906-1 assume !(0 == ~E_4~0); 6547#L911-1 assume !(0 == ~E_5~0); 6362#L916-1 assume !(0 == ~E_6~0); 6363#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6658#L926-1 assume !(0 == ~E_8~0); 6743#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6784#L410 assume !(1 == ~m_pc~0); 6266#L410-2 is_master_triggered_~__retres1~0 := 0; 6267#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6758#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6634#L1053 assume !(0 != activate_threads_~tmp~1); 6635#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6684#L429 assume 1 == ~t1_pc~0; 6726#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6622#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5882#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5883#L1061 assume !(0 != activate_threads_~tmp___0~0); 6588#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6589#L448 assume !(1 == ~t2_pc~0); 5996#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 5997#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6272#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6181#L1069 assume !(0 != activate_threads_~tmp___1~0); 6182#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6775#L467 assume 1 == ~t3_pc~0; 6425#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6063#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6064#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6508#L1077 assume !(0 != activate_threads_~tmp___2~0); 6387#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6012#L486 assume !(1 == ~t4_pc~0); 6013#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 6558#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5994#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5995#L1085 assume !(0 != activate_threads_~tmp___3~0); 6183#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6184#L505 assume 1 == ~t5_pc~0; 6418#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6419#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6807#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6806#L1093 assume !(0 != activate_threads_~tmp___4~0); 6521#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6522#L524 assume 1 == ~t6_pc~0; 6257#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6258#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6531#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5975#L1101 assume !(0 != activate_threads_~tmp___5~0); 5976#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6324#L543 assume !(1 == ~t7_pc~0); 6325#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 6416#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6566#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6567#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6158#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6159#L562 assume 1 == ~t8_pc~0; 6525#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6712#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5922#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5923#L1117 assume !(0 != activate_threads_~tmp___7~0); 6802#L1117-2 assume !(1 == ~M_E~0); 6699#L944-1 assume !(1 == ~T1_E~0); 6348#L949-1 assume !(1 == ~T2_E~0); 6346#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6347#L959-1 assume !(1 == ~T4_E~0); 6707#L964-1 assume !(1 == ~T5_E~0); 6138#L969-1 assume !(1 == ~T6_E~0); 6139#L974-1 assume !(1 == ~T7_E~0); 6670#L979-1 assume !(1 == ~T8_E~0); 6671#L984-1 assume !(1 == ~E_M~0); 6268#L989-1 assume !(1 == ~E_1~0); 6269#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6175#L999-1 assume !(1 == ~E_3~0); 6176#L1004-1 assume !(1 == ~E_4~0); 5899#L1009-1 assume !(1 == ~E_5~0); 5900#L1014-1 assume !(1 == ~E_6~0); 6166#L1019-1 assume !(1 == ~E_7~0); 6631#L1024-1 assume !(1 == ~E_8~0); 6056#L1295-1 [2021-11-02 22:59:23,617 INFO L793 eck$LassoCheckResult]: Loop: 6056#L1295-1 assume !false; 6330#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 6073#L821 assume !false; 6681#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5917#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5919#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6725#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6496#L704 assume !(0 != eval_~tmp~0); 6498#L836 start_simulation_~kernel_st~0 := 2; 6752#L582-1 start_simulation_~kernel_st~0 := 3; 5893#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5850#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5851#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5970#L856-3 assume !(0 == ~T3_E~0); 5971#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5887#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5888#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6186#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6200#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6201#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6396#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6397#L896-3 assume !(0 == ~E_2~0); 6276#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6277#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6400#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6576#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6214#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6215#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6559#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5962#L410-30 assume 1 == ~m_pc~0; 5894#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5896#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6134#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6338#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6730#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6771#L429-30 assume 1 == ~t1_pc~0; 6342#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6316#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6283#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6284#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6101#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6102#L448-30 assume !(1 == ~t2_pc~0); 6625#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 6624#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5897#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5898#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6791#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6792#L467-30 assume 1 == ~t3_pc~0; 6794#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6459#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6460#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6008#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6009#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6309#L486-30 assume 1 == ~t4_pc~0; 6574#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6377#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6378#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6785#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6208#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6088#L505-30 assume !(1 == ~t5_pc~0); 6089#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 6733#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6336#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6337#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 6714#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6715#L524-30 assume 1 == ~t6_pc~0; 6769#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6614#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6778#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6616#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6617#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6126#L543-30 assume 1 == ~t7_pc~0; 5979#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5981#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6765#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6679#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6028#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6029#L562-30 assume 1 == ~t8_pc~0; 6016#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5889#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5890#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5864#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5865#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 6065#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5843#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5844#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6356#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5901#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5902#L969-3 assume !(1 == ~T6_E~0); 6061#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6062#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6432#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6433#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6121#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6122#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6549#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5960#L1009-3 assume !(1 == ~E_5~0); 5961#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6414#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6415#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6388#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6389#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6081#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6199#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 6465#L1314 assume !(0 == start_simulation_~tmp~3); 6467#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6763#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5958#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6756#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 6536#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6537#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 5878#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 5879#L1327 assume !(0 != start_simulation_~tmp___0~1); 6056#L1295-1 [2021-11-02 22:59:23,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,618 INFO L85 PathProgramCache]: Analyzing trace with hash 140552513, now seen corresponding path program 1 times [2021-11-02 22:59:23,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,619 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160390180] [2021-11-02 22:59:23,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,620 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,715 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160390180] [2021-11-02 22:59:23,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160390180] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,716 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,717 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725239242] [2021-11-02 22:59:23,719 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:23,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,721 INFO L85 PathProgramCache]: Analyzing trace with hash 518906394, now seen corresponding path program 1 times [2021-11-02 22:59:23,721 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842807251] [2021-11-02 22:59:23,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,824 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,826 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842807251] [2021-11-02 22:59:23,826 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842807251] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,827 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,828 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587117954] [2021-11-02 22:59:23,828 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:23,829 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:23,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:23,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:23,836 INFO L87 Difference]: Start difference. First operand 968 states and 1454 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:23,861 INFO L93 Difference]: Finished difference Result 968 states and 1453 transitions. [2021-11-02 22:59:23,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:23,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1453 transitions. [2021-11-02 22:59:23,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1453 transitions. [2021-11-02 22:59:23,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:23,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:23,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1453 transitions. [2021-11-02 22:59:23,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:23,888 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1453 transitions. [2021-11-02 22:59:23,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1453 transitions. [2021-11-02 22:59:23,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:23,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.5010330578512396) internal successors, (1453), 967 states have internal predecessors, (1453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:23,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1453 transitions. [2021-11-02 22:59:23,918 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1453 transitions. [2021-11-02 22:59:23,918 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1453 transitions. [2021-11-02 22:59:23,919 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-02 22:59:23,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1453 transitions. [2021-11-02 22:59:23,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:23,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:23,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:23,929 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,929 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:23,930 INFO L791 eck$LassoCheckResult]: Stem: 8499#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8500#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8739#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8512#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 8513#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8260#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8261#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7820#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7814#L609-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7815#L614-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7932#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8022#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8672#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 8020#L846-1 assume !(0 == ~T1_E~0); 8021#L851-1 assume !(0 == ~T2_E~0); 8050#L856-1 assume !(0 == ~T3_E~0); 8051#L861-1 assume !(0 == ~T4_E~0); 8536#L866-1 assume !(0 == ~T5_E~0); 8462#L871-1 assume !(0 == ~T6_E~0); 8463#L876-1 assume !(0 == ~T7_E~0); 8723#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8473#L886-1 assume !(0 == ~E_M~0); 8264#L891-1 assume !(0 == ~E_1~0); 8265#L896-1 assume !(0 == ~E_2~0); 8466#L901-1 assume !(0 == ~E_3~0); 8489#L906-1 assume !(0 == ~E_4~0); 8490#L911-1 assume !(0 == ~E_5~0); 8305#L916-1 assume !(0 == ~E_6~0); 8306#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 8601#L926-1 assume !(0 == ~E_8~0); 8686#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8727#L410 assume !(1 == ~m_pc~0); 8209#L410-2 is_master_triggered_~__retres1~0 := 0; 8210#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8701#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8577#L1053 assume !(0 != activate_threads_~tmp~1); 8578#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8627#L429 assume 1 == ~t1_pc~0; 8669#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8565#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7825#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7826#L1061 assume !(0 != activate_threads_~tmp___0~0); 8531#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8532#L448 assume !(1 == ~t2_pc~0); 7939#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 7940#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8215#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8124#L1069 assume !(0 != activate_threads_~tmp___1~0); 8125#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8718#L467 assume 1 == ~t3_pc~0; 8368#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8006#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8007#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8451#L1077 assume !(0 != activate_threads_~tmp___2~0); 8330#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7955#L486 assume !(1 == ~t4_pc~0); 7956#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 8501#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7937#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7938#L1085 assume !(0 != activate_threads_~tmp___3~0); 8126#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8127#L505 assume 1 == ~t5_pc~0; 8361#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8362#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8750#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8749#L1093 assume !(0 != activate_threads_~tmp___4~0); 8464#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8465#L524 assume 1 == ~t6_pc~0; 8200#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8201#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8474#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7918#L1101 assume !(0 != activate_threads_~tmp___5~0); 7919#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8267#L543 assume !(1 == ~t7_pc~0); 8268#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 8359#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8509#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8510#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8101#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8102#L562 assume 1 == ~t8_pc~0; 8468#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8655#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7865#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7866#L1117 assume !(0 != activate_threads_~tmp___7~0); 8745#L1117-2 assume !(1 == ~M_E~0); 8642#L944-1 assume !(1 == ~T1_E~0); 8291#L949-1 assume !(1 == ~T2_E~0); 8289#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8290#L959-1 assume !(1 == ~T4_E~0); 8650#L964-1 assume !(1 == ~T5_E~0); 8081#L969-1 assume !(1 == ~T6_E~0); 8082#L974-1 assume !(1 == ~T7_E~0); 8613#L979-1 assume !(1 == ~T8_E~0); 8614#L984-1 assume !(1 == ~E_M~0); 8211#L989-1 assume !(1 == ~E_1~0); 8212#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8118#L999-1 assume !(1 == ~E_3~0); 8119#L1004-1 assume !(1 == ~E_4~0); 7842#L1009-1 assume !(1 == ~E_5~0); 7843#L1014-1 assume !(1 == ~E_6~0); 8109#L1019-1 assume !(1 == ~E_7~0); 8574#L1024-1 assume !(1 == ~E_8~0); 7999#L1295-1 [2021-11-02 22:59:23,931 INFO L793 eck$LassoCheckResult]: Loop: 7999#L1295-1 assume !false; 8273#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8016#L821 assume !false; 8624#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7860#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7862#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8668#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 8439#L704 assume !(0 != eval_~tmp~0); 8441#L836 start_simulation_~kernel_st~0 := 2; 8695#L582-1 start_simulation_~kernel_st~0 := 3; 7836#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7793#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7794#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7913#L856-3 assume !(0 == ~T3_E~0); 7914#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7830#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7831#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8129#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8143#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8144#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8339#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8340#L896-3 assume !(0 == ~E_2~0); 8219#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8220#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8343#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8519#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8157#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8158#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8502#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7905#L410-30 assume 1 == ~m_pc~0; 7837#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7839#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8077#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8281#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8673#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8714#L429-30 assume !(1 == ~t1_pc~0); 8258#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 8259#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8226#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8227#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8044#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8045#L448-30 assume 1 == ~t2_pc~0; 8566#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8567#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7840#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7841#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8734#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8735#L467-30 assume 1 == ~t3_pc~0; 8737#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8402#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8403#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7951#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7952#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8252#L486-30 assume 1 == ~t4_pc~0; 8517#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8320#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8321#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8728#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8151#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8031#L505-30 assume !(1 == ~t5_pc~0); 8032#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 8676#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8279#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8280#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 8657#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8658#L524-30 assume 1 == ~t6_pc~0; 8712#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8557#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8721#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8559#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8560#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8069#L543-30 assume 1 == ~t7_pc~0; 7922#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7924#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8708#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8622#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7971#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7972#L562-30 assume 1 == ~t8_pc~0; 7959#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7832#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7833#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7807#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 7808#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 8008#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7786#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7787#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8299#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7844#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7845#L969-3 assume !(1 == ~T6_E~0); 8004#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8005#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8375#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8376#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8064#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8065#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8492#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7903#L1009-3 assume !(1 == ~E_5~0); 7904#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8357#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8358#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8331#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8332#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8024#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8142#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 8408#L1314 assume !(0 == start_simulation_~tmp~3); 8410#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8706#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7901#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8699#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 8479#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 8480#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 7821#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 7822#L1327 assume !(0 != start_simulation_~tmp___0~1); 7999#L1295-1 [2021-11-02 22:59:23,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1210832705, now seen corresponding path program 1 times [2021-11-02 22:59:23,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473213218] [2021-11-02 22:59:23,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,934 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:23,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:23,978 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:23,978 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473213218] [2021-11-02 22:59:23,978 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473213218] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:23,978 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:23,979 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:23,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055422629] [2021-11-02 22:59:23,979 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:23,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:23,980 INFO L85 PathProgramCache]: Analyzing trace with hash -272830758, now seen corresponding path program 1 times [2021-11-02 22:59:23,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:23,980 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406692800] [2021-11-02 22:59:23,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:23,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:23,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,050 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,050 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406692800] [2021-11-02 22:59:24,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406692800] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,051 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185202874] [2021-11-02 22:59:24,052 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:24,052 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:24,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:24,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:24,053 INFO L87 Difference]: Start difference. First operand 968 states and 1453 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:24,078 INFO L93 Difference]: Finished difference Result 968 states and 1452 transitions. [2021-11-02 22:59:24,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:24,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1452 transitions. [2021-11-02 22:59:24,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,103 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1452 transitions. [2021-11-02 22:59:24,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:24,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:24,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1452 transitions. [2021-11-02 22:59:24,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:24,108 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1452 transitions. [2021-11-02 22:59:24,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1452 transitions. [2021-11-02 22:59:24,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:24,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.5) internal successors, (1452), 967 states have internal predecessors, (1452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1452 transitions. [2021-11-02 22:59:24,168 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1452 transitions. [2021-11-02 22:59:24,168 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1452 transitions. [2021-11-02 22:59:24,168 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-02 22:59:24,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1452 transitions. [2021-11-02 22:59:24,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:24,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:24,184 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,184 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,184 INFO L791 eck$LassoCheckResult]: Stem: 10442#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10443#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10682#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10455#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 10456#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10203#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10204#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9763#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9757#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9758#L614-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9875#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9965#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10615#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 9963#L846-1 assume !(0 == ~T1_E~0); 9964#L851-1 assume !(0 == ~T2_E~0); 9993#L856-1 assume !(0 == ~T3_E~0); 9994#L861-1 assume !(0 == ~T4_E~0); 10479#L866-1 assume !(0 == ~T5_E~0); 10405#L871-1 assume !(0 == ~T6_E~0); 10406#L876-1 assume !(0 == ~T7_E~0); 10666#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10416#L886-1 assume !(0 == ~E_M~0); 10207#L891-1 assume !(0 == ~E_1~0); 10208#L896-1 assume !(0 == ~E_2~0); 10409#L901-1 assume !(0 == ~E_3~0); 10432#L906-1 assume !(0 == ~E_4~0); 10433#L911-1 assume !(0 == ~E_5~0); 10248#L916-1 assume !(0 == ~E_6~0); 10249#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10544#L926-1 assume !(0 == ~E_8~0); 10629#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10670#L410 assume !(1 == ~m_pc~0); 10152#L410-2 is_master_triggered_~__retres1~0 := 0; 10153#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10644#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10520#L1053 assume !(0 != activate_threads_~tmp~1); 10521#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10570#L429 assume 1 == ~t1_pc~0; 10612#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10508#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9768#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9769#L1061 assume !(0 != activate_threads_~tmp___0~0); 10474#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10475#L448 assume !(1 == ~t2_pc~0); 9882#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 9883#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10158#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10067#L1069 assume !(0 != activate_threads_~tmp___1~0); 10068#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10661#L467 assume 1 == ~t3_pc~0; 10311#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9949#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9950#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10394#L1077 assume !(0 != activate_threads_~tmp___2~0); 10273#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9898#L486 assume !(1 == ~t4_pc~0); 9899#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 10444#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9880#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9881#L1085 assume !(0 != activate_threads_~tmp___3~0); 10069#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10070#L505 assume 1 == ~t5_pc~0; 10304#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10305#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10693#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10692#L1093 assume !(0 != activate_threads_~tmp___4~0); 10407#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10408#L524 assume 1 == ~t6_pc~0; 10143#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10144#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10417#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9861#L1101 assume !(0 != activate_threads_~tmp___5~0); 9862#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10210#L543 assume !(1 == ~t7_pc~0); 10211#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 10302#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10452#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 10453#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10044#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10045#L562 assume 1 == ~t8_pc~0; 10411#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10598#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9808#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9809#L1117 assume !(0 != activate_threads_~tmp___7~0); 10688#L1117-2 assume !(1 == ~M_E~0); 10585#L944-1 assume !(1 == ~T1_E~0); 10234#L949-1 assume !(1 == ~T2_E~0); 10232#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10233#L959-1 assume !(1 == ~T4_E~0); 10593#L964-1 assume !(1 == ~T5_E~0); 10024#L969-1 assume !(1 == ~T6_E~0); 10025#L974-1 assume !(1 == ~T7_E~0); 10556#L979-1 assume !(1 == ~T8_E~0); 10557#L984-1 assume !(1 == ~E_M~0); 10154#L989-1 assume !(1 == ~E_1~0); 10155#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10061#L999-1 assume !(1 == ~E_3~0); 10062#L1004-1 assume !(1 == ~E_4~0); 9785#L1009-1 assume !(1 == ~E_5~0); 9786#L1014-1 assume !(1 == ~E_6~0); 10052#L1019-1 assume !(1 == ~E_7~0); 10517#L1024-1 assume !(1 == ~E_8~0); 9942#L1295-1 [2021-11-02 22:59:24,185 INFO L793 eck$LassoCheckResult]: Loop: 9942#L1295-1 assume !false; 10216#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9959#L821 assume !false; 10567#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9803#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9805#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10611#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10382#L704 assume !(0 != eval_~tmp~0); 10384#L836 start_simulation_~kernel_st~0 := 2; 10638#L582-1 start_simulation_~kernel_st~0 := 3; 9779#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9736#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9737#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9856#L856-3 assume !(0 == ~T3_E~0); 9857#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9773#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9774#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10072#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10087#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10282#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10283#L896-3 assume !(0 == ~E_2~0); 10162#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10163#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10286#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10462#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10100#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10101#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10445#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9848#L410-30 assume 1 == ~m_pc~0; 9780#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9782#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10020#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10224#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10616#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10657#L429-30 assume 1 == ~t1_pc~0; 10228#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10202#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10169#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10170#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9987#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9988#L448-30 assume 1 == ~t2_pc~0; 10509#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10510#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9783#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9784#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10677#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10678#L467-30 assume 1 == ~t3_pc~0; 10680#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10345#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10346#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9894#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9895#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10195#L486-30 assume 1 == ~t4_pc~0; 10460#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10263#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10264#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10671#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10094#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9974#L505-30 assume !(1 == ~t5_pc~0); 9975#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 10619#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10222#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10223#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 10600#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10601#L524-30 assume !(1 == ~t6_pc~0); 10499#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 10500#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10664#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10502#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10503#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10012#L543-30 assume 1 == ~t7_pc~0; 9865#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9867#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10651#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 10565#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9914#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9915#L562-30 assume 1 == ~t8_pc~0; 9902#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9775#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9776#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9750#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9751#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 9951#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9729#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9730#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10242#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9787#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9788#L969-3 assume !(1 == ~T6_E~0); 9947#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9948#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10318#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10319#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10007#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10008#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10435#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9846#L1009-3 assume !(1 == ~E_5~0); 9847#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10300#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10301#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10274#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10275#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9967#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10085#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 10351#L1314 assume !(0 == start_simulation_~tmp~3); 10353#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10649#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9844#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10642#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 10422#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 10423#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 9764#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 9765#L1327 assume !(0 != start_simulation_~tmp___0~1); 9942#L1295-1 [2021-11-02 22:59:24,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,186 INFO L85 PathProgramCache]: Analyzing trace with hash 408142209, now seen corresponding path program 1 times [2021-11-02 22:59:24,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21434416] [2021-11-02 22:59:24,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,187 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,250 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,250 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21434416] [2021-11-02 22:59:24,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21434416] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,251 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361108067] [2021-11-02 22:59:24,253 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:24,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,253 INFO L85 PathProgramCache]: Analyzing trace with hash -1857810662, now seen corresponding path program 1 times [2021-11-02 22:59:24,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,254 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405916051] [2021-11-02 22:59:24,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,254 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,313 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,318 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405916051] [2021-11-02 22:59:24,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405916051] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,318 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,319 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203360737] [2021-11-02 22:59:24,321 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:24,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:24,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:24,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:24,325 INFO L87 Difference]: Start difference. First operand 968 states and 1452 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:24,358 INFO L93 Difference]: Finished difference Result 968 states and 1451 transitions. [2021-11-02 22:59:24,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:24,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1451 transitions. [2021-11-02 22:59:24,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1451 transitions. [2021-11-02 22:59:24,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:24,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:24,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1451 transitions. [2021-11-02 22:59:24,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:24,388 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1451 transitions. [2021-11-02 22:59:24,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1451 transitions. [2021-11-02 22:59:24,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:24,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.4989669421487604) internal successors, (1451), 967 states have internal predecessors, (1451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1451 transitions. [2021-11-02 22:59:24,417 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1451 transitions. [2021-11-02 22:59:24,417 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1451 transitions. [2021-11-02 22:59:24,417 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-02 22:59:24,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1451 transitions. [2021-11-02 22:59:24,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:24,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:24,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,429 INFO L791 eck$LassoCheckResult]: Stem: 12385#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12386#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12625#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12398#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 12399#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12146#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12147#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11706#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11700#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11701#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11818#L619-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11908#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12558#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 11906#L846-1 assume !(0 == ~T1_E~0); 11907#L851-1 assume !(0 == ~T2_E~0); 11936#L856-1 assume !(0 == ~T3_E~0); 11937#L861-1 assume !(0 == ~T4_E~0); 12422#L866-1 assume !(0 == ~T5_E~0); 12348#L871-1 assume !(0 == ~T6_E~0); 12349#L876-1 assume !(0 == ~T7_E~0); 12609#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12359#L886-1 assume !(0 == ~E_M~0); 12150#L891-1 assume !(0 == ~E_1~0); 12151#L896-1 assume !(0 == ~E_2~0); 12352#L901-1 assume !(0 == ~E_3~0); 12375#L906-1 assume !(0 == ~E_4~0); 12376#L911-1 assume !(0 == ~E_5~0); 12191#L916-1 assume !(0 == ~E_6~0); 12192#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12487#L926-1 assume !(0 == ~E_8~0); 12572#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12613#L410 assume !(1 == ~m_pc~0); 12095#L410-2 is_master_triggered_~__retres1~0 := 0; 12096#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12587#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12463#L1053 assume !(0 != activate_threads_~tmp~1); 12464#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12513#L429 assume 1 == ~t1_pc~0; 12555#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12451#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11711#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11712#L1061 assume !(0 != activate_threads_~tmp___0~0); 12417#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12418#L448 assume !(1 == ~t2_pc~0); 11825#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 11826#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12101#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12010#L1069 assume !(0 != activate_threads_~tmp___1~0); 12011#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12604#L467 assume 1 == ~t3_pc~0; 12254#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11892#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11893#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12337#L1077 assume !(0 != activate_threads_~tmp___2~0); 12216#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11841#L486 assume !(1 == ~t4_pc~0); 11842#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 12387#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11823#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 11824#L1085 assume !(0 != activate_threads_~tmp___3~0); 12012#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12013#L505 assume 1 == ~t5_pc~0; 12247#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12248#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12636#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12635#L1093 assume !(0 != activate_threads_~tmp___4~0); 12350#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12351#L524 assume 1 == ~t6_pc~0; 12086#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12087#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12360#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11804#L1101 assume !(0 != activate_threads_~tmp___5~0); 11805#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12153#L543 assume !(1 == ~t7_pc~0); 12154#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 12245#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12395#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12396#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11987#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11988#L562 assume 1 == ~t8_pc~0; 12354#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12541#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11751#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11752#L1117 assume !(0 != activate_threads_~tmp___7~0); 12631#L1117-2 assume !(1 == ~M_E~0); 12528#L944-1 assume !(1 == ~T1_E~0); 12177#L949-1 assume !(1 == ~T2_E~0); 12175#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12176#L959-1 assume !(1 == ~T4_E~0); 12536#L964-1 assume !(1 == ~T5_E~0); 11967#L969-1 assume !(1 == ~T6_E~0); 11968#L974-1 assume !(1 == ~T7_E~0); 12499#L979-1 assume !(1 == ~T8_E~0); 12500#L984-1 assume !(1 == ~E_M~0); 12097#L989-1 assume !(1 == ~E_1~0); 12098#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12004#L999-1 assume !(1 == ~E_3~0); 12005#L1004-1 assume !(1 == ~E_4~0); 11728#L1009-1 assume !(1 == ~E_5~0); 11729#L1014-1 assume !(1 == ~E_6~0); 11995#L1019-1 assume !(1 == ~E_7~0); 12460#L1024-1 assume !(1 == ~E_8~0); 11885#L1295-1 [2021-11-02 22:59:24,430 INFO L793 eck$LassoCheckResult]: Loop: 11885#L1295-1 assume !false; 12159#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 11902#L821 assume !false; 12510#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11746#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11748#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12554#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12325#L704 assume !(0 != eval_~tmp~0); 12327#L836 start_simulation_~kernel_st~0 := 2; 12581#L582-1 start_simulation_~kernel_st~0 := 3; 11722#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11679#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11680#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11799#L856-3 assume !(0 == ~T3_E~0); 11800#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11716#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11717#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12015#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12029#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12030#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12225#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12226#L896-3 assume !(0 == ~E_2~0); 12105#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12106#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12229#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12405#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12043#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12044#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12388#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11791#L410-30 assume 1 == ~m_pc~0; 11723#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11725#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11963#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12167#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12559#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12600#L429-30 assume !(1 == ~t1_pc~0); 12144#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 12145#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12112#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12113#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11930#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11931#L448-30 assume 1 == ~t2_pc~0; 12452#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12453#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11726#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11727#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12620#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12621#L467-30 assume !(1 == ~t3_pc~0); 12579#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 12288#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12289#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11837#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11838#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12138#L486-30 assume 1 == ~t4_pc~0; 12403#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12206#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12207#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12614#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12037#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11917#L505-30 assume !(1 == ~t5_pc~0); 11918#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 12562#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12165#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12166#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 12543#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12544#L524-30 assume 1 == ~t6_pc~0; 12598#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12443#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12607#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12445#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12446#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11955#L543-30 assume 1 == ~t7_pc~0; 11808#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11810#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12594#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12508#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11857#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11858#L562-30 assume 1 == ~t8_pc~0; 11845#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11718#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11719#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11693#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11694#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 11894#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11672#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11673#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12185#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11730#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11731#L969-3 assume !(1 == ~T6_E~0); 11890#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11891#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12261#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12262#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11950#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11951#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12378#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11789#L1009-3 assume !(1 == ~E_5~0); 11790#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12243#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12244#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12217#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12218#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11910#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12028#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 12294#L1314 assume !(0 == start_simulation_~tmp~3); 12296#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12592#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11787#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12585#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 12365#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 12366#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 11707#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 11708#L1327 assume !(0 != start_simulation_~tmp___0~1); 11885#L1295-1 [2021-11-02 22:59:24,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1291651199, now seen corresponding path program 1 times [2021-11-02 22:59:24,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,431 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049927167] [2021-11-02 22:59:24,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049927167] [2021-11-02 22:59:24,469 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049927167] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,469 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577572384] [2021-11-02 22:59:24,470 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:24,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1450805319, now seen corresponding path program 1 times [2021-11-02 22:59:24,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,472 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426759780] [2021-11-02 22:59:24,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,526 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,526 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426759780] [2021-11-02 22:59:24,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426759780] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,527 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279120355] [2021-11-02 22:59:24,528 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:24,528 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:24,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:24,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:24,529 INFO L87 Difference]: Start difference. First operand 968 states and 1451 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:24,554 INFO L93 Difference]: Finished difference Result 968 states and 1450 transitions. [2021-11-02 22:59:24,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:24,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1450 transitions. [2021-11-02 22:59:24,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1450 transitions. [2021-11-02 22:59:24,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:24,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:24,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1450 transitions. [2021-11-02 22:59:24,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:24,580 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1450 transitions. [2021-11-02 22:59:24,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1450 transitions. [2021-11-02 22:59:24,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:24,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.4979338842975207) internal successors, (1450), 967 states have internal predecessors, (1450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1450 transitions. [2021-11-02 22:59:24,671 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1450 transitions. [2021-11-02 22:59:24,671 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1450 transitions. [2021-11-02 22:59:24,672 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-02 22:59:24,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1450 transitions. [2021-11-02 22:59:24,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:24,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:24,684 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,684 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,685 INFO L791 eck$LassoCheckResult]: Stem: 14328#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14329#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14568#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14341#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 14342#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14089#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14090#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13649#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13643#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13644#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13761#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13851#L624-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14501#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 13849#L846-1 assume !(0 == ~T1_E~0); 13850#L851-1 assume !(0 == ~T2_E~0); 13879#L856-1 assume !(0 == ~T3_E~0); 13880#L861-1 assume !(0 == ~T4_E~0); 14365#L866-1 assume !(0 == ~T5_E~0); 14291#L871-1 assume !(0 == ~T6_E~0); 14292#L876-1 assume !(0 == ~T7_E~0); 14552#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14302#L886-1 assume !(0 == ~E_M~0); 14093#L891-1 assume !(0 == ~E_1~0); 14094#L896-1 assume !(0 == ~E_2~0); 14295#L901-1 assume !(0 == ~E_3~0); 14318#L906-1 assume !(0 == ~E_4~0); 14319#L911-1 assume !(0 == ~E_5~0); 14134#L916-1 assume !(0 == ~E_6~0); 14135#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 14430#L926-1 assume !(0 == ~E_8~0); 14515#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14556#L410 assume !(1 == ~m_pc~0); 14038#L410-2 is_master_triggered_~__retres1~0 := 0; 14039#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14530#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14406#L1053 assume !(0 != activate_threads_~tmp~1); 14407#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14456#L429 assume 1 == ~t1_pc~0; 14498#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14394#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13654#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13655#L1061 assume !(0 != activate_threads_~tmp___0~0); 14360#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14361#L448 assume !(1 == ~t2_pc~0); 13768#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 13769#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14044#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13953#L1069 assume !(0 != activate_threads_~tmp___1~0); 13954#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14547#L467 assume 1 == ~t3_pc~0; 14197#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13835#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13836#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14280#L1077 assume !(0 != activate_threads_~tmp___2~0); 14159#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13784#L486 assume !(1 == ~t4_pc~0); 13785#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 14330#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13766#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 13767#L1085 assume !(0 != activate_threads_~tmp___3~0); 13955#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13956#L505 assume 1 == ~t5_pc~0; 14190#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14191#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14579#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14578#L1093 assume !(0 != activate_threads_~tmp___4~0); 14293#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14294#L524 assume 1 == ~t6_pc~0; 14029#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14030#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14303#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13747#L1101 assume !(0 != activate_threads_~tmp___5~0); 13748#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14096#L543 assume !(1 == ~t7_pc~0); 14097#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 14188#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14338#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14339#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13930#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13931#L562 assume 1 == ~t8_pc~0; 14297#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14484#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13694#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13695#L1117 assume !(0 != activate_threads_~tmp___7~0); 14574#L1117-2 assume !(1 == ~M_E~0); 14471#L944-1 assume !(1 == ~T1_E~0); 14120#L949-1 assume !(1 == ~T2_E~0); 14118#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14119#L959-1 assume !(1 == ~T4_E~0); 14479#L964-1 assume !(1 == ~T5_E~0); 13910#L969-1 assume !(1 == ~T6_E~0); 13911#L974-1 assume !(1 == ~T7_E~0); 14442#L979-1 assume !(1 == ~T8_E~0); 14443#L984-1 assume !(1 == ~E_M~0); 14040#L989-1 assume !(1 == ~E_1~0); 14041#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13947#L999-1 assume !(1 == ~E_3~0); 13948#L1004-1 assume !(1 == ~E_4~0); 13671#L1009-1 assume !(1 == ~E_5~0); 13672#L1014-1 assume !(1 == ~E_6~0); 13938#L1019-1 assume !(1 == ~E_7~0); 14403#L1024-1 assume !(1 == ~E_8~0); 13828#L1295-1 [2021-11-02 22:59:24,686 INFO L793 eck$LassoCheckResult]: Loop: 13828#L1295-1 assume !false; 14102#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 13845#L821 assume !false; 14453#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13689#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13691#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14497#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 14268#L704 assume !(0 != eval_~tmp~0); 14270#L836 start_simulation_~kernel_st~0 := 2; 14524#L582-1 start_simulation_~kernel_st~0 := 3; 13665#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13622#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13623#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13742#L856-3 assume !(0 == ~T3_E~0); 13743#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13659#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13660#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13958#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13972#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13973#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14168#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14169#L896-3 assume !(0 == ~E_2~0); 14048#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14049#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14172#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14348#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13986#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13987#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14331#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13734#L410-30 assume 1 == ~m_pc~0; 13666#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13668#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13906#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14110#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14502#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14543#L429-30 assume 1 == ~t1_pc~0; 14114#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14088#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14055#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14056#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13873#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13874#L448-30 assume 1 == ~t2_pc~0; 14395#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14396#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13669#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13670#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14563#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14564#L467-30 assume 1 == ~t3_pc~0; 14566#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14231#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14232#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13780#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13781#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14081#L486-30 assume 1 == ~t4_pc~0; 14346#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14149#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14150#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14557#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13980#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13860#L505-30 assume !(1 == ~t5_pc~0); 13861#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 14505#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14108#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14109#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 14486#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14487#L524-30 assume !(1 == ~t6_pc~0); 14385#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 14386#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14550#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14388#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14389#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13898#L543-30 assume 1 == ~t7_pc~0; 13751#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13753#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14537#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14451#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13800#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13801#L562-30 assume 1 == ~t8_pc~0; 13788#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13661#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13662#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13636#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13637#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 13837#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13615#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13616#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14128#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13673#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13674#L969-3 assume !(1 == ~T6_E~0); 13833#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13834#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14204#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14205#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13893#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13894#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14321#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13732#L1009-3 assume !(1 == ~E_5~0); 13733#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14186#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14187#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14160#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14161#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13853#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 13971#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 14237#L1314 assume !(0 == start_simulation_~tmp~3); 14239#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14535#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13730#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14528#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 14308#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 14309#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 13650#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 13651#L1327 assume !(0 != start_simulation_~tmp___0~1); 13828#L1295-1 [2021-11-02 22:59:24,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1320151489, now seen corresponding path program 1 times [2021-11-02 22:59:24,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,688 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131407039] [2021-11-02 22:59:24,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,729 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,729 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131407039] [2021-11-02 22:59:24,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131407039] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,730 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,730 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664122523] [2021-11-02 22:59:24,731 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:24,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,732 INFO L85 PathProgramCache]: Analyzing trace with hash -1857810662, now seen corresponding path program 2 times [2021-11-02 22:59:24,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,732 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209068517] [2021-11-02 22:59:24,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,788 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209068517] [2021-11-02 22:59:24,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209068517] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,798 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:24,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678616426] [2021-11-02 22:59:24,800 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:24,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:24,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:24,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:24,801 INFO L87 Difference]: Start difference. First operand 968 states and 1450 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:24,829 INFO L93 Difference]: Finished difference Result 968 states and 1449 transitions. [2021-11-02 22:59:24,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:24,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1449 transitions. [2021-11-02 22:59:24,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1449 transitions. [2021-11-02 22:59:24,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-11-02 22:59:24,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-11-02 22:59:24,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1449 transitions. [2021-11-02 22:59:24,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:24,857 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1449 transitions. [2021-11-02 22:59:24,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1449 transitions. [2021-11-02 22:59:24,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 968. [2021-11-02 22:59:24,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 968 states, 968 states have (on average 1.496900826446281) internal successors, (1449), 967 states have internal predecessors, (1449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:24,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 968 states to 968 states and 1449 transitions. [2021-11-02 22:59:24,899 INFO L704 BuchiCegarLoop]: Abstraction has 968 states and 1449 transitions. [2021-11-02 22:59:24,900 INFO L587 BuchiCegarLoop]: Abstraction has 968 states and 1449 transitions. [2021-11-02 22:59:24,900 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-02 22:59:24,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 968 states and 1449 transitions. [2021-11-02 22:59:24,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 857 [2021-11-02 22:59:24,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:24,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:24,912 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,912 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:24,912 INFO L791 eck$LassoCheckResult]: Stem: 16271#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16272#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16511#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16284#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 16285#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16032#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16033#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15592#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15586#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15587#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15704#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15794#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16444#L629-1 assume 0 == ~M_E~0;~M_E~0 := 1; 15792#L846-1 assume !(0 == ~T1_E~0); 15793#L851-1 assume !(0 == ~T2_E~0); 15822#L856-1 assume !(0 == ~T3_E~0); 15823#L861-1 assume !(0 == ~T4_E~0); 16308#L866-1 assume !(0 == ~T5_E~0); 16234#L871-1 assume !(0 == ~T6_E~0); 16235#L876-1 assume !(0 == ~T7_E~0); 16495#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16245#L886-1 assume !(0 == ~E_M~0); 16036#L891-1 assume !(0 == ~E_1~0); 16037#L896-1 assume !(0 == ~E_2~0); 16238#L901-1 assume !(0 == ~E_3~0); 16261#L906-1 assume !(0 == ~E_4~0); 16262#L911-1 assume !(0 == ~E_5~0); 16077#L916-1 assume !(0 == ~E_6~0); 16078#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 16373#L926-1 assume !(0 == ~E_8~0); 16458#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16499#L410 assume !(1 == ~m_pc~0); 15981#L410-2 is_master_triggered_~__retres1~0 := 0; 15982#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16473#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16349#L1053 assume !(0 != activate_threads_~tmp~1); 16350#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16399#L429 assume 1 == ~t1_pc~0; 16441#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16337#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15597#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15598#L1061 assume !(0 != activate_threads_~tmp___0~0); 16303#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16304#L448 assume !(1 == ~t2_pc~0); 15711#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 15712#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15987#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15896#L1069 assume !(0 != activate_threads_~tmp___1~0); 15897#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16490#L467 assume 1 == ~t3_pc~0; 16140#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15778#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15779#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16223#L1077 assume !(0 != activate_threads_~tmp___2~0); 16102#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15727#L486 assume !(1 == ~t4_pc~0); 15728#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 16273#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15709#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 15710#L1085 assume !(0 != activate_threads_~tmp___3~0); 15898#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15899#L505 assume 1 == ~t5_pc~0; 16133#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16134#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16522#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16521#L1093 assume !(0 != activate_threads_~tmp___4~0); 16236#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16237#L524 assume 1 == ~t6_pc~0; 15972#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15973#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16246#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15690#L1101 assume !(0 != activate_threads_~tmp___5~0); 15691#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16039#L543 assume !(1 == ~t7_pc~0); 16040#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 16131#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16281#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16282#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15873#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15874#L562 assume 1 == ~t8_pc~0; 16240#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16427#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15637#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 15638#L1117 assume !(0 != activate_threads_~tmp___7~0); 16517#L1117-2 assume !(1 == ~M_E~0); 16414#L944-1 assume !(1 == ~T1_E~0); 16063#L949-1 assume !(1 == ~T2_E~0); 16061#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16062#L959-1 assume !(1 == ~T4_E~0); 16422#L964-1 assume !(1 == ~T5_E~0); 15853#L969-1 assume !(1 == ~T6_E~0); 15854#L974-1 assume !(1 == ~T7_E~0); 16385#L979-1 assume !(1 == ~T8_E~0); 16386#L984-1 assume !(1 == ~E_M~0); 15983#L989-1 assume !(1 == ~E_1~0); 15984#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15890#L999-1 assume !(1 == ~E_3~0); 15891#L1004-1 assume !(1 == ~E_4~0); 15614#L1009-1 assume !(1 == ~E_5~0); 15615#L1014-1 assume !(1 == ~E_6~0); 15881#L1019-1 assume !(1 == ~E_7~0); 16346#L1024-1 assume !(1 == ~E_8~0); 15771#L1295-1 [2021-11-02 22:59:24,913 INFO L793 eck$LassoCheckResult]: Loop: 15771#L1295-1 assume !false; 16045#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 15788#L821 assume !false; 16396#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15632#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15634#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16440#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16211#L704 assume !(0 != eval_~tmp~0); 16213#L836 start_simulation_~kernel_st~0 := 2; 16467#L582-1 start_simulation_~kernel_st~0 := 3; 15608#L846-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15565#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15566#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15685#L856-3 assume !(0 == ~T3_E~0); 15686#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15602#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15603#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15901#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15915#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15916#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16111#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16112#L896-3 assume !(0 == ~E_2~0); 15991#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15992#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16115#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16291#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15929#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15930#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16274#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15677#L410-30 assume 1 == ~m_pc~0; 15609#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 15611#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15849#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16053#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16445#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16486#L429-30 assume 1 == ~t1_pc~0; 16057#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16031#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15998#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15999#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15816#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15817#L448-30 assume 1 == ~t2_pc~0; 16338#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16339#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15612#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15613#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16506#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16507#L467-30 assume !(1 == ~t3_pc~0); 16465#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 16174#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16175#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 15723#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15724#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16024#L486-30 assume 1 == ~t4_pc~0; 16289#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16092#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16093#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16500#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15923#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15803#L505-30 assume !(1 == ~t5_pc~0); 15804#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 16448#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16051#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16052#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 16429#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16430#L524-30 assume 1 == ~t6_pc~0; 16484#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16329#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16493#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16331#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16332#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15841#L543-30 assume 1 == ~t7_pc~0; 15694#L544-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15696#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16480#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16394#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15743#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15744#L562-30 assume 1 == ~t8_pc~0; 15731#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15604#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15605#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 15579#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15580#L1117-32 assume 1 == ~M_E~0;~M_E~0 := 2; 15780#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15558#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15559#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16071#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15616#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15617#L969-3 assume !(1 == ~T6_E~0); 15776#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15777#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16147#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16148#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15836#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15837#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16264#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15675#L1009-3 assume !(1 == ~E_5~0); 15676#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16129#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16130#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16103#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16104#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15796#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15914#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 16180#L1314 assume !(0 == start_simulation_~tmp~3); 16182#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16478#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15673#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16471#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 16251#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16252#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 15593#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 15594#L1327 assume !(0 != start_simulation_~tmp___0~1); 15771#L1295-1 [2021-11-02 22:59:24,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1034233793, now seen corresponding path program 1 times [2021-11-02 22:59:24,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,915 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921744254] [2021-11-02 22:59:24,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:24,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:24,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:24,964 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921744254] [2021-11-02 22:59:24,964 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921744254] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:24,965 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:24,965 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:59:24,965 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602595083] [2021-11-02 22:59:24,966 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:24,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:24,966 INFO L85 PathProgramCache]: Analyzing trace with hash -173652646, now seen corresponding path program 2 times [2021-11-02 22:59:24,967 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:24,967 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733424476] [2021-11-02 22:59:24,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:24,967 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:24,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,029 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,029 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733424476] [2021-11-02 22:59:25,030 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733424476] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,030 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,030 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:25,030 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30617406] [2021-11-02 22:59:25,031 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:25,031 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:25,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:25,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:25,032 INFO L87 Difference]: Start difference. First operand 968 states and 1449 transitions. cyclomatic complexity: 482 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:25,102 INFO L93 Difference]: Finished difference Result 1761 states and 2627 transitions. [2021-11-02 22:59:25,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:25,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1761 states and 2627 transitions. [2021-11-02 22:59:25,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1761 states to 1761 states and 2627 transitions. [2021-11-02 22:59:25,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1761 [2021-11-02 22:59:25,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1761 [2021-11-02 22:59:25,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1761 states and 2627 transitions. [2021-11-02 22:59:25,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:25,172 INFO L681 BuchiCegarLoop]: Abstraction has 1761 states and 2627 transitions. [2021-11-02 22:59:25,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1761 states and 2627 transitions. [2021-11-02 22:59:25,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1761 to 1761. [2021-11-02 22:59:25,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4917660420215786) internal successors, (2627), 1760 states have internal predecessors, (2627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2627 transitions. [2021-11-02 22:59:25,228 INFO L704 BuchiCegarLoop]: Abstraction has 1761 states and 2627 transitions. [2021-11-02 22:59:25,228 INFO L587 BuchiCegarLoop]: Abstraction has 1761 states and 2627 transitions. [2021-11-02 22:59:25,228 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-02 22:59:25,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2627 transitions. [2021-11-02 22:59:25,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:25,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:25,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,241 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,242 INFO L791 eck$LassoCheckResult]: Stem: 19018#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19019#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19319#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19031#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 19032#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18774#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18775#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18328#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18322#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18323#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18441#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18531#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19218#L629-1 assume !(0 == ~M_E~0); 18529#L846-1 assume !(0 == ~T1_E~0); 18530#L851-1 assume !(0 == ~T2_E~0); 18559#L856-1 assume !(0 == ~T3_E~0); 18560#L861-1 assume !(0 == ~T4_E~0); 19058#L866-1 assume !(0 == ~T5_E~0); 18979#L871-1 assume !(0 == ~T6_E~0); 18980#L876-1 assume !(0 == ~T7_E~0); 19293#L881-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18991#L886-1 assume !(0 == ~E_M~0); 18778#L891-1 assume !(0 == ~E_1~0); 18779#L896-1 assume !(0 == ~E_2~0); 18983#L901-1 assume !(0 == ~E_3~0); 19008#L906-1 assume !(0 == ~E_4~0); 19009#L911-1 assume !(0 == ~E_5~0); 18819#L916-1 assume !(0 == ~E_6~0); 18820#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 19128#L926-1 assume !(0 == ~E_8~0); 19235#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19300#L410 assume !(1 == ~m_pc~0); 18721#L410-2 is_master_triggered_~__retres1~0 := 0; 18722#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19259#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 19099#L1053 assume !(0 != activate_threads_~tmp~1); 19100#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19162#L429 assume 1 == ~t1_pc~0; 19215#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 19087#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18333#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18334#L1061 assume !(0 != activate_threads_~tmp___0~0); 19053#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19054#L448 assume !(1 == ~t2_pc~0); 18448#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 18449#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18727#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18634#L1069 assume !(0 != activate_threads_~tmp___1~0); 18635#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19287#L467 assume 1 == ~t3_pc~0; 18882#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18515#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18516#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 18968#L1077 assume !(0 != activate_threads_~tmp___2~0); 18844#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18464#L486 assume !(1 == ~t4_pc~0); 18465#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 19020#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18446#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 18447#L1085 assume !(0 != activate_threads_~tmp___3~0); 18636#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18637#L505 assume 1 == ~t5_pc~0; 18875#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18876#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19337#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19336#L1093 assume !(0 != activate_threads_~tmp___4~0); 18981#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18982#L524 assume 1 == ~t6_pc~0; 18712#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 18713#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18992#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18427#L1101 assume !(0 != activate_threads_~tmp___5~0); 18428#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18781#L543 assume !(1 == ~t7_pc~0); 18782#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 18873#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19028#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19029#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18610#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18611#L562 assume 1 == ~t8_pc~0; 18985#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19196#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18373#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18374#L1117 assume !(0 != activate_threads_~tmp___7~0); 19332#L1117-2 assume !(1 == ~M_E~0); 19179#L944-1 assume !(1 == ~T1_E~0); 18805#L949-1 assume !(1 == ~T2_E~0); 18803#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18804#L959-1 assume !(1 == ~T4_E~0); 19189#L964-1 assume !(1 == ~T5_E~0); 18590#L969-1 assume !(1 == ~T6_E~0); 18591#L974-1 assume !(1 == ~T7_E~0); 19147#L979-1 assume !(1 == ~T8_E~0); 19148#L984-1 assume !(1 == ~E_M~0); 18723#L989-1 assume !(1 == ~E_1~0); 18724#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 18628#L999-1 assume !(1 == ~E_3~0); 18629#L1004-1 assume !(1 == ~E_4~0); 18350#L1009-1 assume !(1 == ~E_5~0); 18351#L1014-1 assume !(1 == ~E_6~0); 18619#L1019-1 assume !(1 == ~E_7~0); 19096#L1024-1 assume !(1 == ~E_8~0); 19266#L1295-1 [2021-11-02 22:59:25,242 INFO L793 eck$LassoCheckResult]: Loop: 19266#L1295-1 assume !false; 19244#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 18525#L821 assume !false; 19279#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18368#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18370#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19388#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 19386#L704 assume !(0 != eval_~tmp~0); 19251#L836 start_simulation_~kernel_st~0 := 2; 19252#L582-1 start_simulation_~kernel_st~0 := 3; 19385#L846-2 assume !(0 == ~M_E~0); 19384#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19383#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19382#L856-3 assume !(0 == ~T3_E~0); 19381#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19380#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19379#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19378#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19377#L881-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19186#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19187#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19376#L896-3 assume !(0 == ~E_2~0); 18732#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18733#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18857#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19039#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19040#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19374#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19129#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18414#L410-30 assume 1 == ~m_pc~0; 18345#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 18347#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18586#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18795#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19368#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19280#L429-30 assume 1 == ~t1_pc~0; 19281#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 19367#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18739#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18740#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19366#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19130#L448-30 assume !(1 == ~t2_pc~0); 19131#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 19194#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19195#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 19365#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19364#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19363#L467-30 assume 1 == ~t3_pc~0; 19361#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18918#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18919#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 19360#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18765#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18766#L486-30 assume 1 == ~t4_pc~0; 19283#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18834#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18835#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19301#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19317#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19356#L505-30 assume 1 == ~t5_pc~0; 19236#L506-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19237#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19355#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19354#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 19199#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19200#L524-30 assume 1 == ~t6_pc~0; 19352#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19290#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19291#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19321#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19275#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18578#L543-30 assume !(1 == ~t7_pc~0); 18432#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 18433#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19309#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19310#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19347#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19346#L562-30 assume 1 == ~t8_pc~0; 19344#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19343#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19342#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 19341#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18638#L1117-32 assume !(1 == ~M_E~0); 18517#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18294#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18295#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18813#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18352#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18353#L969-3 assume !(1 == ~T6_E~0); 18513#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18514#L979-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18889#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18890#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18573#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18574#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19011#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18412#L1009-3 assume !(1 == ~E_5~0); 18413#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18871#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18872#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18845#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18846#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18533#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 18654#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 18924#L1314 assume !(0 == start_simulation_~tmp~3); 18926#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 19265#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18410#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19329#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 19445#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19442#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 19440#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 19410#L1327 assume !(0 != start_simulation_~tmp___0~1); 19266#L1295-1 [2021-11-02 22:59:25,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,243 INFO L85 PathProgramCache]: Analyzing trace with hash 842829437, now seen corresponding path program 1 times [2021-11-02 22:59:25,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,244 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744425201] [2021-11-02 22:59:25,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,286 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,286 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744425201] [2021-11-02 22:59:25,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744425201] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,287 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:59:25,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779730721] [2021-11-02 22:59:25,287 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:25,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1223763870, now seen corresponding path program 1 times [2021-11-02 22:59:25,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,288 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300720426] [2021-11-02 22:59:25,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,331 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300720426] [2021-11-02 22:59:25,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300720426] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,331 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:25,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458697310] [2021-11-02 22:59:25,332 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:25,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:25,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:25,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:25,333 INFO L87 Difference]: Start difference. First operand 1761 states and 2627 transitions. cyclomatic complexity: 867 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:25,371 INFO L93 Difference]: Finished difference Result 1761 states and 2619 transitions. [2021-11-02 22:59:25,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:25,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1761 states and 2619 transitions. [2021-11-02 22:59:25,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1761 states to 1761 states and 2619 transitions. [2021-11-02 22:59:25,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1761 [2021-11-02 22:59:25,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1761 [2021-11-02 22:59:25,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1761 states and 2619 transitions. [2021-11-02 22:59:25,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:25,412 INFO L681 BuchiCegarLoop]: Abstraction has 1761 states and 2619 transitions. [2021-11-02 22:59:25,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1761 states and 2619 transitions. [2021-11-02 22:59:25,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1761 to 1761. [2021-11-02 22:59:25,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4872231686541737) internal successors, (2619), 1760 states have internal predecessors, (2619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2619 transitions. [2021-11-02 22:59:25,466 INFO L704 BuchiCegarLoop]: Abstraction has 1761 states and 2619 transitions. [2021-11-02 22:59:25,466 INFO L587 BuchiCegarLoop]: Abstraction has 1761 states and 2619 transitions. [2021-11-02 22:59:25,466 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-02 22:59:25,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2619 transitions. [2021-11-02 22:59:25,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:25,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:25,480 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,480 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,480 INFO L791 eck$LassoCheckResult]: Stem: 22561#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 22562#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 22862#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22575#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 22576#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22313#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22314#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21857#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21851#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21852#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21972#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22064#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22763#L629-1 assume !(0 == ~M_E~0); 22062#L846-1 assume !(0 == ~T1_E~0); 22063#L851-1 assume !(0 == ~T2_E~0); 22094#L856-1 assume !(0 == ~T3_E~0); 22095#L861-1 assume !(0 == ~T4_E~0); 22601#L866-1 assume !(0 == ~T5_E~0); 22522#L871-1 assume !(0 == ~T6_E~0); 22523#L876-1 assume !(0 == ~T7_E~0); 22840#L881-1 assume !(0 == ~T8_E~0); 22535#L886-1 assume !(0 == ~E_M~0); 22315#L891-1 assume !(0 == ~E_1~0); 22316#L896-1 assume !(0 == ~E_2~0); 22526#L901-1 assume !(0 == ~E_3~0); 22552#L906-1 assume !(0 == ~E_4~0); 22553#L911-1 assume !(0 == ~E_5~0); 22358#L916-1 assume !(0 == ~E_6~0); 22359#L921-1 assume 0 == ~E_7~0;~E_7~0 := 1; 22673#L926-1 assume !(0 == ~E_8~0); 22781#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22847#L410 assume !(1 == ~m_pc~0); 22258#L410-2 is_master_triggered_~__retres1~0 := 0; 22259#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22804#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22644#L1053 assume !(0 != activate_threads_~tmp~1); 22645#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22710#L429 assume 1 == ~t1_pc~0; 22762#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22631#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21862#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21863#L1061 assume !(0 != activate_threads_~tmp___0~0); 22596#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22597#L448 assume !(1 == ~t2_pc~0); 21979#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 21980#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22264#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 22170#L1069 assume !(0 != activate_threads_~tmp___1~0); 22171#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22834#L467 assume 1 == ~t3_pc~0; 22424#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22048#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22049#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22511#L1077 assume !(0 != activate_threads_~tmp___2~0); 22383#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21996#L486 assume !(1 == ~t4_pc~0); 21997#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 22565#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21977#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21978#L1085 assume !(0 != activate_threads_~tmp___3~0); 22172#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22173#L505 assume 1 == ~t5_pc~0; 22416#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22417#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22879#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22878#L1093 assume !(0 != activate_threads_~tmp___4~0); 22524#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22525#L524 assume 1 == ~t6_pc~0; 22249#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22250#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22536#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21958#L1101 assume !(0 != activate_threads_~tmp___5~0); 21959#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22318#L543 assume !(1 == ~t7_pc~0); 22319#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 22413#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22572#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 22573#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22147#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22148#L562 assume 1 == ~t8_pc~0; 22528#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 22744#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21902#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21903#L1117 assume !(0 != activate_threads_~tmp___7~0); 22874#L1117-2 assume !(1 == ~M_E~0); 22726#L944-1 assume !(1 == ~T1_E~0); 22344#L949-1 assume !(1 == ~T2_E~0); 22342#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22343#L959-1 assume !(1 == ~T4_E~0); 22737#L964-1 assume !(1 == ~T5_E~0); 22123#L969-1 assume !(1 == ~T6_E~0); 22124#L974-1 assume !(1 == ~T7_E~0); 22694#L979-1 assume !(1 == ~T8_E~0); 22695#L984-1 assume !(1 == ~E_M~0); 22260#L989-1 assume !(1 == ~E_1~0); 22261#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22163#L999-1 assume !(1 == ~E_3~0); 22164#L1004-1 assume !(1 == ~E_4~0); 21879#L1009-1 assume !(1 == ~E_5~0); 21880#L1014-1 assume !(1 == ~E_6~0); 22156#L1019-1 assume !(1 == ~E_7~0); 22641#L1024-1 assume !(1 == ~E_8~0); 22813#L1295-1 [2021-11-02 22:59:25,481 INFO L793 eck$LassoCheckResult]: Loop: 22813#L1295-1 assume !false; 22921#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 22920#L821 assume !false; 22919#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22918#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22758#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22759#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 22872#L704 assume !(0 != eval_~tmp~0); 22797#L836 start_simulation_~kernel_st~0 := 2; 22798#L582-1 start_simulation_~kernel_st~0 := 3; 22907#L846-2 assume !(0 == ~M_E~0); 22906#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22444#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21953#L856-3 assume !(0 == ~T3_E~0); 21954#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22607#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22176#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22177#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22903#L881-3 assume !(0 == ~T8_E~0); 22733#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22734#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22532#L896-3 assume !(0 == ~E_2~0); 22533#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22398#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22399#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22582#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22583#L921-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22563#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22564#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21944#L410-30 assume !(1 == ~m_pc~0); 21945#L410-32 is_master_triggered_~__retres1~0 := 0; 22902#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22333#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22334#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22901#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22827#L429-30 assume 1 == ~t1_pc~0; 22828#L430-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22900#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22275#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22276#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22086#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22087#L448-30 assume 1 == ~t2_pc~0; 22632#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22633#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21877#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21878#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22855#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22856#L467-30 assume !(1 == ~t3_pc~0); 22792#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 22793#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22688#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22689#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22302#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22303#L486-30 assume 1 == ~t4_pc~0; 22580#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22373#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22374#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 22846#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22861#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22073#L505-30 assume !(1 == ~t5_pc~0); 22074#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 22768#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22769#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22891#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 22745#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22746#L524-30 assume 1 == ~t6_pc~0; 22889#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22837#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22838#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 22864#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22820#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22821#L543-30 assume !(1 == ~t7_pc~0); 22886#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 22815#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22816#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 22703#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22011#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22012#L562-30 assume !(1 == ~t8_pc~0); 22000#L562-32 is_transmit8_triggered_~__retres1~8 := 0; 21869#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21870#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 22883#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 22174#L1117-32 assume !(1 == ~M_E~0); 22047#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21823#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21824#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22351#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21881#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21882#L969-3 assume !(1 == ~T6_E~0); 22045#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22046#L979-3 assume !(1 == ~T8_E~0); 22429#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22430#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22106#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22107#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22554#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21941#L1009-3 assume !(1 == ~E_5~0); 21942#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22411#L1019-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22412#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22384#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22385#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22066#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22190#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 22795#L1314 assume !(0 == start_simulation_~tmp~3); 23007#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 23006#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22997#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22996#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 22995#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 22994#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 22993#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 22990#L1327 assume !(0 != start_simulation_~tmp___0~1); 22813#L1295-1 [2021-11-02 22:59:25,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,482 INFO L85 PathProgramCache]: Analyzing trace with hash -1885379909, now seen corresponding path program 1 times [2021-11-02 22:59:25,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,482 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526579761] [2021-11-02 22:59:25,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,482 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,520 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,520 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526579761] [2021-11-02 22:59:25,520 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526579761] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,520 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,520 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:59:25,521 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432078626] [2021-11-02 22:59:25,521 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:25,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,522 INFO L85 PathProgramCache]: Analyzing trace with hash -2039769729, now seen corresponding path program 1 times [2021-11-02 22:59:25,522 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,522 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300793605] [2021-11-02 22:59:25,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,566 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300793605] [2021-11-02 22:59:25,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300793605] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,566 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:25,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004718556] [2021-11-02 22:59:25,567 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:25,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:25,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:25,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:25,568 INFO L87 Difference]: Start difference. First operand 1761 states and 2619 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:25,643 INFO L93 Difference]: Finished difference Result 1761 states and 2591 transitions. [2021-11-02 22:59:25,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:25,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1761 states and 2591 transitions. [2021-11-02 22:59:25,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1761 states to 1761 states and 2591 transitions. [2021-11-02 22:59:25,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1761 [2021-11-02 22:59:25,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1761 [2021-11-02 22:59:25,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1761 states and 2591 transitions. [2021-11-02 22:59:25,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:25,714 INFO L681 BuchiCegarLoop]: Abstraction has 1761 states and 2591 transitions. [2021-11-02 22:59:25,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1761 states and 2591 transitions. [2021-11-02 22:59:25,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1761 to 1761. [2021-11-02 22:59:25,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4713231118682566) internal successors, (2591), 1760 states have internal predecessors, (2591), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:25,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2591 transitions. [2021-11-02 22:59:25,769 INFO L704 BuchiCegarLoop]: Abstraction has 1761 states and 2591 transitions. [2021-11-02 22:59:25,769 INFO L587 BuchiCegarLoop]: Abstraction has 1761 states and 2591 transitions. [2021-11-02 22:59:25,770 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-02 22:59:25,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2591 transitions. [2021-11-02 22:59:25,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1650 [2021-11-02 22:59:25,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:25,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:25,783 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:25,784 INFO L791 eck$LassoCheckResult]: Stem: 26072#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 26073#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 26349#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26085#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 26086#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25832#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25833#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25385#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25379#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25380#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25497#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25589#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26263#L629-1 assume !(0 == ~M_E~0); 25587#L846-1 assume !(0 == ~T1_E~0); 25588#L851-1 assume !(0 == ~T2_E~0); 25619#L856-1 assume !(0 == ~T3_E~0); 25620#L861-1 assume !(0 == ~T4_E~0); 26112#L866-1 assume !(0 == ~T5_E~0); 26035#L871-1 assume !(0 == ~T6_E~0); 26036#L876-1 assume !(0 == ~T7_E~0); 26328#L881-1 assume !(0 == ~T8_E~0); 26046#L886-1 assume !(0 == ~E_M~0); 25834#L891-1 assume !(0 == ~E_1~0); 25835#L896-1 assume !(0 == ~E_2~0); 26039#L901-1 assume !(0 == ~E_3~0); 26064#L906-1 assume !(0 == ~E_4~0); 26065#L911-1 assume !(0 == ~E_5~0); 25875#L916-1 assume !(0 == ~E_6~0); 25876#L921-1 assume !(0 == ~E_7~0); 26181#L926-1 assume !(0 == ~E_8~0); 26279#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26334#L410 assume !(1 == ~m_pc~0); 25778#L410-2 is_master_triggered_~__retres1~0 := 0; 25779#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26298#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 26154#L1053 assume !(0 != activate_threads_~tmp~1); 26155#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26211#L429 assume 1 == ~t1_pc~0; 26262#L430 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26142#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25390#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25391#L1061 assume !(0 != activate_threads_~tmp___0~0); 26107#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26108#L448 assume !(1 == ~t2_pc~0); 25504#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 25505#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25785#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25692#L1069 assume !(0 != activate_threads_~tmp___1~0); 25693#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26323#L467 assume 1 == ~t3_pc~0; 25941#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25573#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25574#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26024#L1077 assume !(0 != activate_threads_~tmp___2~0); 25900#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25521#L486 assume !(1 == ~t4_pc~0); 25522#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 26075#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25502#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 25503#L1085 assume !(0 != activate_threads_~tmp___3~0); 25694#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25695#L505 assume 1 == ~t5_pc~0; 25933#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 25934#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26364#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 26363#L1093 assume !(0 != activate_threads_~tmp___4~0); 26037#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26038#L524 assume 1 == ~t6_pc~0; 25769#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25770#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26047#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 25484#L1101 assume !(0 != activate_threads_~tmp___5~0); 25485#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25837#L543 assume !(1 == ~t7_pc~0); 25838#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 26288#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26082#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26083#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25669#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25670#L562 assume 1 == ~t8_pc~0; 26041#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26242#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25430#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25431#L1117 assume !(0 != activate_threads_~tmp___7~0); 26359#L1117-2 assume !(1 == ~M_E~0); 26226#L944-1 assume !(1 == ~T1_E~0); 25861#L949-1 assume !(1 == ~T2_E~0); 25859#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25860#L959-1 assume !(1 == ~T4_E~0); 26236#L964-1 assume !(1 == ~T5_E~0); 25648#L969-1 assume !(1 == ~T6_E~0); 25649#L974-1 assume !(1 == ~T7_E~0); 26194#L979-1 assume !(1 == ~T8_E~0); 26195#L984-1 assume !(1 == ~E_M~0); 25780#L989-1 assume !(1 == ~E_1~0); 25781#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25686#L999-1 assume !(1 == ~E_3~0); 25687#L1004-1 assume !(1 == ~E_4~0); 25407#L1009-1 assume !(1 == ~E_5~0); 25408#L1014-1 assume !(1 == ~E_6~0); 25679#L1019-1 assume !(1 == ~E_7~0); 26151#L1024-1 assume !(1 == ~E_8~0); 26305#L1295-1 [2021-11-02 22:59:25,785 INFO L793 eck$LassoCheckResult]: Loop: 26305#L1295-1 assume !false; 26283#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 25583#L821 assume !false; 26317#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 25425#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 25427#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26369#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 26010#L704 assume !(0 != eval_~tmp~0); 26012#L836 start_simulation_~kernel_st~0 := 2; 26301#L582-1 start_simulation_~kernel_st~0 := 3; 25401#L846-2 assume !(0 == ~M_E~0); 25358#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25359#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25479#L856-3 assume !(0 == ~T3_E~0); 25480#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25395#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25396#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25698#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25712#L881-3 assume !(0 == ~T8_E~0); 25713#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25909#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25910#L896-3 assume !(0 == ~E_2~0); 25789#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25790#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25913#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26093#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25726#L921-3 assume !(0 == ~E_7~0); 25727#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26074#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25471#L410-30 assume 1 == ~m_pc~0; 25402#L411-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 25404#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25644#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25851#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26264#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26318#L429-30 assume !(1 == ~t1_pc~0); 25828#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 25829#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25796#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25797#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25611#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25612#L448-30 assume !(1 == ~t2_pc~0); 26145#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 26144#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25405#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25406#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26343#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26344#L467-30 assume 1 == ~t3_pc~0; 26346#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25974#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25975#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 25516#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25517#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25822#L486-30 assume 1 == ~t4_pc~0; 26091#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25890#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25891#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 26333#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25720#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25598#L505-30 assume 1 == ~t5_pc~0; 25600#L506-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26267#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25849#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25850#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 26244#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26245#L524-30 assume !(1 == ~t6_pc~0); 26132#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 26133#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26326#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 26136#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 26137#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25636#L543-30 assume !(1 == ~t7_pc~0); 25489#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 26307#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26308#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26203#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25536#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25537#L562-30 assume 1 == ~t8_pc~0; 25524#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 25397#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25398#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25372#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25373#L1117-32 assume !(1 == ~M_E~0); 25696#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27006#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27005#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27004#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26817#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26814#L969-3 assume !(1 == ~T6_E~0); 26812#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26810#L979-3 assume !(1 == ~T8_E~0); 25946#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25947#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25631#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25632#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26066#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25469#L1009-3 assume !(1 == ~E_5~0); 25470#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26134#L1019-3 assume !(1 == ~E_7~0); 26750#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26749#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26742#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26723#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26722#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 25980#L1314 assume !(0 == start_simulation_~tmp~3); 25982#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26335#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26403#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26296#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 26052#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 26053#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 25386#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 25387#L1327 assume !(0 != start_simulation_~tmp___0~1); 26305#L1295-1 [2021-11-02 22:59:25,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,786 INFO L85 PathProgramCache]: Analyzing trace with hash -998157063, now seen corresponding path program 1 times [2021-11-02 22:59:25,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,787 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168618645] [2021-11-02 22:59:25,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,840 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168618645] [2021-11-02 22:59:25,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168618645] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,840 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:25,842 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933925798] [2021-11-02 22:59:25,843 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:25,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:25,843 INFO L85 PathProgramCache]: Analyzing trace with hash -940747100, now seen corresponding path program 1 times [2021-11-02 22:59:25,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:25,844 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487184073] [2021-11-02 22:59:25,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:25,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:25,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:25,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:25,886 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:25,886 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487184073] [2021-11-02 22:59:25,886 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487184073] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:25,886 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:25,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:25,887 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558707476] [2021-11-02 22:59:25,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:25,887 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:25,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:59:25,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:59:25,888 INFO L87 Difference]: Start difference. First operand 1761 states and 2591 transitions. cyclomatic complexity: 831 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:26,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:26,232 INFO L93 Difference]: Finished difference Result 4852 states and 7042 transitions. [2021-11-02 22:59:26,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:59:26,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4852 states and 7042 transitions. [2021-11-02 22:59:26,282 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4605 [2021-11-02 22:59:26,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4852 states to 4852 states and 7042 transitions. [2021-11-02 22:59:26,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4852 [2021-11-02 22:59:26,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4852 [2021-11-02 22:59:26,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4852 states and 7042 transitions. [2021-11-02 22:59:26,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:26,355 INFO L681 BuchiCegarLoop]: Abstraction has 4852 states and 7042 transitions. [2021-11-02 22:59:26,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4852 states and 7042 transitions. [2021-11-02 22:59:26,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4852 to 4612. [2021-11-02 22:59:26,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4612 states, 4612 states have (on average 1.4557675628794449) internal successors, (6714), 4611 states have internal predecessors, (6714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:26,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4612 states to 4612 states and 6714 transitions. [2021-11-02 22:59:26,537 INFO L704 BuchiCegarLoop]: Abstraction has 4612 states and 6714 transitions. [2021-11-02 22:59:26,537 INFO L587 BuchiCegarLoop]: Abstraction has 4612 states and 6714 transitions. [2021-11-02 22:59:26,537 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-02 22:59:26,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4612 states and 6714 transitions. [2021-11-02 22:59:26,565 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4493 [2021-11-02 22:59:26,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:26,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:26,567 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:26,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:26,568 INFO L791 eck$LassoCheckResult]: Stem: 32739#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 32740#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 33140#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32754#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 32755#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32469#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32470#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32008#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32002#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32003#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32122#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32216#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32990#L629-1 assume !(0 == ~M_E~0); 32214#L846-1 assume !(0 == ~T1_E~0); 32215#L851-1 assume !(0 == ~T2_E~0); 32244#L856-1 assume !(0 == ~T3_E~0); 32245#L861-1 assume !(0 == ~T4_E~0); 32788#L866-1 assume !(0 == ~T5_E~0); 32690#L871-1 assume !(0 == ~T6_E~0); 32691#L876-1 assume !(0 == ~T7_E~0); 33092#L881-1 assume !(0 == ~T8_E~0); 32707#L886-1 assume !(0 == ~E_M~0); 32473#L891-1 assume !(0 == ~E_1~0); 32474#L896-1 assume !(0 == ~E_2~0); 32694#L901-1 assume !(0 == ~E_3~0); 32727#L906-1 assume !(0 == ~E_4~0); 32728#L911-1 assume !(0 == ~E_5~0); 32521#L916-1 assume !(0 == ~E_6~0); 32522#L921-1 assume !(0 == ~E_7~0); 32869#L926-1 assume !(0 == ~E_8~0); 33013#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33103#L410 assume !(1 == ~m_pc~0); 32413#L410-2 is_master_triggered_~__retres1~0 := 0; 32414#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33043#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 32837#L1053 assume !(0 != activate_threads_~tmp~1); 32838#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32910#L429 assume !(1 == ~t1_pc~0); 32824#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 32825#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32013#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32014#L1061 assume !(0 != activate_threads_~tmp___0~0); 32783#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32784#L448 assume !(1 == ~t2_pc~0); 32129#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 32130#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32419#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32321#L1069 assume !(0 != activate_threads_~tmp___1~0); 32322#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33084#L467 assume 1 == ~t3_pc~0; 32588#L468 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32200#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32201#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32677#L1077 assume !(0 != activate_threads_~tmp___2~0); 32549#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32144#L486 assume !(1 == ~t4_pc~0); 32145#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 32741#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32127#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32128#L1085 assume !(0 != activate_threads_~tmp___3~0); 32323#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32324#L505 assume 1 == ~t5_pc~0; 32581#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32582#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33177#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33176#L1093 assume !(0 != activate_threads_~tmp___4~0); 32692#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32693#L524 assume 1 == ~t6_pc~0; 32404#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32405#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32708#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32109#L1101 assume !(0 != activate_threads_~tmp___5~0); 32110#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32476#L543 assume !(1 == ~t7_pc~0); 32477#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 33028#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32749#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32750#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32296#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32297#L562 assume 1 == ~t8_pc~0; 32698#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32969#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32054#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32055#L1117 assume !(0 != activate_threads_~tmp___7~0); 33168#L1117-2 assume !(1 == ~M_E~0); 32933#L944-1 assume !(1 == ~T1_E~0); 32504#L949-1 assume !(1 == ~T2_E~0); 32502#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32503#L959-1 assume !(1 == ~T4_E~0); 32950#L964-1 assume !(1 == ~T5_E~0); 32276#L969-1 assume !(1 == ~T6_E~0); 32277#L974-1 assume !(1 == ~T7_E~0); 32891#L979-1 assume !(1 == ~T8_E~0); 32892#L984-1 assume !(1 == ~E_M~0); 32415#L989-1 assume !(1 == ~E_1~0); 32416#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32315#L999-1 assume !(1 == ~E_3~0); 32316#L1004-1 assume !(1 == ~E_4~0); 32031#L1009-1 assume !(1 == ~E_5~0); 32032#L1014-1 assume !(1 == ~E_6~0); 32306#L1019-1 assume !(1 == ~E_7~0); 32834#L1024-1 assume !(1 == ~E_8~0); 33053#L1295-1 [2021-11-02 22:59:26,569 INFO L793 eck$LassoCheckResult]: Loop: 33053#L1295-1 assume !false; 33019#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 32210#L821 assume !false; 35316#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 35261#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32984#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 32985#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 32665#L704 assume !(0 != eval_~tmp~0); 32667#L836 start_simulation_~kernel_st~0 := 2; 33049#L582-1 start_simulation_~kernel_st~0 := 3; 32024#L846-2 assume !(0 == ~M_E~0); 32025#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32609#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32610#L856-3 assume !(0 == ~T3_E~0); 32798#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32799#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32329#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32330#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32346#L881-3 assume !(0 == ~T8_E~0); 32347#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32558#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32559#L896-3 assume !(0 == ~E_2~0); 32423#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32424#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35226#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35227#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35222#L921-3 assume !(0 == ~E_7~0); 35223#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32870#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32871#L410-30 assume !(1 == ~m_pc~0); 32645#L410-32 is_master_triggered_~__retres1~0 := 0; 32646#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32490#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 32491#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 33180#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33181#L429-30 assume !(1 == ~t1_pc~0); 32464#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 32465#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32431#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32432#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32238#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32239#L448-30 assume !(1 == ~t2_pc~0); 36483#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 32963#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32029#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32030#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33139#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33142#L467-30 assume 1 == ~t3_pc~0; 33143#L468-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32626#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32627#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32140#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32141#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32764#L486-30 assume 1 == ~t4_pc~0; 32765#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32539#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32540#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 33104#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36479#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36478#L505-30 assume 1 == ~t5_pc~0; 33014#L506-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32996#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32997#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33148#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 33149#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36476#L524-30 assume 1 == ~t6_pc~0; 36474#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 33089#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33090#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36473#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 33061#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 33062#L543-30 assume !(1 == ~t7_pc~0); 36471#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 33056#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33057#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32902#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32162#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32163#L562-30 assume 1 == ~t8_pc~0; 32597#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 36443#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36442#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 31995#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 31996#L1117-32 assume !(1 == ~M_E~0); 32325#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36490#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32904#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32905#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36488#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36486#L969-3 assume !(1 == ~T6_E~0); 32198#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32199#L979-3 assume !(1 == ~T8_E~0); 32595#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32596#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32258#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32259#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32732#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32733#L1009-3 assume !(1 == ~E_5~0); 32816#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32817#L1019-3 assume !(1 == ~E_7~0); 36247#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36246#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 33099#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32218#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 32345#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 32632#L1314 assume !(0 == start_simulation_~tmp~3); 32634#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 33052#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32091#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 33040#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 33041#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 33102#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 32009#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 32010#L1327 assume !(0 != start_simulation_~tmp___0~1); 33053#L1295-1 [2021-11-02 22:59:26,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:26,570 INFO L85 PathProgramCache]: Analyzing trace with hash -620514246, now seen corresponding path program 1 times [2021-11-02 22:59:26,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:26,572 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125809402] [2021-11-02 22:59:26,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:26,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:26,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:26,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:26,622 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:26,622 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125809402] [2021-11-02 22:59:26,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2125809402] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:26,622 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:26,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:26,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557317477] [2021-11-02 22:59:26,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:26,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:26,625 INFO L85 PathProgramCache]: Analyzing trace with hash 1466479396, now seen corresponding path program 1 times [2021-11-02 22:59:26,625 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:26,625 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132963049] [2021-11-02 22:59:26,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:26,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:26,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:26,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:26,669 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:26,669 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132963049] [2021-11-02 22:59:26,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132963049] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:26,669 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:26,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:26,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325071891] [2021-11-02 22:59:26,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:26,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:26,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:59:26,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:59:26,672 INFO L87 Difference]: Start difference. First operand 4612 states and 6714 transitions. cyclomatic complexity: 2104 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:27,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:27,094 INFO L93 Difference]: Finished difference Result 12959 states and 18667 transitions. [2021-11-02 22:59:27,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:59:27,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12959 states and 18667 transitions. [2021-11-02 22:59:27,212 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12539 [2021-11-02 22:59:27,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12959 states to 12959 states and 18667 transitions. [2021-11-02 22:59:27,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12959 [2021-11-02 22:59:27,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12959 [2021-11-02 22:59:27,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12959 states and 18667 transitions. [2021-11-02 22:59:27,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:27,366 INFO L681 BuchiCegarLoop]: Abstraction has 12959 states and 18667 transitions. [2021-11-02 22:59:27,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12959 states and 18667 transitions. [2021-11-02 22:59:27,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12959 to 12425. [2021-11-02 22:59:27,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12425 states, 12425 states have (on average 1.4445875251509055) internal successors, (17949), 12424 states have internal predecessors, (17949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:27,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12425 states to 12425 states and 17949 transitions. [2021-11-02 22:59:27,829 INFO L704 BuchiCegarLoop]: Abstraction has 12425 states and 17949 transitions. [2021-11-02 22:59:27,829 INFO L587 BuchiCegarLoop]: Abstraction has 12425 states and 17949 transitions. [2021-11-02 22:59:27,829 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-02 22:59:27,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12425 states and 17949 transitions. [2021-11-02 22:59:27,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12287 [2021-11-02 22:59:27,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:27,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:27,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:27,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:27,907 INFO L791 eck$LassoCheckResult]: Stem: 50333#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 50334#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50748#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 50350#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 50351#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50046#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50047#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49589#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49583#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49584#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49702#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49793#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50593#L629-1 assume !(0 == ~M_E~0); 49791#L846-1 assume !(0 == ~T1_E~0); 49792#L851-1 assume !(0 == ~T2_E~0); 49821#L856-1 assume !(0 == ~T3_E~0); 49822#L861-1 assume !(0 == ~T4_E~0); 50380#L866-1 assume !(0 == ~T5_E~0); 50283#L871-1 assume !(0 == ~T6_E~0); 50284#L876-1 assume !(0 == ~T7_E~0); 50701#L881-1 assume !(0 == ~T8_E~0); 50300#L886-1 assume !(0 == ~E_M~0); 50050#L891-1 assume !(0 == ~E_1~0); 50051#L896-1 assume !(0 == ~E_2~0); 50287#L901-1 assume !(0 == ~E_3~0); 50321#L906-1 assume !(0 == ~E_4~0); 50322#L911-1 assume !(0 == ~E_5~0); 50099#L916-1 assume !(0 == ~E_6~0); 50100#L921-1 assume !(0 == ~E_7~0); 50472#L926-1 assume !(0 == ~E_8~0); 50617#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50707#L410 assume !(1 == ~m_pc~0); 49991#L410-2 is_master_triggered_~__retres1~0 := 0; 49992#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50650#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 50435#L1053 assume !(0 != activate_threads_~tmp~1); 50436#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50511#L429 assume !(1 == ~t1_pc~0); 50422#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 50423#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49594#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 49595#L1061 assume !(0 != activate_threads_~tmp___0~0); 50375#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50376#L448 assume !(1 == ~t2_pc~0); 49709#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 49710#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49997#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 49900#L1069 assume !(0 != activate_threads_~tmp___1~0); 49901#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50696#L467 assume !(1 == ~t3_pc~0); 50146#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 49778#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49779#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 50269#L1077 assume !(0 != activate_threads_~tmp___2~0); 50126#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49723#L486 assume !(1 == ~t4_pc~0); 49724#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 50335#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49707#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 49708#L1085 assume !(0 != activate_threads_~tmp___3~0); 49902#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49903#L505 assume 1 == ~t5_pc~0; 50160#L506 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 50161#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50788#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 50787#L1093 assume !(0 != activate_threads_~tmp___4~0); 50285#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50286#L524 assume 1 == ~t6_pc~0; 49982#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 49983#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 50301#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 49689#L1101 assume !(0 != activate_threads_~tmp___5~0); 49690#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50053#L543 assume !(1 == ~t7_pc~0); 50054#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 50634#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 50345#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50346#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49875#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49876#L562 assume 1 == ~t8_pc~0; 50291#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 50571#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49634#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 49635#L1117 assume !(0 != activate_threads_~tmp___7~0); 50777#L1117-2 assume !(1 == ~M_E~0); 50532#L944-1 assume !(1 == ~T1_E~0); 50082#L949-1 assume !(1 == ~T2_E~0); 50080#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50081#L959-1 assume !(1 == ~T4_E~0); 50555#L964-1 assume !(1 == ~T5_E~0); 49853#L969-1 assume !(1 == ~T6_E~0); 49854#L974-1 assume !(1 == ~T7_E~0); 50492#L979-1 assume !(1 == ~T8_E~0); 50493#L984-1 assume !(1 == ~E_M~0); 49993#L989-1 assume !(1 == ~E_1~0); 49994#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49894#L999-1 assume !(1 == ~E_3~0); 49895#L1004-1 assume !(1 == ~E_4~0); 49612#L1009-1 assume !(1 == ~E_5~0); 49613#L1014-1 assume !(1 == ~E_6~0); 49885#L1019-1 assume !(1 == ~E_7~0); 50432#L1024-1 assume !(1 == ~E_8~0); 50662#L1295-1 [2021-11-02 22:59:27,907 INFO L793 eck$LassoCheckResult]: Loop: 50662#L1295-1 assume !false; 59875#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 59873#L821 assume !false; 59871#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 59868#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 59857#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 59851#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 59852#L704 assume !(0 != eval_~tmp~0); 61280#L836 start_simulation_~kernel_st~0 := 2; 61278#L582-1 start_simulation_~kernel_st~0 := 3; 61277#L846-2 assume !(0 == ~M_E~0); 61275#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61274#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61273#L856-3 assume !(0 == ~T3_E~0); 61272#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61270#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61269#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61268#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61266#L881-3 assume !(0 == ~T8_E~0); 61265#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61264#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61263#L896-3 assume !(0 == ~E_2~0); 61262#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61261#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61260#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61258#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61257#L921-3 assume !(0 == ~E_7~0); 61256#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61255#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61254#L410-30 assume !(1 == ~m_pc~0); 61253#L410-32 is_master_triggered_~__retres1~0 := 0; 61252#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61251#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 61250#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 61249#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61248#L429-30 assume !(1 == ~t1_pc~0); 61247#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 61246#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61244#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 61242#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 61241#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61240#L448-30 assume !(1 == ~t2_pc~0); 61236#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 61234#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61232#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 61231#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 61230#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61229#L467-30 assume !(1 == ~t3_pc~0); 61228#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 61227#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61226#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 61225#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 61224#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61222#L486-30 assume !(1 == ~t4_pc~0); 61218#L486-32 is_transmit4_triggered_~__retres1~4 := 0; 61217#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61216#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 61215#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 61214#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 61213#L505-30 assume 1 == ~t5_pc~0; 61209#L506-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 61208#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 61206#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 61204#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 61203#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 61202#L524-30 assume 1 == ~t6_pc~0; 61198#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 61196#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 61194#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 61180#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 61178#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 61175#L543-30 assume !(1 == ~t7_pc~0); 61172#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 50666#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 50667#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50723#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49740#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49741#L562-30 assume 1 == ~t8_pc~0; 50176#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 61155#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49755#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 49756#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 61123#L1117-32 assume !(1 == ~M_E~0); 60829#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61122#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61121#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61120#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61119#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61118#L969-3 assume !(1 == ~T6_E~0); 61117#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61116#L979-3 assume !(1 == ~T8_E~0); 61115#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61114#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61113#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61112#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61111#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49673#L1009-3 assume !(1 == ~E_5~0); 49674#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50154#L1019-3 assume !(1 == ~E_7~0); 50155#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60360#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 60320#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 60311#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 60308#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 60309#L1314 assume !(0 == start_simulation_~tmp~3); 60302#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 60268#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 60258#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 60256#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 60254#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 60252#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 60250#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 60248#L1327 assume !(0 != start_simulation_~tmp___0~1); 50662#L1295-1 [2021-11-02 22:59:27,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:27,908 INFO L85 PathProgramCache]: Analyzing trace with hash -894292741, now seen corresponding path program 1 times [2021-11-02 22:59:27,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:27,909 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277913328] [2021-11-02 22:59:27,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:27,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:27,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:27,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:27,956 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:27,956 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277913328] [2021-11-02 22:59:27,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277913328] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:27,956 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:27,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:27,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879172113] [2021-11-02 22:59:27,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:27,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:27,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1617979358, now seen corresponding path program 1 times [2021-11-02 22:59:27,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:27,958 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438268629] [2021-11-02 22:59:27,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:27,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:27,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:28,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:28,003 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:28,003 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438268629] [2021-11-02 22:59:28,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438268629] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:28,004 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:28,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:28,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600670888] [2021-11-02 22:59:28,004 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:28,004 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:28,007 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:59:28,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:59:28,008 INFO L87 Difference]: Start difference. First operand 12425 states and 17949 transitions. cyclomatic complexity: 5528 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:28,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:28,586 INFO L93 Difference]: Finished difference Result 34940 states and 50042 transitions. [2021-11-02 22:59:28,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:59:28,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34940 states and 50042 transitions. [2021-11-02 22:59:29,153 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 34159 [2021-11-02 22:59:29,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34940 states to 34940 states and 50042 transitions. [2021-11-02 22:59:29,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34940 [2021-11-02 22:59:29,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34940 [2021-11-02 22:59:29,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34940 states and 50042 transitions. [2021-11-02 22:59:29,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:29,658 INFO L681 BuchiCegarLoop]: Abstraction has 34940 states and 50042 transitions. [2021-11-02 22:59:29,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states and 50042 transitions. [2021-11-02 22:59:30,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 33832. [2021-11-02 22:59:30,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33832 states, 33832 states have (on average 1.4359777725230551) internal successors, (48582), 33831 states have internal predecessors, (48582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:30,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33832 states to 33832 states and 48582 transitions. [2021-11-02 22:59:30,777 INFO L704 BuchiCegarLoop]: Abstraction has 33832 states and 48582 transitions. [2021-11-02 22:59:30,778 INFO L587 BuchiCegarLoop]: Abstraction has 33832 states and 48582 transitions. [2021-11-02 22:59:30,778 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-02 22:59:30,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33832 states and 48582 transitions. [2021-11-02 22:59:31,081 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33655 [2021-11-02 22:59:31,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:31,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:31,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:31,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:31,084 INFO L791 eck$LassoCheckResult]: Stem: 97669#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 97670#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 97997#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97683#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 97684#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97411#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97412#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96964#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96958#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96959#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97075#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97164#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97878#L629-1 assume !(0 == ~M_E~0); 97162#L846-1 assume !(0 == ~T1_E~0); 97163#L851-1 assume !(0 == ~T2_E~0); 97192#L856-1 assume !(0 == ~T3_E~0); 97193#L861-1 assume !(0 == ~T4_E~0); 97710#L866-1 assume !(0 == ~T5_E~0); 97627#L871-1 assume !(0 == ~T6_E~0); 97628#L876-1 assume !(0 == ~T7_E~0); 97962#L881-1 assume !(0 == ~T8_E~0); 97640#L886-1 assume !(0 == ~E_M~0); 97413#L891-1 assume !(0 == ~E_1~0); 97414#L896-1 assume !(0 == ~E_2~0); 97631#L901-1 assume !(0 == ~E_3~0); 97661#L906-1 assume !(0 == ~E_4~0); 97662#L911-1 assume !(0 == ~E_5~0); 97459#L916-1 assume !(0 == ~E_6~0); 97460#L921-1 assume !(0 == ~E_7~0); 97789#L926-1 assume !(0 == ~E_8~0); 97897#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97969#L410 assume !(1 == ~m_pc~0); 97354#L410-2 is_master_triggered_~__retres1~0 := 0; 97355#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97923#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 97758#L1053 assume !(0 != activate_threads_~tmp~1); 97759#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97818#L429 assume !(1 == ~t1_pc~0); 97745#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 97746#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96969#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 96970#L1061 assume !(0 != activate_threads_~tmp___0~0); 97705#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97706#L448 assume !(1 == ~t2_pc~0); 97082#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 97083#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97360#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97267#L1069 assume !(0 != activate_threads_~tmp___1~0); 97268#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97957#L467 assume !(1 == ~t3_pc~0); 97505#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 97149#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97150#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 97615#L1077 assume !(0 != activate_threads_~tmp___2~0); 97486#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97097#L486 assume !(1 == ~t4_pc~0); 97098#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 97672#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97080#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 97081#L1085 assume !(0 != activate_threads_~tmp___3~0); 97269#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97270#L505 assume !(1 == ~t5_pc~0); 97580#L505-2 is_transmit5_triggered_~__retres1~5 := 0; 97649#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98015#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 98014#L1093 assume !(0 != activate_threads_~tmp___4~0); 97629#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 97630#L524 assume 1 == ~t6_pc~0; 97345#L525 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 97346#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97641#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 97062#L1101 assume !(0 != activate_threads_~tmp___5~0); 97063#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97416#L543 assume !(1 == ~t7_pc~0); 97417#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 97912#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 97678#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 97679#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 97245#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 97246#L562 assume 1 == ~t8_pc~0; 97635#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 97861#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 97008#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 97009#L1117 assume !(0 != activate_threads_~tmp___7~0); 98008#L1117-2 assume !(1 == ~M_E~0); 97834#L944-1 assume !(1 == ~T1_E~0); 97443#L949-1 assume !(1 == ~T2_E~0); 97441#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97442#L959-1 assume !(1 == ~T4_E~0); 97849#L964-1 assume !(1 == ~T5_E~0); 97221#L969-1 assume !(1 == ~T6_E~0); 97222#L974-1 assume !(1 == ~T7_E~0); 97800#L979-1 assume !(1 == ~T8_E~0); 97801#L984-1 assume !(1 == ~E_M~0); 97356#L989-1 assume !(1 == ~E_1~0); 97357#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 97260#L999-1 assume !(1 == ~E_3~0); 97261#L1004-1 assume !(1 == ~E_4~0); 96986#L1009-1 assume !(1 == ~E_5~0); 96987#L1014-1 assume !(1 == ~E_6~0); 97253#L1019-1 assume !(1 == ~E_7~0); 97755#L1024-1 assume !(1 == ~E_8~0); 97934#L1295-1 [2021-11-02 22:59:31,085 INFO L793 eck$LassoCheckResult]: Loop: 97934#L1295-1 assume !false; 124869#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 124865#L821 assume !false; 124863#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 124813#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 124803#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 124801#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 124798#L704 assume !(0 != eval_~tmp~0); 124799#L836 start_simulation_~kernel_st~0 := 2; 125462#L582-1 start_simulation_~kernel_st~0 := 3; 125460#L846-2 assume !(0 == ~M_E~0); 125458#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 125456#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 125454#L856-3 assume !(0 == ~T3_E~0); 125452#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 125450#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 125448#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 125446#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 125444#L881-3 assume !(0 == ~T8_E~0); 125442#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 125439#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 125437#L896-3 assume !(0 == ~E_2~0); 125435#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 125433#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 125431#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 125429#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 125427#L921-3 assume !(0 == ~E_7~0); 125425#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 125423#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 125421#L410-30 assume !(1 == ~m_pc~0); 125419#L410-32 is_master_triggered_~__retres1~0 := 0; 125417#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 125414#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 125412#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 125410#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 125408#L429-30 assume !(1 == ~t1_pc~0); 125406#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 125404#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 125402#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 125400#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 125398#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 125396#L448-30 assume !(1 == ~t2_pc~0); 125393#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 125391#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 125388#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 125386#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 125384#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 125382#L467-30 assume !(1 == ~t3_pc~0); 125380#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 125377#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 125375#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 125373#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 125371#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 125369#L486-30 assume 1 == ~t4_pc~0; 125367#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 125364#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 125361#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 125359#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 125358#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 125357#L505-30 assume !(1 == ~t5_pc~0); 125356#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 125355#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 125354#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 125353#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 125350#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 125348#L524-30 assume 1 == ~t6_pc~0; 125345#L525-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 125343#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 125341#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 125339#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 125337#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 125334#L543-30 assume !(1 == ~t7_pc~0); 125331#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 125329#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 125327#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 125326#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 125325#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 125324#L562-30 assume 1 == ~t8_pc~0; 125321#L563-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 125319#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 125317#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 125315#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 125313#L1117-32 assume !(1 == ~M_E~0); 125309#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 125307#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125305#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125303#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125301#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 125299#L969-3 assume !(1 == ~T6_E~0); 125297#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125295#L979-3 assume !(1 == ~T8_E~0); 125292#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 125290#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 125288#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 125286#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 125284#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 125282#L1009-3 assume !(1 == ~E_5~0); 125280#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 125278#L1019-3 assume !(1 == ~E_7~0); 125276#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 125274#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 125259#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 125242#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 125240#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 125230#L1314 assume !(0 == start_simulation_~tmp~3); 125227#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 125225#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 125208#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 125203#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 125199#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 125066#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 125058#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 124896#L1327 assume !(0 != start_simulation_~tmp___0~1); 97934#L1295-1 [2021-11-02 22:59:31,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:31,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1379467460, now seen corresponding path program 1 times [2021-11-02 22:59:31,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:31,088 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633107693] [2021-11-02 22:59:31,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:31,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:31,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:31,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:31,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:31,272 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633107693] [2021-11-02 22:59:31,272 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633107693] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:31,272 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:31,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:31,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626653486] [2021-11-02 22:59:31,273 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:31,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:31,274 INFO L85 PathProgramCache]: Analyzing trace with hash 391306082, now seen corresponding path program 1 times [2021-11-02 22:59:31,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:31,274 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941884086] [2021-11-02 22:59:31,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:31,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:31,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:31,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:31,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:31,323 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941884086] [2021-11-02 22:59:31,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941884086] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:31,325 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:31,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:31,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431181193] [2021-11-02 22:59:31,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:31,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:31,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:59:31,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:59:31,327 INFO L87 Difference]: Start difference. First operand 33832 states and 48582 transitions. cyclomatic complexity: 14758 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:32,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:32,280 INFO L93 Difference]: Finished difference Result 94809 states and 135157 transitions. [2021-11-02 22:59:32,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:59:32,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94809 states and 135157 transitions. [2021-11-02 22:59:33,195 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 93261 [2021-11-02 22:59:33,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94809 states to 94809 states and 135157 transitions. [2021-11-02 22:59:33,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94809 [2021-11-02 22:59:33,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94809 [2021-11-02 22:59:33,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94809 states and 135157 transitions. [2021-11-02 22:59:33,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:33,909 INFO L681 BuchiCegarLoop]: Abstraction has 94809 states and 135157 transitions. [2021-11-02 22:59:33,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94809 states and 135157 transitions. [2021-11-02 22:59:35,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94809 to 92383. [2021-11-02 22:59:35,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92383 states, 92383 states have (on average 1.4284771007652923) internal successors, (131967), 92382 states have internal predecessors, (131967), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:36,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92383 states to 92383 states and 131967 transitions. [2021-11-02 22:59:36,510 INFO L704 BuchiCegarLoop]: Abstraction has 92383 states and 131967 transitions. [2021-11-02 22:59:36,510 INFO L587 BuchiCegarLoop]: Abstraction has 92383 states and 131967 transitions. [2021-11-02 22:59:36,511 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-02 22:59:36,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92383 states and 131967 transitions. [2021-11-02 22:59:36,827 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 92127 [2021-11-02 22:59:36,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:36,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:36,835 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:36,835 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:36,836 INFO L791 eck$LassoCheckResult]: Stem: 226328#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 226329#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 226703#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 226343#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 226344#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 226059#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226060#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 225615#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 225609#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 225610#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 225726#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 225816#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226577#L629-1 assume !(0 == ~M_E~0); 225814#L846-1 assume !(0 == ~T1_E~0); 225815#L851-1 assume !(0 == ~T2_E~0); 225844#L856-1 assume !(0 == ~T3_E~0); 225845#L861-1 assume !(0 == ~T4_E~0); 226373#L866-1 assume !(0 == ~T5_E~0); 226285#L871-1 assume !(0 == ~T6_E~0); 226286#L876-1 assume !(0 == ~T7_E~0); 226662#L881-1 assume !(0 == ~T8_E~0); 226298#L886-1 assume !(0 == ~E_M~0); 226062#L891-1 assume !(0 == ~E_1~0); 226063#L896-1 assume !(0 == ~E_2~0); 226289#L901-1 assume !(0 == ~E_3~0); 226320#L906-1 assume !(0 == ~E_4~0); 226321#L911-1 assume !(0 == ~E_5~0); 226113#L916-1 assume !(0 == ~E_6~0); 226114#L921-1 assume !(0 == ~E_7~0); 226463#L926-1 assume !(0 == ~E_8~0); 226591#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 226670#L410 assume !(1 == ~m_pc~0); 226003#L410-2 is_master_triggered_~__retres1~0 := 0; 226004#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 226616#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 226428#L1053 assume !(0 != activate_threads_~tmp~1); 226429#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 226500#L429 assume !(1 == ~t1_pc~0); 226415#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 226416#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 225620#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 225621#L1061 assume !(0 != activate_threads_~tmp___0~0); 226368#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 226369#L448 assume !(1 == ~t2_pc~0); 225733#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 225734#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 226009#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 225918#L1069 assume !(0 != activate_threads_~tmp___1~0); 225919#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226657#L467 assume !(1 == ~t3_pc~0); 226161#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 225801#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 225802#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 226271#L1077 assume !(0 != activate_threads_~tmp___2~0); 226142#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 225748#L486 assume !(1 == ~t4_pc~0); 225749#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 226331#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 225731#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 225732#L1085 assume !(0 != activate_threads_~tmp___3~0); 225920#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 225921#L505 assume !(1 == ~t5_pc~0); 226236#L505-2 is_transmit5_triggered_~__retres1~5 := 0; 226310#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 226730#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 226729#L1093 assume !(0 != activate_threads_~tmp___4~0); 226287#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 226288#L524 assume !(1 == ~t6_pc~0); 226470#L524-2 is_transmit6_triggered_~__retres1~6 := 0; 226299#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 226300#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 225713#L1101 assume !(0 != activate_threads_~tmp___5~0); 225714#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 226065#L543 assume !(1 == ~t7_pc~0); 226066#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 226603#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 226338#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 226339#L1109 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 225897#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 225898#L562 assume 1 == ~t8_pc~0; 226293#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 226559#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 225657#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 225658#L1117 assume !(0 != activate_threads_~tmp___7~0); 226723#L1117-2 assume !(1 == ~M_E~0); 226522#L944-1 assume !(1 == ~T1_E~0); 226093#L949-1 assume !(1 == ~T2_E~0); 226091#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 226092#L959-1 assume !(1 == ~T4_E~0); 226542#L964-1 assume !(1 == ~T5_E~0); 225874#L969-1 assume !(1 == ~T6_E~0); 225875#L974-1 assume !(1 == ~T7_E~0); 226481#L979-1 assume !(1 == ~T8_E~0); 226482#L984-1 assume !(1 == ~E_M~0); 226005#L989-1 assume !(1 == ~E_1~0); 226006#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 225912#L999-1 assume !(1 == ~E_3~0); 225913#L1004-1 assume !(1 == ~E_4~0); 225637#L1009-1 assume !(1 == ~E_5~0); 225638#L1014-1 assume !(1 == ~E_6~0); 225905#L1019-1 assume !(1 == ~E_7~0); 226425#L1024-1 assume !(1 == ~E_8~0); 226624#L1295-1 [2021-11-02 22:59:36,836 INFO L793 eck$LassoCheckResult]: Loop: 226624#L1295-1 assume !false; 232199#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 232196#L821 assume !false; 232195#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 232102#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 232085#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 232076#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 232065#L704 assume !(0 != eval_~tmp~0); 232066#L836 start_simulation_~kernel_st~0 := 2; 313116#L582-1 start_simulation_~kernel_st~0 := 3; 313115#L846-2 assume !(0 == ~M_E~0); 313114#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 313113#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 313112#L856-3 assume !(0 == ~T3_E~0); 313111#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 313110#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 313109#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 313108#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 313107#L881-3 assume !(0 == ~T8_E~0); 313106#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 313105#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 313104#L896-3 assume !(0 == ~E_2~0); 313103#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 313102#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 313101#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 313100#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 313099#L921-3 assume !(0 == ~E_7~0); 313098#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 313097#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 313096#L410-30 assume !(1 == ~m_pc~0); 313095#L410-32 is_master_triggered_~__retres1~0 := 0; 313094#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 313093#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 313092#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 313091#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 313090#L429-30 assume !(1 == ~t1_pc~0); 313089#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 313088#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 313087#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 313086#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 313085#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 232946#L448-30 assume !(1 == ~t2_pc~0); 232947#L448-32 is_transmit2_triggered_~__retres1~2 := 0; 313082#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 313081#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 232931#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 232932#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 232922#L467-30 assume !(1 == ~t3_pc~0); 232923#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 232913#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 232914#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 232905#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 232906#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 232896#L486-30 assume !(1 == ~t4_pc~0); 232898#L486-32 is_transmit4_triggered_~__retres1~4 := 0; 232884#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 232885#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 306858#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 232866#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 232867#L505-30 assume !(1 == ~t5_pc~0); 232855#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 232856#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 232842#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 232843#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 232831#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 232832#L524-30 assume !(1 == ~t6_pc~0); 232819#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 232820#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 232808#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 232809#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 232798#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 232799#L543-30 assume !(1 == ~t7_pc~0); 232560#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 232561#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 232554#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 232555#L1109-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 232549#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 232547#L562-30 assume !(1 == ~t8_pc~0); 232545#L562-32 is_transmit8_triggered_~__retres1~8 := 0; 232544#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 232536#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 232537#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 232531#L1117-32 assume !(1 == ~M_E~0); 232529#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 232522#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 232523#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 232515#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232516#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 232509#L969-3 assume !(1 == ~T6_E~0); 232510#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 232501#L979-3 assume !(1 == ~T8_E~0); 232502#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 232495#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 232496#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 232489#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 232490#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 232483#L1009-3 assume !(1 == ~E_5~0); 232484#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 232477#L1019-3 assume !(1 == ~E_7~0); 232478#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 232471#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 232472#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 302455#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 302454#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 302453#L1314 assume !(0 == start_simulation_~tmp~3); 232450#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 232449#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 232268#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 232264#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 232262#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 232256#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 232255#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 232254#L1327 assume !(0 != start_simulation_~tmp___0~1); 226624#L1295-1 [2021-11-02 22:59:36,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:36,838 INFO L85 PathProgramCache]: Analyzing trace with hash -328018371, now seen corresponding path program 1 times [2021-11-02 22:59:36,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:36,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895669900] [2021-11-02 22:59:36,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:36,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:36,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:36,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:36,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:36,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895669900] [2021-11-02 22:59:36,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895669900] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:36,900 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:36,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 22:59:36,901 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783592460] [2021-11-02 22:59:36,901 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:36,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:36,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1847160001, now seen corresponding path program 1 times [2021-11-02 22:59:36,902 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:36,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487759999] [2021-11-02 22:59:36,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:36,903 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:36,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:36,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:36,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:36,948 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487759999] [2021-11-02 22:59:36,948 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487759999] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:36,948 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:36,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:36,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99483279] [2021-11-02 22:59:36,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:36,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:36,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 22:59:36,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 22:59:36,950 INFO L87 Difference]: Start difference. First operand 92383 states and 131967 transitions. cyclomatic complexity: 39600 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:37,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:37,717 INFO L93 Difference]: Finished difference Result 122879 states and 174505 transitions. [2021-11-02 22:59:37,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 22:59:37,718 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122879 states and 174505 transitions. [2021-11-02 22:59:38,860 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 122497 [2021-11-02 22:59:39,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122879 states to 122879 states and 174505 transitions. [2021-11-02 22:59:39,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122879 [2021-11-02 22:59:39,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122879 [2021-11-02 22:59:39,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122879 states and 174505 transitions. [2021-11-02 22:59:39,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:39,532 INFO L681 BuchiCegarLoop]: Abstraction has 122879 states and 174505 transitions. [2021-11-02 22:59:40,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122879 states and 174505 transitions. [2021-11-02 22:59:41,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122879 to 92545. [2021-11-02 22:59:41,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92545 states, 92545 states have (on average 1.4159922200010806) internal successors, (131043), 92544 states have internal predecessors, (131043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:41,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92545 states to 92545 states and 131043 transitions. [2021-11-02 22:59:41,660 INFO L704 BuchiCegarLoop]: Abstraction has 92545 states and 131043 transitions. [2021-11-02 22:59:41,660 INFO L587 BuchiCegarLoop]: Abstraction has 92545 states and 131043 transitions. [2021-11-02 22:59:41,660 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-02 22:59:41,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92545 states and 131043 transitions. [2021-11-02 22:59:41,943 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 92289 [2021-11-02 22:59:41,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:41,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:41,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:41,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:41,946 INFO L791 eck$LassoCheckResult]: Stem: 441612#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 441613#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 442008#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 441625#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 441626#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 441339#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 441340#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 440890#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 440884#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 440885#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 440999#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 441089#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 441865#L629-1 assume !(0 == ~M_E~0); 441087#L846-1 assume !(0 == ~T1_E~0); 441088#L851-1 assume !(0 == ~T2_E~0); 441115#L856-1 assume !(0 == ~T3_E~0); 441116#L861-1 assume !(0 == ~T4_E~0); 441656#L866-1 assume !(0 == ~T5_E~0); 441566#L871-1 assume !(0 == ~T6_E~0); 441567#L876-1 assume !(0 == ~T7_E~0); 441962#L881-1 assume !(0 == ~T8_E~0); 441581#L886-1 assume !(0 == ~E_M~0); 441343#L891-1 assume !(0 == ~E_1~0); 441344#L896-1 assume !(0 == ~E_2~0); 441570#L901-1 assume !(0 == ~E_3~0); 441602#L906-1 assume !(0 == ~E_4~0); 441603#L911-1 assume !(0 == ~E_5~0); 441389#L916-1 assume !(0 == ~E_6~0); 441390#L921-1 assume !(0 == ~E_7~0); 441749#L926-1 assume !(0 == ~E_8~0); 441889#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 441971#L410 assume !(1 == ~m_pc~0); 441281#L410-2 is_master_triggered_~__retres1~0 := 0; 441282#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 441919#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 441712#L1053 assume !(0 != activate_threads_~tmp~1); 441713#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 441780#L429 assume !(1 == ~t1_pc~0); 441699#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 441700#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 440895#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 440896#L1061 assume !(0 != activate_threads_~tmp___0~0); 441651#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 441652#L448 assume !(1 == ~t2_pc~0); 441006#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 441007#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 441287#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 441194#L1069 assume !(0 != activate_threads_~tmp___1~0); 441195#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 441957#L467 assume !(1 == ~t3_pc~0); 441438#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 441074#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 441075#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 441552#L1077 assume !(0 != activate_threads_~tmp___2~0); 441419#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 441020#L486 assume !(1 == ~t4_pc~0); 441021#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 441614#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 441004#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 441005#L1085 assume !(0 != activate_threads_~tmp___3~0); 441196#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 441197#L505 assume !(1 == ~t5_pc~0); 441520#L505-2 is_transmit5_triggered_~__retres1~5 := 0; 441590#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 442034#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 442033#L1093 assume !(0 != activate_threads_~tmp___4~0); 441568#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 441569#L524 assume !(1 == ~t6_pc~0); 441757#L524-2 is_transmit6_triggered_~__retres1~6 := 0; 441582#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 441583#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 440986#L1101 assume !(0 != activate_threads_~tmp___5~0); 440987#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 441346#L543 assume !(1 == ~t7_pc~0); 441347#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 441905#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 441622#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 441623#L1109 assume !(0 != activate_threads_~tmp___6~0); 441170#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 441171#L562 assume 1 == ~t8_pc~0; 441574#L563 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 441844#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 440932#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 440933#L1117 assume !(0 != activate_threads_~tmp___7~0); 442028#L1117-2 assume !(1 == ~M_E~0); 441805#L944-1 assume !(1 == ~T1_E~0); 441372#L949-1 assume !(1 == ~T2_E~0); 441370#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 441371#L959-1 assume !(1 == ~T4_E~0); 441824#L964-1 assume !(1 == ~T5_E~0); 441147#L969-1 assume !(1 == ~T6_E~0); 441148#L974-1 assume !(1 == ~T7_E~0); 441765#L979-1 assume !(1 == ~T8_E~0); 441766#L984-1 assume !(1 == ~E_M~0); 441283#L989-1 assume !(1 == ~E_1~0); 441284#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 441188#L999-1 assume !(1 == ~E_3~0); 441189#L1004-1 assume !(1 == ~E_4~0); 440912#L1009-1 assume !(1 == ~E_5~0); 440913#L1014-1 assume !(1 == ~E_6~0); 441179#L1019-1 assume !(1 == ~E_7~0); 441709#L1024-1 assume !(1 == ~E_8~0); 441927#L1295-1 [2021-11-02 22:59:41,946 INFO L793 eck$LassoCheckResult]: Loop: 441927#L1295-1 assume !false; 477574#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 477569#L821 assume !false; 477568#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 477408#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 477386#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 477379#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 477369#L704 assume !(0 != eval_~tmp~0); 477359#L836 start_simulation_~kernel_st~0 := 2; 477346#L582-1 start_simulation_~kernel_st~0 := 3; 477336#L846-2 assume !(0 == ~M_E~0); 477329#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 477326#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 477323#L856-3 assume !(0 == ~T3_E~0); 477322#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 477321#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 477319#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 477308#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 477305#L881-3 assume !(0 == ~T8_E~0); 477302#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 477298#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 477295#L896-3 assume !(0 == ~E_2~0); 477292#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 477289#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 477286#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 477283#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 477280#L921-3 assume !(0 == ~E_7~0); 477277#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 477274#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 477269#L410-30 assume !(1 == ~m_pc~0); 477264#L410-32 is_master_triggered_~__retres1~0 := 0; 477259#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 477253#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 477246#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 477239#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 477232#L429-30 assume !(1 == ~t1_pc~0); 477226#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 477219#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 477214#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 477209#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 477205#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 477199#L448-30 assume 1 == ~t2_pc~0; 477193#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 477186#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 477180#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 477173#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 477166#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 477160#L467-30 assume !(1 == ~t3_pc~0); 477154#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 477147#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 477121#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 477118#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 477116#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 477114#L486-30 assume !(1 == ~t4_pc~0); 477111#L486-32 is_transmit4_triggered_~__retres1~4 := 0; 477109#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 477107#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 477105#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 477103#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 477101#L505-30 assume !(1 == ~t5_pc~0); 477099#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 477097#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 477095#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 477093#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 477091#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 477089#L524-30 assume !(1 == ~t6_pc~0); 477087#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 477085#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 477082#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 477080#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 477078#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 477076#L543-30 assume !(1 == ~t7_pc~0); 477073#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 477071#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 477069#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 477066#L1109-30 assume !(0 != activate_threads_~tmp___6~0); 477064#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 477062#L562-30 assume !(1 == ~t8_pc~0); 477060#L562-32 is_transmit8_triggered_~__retres1~8 := 0; 477058#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 477055#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 477052#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 477049#L1117-32 assume !(1 == ~M_E~0); 477044#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 477041#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 477038#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 477035#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 477032#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 477029#L969-3 assume !(1 == ~T6_E~0); 477026#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 477023#L979-3 assume !(1 == ~T8_E~0); 477020#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 477017#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 477014#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 477011#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 477008#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 477005#L1009-3 assume !(1 == ~E_5~0); 477002#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 477001#L1019-3 assume !(1 == ~E_7~0); 477000#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 476998#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 476992#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 476983#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 476981#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 476978#L1314 assume !(0 == start_simulation_~tmp~3); 476979#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 477679#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 477669#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 477633#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 477624#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 477614#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 477602#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 477591#L1327 assume !(0 != start_simulation_~tmp___0~1); 441927#L1295-1 [2021-11-02 22:59:41,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:41,947 INFO L85 PathProgramCache]: Analyzing trace with hash -187469761, now seen corresponding path program 1 times [2021-11-02 22:59:41,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:41,947 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723207341] [2021-11-02 22:59:41,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:41,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:41,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:42,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:42,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:42,002 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723207341] [2021-11-02 22:59:42,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723207341] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:42,002 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:42,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:42,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440738141] [2021-11-02 22:59:42,003 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:42,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:42,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1903863518, now seen corresponding path program 1 times [2021-11-02 22:59:42,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:42,004 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113664596] [2021-11-02 22:59:42,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:42,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:42,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:42,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:42,555 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:42,561 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113664596] [2021-11-02 22:59:42,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113664596] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:42,561 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:42,561 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:42,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618341158] [2021-11-02 22:59:42,562 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:42,562 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:42,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:59:42,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:59:42,564 INFO L87 Difference]: Start difference. First operand 92545 states and 131043 transitions. cyclomatic complexity: 38514 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:43,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:43,924 INFO L93 Difference]: Finished difference Result 256394 states and 361360 transitions. [2021-11-02 22:59:43,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:59:43,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 256394 states and 361360 transitions. [2021-11-02 22:59:46,241 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 253175 [2021-11-02 22:59:46,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 256394 states to 256394 states and 361360 transitions. [2021-11-02 22:59:46,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 256394 [2021-11-02 22:59:47,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 256394 [2021-11-02 22:59:47,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256394 states and 361360 transitions. [2021-11-02 22:59:47,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:47,912 INFO L681 BuchiCegarLoop]: Abstraction has 256394 states and 361360 transitions. [2021-11-02 22:59:48,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256394 states and 361360 transitions. [2021-11-02 22:59:51,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256394 to 252456. [2021-11-02 22:59:51,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252456 states, 252456 states have (on average 1.4121034952625409) internal successors, (356494), 252455 states have internal predecessors, (356494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:52,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252456 states to 252456 states and 356494 transitions. [2021-11-02 22:59:52,310 INFO L704 BuchiCegarLoop]: Abstraction has 252456 states and 356494 transitions. [2021-11-02 22:59:52,310 INFO L587 BuchiCegarLoop]: Abstraction has 252456 states and 356494 transitions. [2021-11-02 22:59:52,310 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-02 22:59:52,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252456 states and 356494 transitions. [2021-11-02 22:59:54,354 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252041 [2021-11-02 22:59:54,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:59:54,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:59:54,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:54,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:59:54,357 INFO L791 eck$LassoCheckResult]: Stem: 790570#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 790571#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 791000#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 790588#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 790589#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 790289#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 790290#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 789839#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 789833#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 789834#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 789948#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 790040#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 790841#L629-1 assume !(0 == ~M_E~0); 790038#L846-1 assume !(0 == ~T1_E~0); 790039#L851-1 assume !(0 == ~T2_E~0); 790066#L856-1 assume !(0 == ~T3_E~0); 790067#L861-1 assume !(0 == ~T4_E~0); 790619#L866-1 assume !(0 == ~T5_E~0); 790522#L871-1 assume !(0 == ~T6_E~0); 790523#L876-1 assume !(0 == ~T7_E~0); 790944#L881-1 assume !(0 == ~T8_E~0); 790536#L886-1 assume !(0 == ~E_M~0); 790293#L891-1 assume !(0 == ~E_1~0); 790294#L896-1 assume !(0 == ~E_2~0); 790526#L901-1 assume !(0 == ~E_3~0); 790561#L906-1 assume !(0 == ~E_4~0); 790562#L911-1 assume !(0 == ~E_5~0); 790340#L916-1 assume !(0 == ~E_6~0); 790341#L921-1 assume !(0 == ~E_7~0); 790719#L926-1 assume !(0 == ~E_8~0); 790865#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 790954#L410 assume !(1 == ~m_pc~0); 790232#L410-2 is_master_triggered_~__retres1~0 := 0; 790233#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 790897#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 790677#L1053 assume !(0 != activate_threads_~tmp~1); 790678#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 790752#L429 assume !(1 == ~t1_pc~0); 790664#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 790665#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 789844#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 789845#L1061 assume !(0 != activate_threads_~tmp___0~0); 790614#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 790615#L448 assume !(1 == ~t2_pc~0); 789955#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 789956#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 790238#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 790143#L1069 assume !(0 != activate_threads_~tmp___1~0); 790144#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 790939#L467 assume !(1 == ~t3_pc~0); 790392#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 790024#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 790025#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 790508#L1077 assume !(0 != activate_threads_~tmp___2~0); 790371#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 789969#L486 assume !(1 == ~t4_pc~0); 789970#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 790572#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 789953#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 789954#L1085 assume !(0 != activate_threads_~tmp___3~0); 790145#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 790146#L505 assume !(1 == ~t5_pc~0); 790472#L505-2 is_transmit5_triggered_~__retres1~5 := 0; 790550#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 791034#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 791033#L1093 assume !(0 != activate_threads_~tmp___4~0); 790524#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 790525#L524 assume !(1 == ~t6_pc~0); 790726#L524-2 is_transmit6_triggered_~__retres1~6 := 0; 790537#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 790538#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 789935#L1101 assume !(0 != activate_threads_~tmp___5~0); 789936#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 790296#L543 assume !(1 == ~t7_pc~0); 790297#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 790883#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 790583#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 790584#L1109 assume !(0 != activate_threads_~tmp___6~0); 790119#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 790120#L562 assume !(1 == ~t8_pc~0); 790530#L562-2 is_transmit8_triggered_~__retres1~8 := 0; 790920#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 789881#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 789882#L1117 assume !(0 != activate_threads_~tmp___7~0); 791025#L1117-2 assume !(1 == ~M_E~0); 790775#L944-1 assume !(1 == ~T1_E~0); 790323#L949-1 assume !(1 == ~T2_E~0); 790321#L954-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 790322#L959-1 assume !(1 == ~T4_E~0); 790799#L964-1 assume !(1 == ~T5_E~0); 790097#L969-1 assume !(1 == ~T6_E~0); 790098#L974-1 assume !(1 == ~T7_E~0); 790738#L979-1 assume !(1 == ~T8_E~0); 790739#L984-1 assume !(1 == ~E_M~0); 790234#L989-1 assume !(1 == ~E_1~0); 790235#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 790137#L999-1 assume !(1 == ~E_3~0); 790138#L1004-1 assume !(1 == ~E_4~0); 789861#L1009-1 assume !(1 == ~E_5~0); 789862#L1014-1 assume !(1 == ~E_6~0); 790128#L1019-1 assume !(1 == ~E_7~0); 790674#L1024-1 assume !(1 == ~E_8~0); 790904#L1295-1 [2021-11-02 22:59:54,357 INFO L793 eck$LassoCheckResult]: Loop: 790904#L1295-1 assume !false; 962464#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 962463#L821 assume !false; 962462#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962461#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 962452#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 962451#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 962448#L704 assume !(0 != eval_~tmp~0); 962450#L836 start_simulation_~kernel_st~0 := 2; 962706#L582-1 start_simulation_~kernel_st~0 := 3; 962704#L846-2 assume !(0 == ~M_E~0); 962702#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 962700#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 962698#L856-3 assume !(0 == ~T3_E~0); 962696#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 962694#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 962692#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 962689#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 962687#L881-3 assume !(0 == ~T8_E~0); 962685#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 962683#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 962681#L896-3 assume !(0 == ~E_2~0); 962679#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 962677#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 962675#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 962673#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 962671#L921-3 assume !(0 == ~E_7~0); 962669#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 962667#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 962664#L410-30 assume !(1 == ~m_pc~0); 962662#L410-32 is_master_triggered_~__retres1~0 := 0; 962660#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 962658#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 962656#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 962654#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 962652#L429-30 assume !(1 == ~t1_pc~0); 962650#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 962648#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 962646#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 962644#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 962642#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 962640#L448-30 assume 1 == ~t2_pc~0; 962638#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 962635#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 962633#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 962631#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 962628#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 962626#L467-30 assume !(1 == ~t3_pc~0); 962624#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 962622#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 962620#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 962618#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 962616#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 962614#L486-30 assume 1 == ~t4_pc~0; 962612#L487-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 962609#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 962607#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 962606#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 962605#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 962604#L505-30 assume !(1 == ~t5_pc~0); 962603#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 962601#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 962599#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 962597#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 962595#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 962593#L524-30 assume !(1 == ~t6_pc~0); 962591#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 962589#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 962587#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 962585#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 962583#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 962581#L543-30 assume !(1 == ~t7_pc~0); 962578#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 962576#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 962573#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 962571#L1109-30 assume !(0 != activate_threads_~tmp___6~0); 962569#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 962567#L562-30 assume !(1 == ~t8_pc~0); 962565#L562-32 is_transmit8_triggered_~__retres1~8 := 0; 962563#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 962561#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 962559#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 962557#L1117-32 assume !(1 == ~M_E~0); 962553#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 962551#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 962549#L954-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 962546#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 962544#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 962542#L969-3 assume !(1 == ~T6_E~0); 962540#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 962538#L979-3 assume !(1 == ~T8_E~0); 962536#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 962534#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 962532#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 962530#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 962528#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 962526#L1009-3 assume !(1 == ~E_5~0); 962524#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 962522#L1019-3 assume !(1 == ~E_7~0); 962520#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 962518#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962510#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 962501#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 962499#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 962496#L1314 assume !(0 == start_simulation_~tmp~3); 962493#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962491#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 962481#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 962479#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 962477#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 962476#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 962475#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 962471#L1327 assume !(0 != start_simulation_~tmp___0~1); 790904#L1295-1 [2021-11-02 22:59:54,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:54,358 INFO L85 PathProgramCache]: Analyzing trace with hash 592511168, now seen corresponding path program 1 times [2021-11-02 22:59:54,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:54,358 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643326630] [2021-11-02 22:59:54,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:54,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:54,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:54,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:54,403 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:54,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643326630] [2021-11-02 22:59:54,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643326630] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:54,413 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:54,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:59:54,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986642430] [2021-11-02 22:59:54,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:59:54,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:59:54,414 INFO L85 PathProgramCache]: Analyzing trace with hash -484619585, now seen corresponding path program 1 times [2021-11-02 22:59:54,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:59:54,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597032967] [2021-11-02 22:59:54,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:59:54,415 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:59:54,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:59:54,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:59:54,451 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:59:54,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597032967] [2021-11-02 22:59:54,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597032967] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:59:54,451 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:59:54,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:59:54,452 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442272719] [2021-11-02 22:59:54,452 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:59:54,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:59:54,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:59:54,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:59:54,454 INFO L87 Difference]: Start difference. First operand 252456 states and 356494 transitions. cyclomatic complexity: 104070 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:59:55,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:59:55,374 INFO L93 Difference]: Finished difference Result 252456 states and 355034 transitions. [2021-11-02 22:59:55,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:59:55,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 252456 states and 355034 transitions. [2021-11-02 22:59:57,831 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252041 [2021-11-02 22:59:58,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 252456 states to 252456 states and 355034 transitions. [2021-11-02 22:59:58,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252456 [2021-11-02 22:59:58,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252456 [2021-11-02 22:59:58,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 252456 states and 355034 transitions. [2021-11-02 22:59:58,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:59:58,909 INFO L681 BuchiCegarLoop]: Abstraction has 252456 states and 355034 transitions. [2021-11-02 22:59:59,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252456 states and 355034 transitions. [2021-11-02 23:00:02,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252456 to 252456. [2021-11-02 23:00:02,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252456 states, 252456 states have (on average 1.4063203092816174) internal successors, (355034), 252455 states have internal predecessors, (355034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:00:04,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252456 states to 252456 states and 355034 transitions. [2021-11-02 23:00:04,317 INFO L704 BuchiCegarLoop]: Abstraction has 252456 states and 355034 transitions. [2021-11-02 23:00:04,317 INFO L587 BuchiCegarLoop]: Abstraction has 252456 states and 355034 transitions. [2021-11-02 23:00:04,317 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-02 23:00:04,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252456 states and 355034 transitions. [2021-11-02 23:00:05,320 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252041 [2021-11-02 23:00:05,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:00:05,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:00:05,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:00:05,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:00:05,324 INFO L791 eck$LassoCheckResult]: Stem: 1295487#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1295488#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1295888#L1258 havoc start_simulation_#t~ret28, start_simulation_#t~ret29, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1295501#L582 assume 1 == ~m_i~0;~m_st~0 := 0; 1295502#L589-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1295213#L594-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1295214#L599-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1294758#L604-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1294752#L609-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1294753#L614-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1294868#L619-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1294963#L624-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1295743#L629-1 assume !(0 == ~M_E~0); 1294961#L846-1 assume !(0 == ~T1_E~0); 1294962#L851-1 assume !(0 == ~T2_E~0); 1294992#L856-1 assume !(0 == ~T3_E~0); 1294993#L861-1 assume !(0 == ~T4_E~0); 1295532#L866-1 assume !(0 == ~T5_E~0); 1295440#L871-1 assume !(0 == ~T6_E~0); 1295441#L876-1 assume !(0 == ~T7_E~0); 1295838#L881-1 assume !(0 == ~T8_E~0); 1295452#L886-1 assume !(0 == ~E_M~0); 1295216#L891-1 assume !(0 == ~E_1~0); 1295217#L896-1 assume !(0 == ~E_2~0); 1295444#L901-1 assume !(0 == ~E_3~0); 1295478#L906-1 assume !(0 == ~E_4~0); 1295479#L911-1 assume !(0 == ~E_5~0); 1295267#L916-1 assume !(0 == ~E_6~0); 1295268#L921-1 assume !(0 == ~E_7~0); 1295629#L926-1 assume !(0 == ~E_8~0); 1295764#L931-1 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1295847#L410 assume !(1 == ~m_pc~0); 1295159#L410-2 is_master_triggered_~__retres1~0 := 0; 1295160#L421 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1295798#L422 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1295587#L1053 assume !(0 != activate_threads_~tmp~1); 1295588#L1053-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1295663#L429 assume !(1 == ~t1_pc~0); 1295573#L429-2 is_transmit1_triggered_~__retres1~1 := 0; 1295574#L440 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1294763#L441 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1294764#L1061 assume !(0 != activate_threads_~tmp___0~0); 1295527#L1061-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1295528#L448 assume !(1 == ~t2_pc~0); 1294875#L448-2 is_transmit2_triggered_~__retres1~2 := 0; 1294876#L459 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1295165#L460 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1295071#L1069 assume !(0 != activate_threads_~tmp___1~0); 1295072#L1069-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1295832#L467 assume !(1 == ~t3_pc~0); 1295316#L467-2 is_transmit3_triggered_~__retres1~3 := 0; 1294947#L478 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1294948#L479 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1295427#L1077 assume !(0 != activate_threads_~tmp___2~0); 1295297#L1077-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1294890#L486 assume !(1 == ~t4_pc~0); 1294891#L486-2 is_transmit4_triggered_~__retres1~4 := 0; 1295490#L497 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1294873#L498 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1294874#L1085 assume !(0 != activate_threads_~tmp___3~0); 1295073#L1085-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1295074#L505 assume !(1 == ~t5_pc~0); 1295395#L505-2 is_transmit5_triggered_~__retres1~5 := 0; 1295466#L516 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1295926#L517 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1295925#L1093 assume !(0 != activate_threads_~tmp___4~0); 1295442#L1093-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1295443#L524 assume !(1 == ~t6_pc~0); 1295635#L524-2 is_transmit6_triggered_~__retres1~6 := 0; 1295453#L535 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1295454#L536 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1294855#L1101 assume !(0 != activate_threads_~tmp___5~0); 1294856#L1101-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1295219#L543 assume !(1 == ~t7_pc~0); 1295220#L543-2 is_transmit7_triggered_~__retres1~7 := 0; 1295782#L554 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1295496#L555 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1295497#L1109 assume !(0 != activate_threads_~tmp___6~0); 1295047#L1109-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1295048#L562 assume !(1 == ~t8_pc~0); 1295448#L562-2 is_transmit8_triggered_~__retres1~8 := 0; 1295818#L573 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1294801#L574 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1294802#L1117 assume !(0 != activate_threads_~tmp___7~0); 1295912#L1117-2 assume !(1 == ~M_E~0); 1295683#L944-1 assume !(1 == ~T1_E~0); 1295250#L949-1 assume !(1 == ~T2_E~0); 1295248#L954-1 assume !(1 == ~T3_E~0); 1295249#L959-1 assume !(1 == ~T4_E~0); 1295705#L964-1 assume !(1 == ~T5_E~0); 1295021#L969-1 assume !(1 == ~T6_E~0); 1295022#L974-1 assume !(1 == ~T7_E~0); 1295644#L979-1 assume !(1 == ~T8_E~0); 1295645#L984-1 assume !(1 == ~E_M~0); 1295161#L989-1 assume !(1 == ~E_1~0); 1295162#L994-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1295064#L999-1 assume !(1 == ~E_3~0); 1295065#L1004-1 assume !(1 == ~E_4~0); 1294781#L1009-1 assume !(1 == ~E_5~0); 1294782#L1014-1 assume !(1 == ~E_6~0); 1295057#L1019-1 assume !(1 == ~E_7~0); 1295584#L1024-1 assume !(1 == ~E_8~0); 1295807#L1295-1 [2021-11-02 23:00:05,324 INFO L793 eck$LassoCheckResult]: Loop: 1295807#L1295-1 assume !false; 1378801#L1296 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1378799#L821 assume !false; 1378797#L700 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1378795#L642 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1378785#L689 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1378783#L690 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1378780#L704 assume !(0 != eval_~tmp~0); 1378781#L836 start_simulation_~kernel_st~0 := 2; 1380101#L582-1 start_simulation_~kernel_st~0 := 3; 1380096#L846-2 assume !(0 == ~M_E~0); 1380091#L846-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1380086#L851-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1380082#L856-3 assume !(0 == ~T3_E~0); 1380078#L861-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1380073#L866-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1380068#L871-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1380064#L876-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1380059#L881-3 assume !(0 == ~T8_E~0); 1380054#L886-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1380049#L891-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1380044#L896-3 assume !(0 == ~E_2~0); 1380039#L901-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1380033#L906-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1380026#L911-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1380018#L916-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1380011#L921-3 assume !(0 == ~E_7~0); 1380004#L926-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1379997#L931-3 havoc activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1379989#L410-30 assume !(1 == ~m_pc~0); 1379983#L410-32 is_master_triggered_~__retres1~0 := 0; 1379978#L421-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1379973#L422-10 activate_threads_#t~ret18 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1379968#L1053-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1379963#L1053-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1379958#L429-30 assume !(1 == ~t1_pc~0); 1379953#L429-32 is_transmit1_triggered_~__retres1~1 := 0; 1379947#L440-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1379942#L441-10 activate_threads_#t~ret19 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1379938#L1061-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1379933#L1061-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1379928#L448-30 assume 1 == ~t2_pc~0; 1379923#L449-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1379916#L459-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1379910#L460-10 activate_threads_#t~ret20 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1379904#L1069-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1379898#L1069-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1379891#L467-30 assume !(1 == ~t3_pc~0); 1379886#L467-32 is_transmit3_triggered_~__retres1~3 := 0; 1379880#L478-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1379876#L479-10 activate_threads_#t~ret21 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1379871#L1077-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1379866#L1077-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1379860#L486-30 assume !(1 == ~t4_pc~0); 1379853#L486-32 is_transmit4_triggered_~__retres1~4 := 0; 1379847#L497-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1379840#L498-10 activate_threads_#t~ret22 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1379833#L1085-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1379828#L1085-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1379822#L505-30 assume !(1 == ~t5_pc~0); 1379817#L505-32 is_transmit5_triggered_~__retres1~5 := 0; 1379810#L516-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1379803#L517-10 activate_threads_#t~ret23 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1379797#L1093-30 assume !(0 != activate_threads_~tmp___4~0); 1379791#L1093-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1379374#L524-30 assume !(1 == ~t6_pc~0); 1379371#L524-32 is_transmit6_triggered_~__retres1~6 := 0; 1379369#L535-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1379367#L536-10 activate_threads_#t~ret24 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1379365#L1101-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1379363#L1101-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1379361#L543-30 assume !(1 == ~t7_pc~0); 1379358#L543-32 is_transmit7_triggered_~__retres1~7 := 0; 1379356#L554-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1379354#L555-10 activate_threads_#t~ret25 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1379352#L1109-30 assume !(0 != activate_threads_~tmp___6~0); 1379350#L1109-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1379349#L562-30 assume !(1 == ~t8_pc~0); 1379348#L562-32 is_transmit8_triggered_~__retres1~8 := 0; 1379346#L573-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1379344#L574-10 activate_threads_#t~ret26 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1379342#L1117-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1379340#L1117-32 assume !(1 == ~M_E~0); 1379336#L944-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1379334#L949-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1379332#L954-3 assume !(1 == ~T3_E~0); 1379330#L959-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1379328#L964-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1379326#L969-3 assume !(1 == ~T6_E~0); 1379324#L974-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1379322#L979-3 assume !(1 == ~T8_E~0); 1379250#L984-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1379241#L989-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1379233#L994-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1379225#L999-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1379214#L1004-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1379204#L1009-3 assume !(1 == ~E_5~0); 1379198#L1014-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1379188#L1019-3 assume !(1 == ~E_7~0); 1379177#L1024-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1379171#L1029-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1378933#L642-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1378924#L689-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1378922#L690-1 start_simulation_#t~ret28 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret28;havoc start_simulation_#t~ret28; 1378919#L1314 assume !(0 == start_simulation_~tmp~3); 1378916#L1314-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret27, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1378914#L642-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1378903#L689-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1378901#L690-2 stop_simulation_#t~ret27 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret27;havoc stop_simulation_#t~ret27; 1378899#L1269 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1378897#L1276 stop_simulation_#res := stop_simulation_~__retres2~0; 1378895#L1277 start_simulation_#t~ret29 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 1378893#L1327 assume !(0 != start_simulation_~tmp___0~1); 1295807#L1295-1 [2021-11-02 23:00:05,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:00:05,325 INFO L85 PathProgramCache]: Analyzing trace with hash -687352510, now seen corresponding path program 1 times [2021-11-02 23:00:05,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:00:05,326 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852099766] [2021-11-02 23:00:05,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:00:05,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:00:05,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:00:05,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:00:05,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:00:05,375 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852099766] [2021-11-02 23:00:05,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852099766] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:00:05,375 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:00:05,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:00:05,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700640917] [2021-11-02 23:00:05,376 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:00:05,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:00:05,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1394390428, now seen corresponding path program 1 times [2021-11-02 23:00:05,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:00:05,377 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469377276] [2021-11-02 23:00:05,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:00:05,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:00:05,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:00:05,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:00:05,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:00:05,416 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469377276] [2021-11-02 23:00:05,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469377276] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:00:05,417 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:00:05,417 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:00:05,417 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125791968] [2021-11-02 23:00:05,418 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:00:05,418 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:00:05,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:00:05,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:00:05,419 INFO L87 Difference]: Start difference. First operand 252456 states and 355034 transitions. cyclomatic complexity: 102610 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:00:06,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:00:06,331 INFO L93 Difference]: Finished difference Result 252456 states and 350674 transitions. [2021-11-02 23:00:06,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:00:06,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 252456 states and 350674 transitions. [2021-11-02 23:00:08,673 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252041 [2021-11-02 23:00:09,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 252456 states to 252456 states and 350674 transitions. [2021-11-02 23:00:09,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252456 [2021-11-02 23:00:09,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252456 [2021-11-02 23:00:09,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 252456 states and 350674 transitions. [2021-11-02 23:00:10,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:00:10,788 INFO L681 BuchiCegarLoop]: Abstraction has 252456 states and 350674 transitions. [2021-11-02 23:00:10,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252456 states and 350674 transitions. [2021-11-02 23:00:13,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252456 to 252456. [2021-11-02 23:00:13,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252456 states, 252456 states have (on average 1.3890499730646133) internal successors, (350674), 252455 states have internal predecessors, (350674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)