./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9ad7fb26 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7da2f86a1305fcd7bf2bc6cc6da60c01c091199da764efbbf1fceaaa05350968 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-9ad7fb2 [2021-11-02 22:20:14,620 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-02 22:20:14,622 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-02 22:20:14,655 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-02 22:20:14,655 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-02 22:20:14,657 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-02 22:20:14,659 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-02 22:20:14,661 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-02 22:20:14,664 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-02 22:20:14,665 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-02 22:20:14,667 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-02 22:20:14,668 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-02 22:20:14,669 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-02 22:20:14,670 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-02 22:20:14,672 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-02 22:20:14,674 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-02 22:20:14,675 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-02 22:20:14,676 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-02 22:20:14,678 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-02 22:20:14,681 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-02 22:20:14,683 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-02 22:20:14,685 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-02 22:20:14,686 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-02 22:20:14,688 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-02 22:20:14,692 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-02 22:20:14,692 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-02 22:20:14,693 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-02 22:20:14,694 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-02 22:20:14,695 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-02 22:20:14,696 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-02 22:20:14,696 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-02 22:20:14,697 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-02 22:20:14,698 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-02 22:20:14,700 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-02 22:20:14,701 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-02 22:20:14,701 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-02 22:20:14,702 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-02 22:20:14,702 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-02 22:20:14,703 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-02 22:20:14,704 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-02 22:20:14,705 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-02 22:20:14,706 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-02 22:20:14,733 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-02 22:20:14,733 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-02 22:20:14,733 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-02 22:20:14,734 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-02 22:20:14,735 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-02 22:20:14,735 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-02 22:20:14,735 INFO L138 SettingsManager]: * Use SBE=true [2021-11-02 22:20:14,736 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-02 22:20:14,736 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-02 22:20:14,736 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-02 22:20:14,736 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-02 22:20:14,737 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-02 22:20:14,737 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-02 22:20:14,737 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-02 22:20:14,737 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-02 22:20:14,738 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-02 22:20:14,738 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-02 22:20:14,738 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-02 22:20:14,738 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-02 22:20:14,739 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-02 22:20:14,739 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-02 22:20:14,739 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-02 22:20:14,739 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-02 22:20:14,740 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-02 22:20:14,740 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-02 22:20:14,740 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-02 22:20:14,740 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-02 22:20:14,740 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-02 22:20:14,741 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-02 22:20:14,741 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-02 22:20:14,741 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-02 22:20:14,741 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-02 22:20:14,742 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-02 22:20:14,743 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7da2f86a1305fcd7bf2bc6cc6da60c01c091199da764efbbf1fceaaa05350968 [2021-11-02 22:20:14,984 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-02 22:20:15,005 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-02 22:20:15,008 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-02 22:20:15,009 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-02 22:20:15,010 INFO L275 PluginConnector]: CDTParser initialized [2021-11-02 22:20:15,011 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-11-02 22:20:15,091 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/data/4a63ec2c5/8bce059d8ad84c509411b0b5becb50da/FLAGc1dedf7e1 [2021-11-02 22:20:15,549 INFO L306 CDTParser]: Found 1 translation units. [2021-11-02 22:20:15,549 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-11-02 22:20:15,568 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/data/4a63ec2c5/8bce059d8ad84c509411b0b5becb50da/FLAGc1dedf7e1 [2021-11-02 22:20:15,894 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/data/4a63ec2c5/8bce059d8ad84c509411b0b5becb50da [2021-11-02 22:20:15,897 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-02 22:20:15,898 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-02 22:20:15,909 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-02 22:20:15,910 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-02 22:20:15,913 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-02 22:20:15,914 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 10:20:15" (1/1) ... [2021-11-02 22:20:15,915 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52d0b770 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:15, skipping insertion in model container [2021-11-02 22:20:15,915 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 10:20:15" (1/1) ... [2021-11-02 22:20:15,925 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-02 22:20:15,987 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-02 22:20:16,167 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[366,379] [2021-11-02 22:20:16,311 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 22:20:16,327 INFO L203 MainTranslator]: Completed pre-run [2021-11-02 22:20:16,339 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[366,379] [2021-11-02 22:20:16,417 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 22:20:16,437 INFO L208 MainTranslator]: Completed translation [2021-11-02 22:20:16,437 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16 WrapperNode [2021-11-02 22:20:16,438 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-02 22:20:16,439 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-02 22:20:16,439 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-02 22:20:16,439 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-02 22:20:16,447 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,462 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,564 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-02 22:20:16,565 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-02 22:20:16,565 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-02 22:20:16,565 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-02 22:20:16,574 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,574 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,583 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,584 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,616 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,642 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,648 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,659 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-02 22:20:16,660 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-02 22:20:16,660 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-02 22:20:16,660 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-02 22:20:16,661 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (1/1) ... [2021-11-02 22:20:16,673 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-02 22:20:16,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/z3 [2021-11-02 22:20:16,712 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-02 22:20:16,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_223effb3-a8f5-42c9-9c63-da907dbab88e/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-02 22:20:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-02 22:20:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-02 22:20:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-02 22:20:16,794 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-02 22:20:18,680 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-02 22:20:18,681 INFO L299 CfgBuilder]: Removed 327 assume(true) statements. [2021-11-02 22:20:18,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 10:20:18 BoogieIcfgContainer [2021-11-02 22:20:18,685 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-02 22:20:18,689 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-02 22:20:18,689 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-02 22:20:18,694 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-02 22:20:18,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:20:18,701 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 10:20:15" (1/3) ... [2021-11-02 22:20:18,703 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2631baec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 10:20:18, skipping insertion in model container [2021-11-02 22:20:18,703 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:20:18,704 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 10:20:16" (2/3) ... [2021-11-02 22:20:18,704 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2631baec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 10:20:18, skipping insertion in model container [2021-11-02 22:20:18,704 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 22:20:18,704 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 10:20:18" (3/3) ... [2021-11-02 22:20:18,706 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2021-11-02 22:20:18,760 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-02 22:20:18,760 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-02 22:20:18,761 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-02 22:20:18,761 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-02 22:20:18,761 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-02 22:20:18,761 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-02 22:20:18,761 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-02 22:20:18,761 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-02 22:20:18,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 979 states, 978 states have (on average 1.5296523517382412) internal successors, (1496), 978 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:18,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 864 [2021-11-02 22:20:18,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:18,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:18,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:18,928 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:18,928 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-02 22:20:18,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 979 states, 978 states have (on average 1.5296523517382412) internal successors, (1496), 978 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:18,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 864 [2021-11-02 22:20:18,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:18,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:18,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:18,970 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:18,986 INFO L791 eck$LassoCheckResult]: Stem: 449#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 873#L-1true havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9#L1270true havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 945#L594true assume !(1 == ~m_i~0);~m_st~0 := 2; 247#L601-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 702#L606-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 426#L611-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 788#L616-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 304#L621-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 514#L626-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 768#L631-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L636-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 540#L641-1true assume 0 == ~M_E~0;~M_E~0 := 1; 296#L858-1true assume !(0 == ~T1_E~0); 3#L863-1true assume !(0 == ~T2_E~0); 785#L868-1true assume !(0 == ~T3_E~0); 907#L873-1true assume !(0 == ~T4_E~0); 782#L878-1true assume !(0 == ~T5_E~0); 745#L883-1true assume !(0 == ~T6_E~0); 810#L888-1true assume !(0 == ~T7_E~0); 399#L893-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 811#L898-1true assume !(0 == ~E_M~0); 960#L903-1true assume !(0 == ~E_1~0); 744#L908-1true assume !(0 == ~E_2~0); 527#L913-1true assume !(0 == ~E_3~0); 35#L918-1true assume !(0 == ~E_4~0); 542#L923-1true assume !(0 == ~E_5~0); 950#L928-1true assume !(0 == ~E_6~0); 92#L933-1true assume 0 == ~E_7~0;~E_7~0 := 1; 525#L938-1true assume !(0 == ~E_8~0); 803#L943-1true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 838#L422true assume !(1 == ~m_pc~0); 694#L422-2true is_master_triggered_~__retres1~0 := 0; 277#L433true is_master_triggered_#res := is_master_triggered_~__retres1~0; 228#L434true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 476#L1065true assume !(0 != activate_threads_~tmp~1); 88#L1065-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19#L441true assume 1 == ~t1_pc~0; 363#L442true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 909#L452true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 877#L453true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 369#L1073true assume !(0 != activate_threads_~tmp___0~0); 769#L1073-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 766#L460true assume !(1 == ~t2_pc~0); 841#L460-2true is_transmit2_triggered_~__retres1~2 := 0; 485#L471true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 865#L472true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 844#L1081true assume !(0 != activate_threads_~tmp___1~0); 439#L1081-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 405#L479true assume 1 == ~t3_pc~0; 263#L480true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 842#L490true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 703#L491true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 208#L1089true assume !(0 != activate_threads_~tmp___2~0); 20#L1089-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76#L498true assume !(1 == ~t4_pc~0); 520#L498-2true is_transmit4_triggered_~__retres1~4 := 0; 262#L509true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 664#L510true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 597#L1097true assume !(0 != activate_threads_~tmp___3~0); 243#L1097-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 926#L517true assume 1 == ~t5_pc~0; 708#L518true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 876#L528true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 297#L529true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 776#L1105true assume !(0 != activate_threads_~tmp___4~0); 322#L1105-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 650#L536true assume 1 == ~t6_pc~0; 288#L537true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 619#L547true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 892#L548true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 905#L1113true assume !(0 != activate_threads_~tmp___5~0); 137#L1113-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 457#L555true assume !(1 == ~t7_pc~0); 515#L555-2true is_transmit7_triggered_~__retres1~7 := 0; 569#L566true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44#L567true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 34#L1121true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 748#L1121-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 50#L574true assume 1 == ~t8_pc~0; 354#L575true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 912#L585true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 85#L586true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 261#L1129true assume !(0 != activate_threads_~tmp___7~0); 119#L1129-2true assume !(1 == ~M_E~0); 130#L956-1true assume !(1 == ~T1_E~0); 927#L961-1true assume !(1 == ~T2_E~0); 400#L966-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 518#L971-1true assume !(1 == ~T4_E~0); 863#L976-1true assume !(1 == ~T5_E~0); 496#L981-1true assume !(1 == ~T6_E~0); 291#L986-1true assume !(1 == ~T7_E~0); 154#L991-1true assume !(1 == ~T8_E~0); 893#L996-1true assume !(1 == ~E_M~0); 793#L1001-1true assume !(1 == ~E_1~0); 446#L1006-1true assume 1 == ~E_2~0;~E_2~0 := 2; 730#L1011-1true assume !(1 == ~E_3~0); 767#L1016-1true assume !(1 == ~E_4~0); 875#L1021-1true assume !(1 == ~E_5~0); 16#L1026-1true assume !(1 == ~E_6~0); 934#L1031-1true assume !(1 == ~E_7~0); 409#L1036-1true assume !(1 == ~E_8~0); 258#L1307-1true [2021-11-02 22:20:19,000 INFO L793 eck$LassoCheckResult]: Loop: 258#L1307-1true assume !false; 861#L1308true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 46#L833true assume !true; 507#L848true start_simulation_~kernel_st~0 := 2; 257#L594-1true start_simulation_~kernel_st~0 := 3; 549#L858-2true assume 0 == ~M_E~0;~M_E~0 := 1; 553#L858-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 482#L863-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 464#L868-3true assume !(0 == ~T3_E~0); 490#L873-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 165#L878-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 26#L883-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 685#L888-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 27#L893-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 308#L898-3true assume 0 == ~E_M~0;~E_M~0 := 1; 622#L903-3true assume 0 == ~E_1~0;~E_1~0 := 1; 808#L908-3true assume !(0 == ~E_2~0); 316#L913-3true assume 0 == ~E_3~0;~E_3~0 := 1; 47#L918-3true assume 0 == ~E_4~0;~E_4~0 := 1; 916#L923-3true assume 0 == ~E_5~0;~E_5~0 := 1; 155#L928-3true assume 0 == ~E_6~0;~E_6~0 := 1; 537#L933-3true assume 0 == ~E_7~0;~E_7~0 := 1; 879#L938-3true assume 0 == ~E_8~0;~E_8~0 := 1; 385#L943-3true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 565#L422-30true assume !(1 == ~m_pc~0); 397#L422-32true is_master_triggered_~__retres1~0 := 0; 928#L433-10true is_master_triggered_#res := is_master_triggered_~__retres1~0; 141#L434-10true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 236#L1065-30true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 102#L1065-32true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 772#L441-30true assume !(1 == ~t1_pc~0); 625#L441-32true is_transmit1_triggered_~__retres1~1 := 0; 171#L452-10true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 559#L453-10true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 492#L1073-30true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 862#L1073-32true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 845#L460-30true assume 1 == ~t2_pc~0; 416#L461-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 467#L471-10true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 528#L472-10true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 214#L1081-30true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 78#L1081-32true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 821#L479-30true assume 1 == ~t3_pc~0; 839#L480-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10#L490-10true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 757#L491-10true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 299#L1089-30true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 728#L1089-32true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 240#L498-30true assume !(1 == ~t4_pc~0); 503#L498-32true is_transmit4_triggered_~__retres1~4 := 0; 740#L509-10true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 168#L510-10true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 754#L1097-30true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 522#L1097-32true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 832#L517-30true assume 1 == ~t5_pc~0; 281#L518-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 804#L528-10true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 935#L529-10true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 586#L1105-30true assume !(0 != activate_threads_~tmp___4~0); 212#L1105-32true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 112#L536-30true assume !(1 == ~t6_pc~0); 931#L536-32true is_transmit6_triggered_~__retres1~6 := 0; 284#L547-10true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 475#L548-10true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 630#L1113-30true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 213#L1113-32true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 478#L555-30true assume !(1 == ~t7_pc~0); 147#L555-32true is_transmit7_triggered_~__retres1~7 := 0; 677#L566-10true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 733#L567-10true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 654#L1121-30true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 957#L1121-32true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 717#L574-30true assume !(1 == ~t8_pc~0); 253#L574-32true is_transmit8_triggered_~__retres1~8 := 0; 579#L585-10true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 203#L586-10true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 265#L1129-30true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 852#L1129-32true assume 1 == ~M_E~0;~M_E~0 := 2; 530#L956-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 384#L961-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 235#L966-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 747#L971-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 425#L976-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 40#L981-3true assume !(1 == ~T6_E~0); 163#L986-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 33#L991-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 510#L996-3true assume 1 == ~E_M~0;~E_M~0 := 2; 631#L1001-3true assume 1 == ~E_1~0;~E_1~0 := 2; 218#L1006-3true assume 1 == ~E_2~0;~E_2~0 := 2; 534#L1011-3true assume 1 == ~E_3~0;~E_3~0 := 2; 724#L1016-3true assume 1 == ~E_4~0;~E_4~0 := 2; 580#L1021-3true assume !(1 == ~E_5~0); 335#L1026-3true assume 1 == ~E_6~0;~E_6~0 := 2; 847#L1031-3true assume 1 == ~E_7~0;~E_7~0 := 2; 504#L1036-3true assume 1 == ~E_8~0;~E_8~0 := 2; 899#L1041-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 500#L654-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 360#L701-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 942#L702-1true start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 204#L1326true assume !(0 == start_simulation_~tmp~3); 683#L1326-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 278#L654-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 853#L701-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 571#L702-2true stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 450#L1281true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 599#L1288true stop_simulation_#res := stop_simulation_~__retres2~0; 864#L1289true start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 848#L1339true assume !(0 != start_simulation_~tmp___0~1); 258#L1307-1true [2021-11-02 22:20:19,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:19,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1715933315, now seen corresponding path program 1 times [2021-11-02 22:20:19,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:19,032 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904422505] [2021-11-02 22:20:19,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:19,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:19,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:19,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:19,314 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:19,314 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904422505] [2021-11-02 22:20:19,315 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904422505] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:19,316 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:19,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:19,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970524307] [2021-11-02 22:20:19,323 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:19,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:19,325 INFO L85 PathProgramCache]: Analyzing trace with hash 252106362, now seen corresponding path program 1 times [2021-11-02 22:20:19,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:19,325 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81394866] [2021-11-02 22:20:19,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:19,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:19,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:19,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:19,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:19,368 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81394866] [2021-11-02 22:20:19,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81394866] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:19,368 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:19,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:19,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539616125] [2021-11-02 22:20:19,371 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:19,372 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:19,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:19,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:19,391 INFO L87 Difference]: Start difference. First operand has 979 states, 978 states have (on average 1.5296523517382412) internal successors, (1496), 978 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:19,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:19,480 INFO L93 Difference]: Finished difference Result 979 states and 1471 transitions. [2021-11-02 22:20:19,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:19,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1471 transitions. [2021-11-02 22:20:19,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:19,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 973 states and 1465 transitions. [2021-11-02 22:20:19,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:19,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:19,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1465 transitions. [2021-11-02 22:20:19,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:19,534 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2021-11-02 22:20:19,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1465 transitions. [2021-11-02 22:20:19,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:19,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.5056526207605345) internal successors, (1465), 972 states have internal predecessors, (1465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:19,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1465 transitions. [2021-11-02 22:20:19,630 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2021-11-02 22:20:19,630 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2021-11-02 22:20:19,631 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-02 22:20:19,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1465 transitions. [2021-11-02 22:20:19,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:19,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:19,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:19,642 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:19,643 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:19,643 INFO L791 eck$LassoCheckResult]: Stem: 2691#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2692#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1981#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1982#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 2430#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2431#L606-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2666#L611-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2667#L616-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2519#L621-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2520#L626-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2753#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2217#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2218#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 2503#L858-1 assume !(0 == ~T1_E~0); 1967#L863-1 assume !(0 == ~T2_E~0); 1968#L868-1 assume !(0 == ~T3_E~0); 2912#L873-1 assume !(0 == ~T4_E~0); 2910#L878-1 assume !(0 == ~T5_E~0); 2895#L883-1 assume !(0 == ~T6_E~0); 2896#L888-1 assume !(0 == ~T7_E~0); 2634#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2635#L898-1 assume !(0 == ~E_M~0); 2920#L903-1 assume !(0 == ~E_1~0); 2894#L908-1 assume !(0 == ~E_2~0); 2765#L913-1 assume !(0 == ~E_3~0); 2046#L918-1 assume !(0 == ~E_4~0); 2047#L923-1 assume !(0 == ~E_5~0); 2773#L928-1 assume !(0 == ~E_6~0); 2161#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 2162#L938-1 assume !(0 == ~E_8~0); 2763#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2916#L422 assume !(1 == ~m_pc~0); 2720#L422-2 is_master_triggered_~__retres1~0 := 0; 2473#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2399#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2400#L1065 assume !(0 != activate_threads_~tmp~1); 2154#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2007#L441 assume 1 == ~t1_pc~0; 2008#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2597#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2935#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2599#L1073 assume !(0 != activate_threads_~tmp___0~0); 2600#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2905#L460 assume !(1 == ~t2_pc~0); 1970#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 1971#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2725#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2925#L1081 assume !(0 != activate_threads_~tmp___1~0); 2679#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2645#L479 assume 1 == ~t3_pc~0; 2455#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2456#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2873#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2367#L1089 assume !(0 != activate_threads_~tmp___2~0); 2010#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2011#L498 assume !(1 == ~t4_pc~0); 2129#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 2453#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2454#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2817#L1097 assume !(0 != activate_threads_~tmp___3~0); 2422#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2423#L517 assume 1 == ~t5_pc~0; 2875#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2876#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2504#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2505#L1105 assume !(0 != activate_threads_~tmp___4~0); 2543#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2544#L536 assume 1 == ~t6_pc~0; 2490#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2491#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2831#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2936#L1113 assume !(0 != activate_threads_~tmp___5~0); 2240#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2241#L555 assume !(1 == ~t7_pc~0); 2698#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 2754#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2065#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2044#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2045#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2075#L574 assume 1 == ~t8_pc~0; 2076#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2588#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2146#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2147#L1129 assume !(0 != activate_threads_~tmp___7~0); 2212#L1129-2 assume !(1 == ~M_E~0); 2213#L956-1 assume !(1 == ~T1_E~0); 2229#L961-1 assume !(1 == ~T2_E~0); 2636#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2637#L971-1 assume !(1 == ~T4_E~0); 2757#L976-1 assume !(1 == ~T5_E~0); 2736#L981-1 assume !(1 == ~T6_E~0); 2494#L986-1 assume !(1 == ~T7_E~0); 2276#L991-1 assume !(1 == ~T8_E~0); 2277#L996-1 assume !(1 == ~E_M~0); 2913#L1001-1 assume !(1 == ~E_1~0); 2686#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2687#L1011-1 assume !(1 == ~E_3~0); 2891#L1016-1 assume !(1 == ~E_4~0); 2906#L1021-1 assume !(1 == ~E_5~0); 1999#L1026-1 assume !(1 == ~E_6~0); 2000#L1031-1 assume !(1 == ~E_7~0); 2650#L1036-1 assume !(1 == ~E_8~0); 2450#L1307-1 [2021-11-02 22:20:19,644 INFO L793 eck$LassoCheckResult]: Loop: 2450#L1307-1 assume !false; 2451#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2068#L833 assume !false; 2069#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2638#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2237#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2827#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2747#L716 assume !(0 != eval_~tmp~0); 2746#L848 start_simulation_~kernel_st~0 := 2; 2448#L594-1 start_simulation_~kernel_st~0 := 3; 2449#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2783#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2723#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2710#L868-3 assume !(0 == ~T3_E~0); 2711#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2293#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2025#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2026#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2027#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2028#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2529#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2833#L908-3 assume !(0 == ~E_2~0); 2539#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2070#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2071#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2278#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2279#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2772#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2617#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2618#L422-30 assume !(1 == ~m_pc~0); 2576#L422-32 is_master_triggered_~__retres1~0 := 0; 2577#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2250#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2251#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2179#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2180#L441-30 assume !(1 == ~t1_pc~0); 2145#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 2144#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2303#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2731#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2732#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2926#L460-30 assume 1 == ~t2_pc~0; 2652#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2653#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2712#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2375#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2135#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2136#L479-30 assume !(1 == ~t3_pc~0); 2869#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 1983#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1984#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2509#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2510#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2415#L498-30 assume 1 == ~t4_pc~0; 2416#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2487#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2298#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2299#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2760#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2761#L517-30 assume 1 == ~t5_pc~0; 2480#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2481#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2917#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2810#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 2372#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2200#L536-30 assume 1 == ~t6_pc~0; 2116#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2117#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2485#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2718#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2373#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2374#L555-30 assume 1 == ~t7_pc~0; 2721#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2264#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2861#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2850#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2851#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2884#L574-30 assume 1 == ~t8_pc~0; 2885#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2442#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2358#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2359#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2458#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 2766#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2616#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2410#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2411#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2665#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2057#L981-3 assume !(1 == ~T6_E~0); 2058#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2042#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2043#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2748#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2380#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2381#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2769#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2806#L1021-3 assume !(1 == ~E_5~0); 2563#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2564#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2744#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2745#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2740#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2316#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2594#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 2360#L1326 assume !(0 == start_simulation_~tmp~3); 2361#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2474#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2260#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2799#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 2693#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2694#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 2818#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 2927#L1339 assume !(0 != start_simulation_~tmp___0~1); 2450#L1307-1 [2021-11-02 22:20:19,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:19,646 INFO L85 PathProgramCache]: Analyzing trace with hash 684892417, now seen corresponding path program 1 times [2021-11-02 22:20:19,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:19,646 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446529424] [2021-11-02 22:20:19,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:19,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:19,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:19,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:19,760 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:19,761 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446529424] [2021-11-02 22:20:19,761 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446529424] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:19,762 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:19,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:19,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497420929] [2021-11-02 22:20:19,764 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:19,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:19,766 INFO L85 PathProgramCache]: Analyzing trace with hash -336611431, now seen corresponding path program 1 times [2021-11-02 22:20:19,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:19,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127862509] [2021-11-02 22:20:19,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:19,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:19,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:19,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:19,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:19,937 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127862509] [2021-11-02 22:20:19,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127862509] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:19,937 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:19,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:19,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849807963] [2021-11-02 22:20:19,938 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:19,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:19,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:19,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:19,940 INFO L87 Difference]: Start difference. First operand 973 states and 1465 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:19,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:19,974 INFO L93 Difference]: Finished difference Result 973 states and 1464 transitions. [2021-11-02 22:20:19,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:19,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1464 transitions. [2021-11-02 22:20:19,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:19,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1464 transitions. [2021-11-02 22:20:19,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:19,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:19,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1464 transitions. [2021-11-02 22:20:19,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:19,998 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2021-11-02 22:20:20,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1464 transitions. [2021-11-02 22:20:20,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:20,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.5046248715313464) internal successors, (1464), 972 states have internal predecessors, (1464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1464 transitions. [2021-11-02 22:20:20,024 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2021-11-02 22:20:20,024 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2021-11-02 22:20:20,024 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-02 22:20:20,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1464 transitions. [2021-11-02 22:20:20,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:20,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:20,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,040 INFO L791 eck$LassoCheckResult]: Stem: 4644#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4645#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3934#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3935#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 4383#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4384#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4619#L611-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4620#L616-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4472#L621-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4473#L626-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4706#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4170#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4171#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 4456#L858-1 assume !(0 == ~T1_E~0); 3920#L863-1 assume !(0 == ~T2_E~0); 3921#L868-1 assume !(0 == ~T3_E~0); 4865#L873-1 assume !(0 == ~T4_E~0); 4863#L878-1 assume !(0 == ~T5_E~0); 4848#L883-1 assume !(0 == ~T6_E~0); 4849#L888-1 assume !(0 == ~T7_E~0); 4587#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4588#L898-1 assume !(0 == ~E_M~0); 4873#L903-1 assume !(0 == ~E_1~0); 4847#L908-1 assume !(0 == ~E_2~0); 4718#L913-1 assume !(0 == ~E_3~0); 3999#L918-1 assume !(0 == ~E_4~0); 4000#L923-1 assume !(0 == ~E_5~0); 4726#L928-1 assume !(0 == ~E_6~0); 4114#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4115#L938-1 assume !(0 == ~E_8~0); 4716#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4869#L422 assume !(1 == ~m_pc~0); 4673#L422-2 is_master_triggered_~__retres1~0 := 0; 4426#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4352#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4353#L1065 assume !(0 != activate_threads_~tmp~1); 4107#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3960#L441 assume 1 == ~t1_pc~0; 3961#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4550#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4888#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4552#L1073 assume !(0 != activate_threads_~tmp___0~0); 4553#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4858#L460 assume !(1 == ~t2_pc~0); 3923#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 3924#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4678#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4878#L1081 assume !(0 != activate_threads_~tmp___1~0); 4632#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4598#L479 assume 1 == ~t3_pc~0; 4408#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4409#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4826#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4320#L1089 assume !(0 != activate_threads_~tmp___2~0); 3963#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3964#L498 assume !(1 == ~t4_pc~0); 4082#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 4406#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4407#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4770#L1097 assume !(0 != activate_threads_~tmp___3~0); 4375#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4376#L517 assume 1 == ~t5_pc~0; 4828#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4829#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4457#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4458#L1105 assume !(0 != activate_threads_~tmp___4~0); 4496#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4497#L536 assume 1 == ~t6_pc~0; 4443#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4444#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4784#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4889#L1113 assume !(0 != activate_threads_~tmp___5~0); 4193#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4194#L555 assume !(1 == ~t7_pc~0); 4651#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 4707#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4018#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3997#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3998#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4028#L574 assume 1 == ~t8_pc~0; 4029#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4541#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4099#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4100#L1129 assume !(0 != activate_threads_~tmp___7~0); 4165#L1129-2 assume !(1 == ~M_E~0); 4166#L956-1 assume !(1 == ~T1_E~0); 4182#L961-1 assume !(1 == ~T2_E~0); 4589#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4590#L971-1 assume !(1 == ~T4_E~0); 4710#L976-1 assume !(1 == ~T5_E~0); 4689#L981-1 assume !(1 == ~T6_E~0); 4447#L986-1 assume !(1 == ~T7_E~0); 4229#L991-1 assume !(1 == ~T8_E~0); 4230#L996-1 assume !(1 == ~E_M~0); 4866#L1001-1 assume !(1 == ~E_1~0); 4639#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4640#L1011-1 assume !(1 == ~E_3~0); 4844#L1016-1 assume !(1 == ~E_4~0); 4859#L1021-1 assume !(1 == ~E_5~0); 3952#L1026-1 assume !(1 == ~E_6~0); 3953#L1031-1 assume !(1 == ~E_7~0); 4603#L1036-1 assume !(1 == ~E_8~0); 4403#L1307-1 [2021-11-02 22:20:20,041 INFO L793 eck$LassoCheckResult]: Loop: 4403#L1307-1 assume !false; 4404#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4021#L833 assume !false; 4022#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4591#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4190#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4780#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4700#L716 assume !(0 != eval_~tmp~0); 4699#L848 start_simulation_~kernel_st~0 := 2; 4401#L594-1 start_simulation_~kernel_st~0 := 3; 4402#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4736#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4676#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4663#L868-3 assume !(0 == ~T3_E~0); 4664#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4246#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3978#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3979#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3980#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3981#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4482#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4786#L908-3 assume !(0 == ~E_2~0); 4492#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4023#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4024#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4231#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4232#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4725#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4570#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4571#L422-30 assume 1 == ~m_pc~0; 4528#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4530#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4203#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4204#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4132#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4133#L441-30 assume 1 == ~t1_pc~0; 4096#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4097#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4256#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4684#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4685#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4879#L460-30 assume 1 == ~t2_pc~0; 4605#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4606#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4665#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4328#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4088#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4089#L479-30 assume !(1 == ~t3_pc~0); 4822#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 3936#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3937#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4462#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4463#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4368#L498-30 assume 1 == ~t4_pc~0; 4369#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4440#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4251#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4252#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4713#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4714#L517-30 assume 1 == ~t5_pc~0; 4433#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4434#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4870#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4763#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 4325#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4153#L536-30 assume 1 == ~t6_pc~0; 4069#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4070#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4438#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4671#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4326#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4327#L555-30 assume 1 == ~t7_pc~0; 4674#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4217#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4814#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4803#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4804#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4837#L574-30 assume 1 == ~t8_pc~0; 4838#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4395#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4311#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4312#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4411#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 4719#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4569#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4363#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4364#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4618#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4010#L981-3 assume !(1 == ~T6_E~0); 4011#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3995#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3996#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4701#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4333#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4334#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4722#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4759#L1021-3 assume !(1 == ~E_5~0); 4516#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4517#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4697#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4698#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4693#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4269#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4547#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 4313#L1326 assume !(0 == start_simulation_~tmp~3); 4314#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4427#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4213#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4752#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 4646#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4647#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 4771#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 4880#L1339 assume !(0 != start_simulation_~tmp___0~1); 4403#L1307-1 [2021-11-02 22:20:20,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,041 INFO L85 PathProgramCache]: Analyzing trace with hash -916178689, now seen corresponding path program 1 times [2021-11-02 22:20:20,042 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,042 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242371073] [2021-11-02 22:20:20,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,043 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,134 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,135 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242371073] [2021-11-02 22:20:20,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242371073] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,135 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415205474] [2021-11-02 22:20:20,136 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:20,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1395447323, now seen corresponding path program 1 times [2021-11-02 22:20:20,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,138 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357905857] [2021-11-02 22:20:20,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,226 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357905857] [2021-11-02 22:20:20,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357905857] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,227 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786537012] [2021-11-02 22:20:20,230 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:20,230 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:20,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:20,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:20,232 INFO L87 Difference]: Start difference. First operand 973 states and 1464 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:20,254 INFO L93 Difference]: Finished difference Result 973 states and 1463 transitions. [2021-11-02 22:20:20,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:20,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1463 transitions. [2021-11-02 22:20:20,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1463 transitions. [2021-11-02 22:20:20,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:20,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:20,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1463 transitions. [2021-11-02 22:20:20,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:20,277 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2021-11-02 22:20:20,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1463 transitions. [2021-11-02 22:20:20,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:20,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.5035971223021583) internal successors, (1463), 972 states have internal predecessors, (1463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1463 transitions. [2021-11-02 22:20:20,303 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2021-11-02 22:20:20,303 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2021-11-02 22:20:20,303 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-02 22:20:20,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1463 transitions. [2021-11-02 22:20:20,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:20,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:20,312 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,313 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,313 INFO L791 eck$LassoCheckResult]: Stem: 6597#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6598#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5887#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5888#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 6336#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6337#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6572#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6573#L616-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6425#L621-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6426#L626-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6659#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6123#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6124#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6409#L858-1 assume !(0 == ~T1_E~0); 5873#L863-1 assume !(0 == ~T2_E~0); 5874#L868-1 assume !(0 == ~T3_E~0); 6818#L873-1 assume !(0 == ~T4_E~0); 6816#L878-1 assume !(0 == ~T5_E~0); 6801#L883-1 assume !(0 == ~T6_E~0); 6802#L888-1 assume !(0 == ~T7_E~0); 6540#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6541#L898-1 assume !(0 == ~E_M~0); 6826#L903-1 assume !(0 == ~E_1~0); 6800#L908-1 assume !(0 == ~E_2~0); 6671#L913-1 assume !(0 == ~E_3~0); 5952#L918-1 assume !(0 == ~E_4~0); 5953#L923-1 assume !(0 == ~E_5~0); 6679#L928-1 assume !(0 == ~E_6~0); 6067#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6068#L938-1 assume !(0 == ~E_8~0); 6669#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6822#L422 assume !(1 == ~m_pc~0); 6626#L422-2 is_master_triggered_~__retres1~0 := 0; 6379#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6305#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6306#L1065 assume !(0 != activate_threads_~tmp~1); 6060#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5913#L441 assume 1 == ~t1_pc~0; 5914#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6503#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6841#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6505#L1073 assume !(0 != activate_threads_~tmp___0~0); 6506#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6811#L460 assume !(1 == ~t2_pc~0); 5876#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 5877#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6631#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6831#L1081 assume !(0 != activate_threads_~tmp___1~0); 6585#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6551#L479 assume 1 == ~t3_pc~0; 6361#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6362#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6779#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6273#L1089 assume !(0 != activate_threads_~tmp___2~0); 5916#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5917#L498 assume !(1 == ~t4_pc~0); 6035#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 6359#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6360#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6723#L1097 assume !(0 != activate_threads_~tmp___3~0); 6328#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6329#L517 assume 1 == ~t5_pc~0; 6781#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6782#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6410#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6411#L1105 assume !(0 != activate_threads_~tmp___4~0); 6449#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6450#L536 assume 1 == ~t6_pc~0; 6396#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6397#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6737#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6842#L1113 assume !(0 != activate_threads_~tmp___5~0); 6146#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6147#L555 assume !(1 == ~t7_pc~0); 6604#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 6660#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5971#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5950#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5951#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5981#L574 assume 1 == ~t8_pc~0; 5982#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6494#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6052#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 6053#L1129 assume !(0 != activate_threads_~tmp___7~0); 6118#L1129-2 assume !(1 == ~M_E~0); 6119#L956-1 assume !(1 == ~T1_E~0); 6135#L961-1 assume !(1 == ~T2_E~0); 6542#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6543#L971-1 assume !(1 == ~T4_E~0); 6663#L976-1 assume !(1 == ~T5_E~0); 6642#L981-1 assume !(1 == ~T6_E~0); 6400#L986-1 assume !(1 == ~T7_E~0); 6182#L991-1 assume !(1 == ~T8_E~0); 6183#L996-1 assume !(1 == ~E_M~0); 6819#L1001-1 assume !(1 == ~E_1~0); 6592#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6593#L1011-1 assume !(1 == ~E_3~0); 6797#L1016-1 assume !(1 == ~E_4~0); 6812#L1021-1 assume !(1 == ~E_5~0); 5905#L1026-1 assume !(1 == ~E_6~0); 5906#L1031-1 assume !(1 == ~E_7~0); 6556#L1036-1 assume !(1 == ~E_8~0); 6356#L1307-1 [2021-11-02 22:20:20,314 INFO L793 eck$LassoCheckResult]: Loop: 6356#L1307-1 assume !false; 6357#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 5974#L833 assume !false; 5975#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6544#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6143#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6733#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 6653#L716 assume !(0 != eval_~tmp~0); 6652#L848 start_simulation_~kernel_st~0 := 2; 6354#L594-1 start_simulation_~kernel_st~0 := 3; 6355#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6689#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6629#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6616#L868-3 assume !(0 == ~T3_E~0); 6617#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6199#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5931#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5932#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5933#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5934#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6435#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6739#L908-3 assume !(0 == ~E_2~0); 6445#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5976#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5977#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6184#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6185#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6678#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6523#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6524#L422-30 assume 1 == ~m_pc~0; 6481#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6483#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6156#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6157#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6085#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6086#L441-30 assume 1 == ~t1_pc~0; 6049#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6050#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6209#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6637#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6638#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6832#L460-30 assume !(1 == ~t2_pc~0); 6560#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 6559#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6618#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6281#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6041#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6042#L479-30 assume !(1 == ~t3_pc~0); 6775#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 5889#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5890#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6415#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6416#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6321#L498-30 assume 1 == ~t4_pc~0; 6322#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6393#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6204#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6205#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6666#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6667#L517-30 assume 1 == ~t5_pc~0; 6386#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6387#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6823#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6716#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 6278#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6106#L536-30 assume 1 == ~t6_pc~0; 6022#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6023#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6391#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6624#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6279#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6280#L555-30 assume 1 == ~t7_pc~0; 6627#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6170#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6767#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 6756#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6757#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6790#L574-30 assume 1 == ~t8_pc~0; 6791#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6348#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6264#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 6265#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6364#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 6672#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6522#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6316#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6317#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6571#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5963#L981-3 assume !(1 == ~T6_E~0); 5964#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5948#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5949#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6654#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6286#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6287#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6675#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6712#L1021-3 assume !(1 == ~E_5~0); 6469#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6470#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6650#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6651#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6646#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6222#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6500#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 6266#L1326 assume !(0 == start_simulation_~tmp~3); 6267#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6380#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6166#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6705#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 6599#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6600#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 6724#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 6833#L1339 assume !(0 != start_simulation_~tmp___0~1); 6356#L1307-1 [2021-11-02 22:20:20,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,315 INFO L85 PathProgramCache]: Analyzing trace with hash 140552513, now seen corresponding path program 1 times [2021-11-02 22:20:20,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,317 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481180439] [2021-11-02 22:20:20,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,317 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,399 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481180439] [2021-11-02 22:20:20,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481180439] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,401 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175908336] [2021-11-02 22:20:20,402 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:20,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,402 INFO L85 PathProgramCache]: Analyzing trace with hash 910031802, now seen corresponding path program 1 times [2021-11-02 22:20:20,403 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,404 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423282842] [2021-11-02 22:20:20,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,404 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,472 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423282842] [2021-11-02 22:20:20,472 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423282842] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,473 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,474 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866628059] [2021-11-02 22:20:20,475 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:20,475 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:20,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:20,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:20,481 INFO L87 Difference]: Start difference. First operand 973 states and 1463 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:20,502 INFO L93 Difference]: Finished difference Result 973 states and 1462 transitions. [2021-11-02 22:20:20,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:20,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1462 transitions. [2021-11-02 22:20:20,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1462 transitions. [2021-11-02 22:20:20,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:20,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:20,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1462 transitions. [2021-11-02 22:20:20,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:20,525 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2021-11-02 22:20:20,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1462 transitions. [2021-11-02 22:20:20,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:20,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.5025693730729701) internal successors, (1462), 972 states have internal predecessors, (1462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1462 transitions. [2021-11-02 22:20:20,549 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2021-11-02 22:20:20,549 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2021-11-02 22:20:20,549 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-02 22:20:20,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1462 transitions. [2021-11-02 22:20:20,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:20,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:20,564 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,565 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,565 INFO L791 eck$LassoCheckResult]: Stem: 8550#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8551#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7840#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7841#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 8289#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8290#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8525#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8526#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8378#L621-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8379#L626-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8612#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8076#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8077#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 8362#L858-1 assume !(0 == ~T1_E~0); 7826#L863-1 assume !(0 == ~T2_E~0); 7827#L868-1 assume !(0 == ~T3_E~0); 8771#L873-1 assume !(0 == ~T4_E~0); 8769#L878-1 assume !(0 == ~T5_E~0); 8754#L883-1 assume !(0 == ~T6_E~0); 8755#L888-1 assume !(0 == ~T7_E~0); 8493#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8494#L898-1 assume !(0 == ~E_M~0); 8779#L903-1 assume !(0 == ~E_1~0); 8753#L908-1 assume !(0 == ~E_2~0); 8624#L913-1 assume !(0 == ~E_3~0); 7905#L918-1 assume !(0 == ~E_4~0); 7906#L923-1 assume !(0 == ~E_5~0); 8632#L928-1 assume !(0 == ~E_6~0); 8020#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 8021#L938-1 assume !(0 == ~E_8~0); 8622#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8775#L422 assume !(1 == ~m_pc~0); 8579#L422-2 is_master_triggered_~__retres1~0 := 0; 8332#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8258#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8259#L1065 assume !(0 != activate_threads_~tmp~1); 8013#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7866#L441 assume 1 == ~t1_pc~0; 7867#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8456#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8794#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8458#L1073 assume !(0 != activate_threads_~tmp___0~0); 8459#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8764#L460 assume !(1 == ~t2_pc~0); 7829#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 7830#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8584#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8784#L1081 assume !(0 != activate_threads_~tmp___1~0); 8538#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8504#L479 assume 1 == ~t3_pc~0; 8314#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8315#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8732#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8226#L1089 assume !(0 != activate_threads_~tmp___2~0); 7869#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7870#L498 assume !(1 == ~t4_pc~0); 7988#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 8312#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8313#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8676#L1097 assume !(0 != activate_threads_~tmp___3~0); 8281#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8282#L517 assume 1 == ~t5_pc~0; 8734#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8735#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8363#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8364#L1105 assume !(0 != activate_threads_~tmp___4~0); 8402#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8403#L536 assume 1 == ~t6_pc~0; 8349#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8350#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8690#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8795#L1113 assume !(0 != activate_threads_~tmp___5~0); 8099#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8100#L555 assume !(1 == ~t7_pc~0); 8557#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 8613#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7924#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7903#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7904#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7934#L574 assume 1 == ~t8_pc~0; 7935#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8447#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8005#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8006#L1129 assume !(0 != activate_threads_~tmp___7~0); 8071#L1129-2 assume !(1 == ~M_E~0); 8072#L956-1 assume !(1 == ~T1_E~0); 8088#L961-1 assume !(1 == ~T2_E~0); 8495#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8496#L971-1 assume !(1 == ~T4_E~0); 8616#L976-1 assume !(1 == ~T5_E~0); 8595#L981-1 assume !(1 == ~T6_E~0); 8353#L986-1 assume !(1 == ~T7_E~0); 8135#L991-1 assume !(1 == ~T8_E~0); 8136#L996-1 assume !(1 == ~E_M~0); 8772#L1001-1 assume !(1 == ~E_1~0); 8545#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8546#L1011-1 assume !(1 == ~E_3~0); 8750#L1016-1 assume !(1 == ~E_4~0); 8765#L1021-1 assume !(1 == ~E_5~0); 7858#L1026-1 assume !(1 == ~E_6~0); 7859#L1031-1 assume !(1 == ~E_7~0); 8509#L1036-1 assume !(1 == ~E_8~0); 8309#L1307-1 [2021-11-02 22:20:20,566 INFO L793 eck$LassoCheckResult]: Loop: 8309#L1307-1 assume !false; 8310#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 7927#L833 assume !false; 7928#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8497#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8096#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8686#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 8606#L716 assume !(0 != eval_~tmp~0); 8605#L848 start_simulation_~kernel_st~0 := 2; 8307#L594-1 start_simulation_~kernel_st~0 := 3; 8308#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8642#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8582#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8569#L868-3 assume !(0 == ~T3_E~0); 8570#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8152#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7884#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7885#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7886#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7887#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8388#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8692#L908-3 assume !(0 == ~E_2~0); 8398#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7929#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7930#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8137#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8138#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8631#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8476#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8477#L422-30 assume 1 == ~m_pc~0; 8434#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8436#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8109#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8110#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8038#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8039#L441-30 assume 1 == ~t1_pc~0; 8002#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8003#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8162#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8590#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8591#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8785#L460-30 assume !(1 == ~t2_pc~0); 8513#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 8512#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8571#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8234#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7994#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7995#L479-30 assume !(1 == ~t3_pc~0); 8728#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 7842#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7843#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8368#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8369#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8274#L498-30 assume 1 == ~t4_pc~0; 8275#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8346#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8157#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8158#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8619#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8620#L517-30 assume 1 == ~t5_pc~0; 8339#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8340#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8776#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8669#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 8231#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8059#L536-30 assume 1 == ~t6_pc~0; 7975#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7976#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8344#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8577#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8232#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8233#L555-30 assume 1 == ~t7_pc~0; 8580#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8123#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8720#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8709#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8710#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8743#L574-30 assume 1 == ~t8_pc~0; 8744#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8301#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8217#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8218#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8317#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 8625#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8475#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8269#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8270#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8524#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7916#L981-3 assume !(1 == ~T6_E~0); 7917#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7901#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7902#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8607#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8239#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8240#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8628#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8665#L1021-3 assume !(1 == ~E_5~0); 8422#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8423#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8603#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8604#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8599#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8175#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8453#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 8219#L1326 assume !(0 == start_simulation_~tmp~3); 8220#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8333#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8119#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8658#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 8552#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 8553#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 8677#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 8786#L1339 assume !(0 != start_simulation_~tmp___0~1); 8309#L1307-1 [2021-11-02 22:20:20,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1210832705, now seen corresponding path program 1 times [2021-11-02 22:20:20,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669198525] [2021-11-02 22:20:20,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,606 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,606 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669198525] [2021-11-02 22:20:20,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1669198525] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,606 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,607 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015761344] [2021-11-02 22:20:20,607 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:20,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,608 INFO L85 PathProgramCache]: Analyzing trace with hash 910031802, now seen corresponding path program 2 times [2021-11-02 22:20:20,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,609 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177451626] [2021-11-02 22:20:20,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,660 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177451626] [2021-11-02 22:20:20,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177451626] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,661 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914725389] [2021-11-02 22:20:20,661 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:20,662 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:20,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:20,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:20,663 INFO L87 Difference]: Start difference. First operand 973 states and 1462 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:20,684 INFO L93 Difference]: Finished difference Result 973 states and 1461 transitions. [2021-11-02 22:20:20,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:20,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1461 transitions. [2021-11-02 22:20:20,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1461 transitions. [2021-11-02 22:20:20,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:20,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:20,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1461 transitions. [2021-11-02 22:20:20,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:20,705 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2021-11-02 22:20:20,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1461 transitions. [2021-11-02 22:20:20,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:20,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.5015416238437822) internal successors, (1461), 972 states have internal predecessors, (1461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1461 transitions. [2021-11-02 22:20:20,730 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2021-11-02 22:20:20,730 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2021-11-02 22:20:20,730 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-02 22:20:20,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1461 transitions. [2021-11-02 22:20:20,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:20,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:20,740 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,740 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,740 INFO L791 eck$LassoCheckResult]: Stem: 10503#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10504#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9793#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9794#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 10242#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10243#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10478#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10479#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10331#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10332#L626-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10565#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10029#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10030#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 10315#L858-1 assume !(0 == ~T1_E~0); 9779#L863-1 assume !(0 == ~T2_E~0); 9780#L868-1 assume !(0 == ~T3_E~0); 10724#L873-1 assume !(0 == ~T4_E~0); 10722#L878-1 assume !(0 == ~T5_E~0); 10707#L883-1 assume !(0 == ~T6_E~0); 10708#L888-1 assume !(0 == ~T7_E~0); 10446#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10447#L898-1 assume !(0 == ~E_M~0); 10732#L903-1 assume !(0 == ~E_1~0); 10706#L908-1 assume !(0 == ~E_2~0); 10577#L913-1 assume !(0 == ~E_3~0); 9858#L918-1 assume !(0 == ~E_4~0); 9859#L923-1 assume !(0 == ~E_5~0); 10585#L928-1 assume !(0 == ~E_6~0); 9973#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9974#L938-1 assume !(0 == ~E_8~0); 10575#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10728#L422 assume !(1 == ~m_pc~0); 10532#L422-2 is_master_triggered_~__retres1~0 := 0; 10285#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10211#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10212#L1065 assume !(0 != activate_threads_~tmp~1); 9966#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9819#L441 assume 1 == ~t1_pc~0; 9820#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10409#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10747#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10411#L1073 assume !(0 != activate_threads_~tmp___0~0); 10412#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10717#L460 assume !(1 == ~t2_pc~0); 9782#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 9783#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10537#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10737#L1081 assume !(0 != activate_threads_~tmp___1~0); 10491#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10457#L479 assume 1 == ~t3_pc~0; 10267#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10268#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10685#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10179#L1089 assume !(0 != activate_threads_~tmp___2~0); 9822#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9823#L498 assume !(1 == ~t4_pc~0); 9941#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 10265#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10266#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10629#L1097 assume !(0 != activate_threads_~tmp___3~0); 10234#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10235#L517 assume 1 == ~t5_pc~0; 10687#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10688#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10316#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10317#L1105 assume !(0 != activate_threads_~tmp___4~0); 10355#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10356#L536 assume 1 == ~t6_pc~0; 10302#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10303#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10643#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 10748#L1113 assume !(0 != activate_threads_~tmp___5~0); 10052#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10053#L555 assume !(1 == ~t7_pc~0); 10510#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 10566#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9877#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9856#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9857#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9887#L574 assume 1 == ~t8_pc~0; 9888#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10400#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9958#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9959#L1129 assume !(0 != activate_threads_~tmp___7~0); 10024#L1129-2 assume !(1 == ~M_E~0); 10025#L956-1 assume !(1 == ~T1_E~0); 10041#L961-1 assume !(1 == ~T2_E~0); 10448#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10449#L971-1 assume !(1 == ~T4_E~0); 10569#L976-1 assume !(1 == ~T5_E~0); 10548#L981-1 assume !(1 == ~T6_E~0); 10306#L986-1 assume !(1 == ~T7_E~0); 10088#L991-1 assume !(1 == ~T8_E~0); 10089#L996-1 assume !(1 == ~E_M~0); 10725#L1001-1 assume !(1 == ~E_1~0); 10498#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10499#L1011-1 assume !(1 == ~E_3~0); 10703#L1016-1 assume !(1 == ~E_4~0); 10718#L1021-1 assume !(1 == ~E_5~0); 9811#L1026-1 assume !(1 == ~E_6~0); 9812#L1031-1 assume !(1 == ~E_7~0); 10462#L1036-1 assume !(1 == ~E_8~0); 10262#L1307-1 [2021-11-02 22:20:20,741 INFO L793 eck$LassoCheckResult]: Loop: 10262#L1307-1 assume !false; 10263#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9880#L833 assume !false; 9881#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10450#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10049#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10639#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 10559#L716 assume !(0 != eval_~tmp~0); 10558#L848 start_simulation_~kernel_st~0 := 2; 10260#L594-1 start_simulation_~kernel_st~0 := 3; 10261#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10595#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10535#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10522#L868-3 assume !(0 == ~T3_E~0); 10523#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10105#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9837#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9838#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9839#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9840#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10341#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10645#L908-3 assume !(0 == ~E_2~0); 10351#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9882#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9883#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10090#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10091#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10584#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10429#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10430#L422-30 assume 1 == ~m_pc~0; 10387#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10389#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10062#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10063#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9991#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9992#L441-30 assume 1 == ~t1_pc~0; 9955#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9956#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10115#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10543#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10544#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10738#L460-30 assume 1 == ~t2_pc~0; 10464#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10465#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10524#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10187#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9947#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9948#L479-30 assume !(1 == ~t3_pc~0); 10681#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 9795#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9796#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10321#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10322#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10227#L498-30 assume 1 == ~t4_pc~0; 10228#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10299#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10110#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10111#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10572#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10573#L517-30 assume 1 == ~t5_pc~0; 10292#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10293#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10729#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10622#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 10184#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10012#L536-30 assume 1 == ~t6_pc~0; 9928#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9929#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10297#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 10530#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10185#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10186#L555-30 assume 1 == ~t7_pc~0; 10533#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10076#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10673#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10662#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10663#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10696#L574-30 assume 1 == ~t8_pc~0; 10697#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10254#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10170#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 10171#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 10270#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 10578#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10428#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10222#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10223#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10477#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9869#L981-3 assume !(1 == ~T6_E~0); 9870#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9854#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9855#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10560#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10192#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10193#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10581#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10618#L1021-3 assume !(1 == ~E_5~0); 10375#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10376#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10556#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10557#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10552#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10128#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10406#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 10172#L1326 assume !(0 == start_simulation_~tmp~3); 10173#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10286#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10072#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10611#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 10505#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 10506#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 10630#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 10739#L1339 assume !(0 != start_simulation_~tmp___0~1); 10262#L1307-1 [2021-11-02 22:20:20,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,742 INFO L85 PathProgramCache]: Analyzing trace with hash 408142209, now seen corresponding path program 1 times [2021-11-02 22:20:20,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,742 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284382275] [2021-11-02 22:20:20,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,799 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284382275] [2021-11-02 22:20:20,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284382275] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,800 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898001590] [2021-11-02 22:20:20,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:20,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1395447323, now seen corresponding path program 2 times [2021-11-02 22:20:20,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,802 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173967434] [2021-11-02 22:20:20,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,857 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173967434] [2021-11-02 22:20:20,858 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173967434] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,858 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,858 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,859 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563500131] [2021-11-02 22:20:20,859 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:20,862 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:20,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:20,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:20,863 INFO L87 Difference]: Start difference. First operand 973 states and 1461 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:20,888 INFO L93 Difference]: Finished difference Result 973 states and 1460 transitions. [2021-11-02 22:20:20,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:20,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1460 transitions. [2021-11-02 22:20:20,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1460 transitions. [2021-11-02 22:20:20,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:20,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:20,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1460 transitions. [2021-11-02 22:20:20,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:20,913 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2021-11-02 22:20:20,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1460 transitions. [2021-11-02 22:20:20,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:20,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.500513874614594) internal successors, (1460), 972 states have internal predecessors, (1460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:20,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1460 transitions. [2021-11-02 22:20:20,938 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2021-11-02 22:20:20,938 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2021-11-02 22:20:20,938 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-02 22:20:20,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1460 transitions. [2021-11-02 22:20:20,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:20,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:20,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:20,947 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,947 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:20,948 INFO L791 eck$LassoCheckResult]: Stem: 12456#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12457#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11746#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11747#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 12195#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12196#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12431#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12432#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12284#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12285#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12518#L631-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11982#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11983#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 12268#L858-1 assume !(0 == ~T1_E~0); 11732#L863-1 assume !(0 == ~T2_E~0); 11733#L868-1 assume !(0 == ~T3_E~0); 12677#L873-1 assume !(0 == ~T4_E~0); 12675#L878-1 assume !(0 == ~T5_E~0); 12660#L883-1 assume !(0 == ~T6_E~0); 12661#L888-1 assume !(0 == ~T7_E~0); 12399#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12400#L898-1 assume !(0 == ~E_M~0); 12685#L903-1 assume !(0 == ~E_1~0); 12659#L908-1 assume !(0 == ~E_2~0); 12530#L913-1 assume !(0 == ~E_3~0); 11811#L918-1 assume !(0 == ~E_4~0); 11812#L923-1 assume !(0 == ~E_5~0); 12538#L928-1 assume !(0 == ~E_6~0); 11926#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 11927#L938-1 assume !(0 == ~E_8~0); 12528#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12681#L422 assume !(1 == ~m_pc~0); 12485#L422-2 is_master_triggered_~__retres1~0 := 0; 12238#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12164#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12165#L1065 assume !(0 != activate_threads_~tmp~1); 11919#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11772#L441 assume 1 == ~t1_pc~0; 11773#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12362#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12700#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12364#L1073 assume !(0 != activate_threads_~tmp___0~0); 12365#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12670#L460 assume !(1 == ~t2_pc~0); 11735#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 11736#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12490#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12690#L1081 assume !(0 != activate_threads_~tmp___1~0); 12444#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12410#L479 assume 1 == ~t3_pc~0; 12220#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12221#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12638#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12132#L1089 assume !(0 != activate_threads_~tmp___2~0); 11775#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11776#L498 assume !(1 == ~t4_pc~0); 11894#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 12218#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12219#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12582#L1097 assume !(0 != activate_threads_~tmp___3~0); 12187#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12188#L517 assume 1 == ~t5_pc~0; 12640#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12641#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12269#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12270#L1105 assume !(0 != activate_threads_~tmp___4~0); 12308#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12309#L536 assume 1 == ~t6_pc~0; 12255#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12256#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12596#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12701#L1113 assume !(0 != activate_threads_~tmp___5~0); 12005#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12006#L555 assume !(1 == ~t7_pc~0); 12463#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 12519#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11830#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11809#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11810#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11840#L574 assume 1 == ~t8_pc~0; 11841#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12353#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11911#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 11912#L1129 assume !(0 != activate_threads_~tmp___7~0); 11977#L1129-2 assume !(1 == ~M_E~0); 11978#L956-1 assume !(1 == ~T1_E~0); 11994#L961-1 assume !(1 == ~T2_E~0); 12401#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12402#L971-1 assume !(1 == ~T4_E~0); 12522#L976-1 assume !(1 == ~T5_E~0); 12501#L981-1 assume !(1 == ~T6_E~0); 12259#L986-1 assume !(1 == ~T7_E~0); 12041#L991-1 assume !(1 == ~T8_E~0); 12042#L996-1 assume !(1 == ~E_M~0); 12678#L1001-1 assume !(1 == ~E_1~0); 12451#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12452#L1011-1 assume !(1 == ~E_3~0); 12656#L1016-1 assume !(1 == ~E_4~0); 12671#L1021-1 assume !(1 == ~E_5~0); 11764#L1026-1 assume !(1 == ~E_6~0); 11765#L1031-1 assume !(1 == ~E_7~0); 12415#L1036-1 assume !(1 == ~E_8~0); 12215#L1307-1 [2021-11-02 22:20:20,948 INFO L793 eck$LassoCheckResult]: Loop: 12215#L1307-1 assume !false; 12216#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 11833#L833 assume !false; 11834#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12403#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12002#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12592#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12512#L716 assume !(0 != eval_~tmp~0); 12511#L848 start_simulation_~kernel_st~0 := 2; 12213#L594-1 start_simulation_~kernel_st~0 := 3; 12214#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12548#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12488#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12475#L868-3 assume !(0 == ~T3_E~0); 12476#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12058#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11790#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11791#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11792#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11793#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12294#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12598#L908-3 assume !(0 == ~E_2~0); 12304#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11835#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11836#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12043#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12044#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12537#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12382#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12383#L422-30 assume 1 == ~m_pc~0; 12340#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12342#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12015#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12016#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11944#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11945#L441-30 assume 1 == ~t1_pc~0; 11908#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11909#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12068#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12496#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12497#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12691#L460-30 assume 1 == ~t2_pc~0; 12417#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12418#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12477#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12140#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11900#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11901#L479-30 assume !(1 == ~t3_pc~0); 12634#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 11748#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11749#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12274#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12275#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12180#L498-30 assume 1 == ~t4_pc~0; 12181#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12252#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12063#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12064#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12525#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12526#L517-30 assume 1 == ~t5_pc~0; 12245#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12246#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12682#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12575#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 12137#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11965#L536-30 assume 1 == ~t6_pc~0; 11881#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11882#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12250#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12483#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12138#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12139#L555-30 assume 1 == ~t7_pc~0; 12486#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12029#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12626#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12615#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12616#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12649#L574-30 assume 1 == ~t8_pc~0; 12650#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12207#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12123#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12124#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12223#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 12531#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12381#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12175#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12176#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12430#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11822#L981-3 assume !(1 == ~T6_E~0); 11823#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11807#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11808#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12513#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12145#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12146#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12534#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12571#L1021-3 assume !(1 == ~E_5~0); 12328#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12329#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12509#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12510#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12505#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12081#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12359#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 12125#L1326 assume !(0 == start_simulation_~tmp~3); 12126#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12239#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12025#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12564#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 12458#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 12459#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 12583#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 12692#L1339 assume !(0 != start_simulation_~tmp___0~1); 12215#L1307-1 [2021-11-02 22:20:20,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1291651199, now seen corresponding path program 1 times [2021-11-02 22:20:20,949 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,949 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501858139] [2021-11-02 22:20:20,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,950 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:20,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:20,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:20,981 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501858139] [2021-11-02 22:20:20,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501858139] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:20,982 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:20,982 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:20,982 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217058927] [2021-11-02 22:20:20,982 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:20,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:20,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1395447323, now seen corresponding path program 3 times [2021-11-02 22:20:20,983 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:20,983 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117242852] [2021-11-02 22:20:20,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:20,984 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:20,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,025 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,025 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117242852] [2021-11-02 22:20:21,025 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117242852] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,025 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,025 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,026 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586516915] [2021-11-02 22:20:21,026 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:21,026 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:21,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:21,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:21,027 INFO L87 Difference]: Start difference. First operand 973 states and 1460 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:21,050 INFO L93 Difference]: Finished difference Result 973 states and 1459 transitions. [2021-11-02 22:20:21,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:21,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1459 transitions. [2021-11-02 22:20:21,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:21,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1459 transitions. [2021-11-02 22:20:21,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:21,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:21,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1459 transitions. [2021-11-02 22:20:21,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:21,072 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2021-11-02 22:20:21,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1459 transitions. [2021-11-02 22:20:21,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:21,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.499486125385406) internal successors, (1459), 972 states have internal predecessors, (1459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1459 transitions. [2021-11-02 22:20:21,097 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2021-11-02 22:20:21,097 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2021-11-02 22:20:21,098 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-02 22:20:21,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1459 transitions. [2021-11-02 22:20:21,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:21,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:21,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:21,106 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,106 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,107 INFO L791 eck$LassoCheckResult]: Stem: 14409#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14410#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13699#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13700#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 14148#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14149#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14384#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14385#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14237#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14238#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14471#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13935#L636-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13936#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 14221#L858-1 assume !(0 == ~T1_E~0); 13685#L863-1 assume !(0 == ~T2_E~0); 13686#L868-1 assume !(0 == ~T3_E~0); 14630#L873-1 assume !(0 == ~T4_E~0); 14628#L878-1 assume !(0 == ~T5_E~0); 14613#L883-1 assume !(0 == ~T6_E~0); 14614#L888-1 assume !(0 == ~T7_E~0); 14352#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14353#L898-1 assume !(0 == ~E_M~0); 14638#L903-1 assume !(0 == ~E_1~0); 14612#L908-1 assume !(0 == ~E_2~0); 14483#L913-1 assume !(0 == ~E_3~0); 13764#L918-1 assume !(0 == ~E_4~0); 13765#L923-1 assume !(0 == ~E_5~0); 14491#L928-1 assume !(0 == ~E_6~0); 13879#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13880#L938-1 assume !(0 == ~E_8~0); 14481#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14634#L422 assume !(1 == ~m_pc~0); 14438#L422-2 is_master_triggered_~__retres1~0 := 0; 14191#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14117#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14118#L1065 assume !(0 != activate_threads_~tmp~1); 13872#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13725#L441 assume 1 == ~t1_pc~0; 13726#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14315#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14653#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14317#L1073 assume !(0 != activate_threads_~tmp___0~0); 14318#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14623#L460 assume !(1 == ~t2_pc~0); 13688#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 13689#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14443#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14643#L1081 assume !(0 != activate_threads_~tmp___1~0); 14397#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14363#L479 assume 1 == ~t3_pc~0; 14173#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14174#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14591#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14085#L1089 assume !(0 != activate_threads_~tmp___2~0); 13728#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13729#L498 assume !(1 == ~t4_pc~0); 13847#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 14171#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14172#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14535#L1097 assume !(0 != activate_threads_~tmp___3~0); 14140#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14141#L517 assume 1 == ~t5_pc~0; 14593#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14594#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14222#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14223#L1105 assume !(0 != activate_threads_~tmp___4~0); 14261#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14262#L536 assume 1 == ~t6_pc~0; 14208#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14209#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14549#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14654#L1113 assume !(0 != activate_threads_~tmp___5~0); 13958#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13959#L555 assume !(1 == ~t7_pc~0); 14416#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 14472#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13783#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13762#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13763#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13793#L574 assume 1 == ~t8_pc~0; 13794#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14306#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13864#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13865#L1129 assume !(0 != activate_threads_~tmp___7~0); 13930#L1129-2 assume !(1 == ~M_E~0); 13931#L956-1 assume !(1 == ~T1_E~0); 13947#L961-1 assume !(1 == ~T2_E~0); 14354#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14355#L971-1 assume !(1 == ~T4_E~0); 14475#L976-1 assume !(1 == ~T5_E~0); 14454#L981-1 assume !(1 == ~T6_E~0); 14212#L986-1 assume !(1 == ~T7_E~0); 13994#L991-1 assume !(1 == ~T8_E~0); 13995#L996-1 assume !(1 == ~E_M~0); 14631#L1001-1 assume !(1 == ~E_1~0); 14404#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14405#L1011-1 assume !(1 == ~E_3~0); 14609#L1016-1 assume !(1 == ~E_4~0); 14624#L1021-1 assume !(1 == ~E_5~0); 13717#L1026-1 assume !(1 == ~E_6~0); 13718#L1031-1 assume !(1 == ~E_7~0); 14368#L1036-1 assume !(1 == ~E_8~0); 14168#L1307-1 [2021-11-02 22:20:21,107 INFO L793 eck$LassoCheckResult]: Loop: 14168#L1307-1 assume !false; 14169#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 13786#L833 assume !false; 13787#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14356#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13955#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14545#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 14465#L716 assume !(0 != eval_~tmp~0); 14464#L848 start_simulation_~kernel_st~0 := 2; 14166#L594-1 start_simulation_~kernel_st~0 := 3; 14167#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14501#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14441#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14428#L868-3 assume !(0 == ~T3_E~0); 14429#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14011#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13743#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13744#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13745#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13746#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14247#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14551#L908-3 assume !(0 == ~E_2~0); 14257#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13788#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13789#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13996#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13997#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14490#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14335#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14336#L422-30 assume 1 == ~m_pc~0; 14293#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14295#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13968#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13969#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13897#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13898#L441-30 assume 1 == ~t1_pc~0; 13861#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13862#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14021#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14449#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14450#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14644#L460-30 assume 1 == ~t2_pc~0; 14370#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14371#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14430#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14093#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13853#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13854#L479-30 assume 1 == ~t3_pc~0; 14640#L480-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13701#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13702#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14227#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14228#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14133#L498-30 assume 1 == ~t4_pc~0; 14134#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14205#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14016#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14017#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14478#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14479#L517-30 assume 1 == ~t5_pc~0; 14198#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14199#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14635#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14528#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 14090#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13918#L536-30 assume 1 == ~t6_pc~0; 13834#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13835#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14203#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14436#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14091#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14092#L555-30 assume 1 == ~t7_pc~0; 14439#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13982#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14579#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14568#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14569#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14602#L574-30 assume 1 == ~t8_pc~0; 14603#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14160#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14076#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14077#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 14176#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 14484#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14334#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14128#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14129#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14383#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13775#L981-3 assume !(1 == ~T6_E~0); 13776#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13760#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13761#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14466#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14098#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14099#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14487#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14524#L1021-3 assume !(1 == ~E_5~0); 14281#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14282#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14462#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14463#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14458#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 14034#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14312#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 14078#L1326 assume !(0 == start_simulation_~tmp~3); 14079#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14192#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13978#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14517#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 14411#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 14412#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 14536#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 14645#L1339 assume !(0 != start_simulation_~tmp___0~1); 14168#L1307-1 [2021-11-02 22:20:21,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1320151489, now seen corresponding path program 1 times [2021-11-02 22:20:21,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,108 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341176194] [2021-11-02 22:20:21,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,137 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341176194] [2021-11-02 22:20:21,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341176194] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,137 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603370366] [2021-11-02 22:20:21,138 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:21,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1721545412, now seen corresponding path program 1 times [2021-11-02 22:20:21,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,139 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394974757] [2021-11-02 22:20:21,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,192 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394974757] [2021-11-02 22:20:21,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394974757] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,195 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,195 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,195 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437709367] [2021-11-02 22:20:21,196 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:21,196 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:21,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:21,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:21,197 INFO L87 Difference]: Start difference. First operand 973 states and 1459 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:21,221 INFO L93 Difference]: Finished difference Result 973 states and 1458 transitions. [2021-11-02 22:20:21,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:21,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1458 transitions. [2021-11-02 22:20:21,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:21,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1458 transitions. [2021-11-02 22:20:21,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-02 22:20:21,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-02 22:20:21,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1458 transitions. [2021-11-02 22:20:21,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:21,243 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2021-11-02 22:20:21,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1458 transitions. [2021-11-02 22:20:21,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2021-11-02 22:20:21,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 973 states have (on average 1.4984583761562178) internal successors, (1458), 972 states have internal predecessors, (1458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1458 transitions. [2021-11-02 22:20:21,272 INFO L704 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2021-11-02 22:20:21,272 INFO L587 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2021-11-02 22:20:21,272 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-02 22:20:21,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1458 transitions. [2021-11-02 22:20:21,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2021-11-02 22:20:21,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:21,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:21,281 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,282 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,282 INFO L791 eck$LassoCheckResult]: Stem: 16362#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16363#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15652#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15653#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 16101#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16102#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16337#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16338#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16190#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16191#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16424#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15888#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15889#L641-1 assume 0 == ~M_E~0;~M_E~0 := 1; 16174#L858-1 assume !(0 == ~T1_E~0); 15638#L863-1 assume !(0 == ~T2_E~0); 15639#L868-1 assume !(0 == ~T3_E~0); 16583#L873-1 assume !(0 == ~T4_E~0); 16581#L878-1 assume !(0 == ~T5_E~0); 16566#L883-1 assume !(0 == ~T6_E~0); 16567#L888-1 assume !(0 == ~T7_E~0); 16305#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16306#L898-1 assume !(0 == ~E_M~0); 16591#L903-1 assume !(0 == ~E_1~0); 16565#L908-1 assume !(0 == ~E_2~0); 16436#L913-1 assume !(0 == ~E_3~0); 15717#L918-1 assume !(0 == ~E_4~0); 15718#L923-1 assume !(0 == ~E_5~0); 16444#L928-1 assume !(0 == ~E_6~0); 15832#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15833#L938-1 assume !(0 == ~E_8~0); 16434#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16587#L422 assume !(1 == ~m_pc~0); 16391#L422-2 is_master_triggered_~__retres1~0 := 0; 16144#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16070#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16071#L1065 assume !(0 != activate_threads_~tmp~1); 15825#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15678#L441 assume 1 == ~t1_pc~0; 15679#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16268#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16606#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16270#L1073 assume !(0 != activate_threads_~tmp___0~0); 16271#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16576#L460 assume !(1 == ~t2_pc~0); 15641#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 15642#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16396#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16596#L1081 assume !(0 != activate_threads_~tmp___1~0); 16350#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16316#L479 assume 1 == ~t3_pc~0; 16126#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16127#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16544#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16038#L1089 assume !(0 != activate_threads_~tmp___2~0); 15681#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15682#L498 assume !(1 == ~t4_pc~0); 15800#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 16124#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16125#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16488#L1097 assume !(0 != activate_threads_~tmp___3~0); 16093#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16094#L517 assume 1 == ~t5_pc~0; 16546#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16547#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16175#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16176#L1105 assume !(0 != activate_threads_~tmp___4~0); 16214#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16215#L536 assume 1 == ~t6_pc~0; 16161#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16162#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16502#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16607#L1113 assume !(0 != activate_threads_~tmp___5~0); 15911#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15912#L555 assume !(1 == ~t7_pc~0); 16369#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 16425#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15736#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 15715#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15716#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15746#L574 assume 1 == ~t8_pc~0; 15747#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16259#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15817#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 15818#L1129 assume !(0 != activate_threads_~tmp___7~0); 15883#L1129-2 assume !(1 == ~M_E~0); 15884#L956-1 assume !(1 == ~T1_E~0); 15900#L961-1 assume !(1 == ~T2_E~0); 16307#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16308#L971-1 assume !(1 == ~T4_E~0); 16428#L976-1 assume !(1 == ~T5_E~0); 16407#L981-1 assume !(1 == ~T6_E~0); 16165#L986-1 assume !(1 == ~T7_E~0); 15947#L991-1 assume !(1 == ~T8_E~0); 15948#L996-1 assume !(1 == ~E_M~0); 16584#L1001-1 assume !(1 == ~E_1~0); 16357#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16358#L1011-1 assume !(1 == ~E_3~0); 16562#L1016-1 assume !(1 == ~E_4~0); 16577#L1021-1 assume !(1 == ~E_5~0); 15670#L1026-1 assume !(1 == ~E_6~0); 15671#L1031-1 assume !(1 == ~E_7~0); 16321#L1036-1 assume !(1 == ~E_8~0); 16121#L1307-1 [2021-11-02 22:20:21,283 INFO L793 eck$LassoCheckResult]: Loop: 16121#L1307-1 assume !false; 16122#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 15739#L833 assume !false; 15740#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16309#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15908#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16498#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16418#L716 assume !(0 != eval_~tmp~0); 16417#L848 start_simulation_~kernel_st~0 := 2; 16119#L594-1 start_simulation_~kernel_st~0 := 3; 16120#L858-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16454#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16394#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16381#L868-3 assume !(0 == ~T3_E~0); 16382#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15964#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15696#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15697#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15698#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15699#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16200#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16504#L908-3 assume !(0 == ~E_2~0); 16210#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15741#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15742#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15949#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15950#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16443#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16288#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16289#L422-30 assume 1 == ~m_pc~0; 16246#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16248#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15921#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15922#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15850#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15851#L441-30 assume 1 == ~t1_pc~0; 15814#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15815#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15974#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16402#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16403#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16597#L460-30 assume 1 == ~t2_pc~0; 16323#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16324#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16383#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16046#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15806#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15807#L479-30 assume 1 == ~t3_pc~0; 16593#L480-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15654#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15655#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16180#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16181#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16086#L498-30 assume 1 == ~t4_pc~0; 16087#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16158#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15969#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15970#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16431#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16432#L517-30 assume 1 == ~t5_pc~0; 16151#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16152#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16588#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16481#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 16043#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15871#L536-30 assume 1 == ~t6_pc~0; 15787#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15788#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16156#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16389#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16044#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16045#L555-30 assume 1 == ~t7_pc~0; 16392#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15935#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16532#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16521#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16522#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16555#L574-30 assume !(1 == ~t8_pc~0); 16112#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 16113#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16029#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16030#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 16129#L1129-32 assume 1 == ~M_E~0;~M_E~0 := 2; 16437#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16287#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16081#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16082#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16336#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15728#L981-3 assume !(1 == ~T6_E~0); 15729#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15713#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15714#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16419#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16051#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16052#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16440#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16477#L1021-3 assume !(1 == ~E_5~0); 16234#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16235#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16415#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16416#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16411#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15987#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16265#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 16031#L1326 assume !(0 == start_simulation_~tmp~3); 16032#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16145#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15931#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16470#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 16364#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16365#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 16489#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 16598#L1339 assume !(0 != start_simulation_~tmp___0~1); 16121#L1307-1 [2021-11-02 22:20:21,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1034233793, now seen corresponding path program 1 times [2021-11-02 22:20:21,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,284 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148047028] [2021-11-02 22:20:21,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,324 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148047028] [2021-11-02 22:20:21,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148047028] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,324 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:21,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977563389] [2021-11-02 22:20:21,326 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:21,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,326 INFO L85 PathProgramCache]: Analyzing trace with hash 808605275, now seen corresponding path program 1 times [2021-11-02 22:20:21,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,327 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128779831] [2021-11-02 22:20:21,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,391 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128779831] [2021-11-02 22:20:21,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128779831] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,392 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800746108] [2021-11-02 22:20:21,393 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:21,393 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:21,393 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:21,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:21,394 INFO L87 Difference]: Start difference. First operand 973 states and 1458 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:21,456 INFO L93 Difference]: Finished difference Result 1771 states and 2645 transitions. [2021-11-02 22:20:21,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:21,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2645 transitions. [2021-11-02 22:20:21,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:21,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2645 transitions. [2021-11-02 22:20:21,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2021-11-02 22:20:21,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2021-11-02 22:20:21,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2645 transitions. [2021-11-02 22:20:21,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:21,493 INFO L681 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2021-11-02 22:20:21,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2645 transitions. [2021-11-02 22:20:21,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2021-11-02 22:20:21,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1771 states, 1771 states have (on average 1.4935064935064934) internal successors, (2645), 1770 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2645 transitions. [2021-11-02 22:20:21,541 INFO L704 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2021-11-02 22:20:21,541 INFO L587 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2021-11-02 22:20:21,542 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-02 22:20:21,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2645 transitions. [2021-11-02 22:20:21,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:21,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:21,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:21,552 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,552 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,553 INFO L791 eck$LassoCheckResult]: Stem: 19122#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19123#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18403#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18404#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 18854#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18855#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19097#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19098#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18944#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18945#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19187#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18640#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18641#L641-1 assume !(0 == ~M_E~0); 18928#L858-1 assume !(0 == ~T1_E~0); 18389#L863-1 assume !(0 == ~T2_E~0); 18390#L868-1 assume !(0 == ~T3_E~0); 19382#L873-1 assume !(0 == ~T4_E~0); 19380#L878-1 assume !(0 == ~T5_E~0); 19358#L883-1 assume !(0 == ~T6_E~0); 19359#L888-1 assume !(0 == ~T7_E~0); 19063#L893-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19064#L898-1 assume !(0 == ~E_M~0); 19391#L903-1 assume !(0 == ~E_1~0); 19357#L908-1 assume !(0 == ~E_2~0); 19199#L913-1 assume !(0 == ~E_3~0); 18468#L918-1 assume !(0 == ~E_4~0); 18469#L923-1 assume !(0 == ~E_5~0); 19207#L928-1 assume !(0 == ~E_6~0); 18584#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18585#L938-1 assume !(0 == ~E_8~0); 19197#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19386#L422 assume !(1 == ~m_pc~0); 19152#L422-2 is_master_triggered_~__retres1~0 := 0; 18897#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18822#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18823#L1065 assume !(0 != activate_threads_~tmp~1); 18577#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18429#L441 assume 1 == ~t1_pc~0; 18430#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 19024#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19411#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 19028#L1073 assume !(0 != activate_threads_~tmp___0~0); 19029#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19374#L460 assume !(1 == ~t2_pc~0); 18392#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 18393#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19157#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 19400#L1081 assume !(0 != activate_threads_~tmp___1~0); 19110#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19074#L479 assume 1 == ~t3_pc~0; 18879#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18880#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19330#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 18790#L1089 assume !(0 != activate_threads_~tmp___2~0); 18432#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18433#L498 assume !(1 == ~t4_pc~0); 18552#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 18877#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18878#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19255#L1097 assume !(0 != activate_threads_~tmp___3~0); 18846#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18847#L517 assume 1 == ~t5_pc~0; 19334#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19335#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18929#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18930#L1105 assume !(0 != activate_threads_~tmp___4~0); 18968#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18969#L536 assume 1 == ~t6_pc~0; 18915#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 18916#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19271#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19413#L1113 assume !(0 != activate_threads_~tmp___5~0); 18663#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18664#L555 assume !(1 == ~t7_pc~0); 19130#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 19188#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18487#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18466#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18467#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18497#L574 assume 1 == ~t8_pc~0; 18498#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19015#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18569#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 18570#L1129 assume !(0 != activate_threads_~tmp___7~0); 18635#L1129-2 assume !(1 == ~M_E~0); 18636#L956-1 assume !(1 == ~T1_E~0); 18652#L961-1 assume !(1 == ~T2_E~0); 19065#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19066#L971-1 assume !(1 == ~T4_E~0); 19191#L976-1 assume !(1 == ~T5_E~0); 19168#L981-1 assume !(1 == ~T6_E~0); 18919#L986-1 assume !(1 == ~T7_E~0); 18699#L991-1 assume !(1 == ~T8_E~0); 18700#L996-1 assume !(1 == ~E_M~0); 19383#L1001-1 assume !(1 == ~E_1~0); 19117#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19118#L1011-1 assume !(1 == ~E_3~0); 19354#L1016-1 assume !(1 == ~E_4~0); 19375#L1021-1 assume !(1 == ~E_5~0); 18421#L1026-1 assume !(1 == ~E_6~0); 18422#L1031-1 assume !(1 == ~E_7~0); 19079#L1036-1 assume !(1 == ~E_8~0); 18874#L1307-1 [2021-11-02 22:20:21,553 INFO L793 eck$LassoCheckResult]: Loop: 18874#L1307-1 assume !false; 18875#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 18490#L833 assume !false; 18491#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 19067#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 19429#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19267#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 19180#L716 assume !(0 != eval_~tmp~0); 19179#L848 start_simulation_~kernel_st~0 := 2; 18872#L594-1 start_simulation_~kernel_st~0 := 3; 18873#L858-2 assume !(0 == ~M_E~0); 19217#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20113#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20112#L868-3 assume !(0 == ~T3_E~0); 20111#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20110#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20109#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20108#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20107#L893-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20106#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20105#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20104#L908-3 assume !(0 == ~E_2~0); 18964#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18492#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18493#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18701#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18702#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19206#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19046#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19047#L422-30 assume 1 == ~m_pc~0; 19001#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 19003#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18673#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18674#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18602#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18603#L441-30 assume 1 == ~t1_pc~0; 18566#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18567#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18726#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 19163#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19164#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19401#L460-30 assume 1 == ~t2_pc~0; 19082#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 19083#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19144#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 18798#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18558#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18559#L479-30 assume 1 == ~t3_pc~0; 19394#L480-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18405#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18406#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 18934#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18935#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18839#L498-30 assume 1 == ~t4_pc~0; 18840#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18911#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18721#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18722#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19194#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19195#L517-30 assume 1 == ~t5_pc~0; 18904#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18905#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19387#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19247#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 18795#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18623#L536-30 assume 1 == ~t6_pc~0; 18539#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 18540#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18909#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19150#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 18796#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18797#L555-30 assume 1 == ~t7_pc~0; 19153#L556-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18687#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19313#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 19297#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19298#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19345#L574-30 assume !(1 == ~t8_pc~0); 18865#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 18866#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18781#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 18782#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18882#L1129-32 assume !(1 == ~M_E~0); 19200#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19045#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18834#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18835#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19096#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18479#L981-3 assume !(1 == ~T6_E~0); 18480#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18464#L991-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18465#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19182#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19281#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19719#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19351#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19352#L1021-3 assume !(1 == ~E_5~0); 19717#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19714#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19712#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19710#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 19643#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 19634#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19632#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 19629#L1326 assume !(0 == start_simulation_~tmp~3); 19318#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18898#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18683#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19405#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 19521#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19256#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 19257#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 19402#L1339 assume !(0 != start_simulation_~tmp___0~1); 18874#L1307-1 [2021-11-02 22:20:21,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,554 INFO L85 PathProgramCache]: Analyzing trace with hash 842829437, now seen corresponding path program 1 times [2021-11-02 22:20:21,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,555 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431206057] [2021-11-02 22:20:21,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,555 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,595 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431206057] [2021-11-02 22:20:21,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431206057] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,595 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:21,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241057072] [2021-11-02 22:20:21,597 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:21,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,597 INFO L85 PathProgramCache]: Analyzing trace with hash -523188897, now seen corresponding path program 1 times [2021-11-02 22:20:21,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,598 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951566487] [2021-11-02 22:20:21,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,642 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951566487] [2021-11-02 22:20:21,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951566487] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,642 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836212631] [2021-11-02 22:20:21,643 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:21,643 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:21,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:21,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:21,644 INFO L87 Difference]: Start difference. First operand 1771 states and 2645 transitions. cyclomatic complexity: 875 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:21,675 INFO L93 Difference]: Finished difference Result 1771 states and 2637 transitions. [2021-11-02 22:20:21,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:21,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2637 transitions. [2021-11-02 22:20:21,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:21,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2637 transitions. [2021-11-02 22:20:21,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2021-11-02 22:20:21,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2021-11-02 22:20:21,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2637 transitions. [2021-11-02 22:20:21,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:21,707 INFO L681 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2021-11-02 22:20:21,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2637 transitions. [2021-11-02 22:20:21,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2021-11-02 22:20:21,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1771 states, 1771 states have (on average 1.4889892715979673) internal successors, (2637), 1770 states have internal predecessors, (2637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2637 transitions. [2021-11-02 22:20:21,751 INFO L704 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2021-11-02 22:20:21,751 INFO L587 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2021-11-02 22:20:21,751 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-02 22:20:21,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2637 transitions. [2021-11-02 22:20:21,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:21,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:21,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:21,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:21,762 INFO L791 eck$LassoCheckResult]: Stem: 22669#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 22670#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 21952#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21953#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 22405#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22406#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22644#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22645#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22500#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22501#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22732#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22188#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22189#L641-1 assume !(0 == ~M_E~0); 22478#L858-1 assume !(0 == ~T1_E~0); 21938#L863-1 assume !(0 == ~T2_E~0); 21939#L868-1 assume !(0 == ~T3_E~0); 22924#L873-1 assume !(0 == ~T4_E~0); 22922#L878-1 assume !(0 == ~T5_E~0); 22904#L883-1 assume !(0 == ~T6_E~0); 22905#L888-1 assume !(0 == ~T7_E~0); 22610#L893-1 assume !(0 == ~T8_E~0); 22611#L898-1 assume !(0 == ~E_M~0); 22935#L903-1 assume !(0 == ~E_1~0); 22903#L908-1 assume !(0 == ~E_2~0); 22744#L913-1 assume !(0 == ~E_3~0); 22017#L918-1 assume !(0 == ~E_4~0); 22018#L923-1 assume !(0 == ~E_5~0); 22752#L928-1 assume !(0 == ~E_6~0); 22132#L933-1 assume 0 == ~E_7~0;~E_7~0 := 1; 22133#L938-1 assume !(0 == ~E_8~0); 22742#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22931#L422 assume !(1 == ~m_pc~0); 22698#L422-2 is_master_triggered_~__retres1~0 := 0; 22447#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22372#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22373#L1065 assume !(0 != activate_threads_~tmp~1); 22127#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21980#L441 assume 1 == ~t1_pc~0; 21981#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22574#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22953#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 22578#L1073 assume !(0 != activate_threads_~tmp___0~0); 22579#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22915#L460 assume !(1 == ~t2_pc~0); 21944#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 21945#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22703#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22943#L1081 assume !(0 != activate_threads_~tmp___1~0); 22657#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22621#L479 assume 1 == ~t3_pc~0; 22428#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22429#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22873#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 22341#L1089 assume !(0 != activate_threads_~tmp___2~0); 21983#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21984#L498 assume !(1 == ~t4_pc~0); 22100#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 22426#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22427#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22799#L1097 assume !(0 != activate_threads_~tmp___3~0); 22395#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22396#L517 assume 1 == ~t5_pc~0; 22879#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22880#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22479#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 22480#L1105 assume !(0 != activate_threads_~tmp___4~0); 22522#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22523#L536 assume 1 == ~t6_pc~0; 22465#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22466#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22815#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 22955#L1113 assume !(0 != activate_threads_~tmp___5~0); 22211#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22212#L555 assume !(1 == ~t7_pc~0); 22678#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 22733#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22038#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 22015#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22016#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22046#L574 assume 1 == ~t8_pc~0; 22047#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 22564#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 22117#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 22118#L1129 assume !(0 != activate_threads_~tmp___7~0); 22184#L1129-2 assume !(1 == ~M_E~0); 22185#L956-1 assume !(1 == ~T1_E~0); 22201#L961-1 assume !(1 == ~T2_E~0); 22612#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22613#L971-1 assume !(1 == ~T4_E~0); 22736#L976-1 assume !(1 == ~T5_E~0); 22714#L981-1 assume !(1 == ~T6_E~0); 22469#L986-1 assume !(1 == ~T7_E~0); 22247#L991-1 assume !(1 == ~T8_E~0); 22248#L996-1 assume !(1 == ~E_M~0); 22925#L1001-1 assume !(1 == ~E_1~0); 22666#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22667#L1011-1 assume !(1 == ~E_3~0); 22899#L1016-1 assume !(1 == ~E_4~0); 22916#L1021-1 assume !(1 == ~E_5~0); 21970#L1026-1 assume !(1 == ~E_6~0); 21971#L1031-1 assume !(1 == ~E_7~0); 22628#L1036-1 assume !(1 == ~E_8~0); 22423#L1307-1 [2021-11-02 22:20:21,762 INFO L793 eck$LassoCheckResult]: Loop: 22423#L1307-1 assume !false; 22424#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 22039#L833 assume !false; 22040#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22614#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22973#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22810#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 22725#L716 assume !(0 != eval_~tmp~0); 22724#L848 start_simulation_~kernel_st~0 := 2; 22421#L594-1 start_simulation_~kernel_st~0 := 3; 22422#L858-2 assume !(0 == ~M_E~0); 22762#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23448#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23446#L868-3 assume !(0 == ~T3_E~0); 23443#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23441#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23439#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23437#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23436#L893-3 assume !(0 == ~T8_E~0); 23435#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23434#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23433#L908-3 assume !(0 == ~E_2~0); 23430#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23428#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23427#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23426#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23425#L933-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23424#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23423#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23422#L422-30 assume !(1 == ~m_pc~0); 23420#L422-32 is_master_triggered_~__retres1~0 := 0; 23419#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23418#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 23417#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23394#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22918#L441-30 assume 1 == ~t1_pc~0; 22114#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22115#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22276#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 22709#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22710#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22942#L460-30 assume 1 == ~t2_pc~0; 22630#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22631#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22690#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22348#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22106#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22107#L479-30 assume !(1 == ~t3_pc~0); 22868#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 21954#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21955#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 22481#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22482#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22388#L498-30 assume 1 == ~t4_pc~0; 22389#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22461#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22271#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22272#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22738#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22739#L517-30 assume 1 == ~t5_pc~0; 22454#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22455#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22932#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 22958#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 23348#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23346#L536-30 assume !(1 == ~t6_pc~0); 23344#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 23341#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23338#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23336#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23335#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23334#L555-30 assume !(1 == ~t7_pc~0); 23332#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 23331#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23330#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23329#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23328#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22888#L574-30 assume 1 == ~t8_pc~0; 22889#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 22415#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 22331#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 22332#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 22431#L1129-32 assume !(1 == ~M_E~0); 22947#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23307#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23304#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23303#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23299#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23298#L981-3 assume !(1 == ~T6_E~0); 23297#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23296#L991-3 assume !(1 == ~T8_E~0); 23295#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23294#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23293#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23292#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23291#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22787#L1021-3 assume !(1 == ~E_5~0); 22539#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22540#L1031-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22722#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22723#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22718#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22289#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22570#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 22333#L1326 assume !(0 == start_simulation_~tmp~3); 22334#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22448#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22231#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22780#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 22671#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 22672#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 22800#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 22944#L1339 assume !(0 != start_simulation_~tmp___0~1); 22423#L1307-1 [2021-11-02 22:20:21,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,763 INFO L85 PathProgramCache]: Analyzing trace with hash -1885379909, now seen corresponding path program 1 times [2021-11-02 22:20:21,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,764 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368159780] [2021-11-02 22:20:21,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,814 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,814 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368159780] [2021-11-02 22:20:21,814 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368159780] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,814 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,814 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:21,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630429942] [2021-11-02 22:20:21,815 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:21,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:21,815 INFO L85 PathProgramCache]: Analyzing trace with hash -1567985728, now seen corresponding path program 1 times [2021-11-02 22:20:21,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:21,816 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508552515] [2021-11-02 22:20:21,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:21,816 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:21,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:21,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:21,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:21,884 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508552515] [2021-11-02 22:20:21,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508552515] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:21,884 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:21,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:21,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729317097] [2021-11-02 22:20:21,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:21,885 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:21,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:21,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:21,886 INFO L87 Difference]: Start difference. First operand 1771 states and 2637 transitions. cyclomatic complexity: 867 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:21,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:21,953 INFO L93 Difference]: Finished difference Result 1771 states and 2609 transitions. [2021-11-02 22:20:21,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:21,954 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2609 transitions. [2021-11-02 22:20:21,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:21,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2609 transitions. [2021-11-02 22:20:21,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2021-11-02 22:20:21,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2021-11-02 22:20:21,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2609 transitions. [2021-11-02 22:20:21,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:21,987 INFO L681 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2021-11-02 22:20:21,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2609 transitions. [2021-11-02 22:20:22,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2021-11-02 22:20:22,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1771 states, 1771 states have (on average 1.4731789949181253) internal successors, (2609), 1770 states have internal predecessors, (2609), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:22,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2609 transitions. [2021-11-02 22:20:22,032 INFO L704 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2021-11-02 22:20:22,032 INFO L587 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2021-11-02 22:20:22,032 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-02 22:20:22,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2609 transitions. [2021-11-02 22:20:22,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2021-11-02 22:20:22,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:22,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:22,043 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:22,043 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:22,044 INFO L791 eck$LassoCheckResult]: Stem: 26214#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 26215#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25501#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25502#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 25950#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25951#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26189#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26190#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26045#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26046#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26276#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25736#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25737#L641-1 assume !(0 == ~M_E~0); 26023#L858-1 assume !(0 == ~T1_E~0); 25487#L863-1 assume !(0 == ~T2_E~0); 25488#L868-1 assume !(0 == ~T3_E~0); 26457#L873-1 assume !(0 == ~T4_E~0); 26455#L878-1 assume !(0 == ~T5_E~0); 26437#L883-1 assume !(0 == ~T6_E~0); 26438#L888-1 assume !(0 == ~T7_E~0); 26157#L893-1 assume !(0 == ~T8_E~0); 26158#L898-1 assume !(0 == ~E_M~0); 26467#L903-1 assume !(0 == ~E_1~0); 26436#L908-1 assume !(0 == ~E_2~0); 26288#L913-1 assume !(0 == ~E_3~0); 25564#L918-1 assume !(0 == ~E_4~0); 25565#L923-1 assume !(0 == ~E_5~0); 26296#L928-1 assume !(0 == ~E_6~0); 25680#L933-1 assume !(0 == ~E_7~0); 25681#L938-1 assume !(0 == ~E_8~0); 26286#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26463#L422 assume !(1 == ~m_pc~0); 26243#L422-2 is_master_triggered_~__retres1~0 := 0; 25991#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25917#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25918#L1065 assume !(0 != activate_threads_~tmp~1); 25675#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25528#L441 assume 1 == ~t1_pc~0; 25529#L442 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26120#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26484#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26125#L1073 assume !(0 != activate_threads_~tmp___0~0); 26126#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26449#L460 assume !(1 == ~t2_pc~0); 25493#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 25494#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26248#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26475#L1081 assume !(0 != activate_threads_~tmp___1~0); 26202#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26168#L479 assume 1 == ~t3_pc~0; 25973#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25974#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26413#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 25885#L1089 assume !(0 != activate_threads_~tmp___2~0); 25531#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25532#L498 assume !(1 == ~t4_pc~0); 25648#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 25971#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25972#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 26345#L1097 assume !(0 != activate_threads_~tmp___3~0); 25940#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25941#L517 assume 1 == ~t5_pc~0; 26417#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26418#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26024#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 26025#L1105 assume !(0 != activate_threads_~tmp___4~0); 26068#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26069#L536 assume 1 == ~t6_pc~0; 26010#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 26011#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26362#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26487#L1113 assume !(0 != activate_threads_~tmp___5~0); 25758#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25759#L555 assume !(1 == ~t7_pc~0); 26223#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 26277#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 25585#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25562#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25563#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25594#L574 assume 1 == ~t8_pc~0; 25595#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26110#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25665#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25666#L1129 assume !(0 != activate_threads_~tmp___7~0); 25732#L1129-2 assume !(1 == ~M_E~0); 25733#L956-1 assume !(1 == ~T1_E~0); 25749#L961-1 assume !(1 == ~T2_E~0); 26159#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26160#L971-1 assume !(1 == ~T4_E~0); 26280#L976-1 assume !(1 == ~T5_E~0); 26259#L981-1 assume !(1 == ~T6_E~0); 26014#L986-1 assume !(1 == ~T7_E~0); 25793#L991-1 assume !(1 == ~T8_E~0); 25794#L996-1 assume !(1 == ~E_M~0); 26458#L1001-1 assume !(1 == ~E_1~0); 26211#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26212#L1011-1 assume !(1 == ~E_3~0); 26433#L1016-1 assume !(1 == ~E_4~0); 26450#L1021-1 assume !(1 == ~E_5~0); 25518#L1026-1 assume !(1 == ~E_6~0); 25519#L1031-1 assume !(1 == ~E_7~0); 26173#L1036-1 assume !(1 == ~E_8~0); 25968#L1307-1 [2021-11-02 22:20:22,044 INFO L793 eck$LassoCheckResult]: Loop: 25968#L1307-1 assume !false; 25969#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 25586#L833 assume !false; 25587#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26161#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26501#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26357#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 26270#L716 assume !(0 != eval_~tmp~0); 26269#L848 start_simulation_~kernel_st~0 := 2; 25966#L594-1 start_simulation_~kernel_st~0 := 3; 25967#L858-2 assume !(0 == ~M_E~0); 26306#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27144#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27142#L868-3 assume !(0 == ~T3_E~0); 27140#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27137#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27135#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27133#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27131#L893-3 assume !(0 == ~T8_E~0); 27129#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27127#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27124#L908-3 assume !(0 == ~E_2~0); 27123#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27122#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27121#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26949#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26948#L933-3 assume !(0 == ~E_7~0); 26947#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26946#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26945#L422-30 assume 1 == ~m_pc~0; 26944#L423-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 26942#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26941#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 26940#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26939#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26938#L441-30 assume 1 == ~t1_pc~0; 26936#L442-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26935#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26934#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26933#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26932#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26931#L460-30 assume !(1 == ~t2_pc~0); 26929#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 26928#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26927#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26926#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26925#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26924#L479-30 assume 1 == ~t3_pc~0; 26922#L480-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 26921#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26920#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 26919#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26918#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26917#L498-30 assume 1 == ~t4_pc~0; 26005#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26006#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25815#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25816#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 26283#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26284#L517-30 assume !(1 == ~t5_pc~0); 26000#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 25999#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26464#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 26337#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 25889#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25719#L536-30 assume 1 == ~t6_pc~0; 25635#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25636#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26003#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26241#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25890#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25891#L555-30 assume !(1 == ~t7_pc~0); 25781#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 25782#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26399#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 26384#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 26385#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 26426#L574-30 assume !(1 == ~t8_pc~0); 25959#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 25960#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25875#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25876#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25976#L1129-32 assume !(1 == ~M_E~0); 26289#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26139#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25928#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25929#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26188#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25575#L981-3 assume !(1 == ~T6_E~0); 25576#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25560#L991-3 assume !(1 == ~T8_E~0); 25561#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26271#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25898#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25899#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26292#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26333#L1021-3 assume !(1 == ~E_5~0); 26085#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26086#L1031-3 assume !(1 == ~E_7~0); 26267#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26268#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26263#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 25833#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26116#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 25877#L1326 assume !(0 == start_simulation_~tmp~3); 25878#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26548#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26539#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26538#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 26537#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 26346#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 26347#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 26476#L1339 assume !(0 != start_simulation_~tmp___0~1); 25968#L1307-1 [2021-11-02 22:20:22,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:22,045 INFO L85 PathProgramCache]: Analyzing trace with hash -998157063, now seen corresponding path program 1 times [2021-11-02 22:20:22,045 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:22,046 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027233706] [2021-11-02 22:20:22,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:22,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:22,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:22,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:22,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:22,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027233706] [2021-11-02 22:20:22,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027233706] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:22,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:22,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:22,097 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256009635] [2021-11-02 22:20:22,097 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:22,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:22,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1086543292, now seen corresponding path program 1 times [2021-11-02 22:20:22,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:22,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592022269] [2021-11-02 22:20:22,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:22,098 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:22,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:22,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:22,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:22,133 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592022269] [2021-11-02 22:20:22,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592022269] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:22,133 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:22,133 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:22,133 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434149811] [2021-11-02 22:20:22,134 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:22,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:22,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:20:22,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:20:22,137 INFO L87 Difference]: Start difference. First operand 1771 states and 2609 transitions. cyclomatic complexity: 839 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:22,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:22,420 INFO L93 Difference]: Finished difference Result 4872 states and 7078 transitions. [2021-11-02 22:20:22,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:20:22,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4872 states and 7078 transitions. [2021-11-02 22:20:22,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4625 [2021-11-02 22:20:22,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4872 states to 4872 states and 7078 transitions. [2021-11-02 22:20:22,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4872 [2021-11-02 22:20:22,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4872 [2021-11-02 22:20:22,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4872 states and 7078 transitions. [2021-11-02 22:20:22,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:22,523 INFO L681 BuchiCegarLoop]: Abstraction has 4872 states and 7078 transitions. [2021-11-02 22:20:22,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4872 states and 7078 transitions. [2021-11-02 22:20:22,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4872 to 4632. [2021-11-02 22:20:22,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4632 states, 4632 states have (on average 1.4572538860103628) internal successors, (6750), 4631 states have internal predecessors, (6750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:22,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4632 states to 4632 states and 6750 transitions. [2021-11-02 22:20:22,689 INFO L704 BuchiCegarLoop]: Abstraction has 4632 states and 6750 transitions. [2021-11-02 22:20:22,690 INFO L587 BuchiCegarLoop]: Abstraction has 4632 states and 6750 transitions. [2021-11-02 22:20:22,690 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-02 22:20:22,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4632 states and 6750 transitions. [2021-11-02 22:20:22,711 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4513 [2021-11-02 22:20:22,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:22,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:22,714 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:22,714 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:22,714 INFO L791 eck$LassoCheckResult]: Stem: 32890#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 32891#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 32154#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32155#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 32607#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32608#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32862#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32863#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32697#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32698#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32953#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32394#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32395#L641-1 assume !(0 == ~M_E~0); 32682#L858-1 assume !(0 == ~T1_E~0); 32140#L863-1 assume !(0 == ~T2_E~0); 32141#L868-1 assume !(0 == ~T3_E~0); 33157#L873-1 assume !(0 == ~T4_E~0); 33155#L878-1 assume !(0 == ~T5_E~0); 33133#L883-1 assume !(0 == ~T6_E~0); 33134#L888-1 assume !(0 == ~T7_E~0); 32823#L893-1 assume !(0 == ~T8_E~0); 32824#L898-1 assume !(0 == ~E_M~0); 33169#L903-1 assume !(0 == ~E_1~0); 33132#L908-1 assume !(0 == ~E_2~0); 32966#L913-1 assume !(0 == ~E_3~0); 32215#L918-1 assume !(0 == ~E_4~0); 32216#L923-1 assume !(0 == ~E_5~0); 32976#L928-1 assume !(0 == ~E_6~0); 32331#L933-1 assume !(0 == ~E_7~0); 32332#L938-1 assume !(0 == ~E_8~0); 32964#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33165#L422 assume !(1 == ~m_pc~0); 33098#L422-2 is_master_triggered_~__retres1~0 := 0; 32652#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32575#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32576#L1065 assume !(0 != activate_threads_~tmp~1); 32324#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32178#L441 assume !(1 == ~t1_pc~0); 32179#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 33159#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33201#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32779#L1073 assume !(0 != activate_threads_~tmp___0~0); 32780#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33149#L460 assume !(1 == ~t2_pc~0); 32143#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 32144#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32923#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 33178#L1081 assume !(0 != activate_threads_~tmp___1~0); 32876#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32834#L479 assume 1 == ~t3_pc~0; 32632#L480 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32633#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33102#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32543#L1089 assume !(0 != activate_threads_~tmp___2~0); 32180#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32181#L498 assume !(1 == ~t4_pc~0); 32300#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 32630#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32631#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33027#L1097 assume !(0 != activate_threads_~tmp___3~0); 32599#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32600#L517 assume 1 == ~t5_pc~0; 33105#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 33106#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32683#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32684#L1105 assume !(0 != activate_threads_~tmp___4~0); 32722#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32723#L536 assume 1 == ~t6_pc~0; 32669#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32670#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33044#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 33211#L1113 assume !(0 != activate_threads_~tmp___5~0); 32416#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32417#L555 assume !(1 == ~t7_pc~0); 32897#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 32954#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32234#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32213#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32214#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32245#L574 assume 1 == ~t8_pc~0; 32246#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32768#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32317#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32318#L1129 assume !(0 != activate_threads_~tmp___7~0); 32387#L1129-2 assume !(1 == ~M_E~0); 32388#L956-1 assume !(1 == ~T1_E~0); 32406#L961-1 assume !(1 == ~T2_E~0); 32825#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32826#L971-1 assume !(1 == ~T4_E~0); 32957#L976-1 assume !(1 == ~T5_E~0); 32934#L981-1 assume !(1 == ~T6_E~0); 32673#L986-1 assume !(1 == ~T7_E~0); 32451#L991-1 assume !(1 == ~T8_E~0); 32452#L996-1 assume !(1 == ~E_M~0); 33160#L1001-1 assume !(1 == ~E_1~0); 32885#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32886#L1011-1 assume !(1 == ~E_3~0); 33128#L1016-1 assume !(1 == ~E_4~0); 33150#L1021-1 assume !(1 == ~E_5~0); 32171#L1026-1 assume !(1 == ~E_6~0); 32172#L1031-1 assume !(1 == ~E_7~0); 32840#L1036-1 assume !(1 == ~E_8~0); 32627#L1307-1 [2021-11-02 22:20:22,715 INFO L793 eck$LassoCheckResult]: Loop: 32627#L1307-1 assume !false; 32628#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 32806#L833 assume !false; 32827#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 32828#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 36022#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 33040#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 32946#L716 assume !(0 != eval_~tmp~0); 32945#L848 start_simulation_~kernel_st~0 := 2; 32625#L594-1 start_simulation_~kernel_st~0 := 3; 32626#L858-2 assume !(0 == ~M_E~0); 32987#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32921#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32910#L868-3 assume !(0 == ~T3_E~0); 32911#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32468#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32194#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32195#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32196#L893-3 assume !(0 == ~T8_E~0); 32197#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32707#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33046#L908-3 assume !(0 == ~E_2~0); 32718#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32239#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32240#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32453#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32454#L933-3 assume !(0 == ~E_7~0); 32975#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32799#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32800#L422-30 assume !(1 == ~m_pc~0); 32816#L422-32 is_master_triggered_~__retres1~0 := 0; 32817#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32424#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32425#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 32349#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32350#L441-30 assume !(1 == ~t1_pc~0); 33047#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 32478#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32479#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32929#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32930#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33179#L460-30 assume !(1 == ~t2_pc~0); 32848#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 32847#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32912#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32551#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32306#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32307#L479-30 assume 1 == ~t3_pc~0; 33174#L480-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32156#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32157#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32687#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32688#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32592#L498-30 assume 1 == ~t4_pc~0; 32593#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32666#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32473#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32474#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36606#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36604#L517-30 assume 1 == ~t5_pc~0; 36601#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36600#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36599#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36598#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 36597#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36596#L536-30 assume !(1 == ~t6_pc~0); 32289#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 32288#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32664#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32918#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32549#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32550#L555-30 assume !(1 == ~t7_pc~0); 32438#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 32439#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33085#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 36586#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 36584#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 33115#L574-30 assume !(1 == ~t8_pc~0); 32618#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 32619#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36576#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 36529#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 33185#L1129-32 assume !(1 == ~M_E~0); 33186#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32798#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32587#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32588#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32861#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32226#L981-3 assume !(1 == ~T6_E~0); 32227#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32211#L991-3 assume !(1 == ~T8_E~0); 32212#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33055#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32557#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32558#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33124#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33125#L1021-3 assume !(1 == ~E_5~0); 32743#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32744#L1031-3 assume !(1 == ~E_7~0); 33180#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36506#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 36504#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32774#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 32775#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 32536#L1326 assume !(0 == start_simulation_~tmp~3); 32537#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 32653#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32436#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 33003#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 32892#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 32893#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 33030#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 33181#L1339 assume !(0 != start_simulation_~tmp___0~1); 32627#L1307-1 [2021-11-02 22:20:22,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:22,716 INFO L85 PathProgramCache]: Analyzing trace with hash -620514246, now seen corresponding path program 1 times [2021-11-02 22:20:22,716 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:22,716 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170392136] [2021-11-02 22:20:22,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:22,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:22,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:22,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:22,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:22,751 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170392136] [2021-11-02 22:20:22,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170392136] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:22,751 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:22,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:22,752 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219658042] [2021-11-02 22:20:22,752 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:22,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:22,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1488568574, now seen corresponding path program 1 times [2021-11-02 22:20:22,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:22,753 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716103888] [2021-11-02 22:20:22,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:22,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:22,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:22,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:22,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:22,787 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716103888] [2021-11-02 22:20:22,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716103888] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:22,787 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:22,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:22,787 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137876861] [2021-11-02 22:20:22,788 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:22,788 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:22,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:20:22,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:20:22,789 INFO L87 Difference]: Start difference. First operand 4632 states and 6750 transitions. cyclomatic complexity: 2120 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:23,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:23,081 INFO L93 Difference]: Finished difference Result 12999 states and 18739 transitions. [2021-11-02 22:20:23,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:20:23,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12999 states and 18739 transitions. [2021-11-02 22:20:23,285 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12579 [2021-11-02 22:20:23,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12999 states to 12999 states and 18739 transitions. [2021-11-02 22:20:23,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12999 [2021-11-02 22:20:23,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12999 [2021-11-02 22:20:23,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12999 states and 18739 transitions. [2021-11-02 22:20:23,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:23,389 INFO L681 BuchiCegarLoop]: Abstraction has 12999 states and 18739 transitions. [2021-11-02 22:20:23,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12999 states and 18739 transitions. [2021-11-02 22:20:23,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12999 to 12465. [2021-11-02 22:20:23,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12465 states, 12465 states have (on average 1.445728038507822) internal successors, (18021), 12464 states have internal predecessors, (18021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:23,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12465 states to 12465 states and 18021 transitions. [2021-11-02 22:20:23,773 INFO L704 BuchiCegarLoop]: Abstraction has 12465 states and 18021 transitions. [2021-11-02 22:20:23,773 INFO L587 BuchiCegarLoop]: Abstraction has 12465 states and 18021 transitions. [2021-11-02 22:20:23,773 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-02 22:20:23,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12465 states and 18021 transitions. [2021-11-02 22:20:23,838 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12327 [2021-11-02 22:20:23,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:23,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:23,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:23,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:23,841 INFO L791 eck$LassoCheckResult]: Stem: 50569#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 50570#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 49794#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49795#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 50258#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50259#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50533#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50534#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50352#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50353#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50644#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50032#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50033#L641-1 assume !(0 == ~M_E~0); 50337#L858-1 assume !(0 == ~T1_E~0); 49781#L863-1 assume !(0 == ~T2_E~0); 49782#L868-1 assume !(0 == ~T3_E~0); 50908#L873-1 assume !(0 == ~T4_E~0); 50905#L878-1 assume !(0 == ~T5_E~0); 50881#L883-1 assume !(0 == ~T6_E~0); 50882#L888-1 assume !(0 == ~T7_E~0); 50490#L893-1 assume !(0 == ~T8_E~0); 50491#L898-1 assume !(0 == ~E_M~0); 50926#L903-1 assume !(0 == ~E_1~0); 50880#L908-1 assume !(0 == ~E_2~0); 50659#L913-1 assume !(0 == ~E_3~0); 49855#L918-1 assume !(0 == ~E_4~0); 49856#L923-1 assume !(0 == ~E_5~0); 50670#L928-1 assume !(0 == ~E_6~0); 49971#L933-1 assume !(0 == ~E_7~0); 49972#L938-1 assume !(0 == ~E_8~0); 50656#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50920#L422 assume !(1 == ~m_pc~0); 50822#L422-2 is_master_triggered_~__retres1~0 := 0; 50302#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50224#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 50225#L1065 assume !(0 != activate_threads_~tmp~1); 49964#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49818#L441 assume !(1 == ~t1_pc~0); 49819#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 50912#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50969#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 50443#L1073 assume !(0 != activate_threads_~tmp___0~0); 50444#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50898#L460 assume !(1 == ~t2_pc~0); 49784#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 49785#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50610#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 50944#L1081 assume !(0 != activate_threads_~tmp___1~0); 50552#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50502#L479 assume !(1 == ~t3_pc~0); 50441#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 50442#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50835#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 50190#L1089 assume !(0 != activate_threads_~tmp___2~0); 49820#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49821#L498 assume !(1 == ~t4_pc~0); 49939#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 50282#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50283#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 50729#L1097 assume !(0 != activate_threads_~tmp___3~0); 50250#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50251#L517 assume 1 == ~t5_pc~0; 50839#L518 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 50840#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50338#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 50339#L1105 assume !(0 != activate_threads_~tmp___4~0); 50376#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50377#L536 assume 1 == ~t6_pc~0; 50323#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 50324#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 50752#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50987#L1113 assume !(0 != activate_threads_~tmp___5~0); 50058#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50059#L555 assume !(1 == ~t7_pc~0); 50578#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 50645#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 49874#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 49853#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49854#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49885#L574 assume 1 == ~t8_pc~0; 49886#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 50427#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49957#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49958#L1129 assume !(0 != activate_threads_~tmp___7~0); 50025#L1129-2 assume !(1 == ~M_E~0); 50026#L956-1 assume !(1 == ~T1_E~0); 50047#L961-1 assume !(1 == ~T2_E~0); 50492#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50493#L971-1 assume !(1 == ~T4_E~0); 50648#L976-1 assume !(1 == ~T5_E~0); 50623#L981-1 assume !(1 == ~T6_E~0); 50328#L986-1 assume !(1 == ~T7_E~0); 50092#L991-1 assume !(1 == ~T8_E~0); 50093#L996-1 assume !(1 == ~E_M~0); 50913#L1001-1 assume !(1 == ~E_1~0); 50562#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50563#L1011-1 assume !(1 == ~E_3~0); 50866#L1016-1 assume !(1 == ~E_4~0); 50899#L1021-1 assume !(1 == ~E_5~0); 49811#L1026-1 assume !(1 == ~E_6~0); 49812#L1031-1 assume !(1 == ~E_7~0); 50508#L1036-1 assume !(1 == ~E_8~0); 50279#L1307-1 [2021-11-02 22:20:23,841 INFO L793 eck$LassoCheckResult]: Loop: 50279#L1307-1 assume !false; 50280#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 49877#L833 assume !false; 49878#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 50699#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 50054#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 51019#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 50635#L716 assume !(0 != eval_~tmp~0); 50637#L848 start_simulation_~kernel_st~0 := 2; 62023#L594-1 start_simulation_~kernel_st~0 := 3; 50681#L858-2 assume !(0 == ~M_E~0); 50682#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50607#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50591#L868-3 assume !(0 == ~T3_E~0); 50592#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50111#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49834#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49835#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49836#L893-3 assume !(0 == ~T8_E~0); 49837#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50360#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50754#L908-3 assume !(0 == ~E_2~0); 50371#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49879#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49880#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50094#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50095#L933-3 assume !(0 == ~E_7~0); 50669#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50465#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50466#L422-30 assume !(1 == ~m_pc~0); 61938#L422-32 is_master_triggered_~__retres1~0 := 0; 61936#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61934#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 61932#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 61930#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61928#L441-30 assume !(1 == ~t1_pc~0); 61926#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 61924#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61922#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 61920#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 61858#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61857#L460-30 assume !(1 == ~t2_pc~0); 61854#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 61852#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61497#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 61496#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 61494#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61493#L479-30 assume !(1 == ~t3_pc~0); 61492#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 61491#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61490#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 61489#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 61487#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61485#L498-30 assume !(1 == ~t4_pc~0); 61482#L498-32 is_transmit4_triggered_~__retres1~4 := 0; 61481#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61480#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 61479#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 61478#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50938#L517-30 assume 1 == ~t5_pc~0; 50309#L518-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 50310#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50921#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 50721#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 50195#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50196#L536-30 assume 1 == ~t6_pc~0; 61461#L537-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 50314#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 50315#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50600#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 50197#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50198#L555-30 assume !(1 == ~t7_pc~0); 61452#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 60741#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 60742#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50783#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 50784#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 50850#L574-30 assume 1 == ~t8_pc~0; 50851#L575-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 50711#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 50180#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50181#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 50286#L1129-32 assume !(1 == ~M_E~0); 50955#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50464#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50237#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50238#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50532#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49866#L981-3 assume !(1 == ~T6_E~0); 49867#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49851#L991-3 assume !(1 == ~T8_E~0); 49852#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50766#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50767#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50665#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50666#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50712#L1021-3 assume !(1 == ~E_5~0); 50713#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50948#L1031-3 assume !(1 == ~E_7~0); 50949#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50991#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 50992#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 61287#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 51008#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 50182#L1326 assume !(0 == start_simulation_~tmp~3); 50183#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 50807#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 61142#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 61141#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 61140#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 61139#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 61138#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 61137#L1339 assume !(0 != start_simulation_~tmp___0~1); 50279#L1307-1 [2021-11-02 22:20:23,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:23,842 INFO L85 PathProgramCache]: Analyzing trace with hash -894292741, now seen corresponding path program 1 times [2021-11-02 22:20:23,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:23,842 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642702450] [2021-11-02 22:20:23,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:23,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:23,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:23,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:23,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:23,883 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642702450] [2021-11-02 22:20:23,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642702450] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:23,884 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:23,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:23,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766913582] [2021-11-02 22:20:23,885 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:23,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:23,885 INFO L85 PathProgramCache]: Analyzing trace with hash 53921858, now seen corresponding path program 1 times [2021-11-02 22:20:23,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:23,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133393082] [2021-11-02 22:20:23,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:23,887 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:23,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:23,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:23,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:23,928 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133393082] [2021-11-02 22:20:23,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133393082] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:23,929 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:23,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:23,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153580758] [2021-11-02 22:20:23,930 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:23,930 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:23,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:20:23,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:20:23,933 INFO L87 Difference]: Start difference. First operand 12465 states and 18021 transitions. cyclomatic complexity: 5560 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:24,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:24,466 INFO L93 Difference]: Finished difference Result 35020 states and 50186 transitions. [2021-11-02 22:20:24,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:20:24,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35020 states and 50186 transitions. [2021-11-02 22:20:24,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 34239 [2021-11-02 22:20:24,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35020 states to 35020 states and 50186 transitions. [2021-11-02 22:20:24,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35020 [2021-11-02 22:20:24,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35020 [2021-11-02 22:20:24,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35020 states and 50186 transitions. [2021-11-02 22:20:24,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:24,954 INFO L681 BuchiCegarLoop]: Abstraction has 35020 states and 50186 transitions. [2021-11-02 22:20:24,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35020 states and 50186 transitions. [2021-11-02 22:20:25,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35020 to 33912. [2021-11-02 22:20:25,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33912 states, 33912 states have (on average 1.436836518046709) internal successors, (48726), 33911 states have internal predecessors, (48726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:25,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33912 states to 33912 states and 48726 transitions. [2021-11-02 22:20:25,841 INFO L704 BuchiCegarLoop]: Abstraction has 33912 states and 48726 transitions. [2021-11-02 22:20:25,841 INFO L587 BuchiCegarLoop]: Abstraction has 33912 states and 48726 transitions. [2021-11-02 22:20:25,841 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-02 22:20:25,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33912 states and 48726 transitions. [2021-11-02 22:20:26,030 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 33735 [2021-11-02 22:20:26,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:26,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:26,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:26,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:26,034 INFO L791 eck$LassoCheckResult]: Stem: 98034#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 98035#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 97289#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97290#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 97747#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97748#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98003#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98004#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97840#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97841#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98105#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97527#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97528#L641-1 assume !(0 == ~M_E~0); 97819#L858-1 assume !(0 == ~T1_E~0); 97276#L863-1 assume !(0 == ~T2_E~0); 97277#L868-1 assume !(0 == ~T3_E~0); 98332#L873-1 assume !(0 == ~T4_E~0); 98330#L878-1 assume !(0 == ~T5_E~0); 98307#L883-1 assume !(0 == ~T6_E~0); 98308#L888-1 assume !(0 == ~T7_E~0); 97962#L893-1 assume !(0 == ~T8_E~0); 97963#L898-1 assume !(0 == ~E_M~0); 98347#L903-1 assume !(0 == ~E_1~0); 98306#L908-1 assume !(0 == ~E_2~0); 98118#L913-1 assume !(0 == ~E_3~0); 97350#L918-1 assume !(0 == ~E_4~0); 97351#L923-1 assume !(0 == ~E_5~0); 98129#L928-1 assume !(0 == ~E_6~0); 97467#L933-1 assume !(0 == ~E_7~0); 97468#L938-1 assume !(0 == ~E_8~0); 98116#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98339#L422 assume !(1 == ~m_pc~0); 98260#L422-2 is_master_triggered_~__retres1~0 := 0; 97787#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97713#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 97714#L1065 assume !(0 != activate_threads_~tmp~1); 97462#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97315#L441 assume !(1 == ~t1_pc~0); 97316#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 98334#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98402#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97923#L1073 assume !(0 != activate_threads_~tmp___0~0); 97924#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98320#L460 assume !(1 == ~t2_pc~0); 97281#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 97282#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98073#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 98375#L1081 assume !(0 != activate_threads_~tmp___1~0); 98017#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97973#L479 assume !(1 == ~t3_pc~0); 97918#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 97919#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98266#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 97681#L1089 assume !(0 != activate_threads_~tmp___2~0); 97317#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97318#L498 assume !(1 == ~t4_pc~0); 97434#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 97768#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97769#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 98180#L1097 assume !(0 != activate_threads_~tmp___3~0); 97737#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97738#L517 assume !(1 == ~t5_pc~0); 98400#L517-2 is_transmit5_triggered_~__retres1~5 := 0; 98401#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97820#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 97821#L1105 assume !(0 != activate_threads_~tmp___4~0); 97862#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 97863#L536 assume 1 == ~t6_pc~0; 97805#L537 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 97806#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 98203#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 98412#L1113 assume !(0 != activate_threads_~tmp___5~0); 97552#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97553#L555 assume !(1 == ~t7_pc~0); 98044#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 98106#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 97371#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 97348#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 97349#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 97380#L574 assume 1 == ~t8_pc~0; 97381#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 97905#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 97453#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 97454#L1129 assume !(0 != activate_threads_~tmp___7~0); 97523#L1129-2 assume !(1 == ~M_E~0); 97524#L956-1 assume !(1 == ~T1_E~0); 97540#L961-1 assume !(1 == ~T2_E~0); 97964#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97965#L971-1 assume !(1 == ~T4_E~0); 98109#L976-1 assume !(1 == ~T5_E~0); 98087#L981-1 assume !(1 == ~T6_E~0); 97810#L986-1 assume !(1 == ~T7_E~0); 97586#L991-1 assume !(1 == ~T8_E~0); 97587#L996-1 assume !(1 == ~E_M~0); 98335#L1001-1 assume !(1 == ~E_1~0); 98029#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 98030#L1011-1 assume !(1 == ~E_3~0); 98291#L1016-1 assume !(1 == ~E_4~0); 98321#L1021-1 assume !(1 == ~E_5~0); 97306#L1026-1 assume !(1 == ~E_6~0); 97307#L1031-1 assume !(1 == ~E_7~0); 97979#L1036-1 assume !(1 == ~E_8~0); 97980#L1307-1 [2021-11-02 22:20:26,035 INFO L793 eck$LassoCheckResult]: Loop: 97980#L1307-1 assume !false; 119385#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 117098#L833 assume !false; 117099#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 117092#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 117081#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 117078#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 117074#L716 assume !(0 != eval_~tmp~0); 117075#L848 start_simulation_~kernel_st~0 := 2; 119632#L594-1 start_simulation_~kernel_st~0 := 3; 119630#L858-2 assume !(0 == ~M_E~0); 119628#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119626#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 119624#L868-3 assume !(0 == ~T3_E~0); 119622#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119620#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119618#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119616#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119614#L893-3 assume !(0 == ~T8_E~0); 119612#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119610#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119608#L908-3 assume !(0 == ~E_2~0); 119606#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119604#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119602#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119600#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 119598#L933-3 assume !(0 == ~E_7~0); 119596#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119594#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119592#L422-30 assume !(1 == ~m_pc~0); 119590#L422-32 is_master_triggered_~__retres1~0 := 0; 119588#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 119586#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 119584#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 119582#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 119580#L441-30 assume !(1 == ~t1_pc~0); 119578#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 119576#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119574#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 119572#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 119570#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 119568#L460-30 assume 1 == ~t2_pc~0; 119565#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 119562#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 119560#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 119558#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 119556#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 119554#L479-30 assume !(1 == ~t3_pc~0); 119552#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 119550#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119548#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 119546#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 119544#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119542#L498-30 assume 1 == ~t4_pc~0; 119539#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 119536#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 119534#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 119532#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 119530#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 119528#L517-30 assume !(1 == ~t5_pc~0); 119526#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 119524#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 119522#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 119520#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 119518#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 119516#L536-30 assume !(1 == ~t6_pc~0); 119513#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 119510#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 119508#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 119506#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 119504#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 119501#L555-30 assume !(1 == ~t7_pc~0); 119498#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 119496#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 119494#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 119492#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 119490#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 119488#L574-30 assume !(1 == ~t8_pc~0); 119485#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 119482#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 119480#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 119478#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 119477#L1129-32 assume !(1 == ~M_E~0); 119474#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119473#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119472#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119470#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119468#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119466#L981-3 assume !(1 == ~T6_E~0); 119464#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 119462#L991-3 assume !(1 == ~T8_E~0); 119459#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119457#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119455#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119453#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119451#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119449#L1021-3 assume !(1 == ~E_5~0); 119448#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119446#L1031-3 assume !(1 == ~E_7~0); 119444#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 119442#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 119434#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 119425#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 119423#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 119419#L1326 assume !(0 == start_simulation_~tmp~3); 119416#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 119414#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 119406#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 119399#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 119400#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 119393#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 119394#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 119387#L1339 assume !(0 != start_simulation_~tmp___0~1); 97980#L1307-1 [2021-11-02 22:20:26,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:26,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1379467460, now seen corresponding path program 1 times [2021-11-02 22:20:26,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:26,037 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173732827] [2021-11-02 22:20:26,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:26,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:26,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:26,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:26,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:26,110 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173732827] [2021-11-02 22:20:26,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173732827] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:26,110 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:26,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:26,111 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878795755] [2021-11-02 22:20:26,111 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:26,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:26,112 INFO L85 PathProgramCache]: Analyzing trace with hash -2078326367, now seen corresponding path program 1 times [2021-11-02 22:20:26,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:26,112 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109745979] [2021-11-02 22:20:26,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:26,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:26,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:26,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:26,201 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:26,202 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109745979] [2021-11-02 22:20:26,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109745979] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:26,203 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:26,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:26,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50106556] [2021-11-02 22:20:26,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:26,204 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:26,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:20:26,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:20:26,205 INFO L87 Difference]: Start difference. First operand 33912 states and 48726 transitions. cyclomatic complexity: 14822 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:27,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:27,183 INFO L93 Difference]: Finished difference Result 94969 states and 135445 transitions. [2021-11-02 22:20:27,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:20:27,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94969 states and 135445 transitions. [2021-11-02 22:20:27,763 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 93421 [2021-11-02 22:20:28,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94969 states to 94969 states and 135445 transitions. [2021-11-02 22:20:28,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94969 [2021-11-02 22:20:28,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94969 [2021-11-02 22:20:28,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94969 states and 135445 transitions. [2021-11-02 22:20:28,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:28,401 INFO L681 BuchiCegarLoop]: Abstraction has 94969 states and 135445 transitions. [2021-11-02 22:20:28,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94969 states and 135445 transitions. [2021-11-02 22:20:29,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94969 to 92543. [2021-11-02 22:20:29,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92543 states, 92543 states have (on average 1.4291194363701198) internal successors, (132255), 92542 states have internal predecessors, (132255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:30,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92543 states to 92543 states and 132255 transitions. [2021-11-02 22:20:30,206 INFO L704 BuchiCegarLoop]: Abstraction has 92543 states and 132255 transitions. [2021-11-02 22:20:30,206 INFO L587 BuchiCegarLoop]: Abstraction has 92543 states and 132255 transitions. [2021-11-02 22:20:30,206 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-02 22:20:30,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92543 states and 132255 transitions. [2021-11-02 22:20:30,625 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 92287 [2021-11-02 22:20:30,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:30,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:30,627 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:30,627 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:30,628 INFO L791 eck$LassoCheckResult]: Stem: 226945#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 226946#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 226180#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 226181#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 226644#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 226645#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226909#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226910#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226735#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226736#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 227018#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226417#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226418#L641-1 assume !(0 == ~M_E~0); 226720#L858-1 assume !(0 == ~T1_E~0); 226167#L863-1 assume !(0 == ~T2_E~0); 226168#L868-1 assume !(0 == ~T3_E~0); 227256#L873-1 assume !(0 == ~T4_E~0); 227253#L878-1 assume !(0 == ~T5_E~0); 227228#L883-1 assume !(0 == ~T6_E~0); 227229#L888-1 assume !(0 == ~T7_E~0); 226865#L893-1 assume !(0 == ~T8_E~0); 226866#L898-1 assume !(0 == ~E_M~0); 227272#L903-1 assume !(0 == ~E_1~0); 227227#L908-1 assume !(0 == ~E_2~0); 227032#L913-1 assume !(0 == ~E_3~0); 226241#L918-1 assume !(0 == ~E_4~0); 226242#L923-1 assume !(0 == ~E_5~0); 227046#L928-1 assume !(0 == ~E_6~0); 226358#L933-1 assume !(0 == ~E_7~0); 226359#L938-1 assume !(0 == ~E_8~0); 227030#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 227265#L422 assume !(1 == ~m_pc~0); 227185#L422-2 is_master_triggered_~__retres1~0 := 0; 226691#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 226609#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 226610#L1065 assume !(0 != activate_threads_~tmp~1); 226351#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 226204#L441 assume !(1 == ~t1_pc~0); 226205#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 227258#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 227326#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 226824#L1073 assume !(0 != activate_threads_~tmp___0~0); 226825#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 227243#L460 assume !(1 == ~t2_pc~0); 226170#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 226171#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 226985#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 227300#L1081 assume !(0 != activate_threads_~tmp___1~0); 226929#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226875#L479 assume !(1 == ~t3_pc~0); 226822#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 226823#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 227193#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 226576#L1089 assume !(0 != activate_threads_~tmp___2~0); 226206#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 226207#L498 assume !(1 == ~t4_pc~0); 226325#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 226668#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 226669#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 227101#L1097 assume !(0 != activate_threads_~tmp___3~0); 226636#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 226637#L517 assume !(1 == ~t5_pc~0); 227324#L517-2 is_transmit5_triggered_~__retres1~5 := 0; 227325#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 226721#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 226722#L1105 assume !(0 != activate_threads_~tmp___4~0); 226760#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 226761#L536 assume !(1 == ~t6_pc~0); 227147#L536-2 is_transmit6_triggered_~__retres1~6 := 0; 227120#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 227121#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 227339#L1113 assume !(0 != activate_threads_~tmp___5~0); 226445#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 226446#L555 assume !(1 == ~t7_pc~0); 226954#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 227019#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 226260#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 226239#L1121 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 226240#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 226271#L574 assume 1 == ~t8_pc~0; 226272#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 226808#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 226344#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 226345#L1129 assume !(0 != activate_threads_~tmp___7~0); 226410#L1129-2 assume !(1 == ~M_E~0); 226411#L956-1 assume !(1 == ~T1_E~0); 226431#L961-1 assume !(1 == ~T2_E~0); 226867#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 226868#L971-1 assume !(1 == ~T4_E~0); 227022#L976-1 assume !(1 == ~T5_E~0); 227000#L981-1 assume !(1 == ~T6_E~0); 226710#L986-1 assume !(1 == ~T7_E~0); 226479#L991-1 assume !(1 == ~T8_E~0); 226480#L996-1 assume !(1 == ~E_M~0); 227259#L1001-1 assume !(1 == ~E_1~0); 226938#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 226939#L1011-1 assume !(1 == ~E_3~0); 227218#L1016-1 assume !(1 == ~E_4~0); 227244#L1021-1 assume !(1 == ~E_5~0); 226197#L1026-1 assume !(1 == ~E_6~0); 226198#L1031-1 assume !(1 == ~E_7~0); 226881#L1036-1 assume !(1 == ~E_8~0); 226882#L1307-1 [2021-11-02 22:20:30,628 INFO L793 eck$LassoCheckResult]: Loop: 226882#L1307-1 assume !false; 275627#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 275626#L833 assume !false; 275625#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 275624#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 275615#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 275614#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 275612#L716 assume !(0 != eval_~tmp~0); 275613#L848 start_simulation_~kernel_st~0 := 2; 276052#L594-1 start_simulation_~kernel_st~0 := 3; 276051#L858-2 assume !(0 == ~M_E~0); 276050#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 276049#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 276048#L868-3 assume !(0 == ~T3_E~0); 276047#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 276046#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 276045#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 276044#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 276043#L893-3 assume !(0 == ~T8_E~0); 276042#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 276041#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 276040#L908-3 assume !(0 == ~E_2~0); 276039#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 276038#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 276037#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 276036#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 276035#L933-3 assume !(0 == ~E_7~0); 276034#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 276033#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 276032#L422-30 assume !(1 == ~m_pc~0); 276031#L422-32 is_master_triggered_~__retres1~0 := 0; 276030#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 276029#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 276028#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 276027#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 276026#L441-30 assume !(1 == ~t1_pc~0); 276025#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 276024#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 276023#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 276022#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 276021#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 276020#L460-30 assume !(1 == ~t2_pc~0); 276018#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 276017#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 276016#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 276015#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 276014#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 276013#L479-30 assume !(1 == ~t3_pc~0); 276012#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 276011#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 276010#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 276009#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 276008#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 276007#L498-30 assume !(1 == ~t4_pc~0); 276005#L498-32 is_transmit4_triggered_~__retres1~4 := 0; 276004#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 276003#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 276002#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 276001#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 276000#L517-30 assume !(1 == ~t5_pc~0); 275999#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 275998#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 275997#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 275996#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 275995#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 275994#L536-30 assume !(1 == ~t6_pc~0); 275993#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 275992#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 275991#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 275990#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 275989#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 275988#L555-30 assume !(1 == ~t7_pc~0); 275986#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 275985#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 275984#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 275983#L1121-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 275982#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 275981#L574-30 assume !(1 == ~t8_pc~0); 275980#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 275978#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 275977#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 275976#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 275975#L1129-32 assume !(1 == ~M_E~0); 275973#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 275972#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 275971#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 275970#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 275969#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 275968#L981-3 assume !(1 == ~T6_E~0); 275967#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 275966#L991-3 assume !(1 == ~T8_E~0); 275965#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 275964#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 275963#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 275962#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 275961#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 275960#L1021-3 assume !(1 == ~E_5~0); 275959#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 275958#L1031-3 assume !(1 == ~E_7~0); 275957#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 275956#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 275868#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 275860#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 275859#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 275857#L1326 assume !(0 == start_simulation_~tmp~3); 275855#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 275854#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 275845#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 275844#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 275843#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 275842#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 275841#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 275840#L1339 assume !(0 != start_simulation_~tmp___0~1); 226882#L1307-1 [2021-11-02 22:20:30,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:30,629 INFO L85 PathProgramCache]: Analyzing trace with hash -328018371, now seen corresponding path program 1 times [2021-11-02 22:20:30,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:30,629 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406940330] [2021-11-02 22:20:30,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:30,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:30,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:30,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:30,679 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:30,679 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406940330] [2021-11-02 22:20:30,679 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406940330] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:30,680 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:30,680 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 22:20:30,680 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190326649] [2021-11-02 22:20:30,681 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:30,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:30,681 INFO L85 PathProgramCache]: Analyzing trace with hash -175258785, now seen corresponding path program 1 times [2021-11-02 22:20:30,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:30,682 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282277873] [2021-11-02 22:20:30,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:30,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:30,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:30,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:30,717 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:30,717 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282277873] [2021-11-02 22:20:30,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282277873] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:30,718 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:30,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:30,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703475975] [2021-11-02 22:20:30,719 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:30,719 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:30,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 22:20:30,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 22:20:30,720 INFO L87 Difference]: Start difference. First operand 92543 states and 132255 transitions. cyclomatic complexity: 39728 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:31,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:31,395 INFO L93 Difference]: Finished difference Result 123199 states and 175081 transitions. [2021-11-02 22:20:31,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 22:20:31,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123199 states and 175081 transitions. [2021-11-02 22:20:32,120 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 122817 [2021-11-02 22:20:32,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123199 states to 123199 states and 175081 transitions. [2021-11-02 22:20:32,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123199 [2021-11-02 22:20:32,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123199 [2021-11-02 22:20:32,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123199 states and 175081 transitions. [2021-11-02 22:20:32,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:32,956 INFO L681 BuchiCegarLoop]: Abstraction has 123199 states and 175081 transitions. [2021-11-02 22:20:33,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123199 states and 175081 transitions. [2021-11-02 22:20:34,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123199 to 92705. [2021-11-02 22:20:34,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92705 states, 92705 states have (on average 1.4166549808532443) internal successors, (131331), 92704 states have internal predecessors, (131331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:34,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92705 states to 92705 states and 131331 transitions. [2021-11-02 22:20:34,595 INFO L704 BuchiCegarLoop]: Abstraction has 92705 states and 131331 transitions. [2021-11-02 22:20:34,596 INFO L587 BuchiCegarLoop]: Abstraction has 92705 states and 131331 transitions. [2021-11-02 22:20:34,596 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-02 22:20:34,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92705 states and 131331 transitions. [2021-11-02 22:20:34,843 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 92449 [2021-11-02 22:20:34,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:34,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:34,845 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:34,846 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:34,846 INFO L791 eck$LassoCheckResult]: Stem: 442696#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 442697#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 441935#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 441936#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 442398#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 442399#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 442665#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 442666#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 442489#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 442490#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 442767#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 442175#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 442176#L641-1 assume !(0 == ~M_E~0); 442473#L858-1 assume !(0 == ~T1_E~0); 441922#L863-1 assume !(0 == ~T2_E~0); 441923#L868-1 assume !(0 == ~T3_E~0); 443006#L873-1 assume !(0 == ~T4_E~0); 443004#L878-1 assume !(0 == ~T5_E~0); 442983#L883-1 assume !(0 == ~T6_E~0); 442984#L888-1 assume !(0 == ~T7_E~0); 442625#L893-1 assume !(0 == ~T8_E~0); 442626#L898-1 assume !(0 == ~E_M~0); 443021#L903-1 assume !(0 == ~E_1~0); 442982#L908-1 assume !(0 == ~E_2~0); 442781#L913-1 assume !(0 == ~E_3~0); 441996#L918-1 assume !(0 == ~E_4~0); 441997#L923-1 assume !(0 == ~E_5~0); 442790#L928-1 assume !(0 == ~E_6~0); 442115#L933-1 assume !(0 == ~E_7~0); 442116#L938-1 assume !(0 == ~E_8~0); 442779#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 443014#L422 assume !(1 == ~m_pc~0); 442932#L422-2 is_master_triggered_~__retres1~0 := 0; 442445#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 442365#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 442366#L1065 assume !(0 != activate_threads_~tmp~1); 442108#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 441959#L441 assume !(1 == ~t1_pc~0); 441960#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 443008#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 443071#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 442583#L1073 assume !(0 != activate_threads_~tmp___0~0); 442584#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 442996#L460 assume !(1 == ~t2_pc~0); 441925#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 441926#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 442734#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 443046#L1081 assume !(0 != activate_threads_~tmp___1~0); 442682#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 442636#L479 assume !(1 == ~t3_pc~0); 442580#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 442581#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 442939#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 442333#L1089 assume !(0 != activate_threads_~tmp___2~0); 441961#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 441962#L498 assume !(1 == ~t4_pc~0); 442081#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 442422#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 442423#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 442845#L1097 assume !(0 != activate_threads_~tmp___3~0); 442390#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 442391#L517 assume !(1 == ~t5_pc~0); 443069#L517-2 is_transmit5_triggered_~__retres1~5 := 0; 443070#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 442474#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 442475#L1105 assume !(0 != activate_threads_~tmp___4~0); 442514#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 442515#L536 assume !(1 == ~t6_pc~0); 442894#L536-2 is_transmit6_triggered_~__retres1~6 := 0; 442868#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 442869#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 443081#L1113 assume !(0 != activate_threads_~tmp___5~0); 442201#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 442202#L555 assume !(1 == ~t7_pc~0); 442704#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 442768#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 442015#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 441994#L1121 assume !(0 != activate_threads_~tmp___6~0); 441995#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 442026#L574 assume 1 == ~t8_pc~0; 442027#L575 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 442562#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 442100#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 442101#L1129 assume !(0 != activate_threads_~tmp___7~0); 442168#L1129-2 assume !(1 == ~M_E~0); 442169#L956-1 assume !(1 == ~T1_E~0); 442188#L961-1 assume !(1 == ~T2_E~0); 442627#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 442628#L971-1 assume !(1 == ~T4_E~0); 442771#L976-1 assume !(1 == ~T5_E~0); 442748#L981-1 assume !(1 == ~T6_E~0); 442463#L986-1 assume !(1 == ~T7_E~0); 442236#L991-1 assume !(1 == ~T8_E~0); 442237#L996-1 assume !(1 == ~E_M~0); 443009#L1001-1 assume !(1 == ~E_1~0); 442689#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 442690#L1011-1 assume !(1 == ~E_3~0); 442968#L1016-1 assume !(1 == ~E_4~0); 442997#L1021-1 assume !(1 == ~E_5~0); 441952#L1026-1 assume !(1 == ~E_6~0); 441953#L1031-1 assume !(1 == ~E_7~0); 442642#L1036-1 assume !(1 == ~E_8~0); 442643#L1307-1 [2021-11-02 22:20:34,847 INFO L793 eck$LassoCheckResult]: Loop: 442643#L1307-1 assume !false; 482457#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 501596#L833 assume !false; 501595#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 501594#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 501585#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 501584#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 501582#L716 assume !(0 != eval_~tmp~0); 501583#L848 start_simulation_~kernel_st~0 := 2; 508361#L594-1 start_simulation_~kernel_st~0 := 3; 508360#L858-2 assume !(0 == ~M_E~0); 508359#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 508358#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 508357#L868-3 assume !(0 == ~T3_E~0); 508356#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 508355#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 508354#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 508353#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 508352#L893-3 assume !(0 == ~T8_E~0); 508351#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 508350#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 508349#L908-3 assume !(0 == ~E_2~0); 508348#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 508347#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 508346#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 508345#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 508344#L933-3 assume !(0 == ~E_7~0); 508343#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 508342#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 508341#L422-30 assume !(1 == ~m_pc~0); 508340#L422-32 is_master_triggered_~__retres1~0 := 0; 508339#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 508338#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 508337#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 508336#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 508335#L441-30 assume !(1 == ~t1_pc~0); 508334#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 508333#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 508332#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 508331#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 508330#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 508329#L460-30 assume !(1 == ~t2_pc~0); 508327#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 508326#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 508325#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 508324#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 508323#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 508322#L479-30 assume !(1 == ~t3_pc~0); 508321#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 508320#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 508319#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 508318#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 508317#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 508316#L498-30 assume 1 == ~t4_pc~0; 508315#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 508313#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 508312#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 508311#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 508310#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 508309#L517-30 assume !(1 == ~t5_pc~0); 508308#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 508307#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 508306#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 508305#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 508304#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 508303#L536-30 assume !(1 == ~t6_pc~0); 508302#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 508301#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 508300#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 508299#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 508298#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 508297#L555-30 assume !(1 == ~t7_pc~0); 508295#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 508294#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 508293#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 508292#L1121-30 assume !(0 != activate_threads_~tmp___6~0); 508291#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 508290#L574-30 assume !(1 == ~t8_pc~0); 508289#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 508287#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 508286#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 508285#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 508284#L1129-32 assume !(1 == ~M_E~0); 481600#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 508283#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 508282#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 508281#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 508280#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 508279#L981-3 assume !(1 == ~T6_E~0); 508278#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 508277#L991-3 assume !(1 == ~T8_E~0); 508276#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 508275#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 508274#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 508273#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 508272#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 508271#L1021-3 assume !(1 == ~E_5~0); 508270#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 508269#L1031-3 assume !(1 == ~E_7~0); 481720#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 481717#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 481707#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 481693#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 481686#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 481687#L1326 assume !(0 == start_simulation_~tmp~3); 503684#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 482574#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 482557#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 482549#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 482542#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 482537#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 482520#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 482519#L1339 assume !(0 != start_simulation_~tmp___0~1); 442643#L1307-1 [2021-11-02 22:20:34,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:34,847 INFO L85 PathProgramCache]: Analyzing trace with hash -187469761, now seen corresponding path program 1 times [2021-11-02 22:20:34,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:34,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195258630] [2021-11-02 22:20:34,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:34,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:34,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:34,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:34,891 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:34,891 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195258630] [2021-11-02 22:20:34,892 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195258630] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:34,892 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:34,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:34,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093086248] [2021-11-02 22:20:34,893 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:34,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:34,893 INFO L85 PathProgramCache]: Analyzing trace with hash 701866110, now seen corresponding path program 1 times [2021-11-02 22:20:34,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:34,894 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509001907] [2021-11-02 22:20:34,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:34,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:34,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:34,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:34,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:34,927 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509001907] [2021-11-02 22:20:34,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509001907] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:34,927 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:34,927 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:34,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985833633] [2021-11-02 22:20:34,928 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:34,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:34,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 22:20:34,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 22:20:34,929 INFO L87 Difference]: Start difference. First operand 92705 states and 131331 transitions. cyclomatic complexity: 38642 Second operand has 4 states, 4 states have (on average 25.5) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:36,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:36,493 INFO L93 Difference]: Finished difference Result 256714 states and 361936 transitions. [2021-11-02 22:20:36,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 22:20:36,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 256714 states and 361936 transitions. [2021-11-02 22:20:37,927 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 253495 [2021-11-02 22:20:38,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 256714 states to 256714 states and 361936 transitions. [2021-11-02 22:20:38,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 256714 [2021-11-02 22:20:38,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 256714 [2021-11-02 22:20:38,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256714 states and 361936 transitions. [2021-11-02 22:20:38,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:38,720 INFO L681 BuchiCegarLoop]: Abstraction has 256714 states and 361936 transitions. [2021-11-02 22:20:38,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256714 states and 361936 transitions. [2021-11-02 22:20:41,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256714 to 252776. [2021-11-02 22:20:42,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252776 states, 252776 states have (on average 1.4125945501155173) internal successors, (357070), 252775 states have internal predecessors, (357070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:42,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252776 states to 252776 states and 357070 transitions. [2021-11-02 22:20:42,981 INFO L704 BuchiCegarLoop]: Abstraction has 252776 states and 357070 transitions. [2021-11-02 22:20:42,981 INFO L587 BuchiCegarLoop]: Abstraction has 252776 states and 357070 transitions. [2021-11-02 22:20:42,981 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-02 22:20:42,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252776 states and 357070 transitions. [2021-11-02 22:20:43,606 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252361 [2021-11-02 22:20:43,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:43,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:43,608 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:43,608 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:43,609 INFO L791 eck$LassoCheckResult]: Stem: 792129#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 792130#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 791364#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 791365#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 791821#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 791822#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 792095#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 792096#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 791910#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 791911#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 792207#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 791599#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 791600#L641-1 assume !(0 == ~M_E~0); 791895#L858-1 assume !(0 == ~T1_E~0); 791351#L863-1 assume !(0 == ~T2_E~0); 791352#L868-1 assume !(0 == ~T3_E~0); 792450#L873-1 assume !(0 == ~T4_E~0); 792447#L878-1 assume !(0 == ~T5_E~0); 792420#L883-1 assume !(0 == ~T6_E~0); 792421#L888-1 assume !(0 == ~T7_E~0); 792053#L893-1 assume !(0 == ~T8_E~0); 792054#L898-1 assume !(0 == ~E_M~0); 792467#L903-1 assume !(0 == ~E_1~0); 792419#L908-1 assume !(0 == ~E_2~0); 792220#L913-1 assume !(0 == ~E_3~0); 791423#L918-1 assume !(0 == ~E_4~0); 791424#L923-1 assume !(0 == ~E_5~0); 792232#L928-1 assume !(0 == ~E_6~0); 791540#L933-1 assume !(0 == ~E_7~0); 791541#L938-1 assume !(0 == ~E_8~0); 792218#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 792460#L422 assume !(1 == ~m_pc~0); 792368#L422-2 is_master_triggered_~__retres1~0 := 0; 791865#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 791786#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 791787#L1065 assume !(0 != activate_threads_~tmp~1); 791533#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 791387#L441 assume !(1 == ~t1_pc~0); 791388#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 792451#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 792516#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 792010#L1073 assume !(0 != activate_threads_~tmp___0~0); 792011#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 792438#L460 assume !(1 == ~t2_pc~0); 791354#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 791355#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 792173#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 792496#L1081 assume !(0 != activate_threads_~tmp___1~0); 792111#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 792064#L479 assume !(1 == ~t3_pc~0); 792006#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 792007#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 792378#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 791753#L1089 assume !(0 != activate_threads_~tmp___2~0); 791389#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 791390#L498 assume !(1 == ~t4_pc~0); 791507#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 791844#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 791845#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 792292#L1097 assume !(0 != activate_threads_~tmp___3~0); 791813#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 791814#L517 assume !(1 == ~t5_pc~0); 792514#L517-2 is_transmit5_triggered_~__retres1~5 := 0; 792515#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 791896#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 791897#L1105 assume !(0 != activate_threads_~tmp___4~0); 791936#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 791937#L536 assume !(1 == ~t6_pc~0); 792336#L536-2 is_transmit6_triggered_~__retres1~6 := 0; 792309#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 792310#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 792530#L1113 assume !(0 != activate_threads_~tmp___5~0); 791623#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 791624#L555 assume !(1 == ~t7_pc~0); 792143#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 792208#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 791442#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 791421#L1121 assume !(0 != activate_threads_~tmp___6~0); 791422#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 791453#L574 assume !(1 == ~t8_pc~0); 791454#L574-2 is_transmit8_triggered_~__retres1~8 := 0; 792209#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 791526#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 791527#L1129 assume !(0 != activate_threads_~tmp___7~0); 791592#L1129-2 assume !(1 == ~M_E~0); 791593#L956-1 assume !(1 == ~T1_E~0); 791611#L961-1 assume !(1 == ~T2_E~0); 792055#L966-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 792056#L971-1 assume !(1 == ~T4_E~0); 792212#L976-1 assume !(1 == ~T5_E~0); 792188#L981-1 assume !(1 == ~T6_E~0); 791885#L986-1 assume !(1 == ~T7_E~0); 791658#L991-1 assume !(1 == ~T8_E~0); 791659#L996-1 assume !(1 == ~E_M~0); 792453#L1001-1 assume !(1 == ~E_1~0); 792122#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 792123#L1011-1 assume !(1 == ~E_3~0); 792403#L1016-1 assume !(1 == ~E_4~0); 792439#L1021-1 assume !(1 == ~E_5~0); 791380#L1026-1 assume !(1 == ~E_6~0); 791381#L1031-1 assume !(1 == ~E_7~0); 792071#L1036-1 assume !(1 == ~E_8~0); 792072#L1307-1 [2021-11-02 22:20:43,609 INFO L793 eck$LassoCheckResult]: Loop: 792072#L1307-1 assume !false; 1014686#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1014685#L833 assume !false; 1014684#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 968531#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 968522#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 968520#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 968517#L716 assume !(0 != eval_~tmp~0); 968518#L848 start_simulation_~kernel_st~0 := 2; 980027#L594-1 start_simulation_~kernel_st~0 := 3; 980025#L858-2 assume !(0 == ~M_E~0); 980023#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 980021#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 980019#L868-3 assume !(0 == ~T3_E~0); 980016#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 980014#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 980012#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 980010#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 980008#L893-3 assume !(0 == ~T8_E~0); 980005#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 980004#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 980001#L908-3 assume !(0 == ~E_2~0); 979999#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 979997#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 979995#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 979993#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 979991#L933-3 assume !(0 == ~E_7~0); 979990#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 979988#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 979986#L422-30 assume !(1 == ~m_pc~0); 979984#L422-32 is_master_triggered_~__retres1~0 := 0; 979982#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 979979#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 979977#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 979975#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 979973#L441-30 assume !(1 == ~t1_pc~0); 979971#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 979969#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 979967#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 979965#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 979963#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 979961#L460-30 assume !(1 == ~t2_pc~0); 979958#L460-32 is_transmit2_triggered_~__retres1~2 := 0; 979957#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 979956#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 970351#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 969068#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 969064#L479-30 assume !(1 == ~t3_pc~0); 969062#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 969059#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 969057#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 969055#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 969053#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 969051#L498-30 assume !(1 == ~t4_pc~0); 969048#L498-32 is_transmit4_triggered_~__retres1~4 := 0; 969046#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 969044#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 969042#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 969040#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 969038#L517-30 assume !(1 == ~t5_pc~0); 969036#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 969033#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 969031#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 969029#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 969027#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 969025#L536-30 assume !(1 == ~t6_pc~0); 969023#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 969022#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 969019#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 969017#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 969015#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 969013#L555-30 assume !(1 == ~t7_pc~0); 969010#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 969008#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 969007#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 969005#L1121-30 assume !(0 != activate_threads_~tmp___6~0); 969003#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 969001#L574-30 assume !(1 == ~t8_pc~0); 968999#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 968996#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 968994#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 968992#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 968990#L1129-32 assume !(1 == ~M_E~0); 968830#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 968987#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 968985#L966-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 968983#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 968981#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 968979#L981-3 assume !(1 == ~T6_E~0); 968977#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 968974#L991-3 assume !(1 == ~T8_E~0); 968972#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 968970#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 968968#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 968966#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 968964#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 968962#L1021-3 assume !(1 == ~E_5~0); 968960#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 968958#L1031-3 assume !(1 == ~E_7~0); 968956#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 968954#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 968948#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 968939#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 968937#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 968934#L1326 assume !(0 == start_simulation_~tmp~3); 968935#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1014702#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1014693#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1014692#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 1014691#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1014690#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 1014689#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 1014688#L1339 assume !(0 != start_simulation_~tmp___0~1); 792072#L1307-1 [2021-11-02 22:20:43,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:43,610 INFO L85 PathProgramCache]: Analyzing trace with hash 592511168, now seen corresponding path program 1 times [2021-11-02 22:20:43,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:43,610 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587957070] [2021-11-02 22:20:43,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:43,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:43,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:43,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:43,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:43,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587957070] [2021-11-02 22:20:43,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587957070] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:43,648 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:43,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:43,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416414602] [2021-11-02 22:20:43,649 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:43,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:43,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1204618083, now seen corresponding path program 1 times [2021-11-02 22:20:43,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:43,650 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217198436] [2021-11-02 22:20:43,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:43,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:43,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:44,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:44,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:44,375 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217198436] [2021-11-02 22:20:44,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217198436] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:44,375 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:44,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:44,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283556573] [2021-11-02 22:20:44,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:44,391 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:44,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:44,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:44,393 INFO L87 Difference]: Start difference. First operand 252776 states and 357070 transitions. cyclomatic complexity: 104326 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:45,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:45,094 INFO L93 Difference]: Finished difference Result 252776 states and 355610 transitions. [2021-11-02 22:20:45,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:45,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 252776 states and 355610 transitions. [2021-11-02 22:20:46,742 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252361 [2021-11-02 22:20:47,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 252776 states to 252776 states and 355610 transitions. [2021-11-02 22:20:47,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252776 [2021-11-02 22:20:47,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252776 [2021-11-02 22:20:47,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 252776 states and 355610 transitions. [2021-11-02 22:20:47,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:47,451 INFO L681 BuchiCegarLoop]: Abstraction has 252776 states and 355610 transitions. [2021-11-02 22:20:47,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252776 states and 355610 transitions. [2021-11-02 22:20:50,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252776 to 252776. [2021-11-02 22:20:50,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252776 states, 252776 states have (on average 1.4068186853182265) internal successors, (355610), 252775 states have internal predecessors, (355610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:50,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252776 states to 252776 states and 355610 transitions. [2021-11-02 22:20:50,803 INFO L704 BuchiCegarLoop]: Abstraction has 252776 states and 355610 transitions. [2021-11-02 22:20:50,803 INFO L587 BuchiCegarLoop]: Abstraction has 252776 states and 355610 transitions. [2021-11-02 22:20:50,803 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-02 22:20:50,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252776 states and 355610 transitions. [2021-11-02 22:20:52,487 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252361 [2021-11-02 22:20:52,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 22:20:52,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 22:20:52,517 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:52,517 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 22:20:52,517 INFO L791 eck$LassoCheckResult]: Stem: 1297682#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1297683#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1296923#L1270 havoc start_simulation_#t~ret29, start_simulation_#t~ret30, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1296924#L594 assume 1 == ~m_i~0;~m_st~0 := 0; 1297381#L601-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1297382#L606-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1297645#L611-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1297646#L616-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1297471#L621-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1297472#L626-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1297766#L631-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1297159#L636-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1297160#L641-1 assume !(0 == ~M_E~0); 1297451#L858-1 assume !(0 == ~T1_E~0); 1296910#L863-1 assume !(0 == ~T2_E~0); 1296911#L868-1 assume !(0 == ~T3_E~0); 1298010#L873-1 assume !(0 == ~T4_E~0); 1298007#L878-1 assume !(0 == ~T5_E~0); 1297983#L883-1 assume !(0 == ~T6_E~0); 1297984#L888-1 assume !(0 == ~T7_E~0); 1297600#L893-1 assume !(0 == ~T8_E~0); 1297601#L898-1 assume !(0 == ~E_M~0); 1298026#L903-1 assume !(0 == ~E_1~0); 1297982#L908-1 assume !(0 == ~E_2~0); 1297779#L913-1 assume !(0 == ~E_3~0); 1296982#L918-1 assume !(0 == ~E_4~0); 1296983#L923-1 assume !(0 == ~E_5~0); 1297791#L928-1 assume !(0 == ~E_6~0); 1297099#L933-1 assume !(0 == ~E_7~0); 1297100#L938-1 assume !(0 == ~E_8~0); 1297777#L943-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1298020#L422 assume !(1 == ~m_pc~0); 1297936#L422-2 is_master_triggered_~__retres1~0 := 0; 1297423#L433 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1297347#L434 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1297348#L1065 assume !(0 != activate_threads_~tmp~1); 1297094#L1065-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1296948#L441 assume !(1 == ~t1_pc~0); 1296949#L441-2 is_transmit1_triggered_~__retres1~1 := 0; 1298013#L452 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1298086#L453 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1297558#L1073 assume !(0 != activate_threads_~tmp___0~0); 1297559#L1073-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1297998#L460 assume !(1 == ~t2_pc~0); 1296915#L460-2 is_transmit2_triggered_~__retres1~2 := 0; 1296916#L471 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1297731#L472 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1298060#L1081 assume !(0 != activate_threads_~tmp___1~0); 1297664#L1081-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1297610#L479 assume !(1 == ~t3_pc~0); 1297553#L479-2 is_transmit3_triggered_~__retres1~3 := 0; 1297554#L490 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1297944#L491 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1297314#L1089 assume !(0 != activate_threads_~tmp___2~0); 1296950#L1089-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1296951#L498 assume !(1 == ~t4_pc~0); 1297066#L498-2 is_transmit4_triggered_~__retres1~4 := 0; 1297404#L509 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1297405#L510 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1297855#L1097 assume !(0 != activate_threads_~tmp___3~0); 1297370#L1097-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1297371#L517 assume !(1 == ~t5_pc~0); 1298083#L517-2 is_transmit5_triggered_~__retres1~5 := 0; 1298084#L528 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1297452#L529 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1297453#L1105 assume !(0 != activate_threads_~tmp___4~0); 1297496#L1105-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1297497#L536 assume !(1 == ~t6_pc~0); 1297903#L536-2 is_transmit6_triggered_~__retres1~6 := 0; 1297876#L547 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1297877#L548 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1298104#L1113 assume !(0 != activate_threads_~tmp___5~0); 1297184#L1113-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1297185#L555 assume !(1 == ~t7_pc~0); 1297696#L555-2 is_transmit7_triggered_~__retres1~7 := 0; 1297767#L566 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1297003#L567 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1296980#L1121 assume !(0 != activate_threads_~tmp___6~0); 1296981#L1121-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1297012#L574 assume !(1 == ~t8_pc~0); 1297013#L574-2 is_transmit8_triggered_~__retres1~8 := 0; 1297770#L585 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1297085#L586 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1297086#L1129 assume !(0 != activate_threads_~tmp___7~0); 1297155#L1129-2 assume !(1 == ~M_E~0); 1297156#L956-1 assume !(1 == ~T1_E~0); 1297173#L961-1 assume !(1 == ~T2_E~0); 1297602#L966-1 assume !(1 == ~T3_E~0); 1297603#L971-1 assume !(1 == ~T4_E~0); 1297771#L976-1 assume !(1 == ~T5_E~0); 1297745#L981-1 assume !(1 == ~T6_E~0); 1297441#L986-1 assume !(1 == ~T7_E~0); 1297218#L991-1 assume !(1 == ~T8_E~0); 1297219#L996-1 assume !(1 == ~E_M~0); 1298016#L1001-1 assume !(1 == ~E_1~0); 1297677#L1006-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1297678#L1011-1 assume !(1 == ~E_3~0); 1297967#L1016-1 assume !(1 == ~E_4~0); 1297999#L1021-1 assume !(1 == ~E_5~0); 1296939#L1026-1 assume !(1 == ~E_6~0); 1296940#L1031-1 assume !(1 == ~E_7~0); 1297616#L1036-1 assume !(1 == ~E_8~0); 1297617#L1307-1 [2021-11-02 22:20:52,519 INFO L793 eck$LassoCheckResult]: Loop: 1297617#L1307-1 assume !false; 1381178#L1308 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1380885#L833 assume !false; 1381175#L712 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1381173#L654 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1381163#L701 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1381161#L702 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1381158#L716 assume !(0 != eval_~tmp~0); 1381159#L848 start_simulation_~kernel_st~0 := 2; 1381416#L594-1 start_simulation_~kernel_st~0 := 3; 1381414#L858-2 assume !(0 == ~M_E~0); 1381412#L858-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1381410#L863-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1381408#L868-3 assume !(0 == ~T3_E~0); 1381406#L873-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1381404#L878-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1381402#L883-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1381400#L888-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1381398#L893-3 assume !(0 == ~T8_E~0); 1381396#L898-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1381394#L903-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1381392#L908-3 assume !(0 == ~E_2~0); 1381390#L913-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1381388#L918-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1381386#L923-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1381384#L928-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1381382#L933-3 assume !(0 == ~E_7~0); 1381380#L938-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1381377#L943-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1381375#L422-30 assume !(1 == ~m_pc~0); 1381373#L422-32 is_master_triggered_~__retres1~0 := 0; 1381371#L433-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1381369#L434-10 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1381367#L1065-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1381365#L1065-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1381363#L441-30 assume !(1 == ~t1_pc~0); 1381361#L441-32 is_transmit1_triggered_~__retres1~1 := 0; 1381359#L452-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1381357#L453-10 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1381355#L1073-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1381352#L1073-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1381350#L460-30 assume 1 == ~t2_pc~0; 1381348#L461-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1381345#L471-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1381343#L472-10 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1381341#L1081-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1381339#L1081-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1381337#L479-30 assume !(1 == ~t3_pc~0); 1381335#L479-32 is_transmit3_triggered_~__retres1~3 := 0; 1381333#L490-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1381331#L491-10 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1381329#L1089-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1381327#L1089-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1381325#L498-30 assume 1 == ~t4_pc~0; 1381323#L499-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1381320#L509-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1381318#L510-10 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1381315#L1097-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1381313#L1097-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1381311#L517-30 assume !(1 == ~t5_pc~0); 1381309#L517-32 is_transmit5_triggered_~__retres1~5 := 0; 1381307#L528-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1381305#L529-10 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1381303#L1105-30 assume !(0 != activate_threads_~tmp___4~0); 1381301#L1105-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1381299#L536-30 assume !(1 == ~t6_pc~0); 1381297#L536-32 is_transmit6_triggered_~__retres1~6 := 0; 1381295#L547-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1381294#L548-10 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1381293#L1113-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1381292#L1113-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1381290#L555-30 assume !(1 == ~t7_pc~0); 1381287#L555-32 is_transmit7_triggered_~__retres1~7 := 0; 1381285#L566-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1381283#L567-10 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1381281#L1121-30 assume !(0 != activate_threads_~tmp___6~0); 1381279#L1121-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1381277#L574-30 assume !(1 == ~t8_pc~0); 1381275#L574-32 is_transmit8_triggered_~__retres1~8 := 0; 1381273#L585-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1381271#L586-10 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1381269#L1129-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1381267#L1129-32 assume !(1 == ~M_E~0); 1381263#L956-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1381260#L961-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1381258#L966-3 assume !(1 == ~T3_E~0); 1381256#L971-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1381254#L976-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1381252#L981-3 assume !(1 == ~T6_E~0); 1381250#L986-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1381248#L991-3 assume !(1 == ~T8_E~0); 1381246#L996-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1381244#L1001-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1381242#L1006-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1381240#L1011-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1381238#L1016-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1381235#L1021-3 assume !(1 == ~E_5~0); 1381233#L1026-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1381231#L1031-3 assume !(1 == ~E_7~0); 1381229#L1036-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1381227#L1041-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1381221#L654-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1381212#L701-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1381210#L702-1 start_simulation_#t~ret29 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret29;havoc start_simulation_#t~ret29; 1381207#L1326 assume !(0 == start_simulation_~tmp~3); 1381204#L1326-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret28, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1381202#L654-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1381192#L701-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1381190#L702-2 stop_simulation_#t~ret28 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret28;havoc stop_simulation_#t~ret28; 1381188#L1281 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1381185#L1288 stop_simulation_#res := stop_simulation_~__retres2~0; 1381183#L1289 start_simulation_#t~ret30 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 1381181#L1339 assume !(0 != start_simulation_~tmp___0~1); 1297617#L1307-1 [2021-11-02 22:20:52,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:52,520 INFO L85 PathProgramCache]: Analyzing trace with hash -687352510, now seen corresponding path program 1 times [2021-11-02 22:20:52,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:52,521 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393143633] [2021-11-02 22:20:52,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:52,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:52,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:52,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:52,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:52,566 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393143633] [2021-11-02 22:20:52,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393143633] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:52,566 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:52,566 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 22:20:52,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837897609] [2021-11-02 22:20:52,568 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 22:20:52,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 22:20:52,568 INFO L85 PathProgramCache]: Analyzing trace with hash 677808541, now seen corresponding path program 1 times [2021-11-02 22:20:52,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 22:20:52,569 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388204725] [2021-11-02 22:20:52,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 22:20:52,569 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 22:20:52,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 22:20:52,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 22:20:52,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 22:20:52,602 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [388204725] [2021-11-02 22:20:52,603 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [388204725] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 22:20:52,603 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 22:20:52,603 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 22:20:52,603 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421439186] [2021-11-02 22:20:52,604 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 22:20:52,605 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 22:20:52,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 22:20:52,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 22:20:52,606 INFO L87 Difference]: Start difference. First operand 252776 states and 355610 transitions. cyclomatic complexity: 102866 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 2 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 22:20:53,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 22:20:53,364 INFO L93 Difference]: Finished difference Result 252776 states and 351250 transitions. [2021-11-02 22:20:53,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 22:20:53,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 252776 states and 351250 transitions. [2021-11-02 22:20:55,217 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 252361 [2021-11-02 22:20:55,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 252776 states to 252776 states and 351250 transitions. [2021-11-02 22:20:55,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252776 [2021-11-02 22:20:55,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252776 [2021-11-02 22:20:55,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 252776 states and 351250 transitions. [2021-11-02 22:20:56,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 22:20:56,033 INFO L681 BuchiCegarLoop]: Abstraction has 252776 states and 351250 transitions. [2021-11-02 22:20:56,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252776 states and 351250 transitions.