./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9ad7fb26 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 34da81a3627e632825cfe1416aa8cea0cd7fd89761d284c0cf107dc2c277f985 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-9ad7fb2 [2021-11-02 23:01:36,262 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-02 23:01:36,266 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-02 23:01:36,307 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-02 23:01:36,312 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-02 23:01:36,316 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-02 23:01:36,320 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-02 23:01:36,325 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-02 23:01:36,328 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-02 23:01:36,336 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-02 23:01:36,337 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-02 23:01:36,339 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-02 23:01:36,340 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-02 23:01:36,343 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-02 23:01:36,346 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-02 23:01:36,353 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-02 23:01:36,355 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-02 23:01:36,356 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-02 23:01:36,362 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-02 23:01:36,370 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-02 23:01:36,373 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-02 23:01:36,375 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-02 23:01:36,379 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-02 23:01:36,381 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-02 23:01:36,393 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-02 23:01:36,395 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-02 23:01:36,395 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-02 23:01:36,396 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-02 23:01:36,397 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-02 23:01:36,398 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-02 23:01:36,399 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-02 23:01:36,400 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-02 23:01:36,401 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-02 23:01:36,402 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-02 23:01:36,403 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-02 23:01:36,404 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-02 23:01:36,405 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-02 23:01:36,405 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-02 23:01:36,405 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-02 23:01:36,407 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-02 23:01:36,407 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-02 23:01:36,408 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-02 23:01:36,441 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-02 23:01:36,442 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-02 23:01:36,442 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-02 23:01:36,442 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-02 23:01:36,444 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-02 23:01:36,444 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-02 23:01:36,445 INFO L138 SettingsManager]: * Use SBE=true [2021-11-02 23:01:36,445 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-02 23:01:36,445 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-02 23:01:36,445 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-02 23:01:36,446 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-02 23:01:36,446 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-02 23:01:36,446 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-02 23:01:36,447 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-02 23:01:36,447 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-02 23:01:36,447 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-02 23:01:36,447 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-02 23:01:36,448 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-02 23:01:36,448 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-02 23:01:36,448 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-02 23:01:36,448 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-02 23:01:36,449 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-02 23:01:36,449 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-02 23:01:36,449 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-02 23:01:36,449 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-02 23:01:36,450 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-02 23:01:36,450 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-02 23:01:36,450 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-02 23:01:36,451 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-02 23:01:36,451 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-02 23:01:36,451 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-02 23:01:36,451 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-02 23:01:36,453 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-02 23:01:36,453 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 34da81a3627e632825cfe1416aa8cea0cd7fd89761d284c0cf107dc2c277f985 [2021-11-02 23:01:36,822 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-02 23:01:36,865 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-02 23:01:36,868 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-02 23:01:36,870 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-02 23:01:36,872 INFO L275 PluginConnector]: CDTParser initialized [2021-11-02 23:01:36,873 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-11-02 23:01:36,975 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/data/693dc48b3/3a8fb80030554b5b9b355fbfe7d33adb/FLAG99c903607 [2021-11-02 23:01:37,638 INFO L306 CDTParser]: Found 1 translation units. [2021-11-02 23:01:37,639 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-11-02 23:01:37,657 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/data/693dc48b3/3a8fb80030554b5b9b355fbfe7d33adb/FLAG99c903607 [2021-11-02 23:01:37,934 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/data/693dc48b3/3a8fb80030554b5b9b355fbfe7d33adb [2021-11-02 23:01:37,938 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-02 23:01:37,940 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-02 23:01:37,953 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-02 23:01:37,953 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-02 23:01:37,957 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-02 23:01:37,958 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:01:37" (1/1) ... [2021-11-02 23:01:37,962 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3b496116 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:37, skipping insertion in model container [2021-11-02 23:01:37,962 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:01:37" (1/1) ... [2021-11-02 23:01:37,971 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-02 23:01:38,036 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-02 23:01:38,204 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[366,379] [2021-11-02 23:01:38,335 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:01:38,347 INFO L203 MainTranslator]: Completed pre-run [2021-11-02 23:01:38,358 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[366,379] [2021-11-02 23:01:38,425 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:01:38,445 INFO L208 MainTranslator]: Completed translation [2021-11-02 23:01:38,446 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38 WrapperNode [2021-11-02 23:01:38,446 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-02 23:01:38,447 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-02 23:01:38,447 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-02 23:01:38,447 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-02 23:01:38,455 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,468 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,582 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-02 23:01:38,583 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-02 23:01:38,583 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-02 23:01:38,583 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-02 23:01:38,592 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,592 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,607 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,607 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,686 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,739 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,750 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,770 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-02 23:01:38,772 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-02 23:01:38,773 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-02 23:01:38,773 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-02 23:01:38,774 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (1/1) ... [2021-11-02 23:01:38,784 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-02 23:01:38,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/z3 [2021-11-02 23:01:38,814 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-02 23:01:38,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_63a90b61-eb04-4b45-9b11-045c019447a5/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-02 23:01:38,862 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-02 23:01:38,863 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-02 23:01:38,863 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-02 23:01:38,863 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-02 23:01:40,803 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-02 23:01:40,803 INFO L299 CfgBuilder]: Removed 376 assume(true) statements. [2021-11-02 23:01:40,807 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:01:40 BoogieIcfgContainer [2021-11-02 23:01:40,808 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-02 23:01:40,809 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-02 23:01:40,809 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-02 23:01:40,814 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-02 23:01:40,814 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:01:40,815 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 11:01:37" (1/3) ... [2021-11-02 23:01:40,816 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a4aaae4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:01:40, skipping insertion in model container [2021-11-02 23:01:40,816 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:01:40,816 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:01:38" (2/3) ... [2021-11-02 23:01:40,816 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a4aaae4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:01:40, skipping insertion in model container [2021-11-02 23:01:40,816 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:01:40,816 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:01:40" (3/3) ... [2021-11-02 23:01:40,817 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2021-11-02 23:01:40,876 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-02 23:01:40,876 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-02 23:01:40,876 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-02 23:01:40,877 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-02 23:01:40,877 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-02 23:01:40,877 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-02 23:01:40,877 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-02 23:01:40,877 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-02 23:01:40,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:41,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1021 [2021-11-02 23:01:41,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:41,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:41,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,070 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,070 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-02 23:01:41,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:41,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1021 [2021-11-02 23:01:41,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:41,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:41,093 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,102 INFO L791 eck$LassoCheckResult]: Stem: 546#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1046#L-1true havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1032#L1383true havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35#L643true assume !(1 == ~m_i~0);~m_st~0 := 2; 150#L650-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 743#L655-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 847#L660-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 309#L665-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 949#L670-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 800#L675-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 890#L680-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 984#L685-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 868#L690-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1120#L695-1true assume !(0 == ~M_E~0); 989#L931-1true assume !(0 == ~T1_E~0); 1018#L936-1true assume !(0 == ~T2_E~0); 1108#L941-1true assume !(0 == ~T3_E~0); 371#L946-1true assume !(0 == ~T4_E~0); 888#L951-1true assume !(0 == ~T5_E~0); 182#L956-1true assume !(0 == ~T6_E~0); 1094#L961-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 496#L966-1true assume !(0 == ~T8_E~0); 622#L971-1true assume !(0 == ~T9_E~0); 1040#L976-1true assume !(0 == ~E_M~0); 591#L981-1true assume !(0 == ~E_1~0); 378#L986-1true assume !(0 == ~E_2~0); 212#L991-1true assume !(0 == ~E_3~0); 1074#L996-1true assume !(0 == ~E_4~0); 966#L1001-1true assume 0 == ~E_5~0;~E_5~0 := 1; 544#L1006-1true assume !(0 == ~E_6~0); 891#L1011-1true assume !(0 == ~E_7~0); 926#L1016-1true assume !(0 == ~E_8~0); 1047#L1021-1true assume !(0 == ~E_9~0); 17#L1026-1true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1085#L452true assume !(1 == ~m_pc~0); 203#L452-2true is_master_triggered_~__retres1~0 := 0; 479#L463true is_master_triggered_#res := is_master_triggered_~__retres1~0; 537#L464true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 721#L1159true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 731#L1159-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 581#L471true assume 1 == ~t1_pc~0; 1042#L472true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 211#L482true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 529#L483true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1008#L1167true assume !(0 != activate_threads_~tmp___0~0); 345#L1167-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1025#L490true assume !(1 == ~t2_pc~0); 444#L490-2true is_transmit2_triggered_~__retres1~2 := 0; 486#L501true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 600#L502true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 178#L1175true assume !(0 != activate_threads_~tmp___1~0); 389#L1175-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 337#L509true assume 1 == ~t3_pc~0; 790#L510true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 186#L520true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 964#L521true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 650#L1183true assume !(0 != activate_threads_~tmp___2~0); 577#L1183-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1049#L528true assume !(1 == ~t4_pc~0); 975#L528-2true is_transmit4_triggered_~__retres1~4 := 0; 342#L539true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 730#L540true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 204#L1191true assume !(0 != activate_threads_~tmp___3~0); 629#L1191-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 740#L547true assume 1 == ~t5_pc~0; 1075#L548true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 423#L558true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 192#L559true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 373#L1199true assume !(0 != activate_threads_~tmp___4~0); 1072#L1199-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 684#L566true assume !(1 == ~t6_pc~0); 53#L566-2true is_transmit6_triggered_~__retres1~6 := 0; 214#L577true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1055#L578true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 167#L1207true assume !(0 != activate_threads_~tmp___5~0); 99#L1207-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1089#L585true assume 1 == ~t7_pc~0; 102#L586true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1054#L596true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 983#L597true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 646#L1215true assume !(0 != activate_threads_~tmp___6~0); 1082#L1215-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 756#L604true assume 1 == ~t8_pc~0; 1070#L605true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 714#L615true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 533#L616true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1065#L1223true assume !(0 != activate_threads_~tmp___7~0); 870#L1223-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 862#L623true assume !(1 == ~t9_pc~0); 29#L623-2true is_transmit9_triggered_~__retres1~9 := 0; 1104#L634true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 580#L635true activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 773#L1231true assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 448#L1231-2true assume !(1 == ~M_E~0); 1113#L1039-1true assume !(1 == ~T1_E~0); 877#L1044-1true assume !(1 == ~T2_E~0); 346#L1049-1true assume !(1 == ~T3_E~0); 1124#L1054-1true assume !(1 == ~T4_E~0); 502#L1059-1true assume !(1 == ~T5_E~0); 202#L1064-1true assume !(1 == ~T6_E~0); 693#L1069-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1038#L1074-1true assume !(1 == ~T8_E~0); 750#L1079-1true assume !(1 == ~T9_E~0); 720#L1084-1true assume !(1 == ~E_M~0); 901#L1089-1true assume !(1 == ~E_1~0); 777#L1094-1true assume !(1 == ~E_2~0); 403#L1099-1true assume !(1 == ~E_3~0); 910#L1104-1true assume !(1 == ~E_4~0); 583#L1109-1true assume 1 == ~E_5~0;~E_5~0 := 2; 279#L1114-1true assume !(1 == ~E_6~0); 1079#L1119-1true assume !(1 == ~E_7~0); 310#L1124-1true assume !(1 == ~E_8~0); 33#L1129-1true assume !(1 == ~E_9~0); 438#L1420-1true [2021-11-02 23:01:41,105 INFO L793 eck$LassoCheckResult]: Loop: 438#L1420-1true assume !false; 324#L1421true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 253#L906true assume !true; 686#L921true start_simulation_~kernel_st~0 := 2; 961#L643-1true start_simulation_~kernel_st~0 := 3; 920#L931-2true assume 0 == ~M_E~0;~M_E~0 := 1; 627#L931-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 295#L936-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 402#L941-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 672#L946-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 235#L951-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 639#L956-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 483#L961-3true assume !(0 == ~T7_E~0); 302#L966-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 907#L971-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 522#L976-3true assume 0 == ~E_M~0;~E_M~0 := 1; 44#L981-3true assume 0 == ~E_1~0;~E_1~0 := 1; 224#L986-3true assume 0 == ~E_2~0;~E_2~0 := 1; 34#L991-3true assume 0 == ~E_3~0;~E_3~0 := 1; 607#L996-3true assume 0 == ~E_4~0;~E_4~0 := 1; 749#L1001-3true assume !(0 == ~E_5~0); 286#L1006-3true assume 0 == ~E_6~0;~E_6~0 := 1; 644#L1011-3true assume 0 == ~E_7~0;~E_7~0 := 1; 883#L1016-3true assume 0 == ~E_8~0;~E_8~0 := 1; 701#L1021-3true assume 0 == ~E_9~0;~E_9~0 := 1; 418#L1026-3true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 443#L452-33true assume !(1 == ~m_pc~0); 809#L452-35true is_master_triggered_~__retres1~0 := 0; 174#L463-11true is_master_triggered_#res := is_master_triggered_~__retres1~0; 697#L464-11true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 654#L1159-33true assume !(0 != activate_threads_~tmp~1); 904#L1159-35true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 747#L471-33true assume 1 == ~t1_pc~0; 234#L472-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 825#L482-11true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 896#L483-11true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6#L1167-33true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 505#L1167-35true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 266#L490-33true assume !(1 == ~t2_pc~0); 319#L490-35true is_transmit2_triggered_~__retres1~2 := 0; 948#L501-11true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 946#L502-11true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 844#L1175-33true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 977#L1175-35true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9#L509-33true assume 1 == ~t3_pc~0; 120#L510-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 506#L520-11true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 967#L521-11true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 432#L1183-33true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 105#L1183-35true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 656#L528-33true assume !(1 == ~t4_pc~0); 130#L528-35true is_transmit4_triggered_~__retres1~4 := 0; 131#L539-11true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 142#L540-11true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 525#L1191-33true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 647#L1191-35true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 291#L547-33true assume !(1 == ~t5_pc~0); 260#L547-35true is_transmit5_triggered_~__retres1~5 := 0; 499#L558-11true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 552#L559-11true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 692#L1199-33true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 775#L1199-35true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 72#L566-33true assume !(1 == ~t6_pc~0); 736#L566-35true is_transmit6_triggered_~__retres1~6 := 0; 27#L577-11true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 335#L578-11true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 497#L1207-33true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1017#L1207-35true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 141#L585-33true assume 1 == ~t7_pc~0; 173#L586-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 312#L596-11true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 536#L597-11true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 566#L1215-33true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 333#L1215-35true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 368#L604-33true assume !(1 == ~t8_pc~0); 478#L604-35true is_transmit8_triggered_~__retres1~8 := 0; 712#L615-11true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 121#L616-11true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 547#L1223-33true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 677#L1223-35true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1012#L623-33true assume 1 == ~t9_pc~0; 1076#L624-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 542#L634-11true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1006#L635-11true activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 599#L1231-33true assume !(0 != activate_threads_~tmp___8~0); 93#L1231-35true assume 1 == ~M_E~0;~M_E~0 := 2; 619#L1039-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 669#L1044-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 163#L1049-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 561#L1054-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 62#L1059-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1132#L1064-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 351#L1069-3true assume !(1 == ~T7_E~0); 593#L1074-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 850#L1079-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 509#L1084-3true assume 1 == ~E_M~0;~E_M~0 := 2; 434#L1089-3true assume 1 == ~E_1~0;~E_1~0 := 2; 559#L1094-3true assume 1 == ~E_2~0;~E_2~0 := 2; 372#L1099-3true assume 1 == ~E_3~0;~E_3~0 := 2; 613#L1104-3true assume 1 == ~E_4~0;~E_4~0 := 2; 921#L1109-3true assume !(1 == ~E_5~0); 597#L1114-3true assume 1 == ~E_6~0;~E_6~0 := 2; 995#L1119-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1127#L1124-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1035#L1129-3true assume 1 == ~E_9~0;~E_9~0 := 2; 207#L1134-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 582#L708-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 909#L760-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 694#L761-1true start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 767#L1439true assume !(0 == start_simulation_~tmp~3); 947#L1439-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 273#L708-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 843#L760-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 400#L761-2true stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 294#L1394true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 996#L1401true stop_simulation_#res := stop_simulation_~__retres2~0; 219#L1402true start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 323#L1452true assume !(0 != start_simulation_~tmp___0~1); 438#L1420-1true [2021-11-02 23:01:41,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:41,115 INFO L85 PathProgramCache]: Analyzing trace with hash -168145620, now seen corresponding path program 1 times [2021-11-02 23:01:41,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:41,124 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091737514] [2021-11-02 23:01:41,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:41,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:41,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:41,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:41,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:41,334 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091737514] [2021-11-02 23:01:41,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091737514] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:41,335 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:41,335 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:41,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434316464] [2021-11-02 23:01:41,342 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:41,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:41,343 INFO L85 PathProgramCache]: Analyzing trace with hash -805039281, now seen corresponding path program 1 times [2021-11-02 23:01:41,344 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:41,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913862594] [2021-11-02 23:01:41,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:41,345 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:41,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:41,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:41,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:41,411 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913862594] [2021-11-02 23:01:41,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913862594] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:41,413 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:41,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:01:41,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379853288] [2021-11-02 23:01:41,415 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:41,417 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:41,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:41,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:41,436 INFO L87 Difference]: Start difference. First operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:41,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:41,511 INFO L93 Difference]: Finished difference Result 1148 states and 1720 transitions. [2021-11-02 23:01:41,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:41,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1148 states and 1720 transitions. [2021-11-02 23:01:41,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:41,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1148 states to 1143 states and 1715 transitions. [2021-11-02 23:01:41,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:41,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:41,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1715 transitions. [2021-11-02 23:01:41,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:41,551 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-02 23:01:41,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1715 transitions. [2021-11-02 23:01:41,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:41,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.500437445319335) internal successors, (1715), 1142 states have internal predecessors, (1715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:41,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1715 transitions. [2021-11-02 23:01:41,641 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-02 23:01:41,641 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-02 23:01:41,641 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-02 23:01:41,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1715 transitions. [2021-11-02 23:01:41,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:41,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:41,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:41,661 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,661 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:41,663 INFO L791 eck$LassoCheckResult]: Stem: 3177#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3178#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3437#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2380#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 2381#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2620#L655-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3336#L660-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2907#L665-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2908#L670-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3366#L675-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3367#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3405#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3399#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3400#L695-1 assume !(0 == ~M_E~0); 3430#L931-1 assume !(0 == ~T1_E~0); 3431#L936-1 assume !(0 == ~T2_E~0); 3435#L941-1 assume !(0 == ~T3_E~0); 2985#L946-1 assume !(0 == ~T4_E~0); 2986#L951-1 assume !(0 == ~T5_E~0); 2677#L956-1 assume !(0 == ~T6_E~0); 2678#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3124#L966-1 assume !(0 == ~T8_E~0); 3125#L971-1 assume !(0 == ~T9_E~0); 3247#L976-1 assume !(0 == ~E_M~0); 3222#L981-1 assume !(0 == ~E_1~0); 2994#L986-1 assume !(0 == ~E_2~0); 2736#L991-1 assume !(0 == ~E_3~0); 2737#L996-1 assume !(0 == ~E_4~0); 3421#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3175#L1006-1 assume !(0 == ~E_6~0); 3176#L1011-1 assume !(0 == ~E_7~0); 3406#L1016-1 assume !(0 == ~E_8~0); 3414#L1021-1 assume !(0 == ~E_9~0); 2338#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2339#L452 assume !(1 == ~m_pc~0); 2718#L452-2 is_master_triggered_~__retres1~0 := 0; 2719#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3103#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3170#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3325#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3213#L471 assume 1 == ~t1_pc~0; 3214#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2734#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2735#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3159#L1167 assume !(0 != activate_threads_~tmp___0~0); 2961#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2962#L490 assume !(1 == ~t2_pc~0); 3069#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 3070#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3108#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2669#L1175 assume !(0 != activate_threads_~tmp___1~0); 2670#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2947#L509 assume 1 == ~t3_pc~0; 2948#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2684#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2685#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3270#L1183 assume !(0 != activate_threads_~tmp___2~0); 3208#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3209#L528 assume !(1 == ~t4_pc~0); 3000#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 2956#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2957#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2720#L1191 assume !(0 != activate_threads_~tmp___3~0); 2721#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3254#L547 assume 1 == ~t5_pc~0; 3334#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3046#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2696#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2697#L1199 assume !(0 != activate_threads_~tmp___4~0); 2989#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3295#L566 assume !(1 == ~t6_pc~0); 2414#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 2413#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2739#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2651#L1207 assume !(0 != activate_threads_~tmp___5~0); 2520#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2521#L585 assume 1 == ~t7_pc~0; 2524#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2525#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3427#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3266#L1215 assume !(0 != activate_threads_~tmp___6~0); 3267#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3343#L604 assume 1 == ~t8_pc~0; 3344#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3319#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3164#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3165#L1223 assume !(0 != activate_threads_~tmp___7~0); 3401#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3396#L623 assume !(1 == ~t9_pc~0); 2367#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 2368#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3211#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3212#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 3073#L1231-2 assume !(1 == ~M_E~0); 3074#L1039-1 assume !(1 == ~T1_E~0); 3404#L1044-1 assume !(1 == ~T2_E~0); 2963#L1049-1 assume !(1 == ~T3_E~0); 2964#L1054-1 assume !(1 == ~T4_E~0); 3130#L1059-1 assume !(1 == ~T5_E~0); 2716#L1064-1 assume !(1 == ~T6_E~0); 2717#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3303#L1074-1 assume !(1 == ~T8_E~0); 3341#L1079-1 assume !(1 == ~T9_E~0); 3323#L1084-1 assume !(1 == ~E_M~0); 3324#L1089-1 assume !(1 == ~E_1~0); 3357#L1094-1 assume !(1 == ~E_2~0); 3027#L1099-1 assume !(1 == ~E_3~0); 3028#L1104-1 assume !(1 == ~E_4~0); 3216#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2854#L1114-1 assume !(1 == ~E_6~0); 2855#L1119-1 assume !(1 == ~E_7~0); 2909#L1124-1 assume !(1 == ~E_8~0); 2376#L1129-1 assume !(1 == ~E_9~0); 2377#L1420-1 [2021-11-02 23:01:41,665 INFO L793 eck$LassoCheckResult]: Loop: 2377#L1420-1 assume !false; 2930#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 2806#L906 assume !false; 2807#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 3204#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2348#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 3001#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3002#L775 assume !(0 != eval_~tmp~0); 3296#L921 start_simulation_~kernel_st~0 := 2; 3297#L643-1 start_simulation_~kernel_st~0 := 3; 3412#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3253#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2883#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2884#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3026#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2774#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2775#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3106#L961-3 assume !(0 == ~T7_E~0); 2893#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2894#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3150#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2398#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2399#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2378#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2379#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3234#L1001-3 assume !(0 == ~E_5~0); 2868#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2869#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3265#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3310#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3042#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3043#L452-33 assume 1 == ~m_pc~0; 2992#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2663#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2664#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3274#L1159-33 assume !(0 != activate_threads_~tmp~1); 3275#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3339#L471-33 assume 1 == ~t1_pc~0; 2771#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2772#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3377#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2313#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2314#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2828#L490-33 assume !(1 == ~t2_pc~0); 2829#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 2925#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3418#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3386#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3387#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2320#L509-33 assume 1 == ~t3_pc~0; 2321#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2484#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3133#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3058#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2532#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2533#L528-33 assume !(1 == ~t4_pc~0); 2579#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 2580#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2581#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2604#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3154#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2877#L547-33 assume !(1 == ~t5_pc~0); 2818#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 2819#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3128#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3183#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3302#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2463#L566-33 assume !(1 == ~t6_pc~0); 2464#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 2361#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2362#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2945#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3123#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2594#L585-33 assume 1 == ~t7_pc~0; 2595#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2662#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2906#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3168#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2942#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2943#L604-33 assume 1 == ~t8_pc~0; 2506#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2507#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2556#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 2557#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 3179#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3289#L623-33 assume 1 == ~t9_pc~0; 3434#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 2446#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3173#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3228#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 2504#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 2505#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3246#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2642#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2643#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2438#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2439#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2969#L1069-3 assume !(1 == ~T7_E~0); 2970#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3224#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3134#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3059#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3060#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2987#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2988#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3240#L1109-3 assume !(1 == ~E_5~0); 3226#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3227#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3433#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3439#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2726#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 2727#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2561#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 3304#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 3305#L1439 assume !(0 == start_simulation_~tmp~3); 3352#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 2843#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2626#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 3022#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 2881#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2882#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 2744#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 2745#L1452 assume !(0 != start_simulation_~tmp___0~1); 2377#L1420-1 [2021-11-02 23:01:41,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:41,666 INFO L85 PathProgramCache]: Analyzing trace with hash 1963205102, now seen corresponding path program 1 times [2021-11-02 23:01:41,667 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:41,667 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44346851] [2021-11-02 23:01:41,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:41,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:41,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:41,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:41,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:41,793 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44346851] [2021-11-02 23:01:41,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44346851] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:41,794 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:41,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:41,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972525455] [2021-11-02 23:01:41,796 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:41,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:41,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1897434016, now seen corresponding path program 1 times [2021-11-02 23:01:41,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:41,801 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671414899] [2021-11-02 23:01:41,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:41,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:41,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:41,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:41,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:41,933 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671414899] [2021-11-02 23:01:41,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671414899] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:41,934 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:41,934 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:41,934 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748256362] [2021-11-02 23:01:41,935 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:41,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:41,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:41,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:41,936 INFO L87 Difference]: Start difference. First operand 1143 states and 1715 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:41,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:41,970 INFO L93 Difference]: Finished difference Result 1143 states and 1714 transitions. [2021-11-02 23:01:41,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:41,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1714 transitions. [2021-11-02 23:01:41,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:41,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1714 transitions. [2021-11-02 23:01:41,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:41,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:41,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1714 transitions. [2021-11-02 23:01:41,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:42,000 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-02 23:01:42,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1714 transitions. [2021-11-02 23:01:42,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:42,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.499562554680665) internal successors, (1714), 1142 states have internal predecessors, (1714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1714 transitions. [2021-11-02 23:01:42,034 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-02 23:01:42,034 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-02 23:01:42,034 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-02 23:01:42,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1714 transitions. [2021-11-02 23:01:42,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:42,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:42,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,048 INFO L791 eck$LassoCheckResult]: Stem: 5472#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5473#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5732#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4675#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 4676#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4919#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5631#L660-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5202#L665-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5203#L670-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5661#L675-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5662#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5700#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5694#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5695#L695-1 assume !(0 == ~M_E~0); 5725#L931-1 assume !(0 == ~T1_E~0); 5726#L936-1 assume !(0 == ~T2_E~0); 5730#L941-1 assume !(0 == ~T3_E~0); 5280#L946-1 assume !(0 == ~T4_E~0); 5281#L951-1 assume !(0 == ~T5_E~0); 4972#L956-1 assume !(0 == ~T6_E~0); 4973#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5419#L966-1 assume !(0 == ~T8_E~0); 5420#L971-1 assume !(0 == ~T9_E~0); 5542#L976-1 assume !(0 == ~E_M~0); 5517#L981-1 assume !(0 == ~E_1~0); 5289#L986-1 assume !(0 == ~E_2~0); 5031#L991-1 assume !(0 == ~E_3~0); 5032#L996-1 assume !(0 == ~E_4~0); 5716#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5470#L1006-1 assume !(0 == ~E_6~0); 5471#L1011-1 assume !(0 == ~E_7~0); 5701#L1016-1 assume !(0 == ~E_8~0); 5709#L1021-1 assume !(0 == ~E_9~0); 4633#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4634#L452 assume !(1 == ~m_pc~0); 5013#L452-2 is_master_triggered_~__retres1~0 := 0; 5014#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5398#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5465#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5620#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5508#L471 assume 1 == ~t1_pc~0; 5509#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5029#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5030#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5455#L1167 assume !(0 != activate_threads_~tmp___0~0); 5256#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5257#L490 assume !(1 == ~t2_pc~0); 5364#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 5365#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5403#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4964#L1175 assume !(0 != activate_threads_~tmp___1~0); 4965#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5242#L509 assume 1 == ~t3_pc~0; 5243#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4979#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4980#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5565#L1183 assume !(0 != activate_threads_~tmp___2~0); 5503#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5504#L528 assume !(1 == ~t4_pc~0); 5295#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 5251#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5252#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5015#L1191 assume !(0 != activate_threads_~tmp___3~0); 5016#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5549#L547 assume 1 == ~t5_pc~0; 5629#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5341#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4991#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4992#L1199 assume !(0 != activate_threads_~tmp___4~0); 5284#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5590#L566 assume !(1 == ~t6_pc~0); 4711#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 4710#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5034#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4946#L1207 assume !(0 != activate_threads_~tmp___5~0); 4815#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4816#L585 assume 1 == ~t7_pc~0; 4819#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4820#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5722#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5561#L1215 assume !(0 != activate_threads_~tmp___6~0); 5562#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5638#L604 assume 1 == ~t8_pc~0; 5639#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5614#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5459#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5460#L1223 assume !(0 != activate_threads_~tmp___7~0); 5696#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5691#L623 assume !(1 == ~t9_pc~0); 4662#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 4663#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5506#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5507#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 5369#L1231-2 assume !(1 == ~M_E~0); 5370#L1039-1 assume !(1 == ~T1_E~0); 5699#L1044-1 assume !(1 == ~T2_E~0); 5260#L1049-1 assume !(1 == ~T3_E~0); 5261#L1054-1 assume !(1 == ~T4_E~0); 5425#L1059-1 assume !(1 == ~T5_E~0); 5011#L1064-1 assume !(1 == ~T6_E~0); 5012#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5598#L1074-1 assume !(1 == ~T8_E~0); 5636#L1079-1 assume !(1 == ~T9_E~0); 5618#L1084-1 assume !(1 == ~E_M~0); 5619#L1089-1 assume !(1 == ~E_1~0); 5652#L1094-1 assume !(1 == ~E_2~0); 5322#L1099-1 assume !(1 == ~E_3~0); 5323#L1104-1 assume !(1 == ~E_4~0); 5511#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5150#L1114-1 assume !(1 == ~E_6~0); 5151#L1119-1 assume !(1 == ~E_7~0); 5204#L1124-1 assume !(1 == ~E_8~0); 4671#L1129-1 assume !(1 == ~E_9~0); 4672#L1420-1 [2021-11-02 23:01:42,049 INFO L793 eck$LassoCheckResult]: Loop: 4672#L1420-1 assume !false; 5227#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 5101#L906 assume !false; 5102#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 5499#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4643#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 5297#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5298#L775 assume !(0 != eval_~tmp~0); 5591#L921 start_simulation_~kernel_st~0 := 2; 5592#L643-1 start_simulation_~kernel_st~0 := 3; 5707#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5548#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5178#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5179#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5321#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5069#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5070#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5401#L961-3 assume !(0 == ~T7_E~0); 5188#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5189#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5445#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4693#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4694#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4673#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4674#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5529#L1001-3 assume !(0 == ~E_5~0); 5163#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5164#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5560#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5607#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5337#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5338#L452-33 assume 1 == ~m_pc~0; 5287#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4958#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4959#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5570#L1159-33 assume !(0 != activate_threads_~tmp~1); 5571#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5634#L471-33 assume 1 == ~t1_pc~0; 5066#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5067#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5673#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4608#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4609#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5125#L490-33 assume !(1 == ~t2_pc~0); 5126#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 5220#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5713#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5681#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5682#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4615#L509-33 assume 1 == ~t3_pc~0; 4616#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4776#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5428#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5353#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4827#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4828#L528-33 assume 1 == ~t4_pc~0; 5569#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4872#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4876#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4899#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5449#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5170#L547-33 assume 1 == ~t5_pc~0; 5171#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5111#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5423#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5478#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5596#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4758#L566-33 assume !(1 == ~t6_pc~0); 4759#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 4658#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4659#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5240#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5418#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4894#L585-33 assume !(1 == ~t7_pc~0); 4896#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 4957#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5201#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5463#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5237#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5238#L604-33 assume 1 == ~t8_pc~0; 4804#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4805#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4851#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4852#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5474#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5584#L623-33 assume 1 == ~t9_pc~0; 5729#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 4741#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5468#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5523#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 4799#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 4800#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5541#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4937#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4938#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4733#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4734#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5264#L1069-3 assume !(1 == ~T7_E~0); 5265#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5519#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5429#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5356#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5357#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5282#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5283#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5535#L1109-3 assume !(1 == ~E_5~0); 5521#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5522#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5728#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5734#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5021#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 5022#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4856#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 5599#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 5600#L1439 assume !(0 == start_simulation_~tmp~3); 5647#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 5138#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4921#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 5317#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 5176#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5177#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 5039#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 5040#L1452 assume !(0 != start_simulation_~tmp___0~1); 4672#L1420-1 [2021-11-02 23:01:42,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,050 INFO L85 PathProgramCache]: Analyzing trace with hash -358596816, now seen corresponding path program 1 times [2021-11-02 23:01:42,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,051 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346663373] [2021-11-02 23:01:42,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,051 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,105 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346663373] [2021-11-02 23:01:42,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346663373] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,105 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,106 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,106 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100977094] [2021-11-02 23:01:42,107 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:42,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1304624577, now seen corresponding path program 1 times [2021-11-02 23:01:42,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,108 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720220479] [2021-11-02 23:01:42,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,178 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,179 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720220479] [2021-11-02 23:01:42,179 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720220479] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,179 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,180 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,180 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288683526] [2021-11-02 23:01:42,181 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:42,181 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:42,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:42,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:42,182 INFO L87 Difference]: Start difference. First operand 1143 states and 1714 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:42,211 INFO L93 Difference]: Finished difference Result 1143 states and 1713 transitions. [2021-11-02 23:01:42,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:42,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1713 transitions. [2021-11-02 23:01:42,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1713 transitions. [2021-11-02 23:01:42,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:42,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:42,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1713 transitions. [2021-11-02 23:01:42,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:42,242 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-02 23:01:42,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1713 transitions. [2021-11-02 23:01:42,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:42,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4986876640419948) internal successors, (1713), 1142 states have internal predecessors, (1713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1713 transitions. [2021-11-02 23:01:42,278 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-02 23:01:42,279 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-02 23:01:42,279 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-02 23:01:42,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1713 transitions. [2021-11-02 23:01:42,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:42,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:42,292 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,292 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,293 INFO L791 eck$LassoCheckResult]: Stem: 7765#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7766#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8025#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6968#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 6969#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7212#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7924#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7497#L665-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7498#L670-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7954#L675-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7955#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7993#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7987#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7988#L695-1 assume !(0 == ~M_E~0); 8018#L931-1 assume !(0 == ~T1_E~0); 8019#L936-1 assume !(0 == ~T2_E~0); 8023#L941-1 assume !(0 == ~T3_E~0); 7573#L946-1 assume !(0 == ~T4_E~0); 7574#L951-1 assume !(0 == ~T5_E~0); 7265#L956-1 assume !(0 == ~T6_E~0); 7266#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7712#L966-1 assume !(0 == ~T8_E~0); 7713#L971-1 assume !(0 == ~T9_E~0); 7835#L976-1 assume !(0 == ~E_M~0); 7811#L981-1 assume !(0 == ~E_1~0); 7582#L986-1 assume !(0 == ~E_2~0); 7324#L991-1 assume !(0 == ~E_3~0); 7325#L996-1 assume !(0 == ~E_4~0); 8009#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 7763#L1006-1 assume !(0 == ~E_6~0); 7764#L1011-1 assume !(0 == ~E_7~0); 7994#L1016-1 assume !(0 == ~E_8~0); 8002#L1021-1 assume !(0 == ~E_9~0); 6926#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6927#L452 assume !(1 == ~m_pc~0); 7306#L452-2 is_master_triggered_~__retres1~0 := 0; 7307#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7691#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7758#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7913#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7801#L471 assume 1 == ~t1_pc~0; 7802#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7322#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7323#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7748#L1167 assume !(0 != activate_threads_~tmp___0~0); 7549#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7550#L490 assume !(1 == ~t2_pc~0); 7657#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 7658#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7696#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7257#L1175 assume !(0 != activate_threads_~tmp___1~0); 7258#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7535#L509 assume 1 == ~t3_pc~0; 7536#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7274#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7275#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7858#L1183 assume !(0 != activate_threads_~tmp___2~0); 7796#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7797#L528 assume !(1 == ~t4_pc~0); 7588#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 7544#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7545#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7308#L1191 assume !(0 != activate_threads_~tmp___3~0); 7309#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7842#L547 assume 1 == ~t5_pc~0; 7922#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7634#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7284#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7285#L1199 assume !(0 != activate_threads_~tmp___4~0); 7577#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7883#L566 assume !(1 == ~t6_pc~0); 7007#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 7006#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7327#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 7239#L1207 assume !(0 != activate_threads_~tmp___5~0); 7108#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7109#L585 assume 1 == ~t7_pc~0; 7112#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7113#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8015#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7854#L1215 assume !(0 != activate_threads_~tmp___6~0); 7855#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7931#L604 assume 1 == ~t8_pc~0; 7932#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7907#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7752#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7753#L1223 assume !(0 != activate_threads_~tmp___7~0); 7989#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7984#L623 assume !(1 == ~t9_pc~0); 6955#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 6956#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7799#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7800#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 7662#L1231-2 assume !(1 == ~M_E~0); 7663#L1039-1 assume !(1 == ~T1_E~0); 7992#L1044-1 assume !(1 == ~T2_E~0); 7553#L1049-1 assume !(1 == ~T3_E~0); 7554#L1054-1 assume !(1 == ~T4_E~0); 7718#L1059-1 assume !(1 == ~T5_E~0); 7304#L1064-1 assume !(1 == ~T6_E~0); 7305#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7891#L1074-1 assume !(1 == ~T8_E~0); 7929#L1079-1 assume !(1 == ~T9_E~0); 7911#L1084-1 assume !(1 == ~E_M~0); 7912#L1089-1 assume !(1 == ~E_1~0); 7945#L1094-1 assume !(1 == ~E_2~0); 7615#L1099-1 assume !(1 == ~E_3~0); 7616#L1104-1 assume !(1 == ~E_4~0); 7804#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7443#L1114-1 assume !(1 == ~E_6~0); 7444#L1119-1 assume !(1 == ~E_7~0); 7499#L1124-1 assume !(1 == ~E_8~0); 6964#L1129-1 assume !(1 == ~E_9~0); 6965#L1420-1 [2021-11-02 23:01:42,294 INFO L793 eck$LassoCheckResult]: Loop: 6965#L1420-1 assume !false; 7520#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 7394#L906 assume !false; 7395#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7792#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 6941#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 7590#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7591#L775 assume !(0 != eval_~tmp~0); 7884#L921 start_simulation_~kernel_st~0 := 2; 7885#L643-1 start_simulation_~kernel_st~0 := 3; 8000#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7841#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7471#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7472#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7614#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7362#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7363#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7694#L961-3 assume !(0 == ~T7_E~0); 7481#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7482#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7738#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6986#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6987#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6966#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6967#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7822#L1001-3 assume !(0 == ~E_5~0); 7456#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7457#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7853#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7900#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7630#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7631#L452-33 assume 1 == ~m_pc~0; 7580#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7251#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7252#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7862#L1159-33 assume !(0 != activate_threads_~tmp~1); 7863#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7925#L471-33 assume !(1 == ~t1_pc~0); 7361#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 7360#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7965#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6901#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6902#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7413#L490-33 assume !(1 == ~t2_pc~0); 7414#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 7510#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8006#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7974#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7975#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6908#L509-33 assume 1 == ~t3_pc~0; 6909#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7072#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7721#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7646#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7120#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7121#L528-33 assume 1 == ~t4_pc~0; 7864#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7168#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7169#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7192#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7742#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7465#L547-33 assume 1 == ~t5_pc~0; 7466#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7407#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7716#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7771#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7889#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7051#L566-33 assume !(1 == ~t6_pc~0); 7052#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 6951#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6952#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 7533#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7711#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7187#L585-33 assume 1 == ~t7_pc~0; 7188#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7250#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7496#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7756#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7530#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7531#L604-33 assume 1 == ~t8_pc~0; 7097#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7098#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7144#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7145#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 7767#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7877#L623-33 assume 1 == ~t9_pc~0; 8022#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 7034#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7761#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7816#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 7092#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 7093#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7834#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7230#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7231#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7026#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7027#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7557#L1069-3 assume !(1 == ~T7_E~0); 7558#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7812#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7725#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7649#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7650#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7575#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7576#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7829#L1109-3 assume !(1 == ~E_5~0); 7814#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7815#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8021#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8027#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7314#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7315#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 7149#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 7892#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 7893#L1439 assume !(0 == start_simulation_~tmp~3); 7940#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7431#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 7214#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 7610#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 7469#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7470#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 7332#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 7333#L1452 assume !(0 != start_simulation_~tmp___0~1); 6965#L1420-1 [2021-11-02 23:01:42,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1783263662, now seen corresponding path program 1 times [2021-11-02 23:01:42,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,296 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180937661] [2021-11-02 23:01:42,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,297 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180937661] [2021-11-02 23:01:42,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180937661] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,420 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643997810] [2021-11-02 23:01:42,421 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:42,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,422 INFO L85 PathProgramCache]: Analyzing trace with hash -338085311, now seen corresponding path program 1 times [2021-11-02 23:01:42,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,422 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236192124] [2021-11-02 23:01:42,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,492 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,498 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236192124] [2021-11-02 23:01:42,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236192124] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,498 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705111436] [2021-11-02 23:01:42,500 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:42,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:42,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:42,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:42,508 INFO L87 Difference]: Start difference. First operand 1143 states and 1713 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:42,534 INFO L93 Difference]: Finished difference Result 1143 states and 1712 transitions. [2021-11-02 23:01:42,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:42,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1712 transitions. [2021-11-02 23:01:42,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1712 transitions. [2021-11-02 23:01:42,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:42,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:42,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1712 transitions. [2021-11-02 23:01:42,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:42,564 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-02 23:01:42,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1712 transitions. [2021-11-02 23:01:42,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:42,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4978127734033246) internal successors, (1712), 1142 states have internal predecessors, (1712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1712 transitions. [2021-11-02 23:01:42,595 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-02 23:01:42,596 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-02 23:01:42,596 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-02 23:01:42,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1712 transitions. [2021-11-02 23:01:42,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:42,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:42,613 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,613 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,614 INFO L791 eck$LassoCheckResult]: Stem: 10058#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10059#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10318#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9261#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 9262#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9505#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10217#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9790#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9791#L670-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10247#L675-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10248#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10286#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10280#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10281#L695-1 assume !(0 == ~M_E~0); 10312#L931-1 assume !(0 == ~T1_E~0); 10313#L936-1 assume !(0 == ~T2_E~0); 10316#L941-1 assume !(0 == ~T3_E~0); 9866#L946-1 assume !(0 == ~T4_E~0); 9867#L951-1 assume !(0 == ~T5_E~0); 9558#L956-1 assume !(0 == ~T6_E~0); 9559#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10005#L966-1 assume !(0 == ~T8_E~0); 10006#L971-1 assume !(0 == ~T9_E~0); 10128#L976-1 assume !(0 == ~E_M~0); 10104#L981-1 assume !(0 == ~E_1~0); 9877#L986-1 assume !(0 == ~E_2~0); 9617#L991-1 assume !(0 == ~E_3~0); 9618#L996-1 assume !(0 == ~E_4~0); 10302#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10056#L1006-1 assume !(0 == ~E_6~0); 10057#L1011-1 assume !(0 == ~E_7~0); 10287#L1016-1 assume !(0 == ~E_8~0); 10295#L1021-1 assume !(0 == ~E_9~0); 9219#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9220#L452 assume !(1 == ~m_pc~0); 9599#L452-2 is_master_triggered_~__retres1~0 := 0; 9600#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9984#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10051#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10206#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10094#L471 assume 1 == ~t1_pc~0; 10095#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9615#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9616#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10041#L1167 assume !(0 != activate_threads_~tmp___0~0); 9842#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9843#L490 assume !(1 == ~t2_pc~0); 9950#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 9951#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9989#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9551#L1175 assume !(0 != activate_threads_~tmp___1~0); 9552#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9828#L509 assume 1 == ~t3_pc~0; 9829#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9569#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9570#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10151#L1183 assume !(0 != activate_threads_~tmp___2~0); 10089#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10090#L528 assume !(1 == ~t4_pc~0); 9881#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 9837#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9838#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9601#L1191 assume !(0 != activate_threads_~tmp___3~0); 9602#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10135#L547 assume 1 == ~t5_pc~0; 10215#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9927#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9577#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9578#L1199 assume !(0 != activate_threads_~tmp___4~0); 9870#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10176#L566 assume !(1 == ~t6_pc~0); 9300#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 9299#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9620#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9534#L1207 assume !(0 != activate_threads_~tmp___5~0); 9401#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9402#L585 assume 1 == ~t7_pc~0; 9405#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9406#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10308#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10147#L1215 assume !(0 != activate_threads_~tmp___6~0); 10148#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10226#L604 assume 1 == ~t8_pc~0; 10227#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10200#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10045#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 10046#L1223 assume !(0 != activate_threads_~tmp___7~0); 10282#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 10277#L623 assume !(1 == ~t9_pc~0); 9248#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 9249#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 10092#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 10093#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 9955#L1231-2 assume !(1 == ~M_E~0); 9956#L1039-1 assume !(1 == ~T1_E~0); 10285#L1044-1 assume !(1 == ~T2_E~0); 9846#L1049-1 assume !(1 == ~T3_E~0); 9847#L1054-1 assume !(1 == ~T4_E~0); 10012#L1059-1 assume !(1 == ~T5_E~0); 9597#L1064-1 assume !(1 == ~T6_E~0); 9598#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10184#L1074-1 assume !(1 == ~T8_E~0); 10222#L1079-1 assume !(1 == ~T9_E~0); 10204#L1084-1 assume !(1 == ~E_M~0); 10205#L1089-1 assume !(1 == ~E_1~0); 10238#L1094-1 assume !(1 == ~E_2~0); 9908#L1099-1 assume !(1 == ~E_3~0); 9909#L1104-1 assume !(1 == ~E_4~0); 10097#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9736#L1114-1 assume !(1 == ~E_6~0); 9737#L1119-1 assume !(1 == ~E_7~0); 9792#L1124-1 assume !(1 == ~E_8~0); 9259#L1129-1 assume !(1 == ~E_9~0); 9260#L1420-1 [2021-11-02 23:01:42,615 INFO L793 eck$LassoCheckResult]: Loop: 9260#L1420-1 assume !false; 9814#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 9687#L906 assume !false; 9688#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 10085#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9234#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 9883#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9884#L775 assume !(0 != eval_~tmp~0); 10177#L921 start_simulation_~kernel_st~0 := 2; 10178#L643-1 start_simulation_~kernel_st~0 := 3; 10293#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10134#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9764#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9765#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9907#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9655#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9656#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9987#L961-3 assume !(0 == ~T7_E~0); 9774#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9775#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10031#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9279#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9280#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9257#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9258#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10115#L1001-3 assume !(0 == ~E_5~0); 9749#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9750#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10146#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10191#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9923#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9924#L452-33 assume 1 == ~m_pc~0; 9873#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9544#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9545#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10155#L1159-33 assume !(0 != activate_threads_~tmp~1); 10156#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10220#L471-33 assume 1 == ~t1_pc~0; 9652#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9653#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10258#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9194#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9195#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9709#L490-33 assume !(1 == ~t2_pc~0); 9710#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 9806#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10299#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10267#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10268#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9201#L509-33 assume 1 == ~t3_pc~0; 9202#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9365#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10014#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9939#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9413#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9414#L528-33 assume !(1 == ~t4_pc~0); 9460#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 9461#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9462#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9485#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10035#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9758#L547-33 assume !(1 == ~t5_pc~0); 9699#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 9700#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10009#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10064#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10183#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9344#L566-33 assume !(1 == ~t6_pc~0); 9345#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 9244#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9245#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9826#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10004#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9482#L585-33 assume 1 == ~t7_pc~0; 9483#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9543#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9789#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10049#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9823#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9824#L604-33 assume !(1 == ~t8_pc~0); 9392#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 9391#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9439#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9440#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 10060#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 10170#L623-33 assume !(1 == ~t9_pc~0); 9329#L623-35 is_transmit9_triggered_~__retres1~9 := 0; 9330#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 10054#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 10109#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 9385#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 9386#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10127#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9525#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9526#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9319#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9320#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9850#L1069-3 assume !(1 == ~T7_E~0); 9851#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10105#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10018#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9942#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9943#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9868#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9869#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10122#L1109-3 assume !(1 == ~E_5~0); 10107#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10108#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10314#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10320#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9607#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 9608#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9442#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 10185#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 10186#L1439 assume !(0 == start_simulation_~tmp~3); 10233#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 9724#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9507#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 9904#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 9762#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9763#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 9625#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 9626#L1452 assume !(0 != start_simulation_~tmp___0~1); 9260#L1420-1 [2021-11-02 23:01:42,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1888422032, now seen corresponding path program 1 times [2021-11-02 23:01:42,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,617 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342823665] [2021-11-02 23:01:42,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,674 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342823665] [2021-11-02 23:01:42,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342823665] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,674 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,675 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,675 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054961813] [2021-11-02 23:01:42,676 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:42,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1645751262, now seen corresponding path program 1 times [2021-11-02 23:01:42,677 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,677 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928742047] [2021-11-02 23:01:42,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,677 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,742 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,743 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928742047] [2021-11-02 23:01:42,744 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928742047] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,745 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,745 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:42,746 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349887427] [2021-11-02 23:01:42,746 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:42,747 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:42,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:42,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:42,748 INFO L87 Difference]: Start difference. First operand 1143 states and 1712 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:42,783 INFO L93 Difference]: Finished difference Result 1143 states and 1711 transitions. [2021-11-02 23:01:42,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:42,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1711 transitions. [2021-11-02 23:01:42,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1711 transitions. [2021-11-02 23:01:42,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:42,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:42,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1711 transitions. [2021-11-02 23:01:42,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:42,817 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-02 23:01:42,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1711 transitions. [2021-11-02 23:01:42,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:42,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4969378827646544) internal successors, (1711), 1142 states have internal predecessors, (1711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:42,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1711 transitions. [2021-11-02 23:01:42,850 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-02 23:01:42,850 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-02 23:01:42,850 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-02 23:01:42,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1711 transitions. [2021-11-02 23:01:42,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:42,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:42,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:42,863 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:42,864 INFO L791 eck$LassoCheckResult]: Stem: 12353#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12354#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12613#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11556#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 11557#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11796#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12512#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12082#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12083#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12542#L675-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12543#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12581#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12575#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12576#L695-1 assume !(0 == ~M_E~0); 12606#L931-1 assume !(0 == ~T1_E~0); 12607#L936-1 assume !(0 == ~T2_E~0); 12611#L941-1 assume !(0 == ~T3_E~0); 12161#L946-1 assume !(0 == ~T4_E~0); 12162#L951-1 assume !(0 == ~T5_E~0); 11851#L956-1 assume !(0 == ~T6_E~0); 11852#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12299#L966-1 assume !(0 == ~T8_E~0); 12300#L971-1 assume !(0 == ~T9_E~0); 12423#L976-1 assume !(0 == ~E_M~0); 12398#L981-1 assume !(0 == ~E_1~0); 12170#L986-1 assume !(0 == ~E_2~0); 11912#L991-1 assume !(0 == ~E_3~0); 11913#L996-1 assume !(0 == ~E_4~0); 12597#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12351#L1006-1 assume !(0 == ~E_6~0); 12352#L1011-1 assume !(0 == ~E_7~0); 12582#L1016-1 assume !(0 == ~E_8~0); 12590#L1021-1 assume !(0 == ~E_9~0); 11514#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11515#L452 assume !(1 == ~m_pc~0); 11894#L452-2 is_master_triggered_~__retres1~0 := 0; 11895#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12279#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12345#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12501#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12389#L471 assume 1 == ~t1_pc~0; 12390#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11910#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11911#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12335#L1167 assume !(0 != activate_threads_~tmp___0~0); 12137#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12138#L490 assume !(1 == ~t2_pc~0); 12245#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 12246#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12284#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11845#L1175 assume !(0 != activate_threads_~tmp___1~0); 11846#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12123#L509 assume 1 == ~t3_pc~0; 12124#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11860#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11861#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12446#L1183 assume !(0 != activate_threads_~tmp___2~0); 12384#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12385#L528 assume !(1 == ~t4_pc~0); 12175#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 12132#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12133#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 11896#L1191 assume !(0 != activate_threads_~tmp___3~0); 11897#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12430#L547 assume 1 == ~t5_pc~0; 12510#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12222#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11872#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11873#L1199 assume !(0 != activate_threads_~tmp___4~0); 12165#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12471#L566 assume !(1 == ~t6_pc~0); 11590#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 11589#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11915#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 11827#L1207 assume !(0 != activate_threads_~tmp___5~0); 11694#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11695#L585 assume 1 == ~t7_pc~0; 11700#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11701#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12603#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12442#L1215 assume !(0 != activate_threads_~tmp___6~0); 12443#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12519#L604 assume 1 == ~t8_pc~0; 12520#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12495#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12340#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12341#L1223 assume !(0 != activate_threads_~tmp___7~0); 12577#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12572#L623 assume !(1 == ~t9_pc~0); 11543#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 11544#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12387#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12388#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 12249#L1231-2 assume !(1 == ~M_E~0); 12250#L1039-1 assume !(1 == ~T1_E~0); 12580#L1044-1 assume !(1 == ~T2_E~0); 12139#L1049-1 assume !(1 == ~T3_E~0); 12140#L1054-1 assume !(1 == ~T4_E~0); 12306#L1059-1 assume !(1 == ~T5_E~0); 11892#L1064-1 assume !(1 == ~T6_E~0); 11893#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12479#L1074-1 assume !(1 == ~T8_E~0); 12517#L1079-1 assume !(1 == ~T9_E~0); 12499#L1084-1 assume !(1 == ~E_M~0); 12500#L1089-1 assume !(1 == ~E_1~0); 12533#L1094-1 assume !(1 == ~E_2~0); 12203#L1099-1 assume !(1 == ~E_3~0); 12204#L1104-1 assume !(1 == ~E_4~0); 12392#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12030#L1114-1 assume !(1 == ~E_6~0); 12031#L1119-1 assume !(1 == ~E_7~0); 12084#L1124-1 assume !(1 == ~E_8~0); 11552#L1129-1 assume !(1 == ~E_9~0); 11553#L1420-1 [2021-11-02 23:01:42,864 INFO L793 eck$LassoCheckResult]: Loop: 11553#L1420-1 assume !false; 12106#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 11982#L906 assume !false; 11983#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 12380#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11524#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 12177#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12178#L775 assume !(0 != eval_~tmp~0); 12472#L921 start_simulation_~kernel_st~0 := 2; 12473#L643-1 start_simulation_~kernel_st~0 := 3; 12588#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12429#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12059#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12060#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12202#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11950#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11951#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12282#L961-3 assume !(0 == ~T7_E~0); 12069#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12070#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12326#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11574#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11575#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11554#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11555#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12410#L1001-3 assume !(0 == ~E_5~0); 12044#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12045#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12441#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12486#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12218#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12219#L452-33 assume 1 == ~m_pc~0; 12168#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11839#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11840#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12450#L1159-33 assume !(0 != activate_threads_~tmp~1); 12451#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12515#L471-33 assume 1 == ~t1_pc~0; 11947#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11948#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12553#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11489#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11490#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12004#L490-33 assume !(1 == ~t2_pc~0); 12005#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 12101#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12594#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12562#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12563#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11496#L509-33 assume 1 == ~t3_pc~0; 11497#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11660#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12309#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12234#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11708#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11709#L528-33 assume 1 == ~t4_pc~0; 12452#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11756#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11757#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 11780#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12330#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12053#L547-33 assume 1 == ~t5_pc~0; 12054#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11995#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12304#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12359#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12478#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11639#L566-33 assume !(1 == ~t6_pc~0); 11640#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 11539#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11540#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12121#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12301#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11777#L585-33 assume 1 == ~t7_pc~0; 11778#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11838#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12087#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12344#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12118#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12119#L604-33 assume 1 == ~t8_pc~0; 11685#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11686#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11734#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 11735#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12355#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12465#L623-33 assume 1 == ~t9_pc~0; 12610#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 11625#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12349#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12404#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 11680#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 11681#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12422#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11820#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11821#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11614#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11615#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12145#L1069-3 assume !(1 == ~T7_E~0); 12146#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12400#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12313#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12237#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12238#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12163#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12164#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12417#L1109-3 assume !(1 == ~E_5~0); 12402#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12403#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12609#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12615#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11902#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 11903#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11737#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 12480#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 12481#L1439 assume !(0 == start_simulation_~tmp~3); 12528#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 12019#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11802#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 12199#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 12057#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12058#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 11920#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 11921#L1452 assume !(0 != start_simulation_~tmp___0~1); 11553#L1420-1 [2021-11-02 23:01:42,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,865 INFO L85 PathProgramCache]: Analyzing trace with hash -2006863506, now seen corresponding path program 1 times [2021-11-02 23:01:42,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,866 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711061448] [2021-11-02 23:01:42,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,906 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,906 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711061448] [2021-11-02 23:01:42,907 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711061448] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,907 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957317235] [2021-11-02 23:01:42,908 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:42,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:42,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1260005662, now seen corresponding path program 1 times [2021-11-02 23:01:42,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:42,909 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982858606] [2021-11-02 23:01:42,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:42,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:42,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:42,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:42,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:42,973 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982858606] [2021-11-02 23:01:42,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982858606] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:42,974 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:42,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:42,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250631334] [2021-11-02 23:01:42,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:42,982 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:42,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:42,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:42,984 INFO L87 Difference]: Start difference. First operand 1143 states and 1711 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:43,010 INFO L93 Difference]: Finished difference Result 1143 states and 1710 transitions. [2021-11-02 23:01:43,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:43,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1710 transitions. [2021-11-02 23:01:43,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1710 transitions. [2021-11-02 23:01:43,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:43,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:43,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1710 transitions. [2021-11-02 23:01:43,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:43,041 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-02 23:01:43,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1710 transitions. [2021-11-02 23:01:43,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:43,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4960629921259843) internal successors, (1710), 1142 states have internal predecessors, (1710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1710 transitions. [2021-11-02 23:01:43,111 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-02 23:01:43,111 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-02 23:01:43,111 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-02 23:01:43,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1710 transitions. [2021-11-02 23:01:43,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:43,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:43,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,127 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,127 INFO L791 eck$LassoCheckResult]: Stem: 14646#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14647#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14906#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13849#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 13850#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14089#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14805#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14375#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14376#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14835#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14836#L680-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14874#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14868#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14869#L695-1 assume !(0 == ~M_E~0); 14899#L931-1 assume !(0 == ~T1_E~0); 14900#L936-1 assume !(0 == ~T2_E~0); 14904#L941-1 assume !(0 == ~T3_E~0); 14454#L946-1 assume !(0 == ~T4_E~0); 14455#L951-1 assume !(0 == ~T5_E~0); 14144#L956-1 assume !(0 == ~T6_E~0); 14145#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14592#L966-1 assume !(0 == ~T8_E~0); 14593#L971-1 assume !(0 == ~T9_E~0); 14716#L976-1 assume !(0 == ~E_M~0); 14691#L981-1 assume !(0 == ~E_1~0); 14463#L986-1 assume !(0 == ~E_2~0); 14205#L991-1 assume !(0 == ~E_3~0); 14206#L996-1 assume !(0 == ~E_4~0); 14890#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14644#L1006-1 assume !(0 == ~E_6~0); 14645#L1011-1 assume !(0 == ~E_7~0); 14875#L1016-1 assume !(0 == ~E_8~0); 14883#L1021-1 assume !(0 == ~E_9~0); 13807#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13808#L452 assume !(1 == ~m_pc~0); 14187#L452-2 is_master_triggered_~__retres1~0 := 0; 14188#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14572#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14638#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14794#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14682#L471 assume 1 == ~t1_pc~0; 14683#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14203#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14204#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14628#L1167 assume !(0 != activate_threads_~tmp___0~0); 14430#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14431#L490 assume !(1 == ~t2_pc~0); 14538#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 14539#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14577#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14138#L1175 assume !(0 != activate_threads_~tmp___1~0); 14139#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14416#L509 assume 1 == ~t3_pc~0; 14417#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14153#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14154#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14739#L1183 assume !(0 != activate_threads_~tmp___2~0); 14677#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14678#L528 assume !(1 == ~t4_pc~0); 14468#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 14425#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14426#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14189#L1191 assume !(0 != activate_threads_~tmp___3~0); 14190#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14723#L547 assume 1 == ~t5_pc~0; 14803#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14515#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14165#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14166#L1199 assume !(0 != activate_threads_~tmp___4~0); 14458#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14764#L566 assume !(1 == ~t6_pc~0); 13883#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 13882#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14208#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14120#L1207 assume !(0 != activate_threads_~tmp___5~0); 13987#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13988#L585 assume 1 == ~t7_pc~0; 13993#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13994#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14896#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14735#L1215 assume !(0 != activate_threads_~tmp___6~0); 14736#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14812#L604 assume 1 == ~t8_pc~0; 14813#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14788#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14633#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14634#L1223 assume !(0 != activate_threads_~tmp___7~0); 14870#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 14865#L623 assume !(1 == ~t9_pc~0); 13836#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 13837#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 14680#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 14681#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 14542#L1231-2 assume !(1 == ~M_E~0); 14543#L1039-1 assume !(1 == ~T1_E~0); 14873#L1044-1 assume !(1 == ~T2_E~0); 14432#L1049-1 assume !(1 == ~T3_E~0); 14433#L1054-1 assume !(1 == ~T4_E~0); 14599#L1059-1 assume !(1 == ~T5_E~0); 14185#L1064-1 assume !(1 == ~T6_E~0); 14186#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14772#L1074-1 assume !(1 == ~T8_E~0); 14810#L1079-1 assume !(1 == ~T9_E~0); 14792#L1084-1 assume !(1 == ~E_M~0); 14793#L1089-1 assume !(1 == ~E_1~0); 14826#L1094-1 assume !(1 == ~E_2~0); 14496#L1099-1 assume !(1 == ~E_3~0); 14497#L1104-1 assume !(1 == ~E_4~0); 14685#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14323#L1114-1 assume !(1 == ~E_6~0); 14324#L1119-1 assume !(1 == ~E_7~0); 14377#L1124-1 assume !(1 == ~E_8~0); 13845#L1129-1 assume !(1 == ~E_9~0); 13846#L1420-1 [2021-11-02 23:01:43,127 INFO L793 eck$LassoCheckResult]: Loop: 13846#L1420-1 assume !false; 14399#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 14275#L906 assume !false; 14276#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14673#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 13817#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 14470#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 14471#L775 assume !(0 != eval_~tmp~0); 14765#L921 start_simulation_~kernel_st~0 := 2; 14766#L643-1 start_simulation_~kernel_st~0 := 3; 14881#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14722#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14352#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14353#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14495#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14243#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14244#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14575#L961-3 assume !(0 == ~T7_E~0); 14362#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14363#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14619#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13867#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13868#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13847#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13848#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14703#L1001-3 assume !(0 == ~E_5~0); 14337#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14338#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14734#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14779#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14511#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14512#L452-33 assume 1 == ~m_pc~0; 14461#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14132#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14133#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14743#L1159-33 assume !(0 != activate_threads_~tmp~1); 14744#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14808#L471-33 assume 1 == ~t1_pc~0; 14240#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14241#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14846#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13782#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13783#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14297#L490-33 assume !(1 == ~t2_pc~0); 14298#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 14394#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14887#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14855#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14856#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13789#L509-33 assume 1 == ~t3_pc~0; 13790#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13953#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14602#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14527#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14001#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14002#L528-33 assume !(1 == ~t4_pc~0); 14048#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 14049#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14050#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14073#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14623#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14346#L547-33 assume 1 == ~t5_pc~0; 14347#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14288#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14597#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14652#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14771#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13932#L566-33 assume !(1 == ~t6_pc~0); 13933#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 13832#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13833#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14414#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14594#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14070#L585-33 assume 1 == ~t7_pc~0; 14071#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14131#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14380#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14637#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14411#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14412#L604-33 assume 1 == ~t8_pc~0; 13978#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13979#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14027#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14028#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 14648#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 14758#L623-33 assume 1 == ~t9_pc~0; 14903#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 13918#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 14642#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 14697#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 13973#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 13974#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14715#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14113#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14114#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13907#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13908#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14438#L1069-3 assume !(1 == ~T7_E~0); 14439#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14693#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14606#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14530#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14531#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14456#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14457#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14710#L1109-3 assume !(1 == ~E_5~0); 14695#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14696#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14902#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14908#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14195#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14196#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 14030#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 14773#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 14774#L1439 assume !(0 == start_simulation_~tmp~3); 14821#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14312#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 14095#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 14492#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 14350#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14351#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 14213#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 14214#L1452 assume !(0 != start_simulation_~tmp___0~1); 13846#L1420-1 [2021-11-02 23:01:43,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,128 INFO L85 PathProgramCache]: Analyzing trace with hash 898809776, now seen corresponding path program 1 times [2021-11-02 23:01:43,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,129 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413851071] [2021-11-02 23:01:43,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,186 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413851071] [2021-11-02 23:01:43,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413851071] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,187 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,187 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,187 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76224344] [2021-11-02 23:01:43,188 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:43,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,188 INFO L85 PathProgramCache]: Analyzing trace with hash 577807361, now seen corresponding path program 1 times [2021-11-02 23:01:43,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,190 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867889909] [2021-11-02 23:01:43,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,190 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,252 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867889909] [2021-11-02 23:01:43,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867889909] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,252 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337101588] [2021-11-02 23:01:43,253 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:43,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:43,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:43,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:43,255 INFO L87 Difference]: Start difference. First operand 1143 states and 1710 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:43,282 INFO L93 Difference]: Finished difference Result 1143 states and 1709 transitions. [2021-11-02 23:01:43,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:43,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1709 transitions. [2021-11-02 23:01:43,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1709 transitions. [2021-11-02 23:01:43,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:43,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:43,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1709 transitions. [2021-11-02 23:01:43,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:43,311 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-02 23:01:43,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1709 transitions. [2021-11-02 23:01:43,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:43,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.495188101487314) internal successors, (1709), 1142 states have internal predecessors, (1709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1709 transitions. [2021-11-02 23:01:43,347 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-02 23:01:43,348 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-02 23:01:43,348 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-02 23:01:43,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1709 transitions. [2021-11-02 23:01:43,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:43,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:43,362 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,362 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,363 INFO L791 eck$LassoCheckResult]: Stem: 16939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16940#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17199#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16142#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 16143#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16382#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17098#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16668#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16669#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17128#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17129#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17167#L685-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17161#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17162#L695-1 assume !(0 == ~M_E~0); 17192#L931-1 assume !(0 == ~T1_E~0); 17193#L936-1 assume !(0 == ~T2_E~0); 17197#L941-1 assume !(0 == ~T3_E~0); 16747#L946-1 assume !(0 == ~T4_E~0); 16748#L951-1 assume !(0 == ~T5_E~0); 16437#L956-1 assume !(0 == ~T6_E~0); 16438#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16885#L966-1 assume !(0 == ~T8_E~0); 16886#L971-1 assume !(0 == ~T9_E~0); 17009#L976-1 assume !(0 == ~E_M~0); 16984#L981-1 assume !(0 == ~E_1~0); 16756#L986-1 assume !(0 == ~E_2~0); 16498#L991-1 assume !(0 == ~E_3~0); 16499#L996-1 assume !(0 == ~E_4~0); 17183#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 16937#L1006-1 assume !(0 == ~E_6~0); 16938#L1011-1 assume !(0 == ~E_7~0); 17168#L1016-1 assume !(0 == ~E_8~0); 17176#L1021-1 assume !(0 == ~E_9~0); 16100#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16101#L452 assume !(1 == ~m_pc~0); 16480#L452-2 is_master_triggered_~__retres1~0 := 0; 16481#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16865#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16931#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17087#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16975#L471 assume 1 == ~t1_pc~0; 16976#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16496#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16497#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16921#L1167 assume !(0 != activate_threads_~tmp___0~0); 16723#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16724#L490 assume !(1 == ~t2_pc~0); 16831#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 16832#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16870#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16431#L1175 assume !(0 != activate_threads_~tmp___1~0); 16432#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16709#L509 assume 1 == ~t3_pc~0; 16710#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16446#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16447#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 17032#L1183 assume !(0 != activate_threads_~tmp___2~0); 16970#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16971#L528 assume !(1 == ~t4_pc~0); 16761#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 16718#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16719#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16482#L1191 assume !(0 != activate_threads_~tmp___3~0); 16483#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17016#L547 assume 1 == ~t5_pc~0; 17096#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16808#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16458#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16459#L1199 assume !(0 != activate_threads_~tmp___4~0); 16751#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17057#L566 assume !(1 == ~t6_pc~0); 16176#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 16175#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16501#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16413#L1207 assume !(0 != activate_threads_~tmp___5~0); 16280#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16281#L585 assume 1 == ~t7_pc~0; 16286#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16287#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17189#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 17028#L1215 assume !(0 != activate_threads_~tmp___6~0); 17029#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17105#L604 assume 1 == ~t8_pc~0; 17106#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 17081#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16926#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16927#L1223 assume !(0 != activate_threads_~tmp___7~0); 17163#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17158#L623 assume !(1 == ~t9_pc~0); 16129#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 16130#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16973#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16974#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 16835#L1231-2 assume !(1 == ~M_E~0); 16836#L1039-1 assume !(1 == ~T1_E~0); 17166#L1044-1 assume !(1 == ~T2_E~0); 16725#L1049-1 assume !(1 == ~T3_E~0); 16726#L1054-1 assume !(1 == ~T4_E~0); 16892#L1059-1 assume !(1 == ~T5_E~0); 16478#L1064-1 assume !(1 == ~T6_E~0); 16479#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17065#L1074-1 assume !(1 == ~T8_E~0); 17103#L1079-1 assume !(1 == ~T9_E~0); 17085#L1084-1 assume !(1 == ~E_M~0); 17086#L1089-1 assume !(1 == ~E_1~0); 17119#L1094-1 assume !(1 == ~E_2~0); 16789#L1099-1 assume !(1 == ~E_3~0); 16790#L1104-1 assume !(1 == ~E_4~0); 16978#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 16616#L1114-1 assume !(1 == ~E_6~0); 16617#L1119-1 assume !(1 == ~E_7~0); 16670#L1124-1 assume !(1 == ~E_8~0); 16138#L1129-1 assume !(1 == ~E_9~0); 16139#L1420-1 [2021-11-02 23:01:43,363 INFO L793 eck$LassoCheckResult]: Loop: 16139#L1420-1 assume !false; 16692#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 16568#L906 assume !false; 16569#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16966#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16110#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 16763#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 16764#L775 assume !(0 != eval_~tmp~0); 17058#L921 start_simulation_~kernel_st~0 := 2; 17059#L643-1 start_simulation_~kernel_st~0 := 3; 17174#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17015#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16645#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16646#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16788#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16536#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16537#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16868#L961-3 assume !(0 == ~T7_E~0); 16655#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16656#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16912#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16160#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16161#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16140#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16141#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16996#L1001-3 assume !(0 == ~E_5~0); 16630#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16631#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17027#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17072#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16804#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16805#L452-33 assume 1 == ~m_pc~0; 16754#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16425#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16426#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 17036#L1159-33 assume !(0 != activate_threads_~tmp~1); 17037#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17101#L471-33 assume 1 == ~t1_pc~0; 16533#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16534#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17139#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16075#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16076#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16590#L490-33 assume 1 == ~t2_pc~0; 16592#L491-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16687#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17180#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17148#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17149#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16082#L509-33 assume 1 == ~t3_pc~0; 16083#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16246#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16895#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16820#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16294#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16295#L528-33 assume !(1 == ~t4_pc~0); 16341#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 16342#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16343#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16366#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16916#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16639#L547-33 assume 1 == ~t5_pc~0; 16640#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16581#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16890#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16945#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17064#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16225#L566-33 assume !(1 == ~t6_pc~0); 16226#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 16125#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16126#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16707#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16887#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16363#L585-33 assume 1 == ~t7_pc~0; 16364#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16424#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16673#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16930#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16704#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16705#L604-33 assume !(1 == ~t8_pc~0); 16273#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 16272#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16320#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16321#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 16941#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17051#L623-33 assume !(1 == ~t9_pc~0); 16210#L623-35 is_transmit9_triggered_~__retres1~9 := 0; 16211#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16935#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16990#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 16266#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 16267#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17008#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16406#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16407#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16200#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16201#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16731#L1069-3 assume !(1 == ~T7_E~0); 16732#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16986#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16899#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16823#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16824#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16749#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16750#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17003#L1109-3 assume !(1 == ~E_5~0); 16988#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16989#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17195#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17201#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16488#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16489#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16323#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 17066#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 17067#L1439 assume !(0 == start_simulation_~tmp~3); 17114#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16605#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16388#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 16785#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 16643#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16644#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 16506#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 16507#L1452 assume !(0 != start_simulation_~tmp___0~1); 16139#L1420-1 [2021-11-02 23:01:43,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1362763474, now seen corresponding path program 1 times [2021-11-02 23:01:43,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,364 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394181518] [2021-11-02 23:01:43,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394181518] [2021-11-02 23:01:43,419 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394181518] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,419 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,419 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357325310] [2021-11-02 23:01:43,420 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:43,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,421 INFO L85 PathProgramCache]: Analyzing trace with hash -1190902560, now seen corresponding path program 1 times [2021-11-02 23:01:43,421 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,421 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894307783] [2021-11-02 23:01:43,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,477 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894307783] [2021-11-02 23:01:43,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894307783] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,479 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,480 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472143394] [2021-11-02 23:01:43,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:43,480 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:43,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:43,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:43,481 INFO L87 Difference]: Start difference. First operand 1143 states and 1709 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:43,507 INFO L93 Difference]: Finished difference Result 1143 states and 1708 transitions. [2021-11-02 23:01:43,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:43,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1708 transitions. [2021-11-02 23:01:43,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1708 transitions. [2021-11-02 23:01:43,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:43,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:43,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1708 transitions. [2021-11-02 23:01:43,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:43,531 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-02 23:01:43,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1708 transitions. [2021-11-02 23:01:43,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:43,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4943132108486439) internal successors, (1708), 1142 states have internal predecessors, (1708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1708 transitions. [2021-11-02 23:01:43,562 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-02 23:01:43,562 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-02 23:01:43,562 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-02 23:01:43,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1708 transitions. [2021-11-02 23:01:43,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:43,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:43,571 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,571 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,571 INFO L791 eck$LassoCheckResult]: Stem: 19232#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19233#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19492#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18435#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 18436#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18675#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19391#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18961#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18962#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19421#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19422#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19460#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19454#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19455#L695-1 assume !(0 == ~M_E~0); 19485#L931-1 assume !(0 == ~T1_E~0); 19486#L936-1 assume !(0 == ~T2_E~0); 19490#L941-1 assume !(0 == ~T3_E~0); 19040#L946-1 assume !(0 == ~T4_E~0); 19041#L951-1 assume !(0 == ~T5_E~0); 18730#L956-1 assume !(0 == ~T6_E~0); 18731#L961-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19178#L966-1 assume !(0 == ~T8_E~0); 19179#L971-1 assume !(0 == ~T9_E~0); 19302#L976-1 assume !(0 == ~E_M~0); 19277#L981-1 assume !(0 == ~E_1~0); 19049#L986-1 assume !(0 == ~E_2~0); 18791#L991-1 assume !(0 == ~E_3~0); 18792#L996-1 assume !(0 == ~E_4~0); 19476#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 19230#L1006-1 assume !(0 == ~E_6~0); 19231#L1011-1 assume !(0 == ~E_7~0); 19461#L1016-1 assume !(0 == ~E_8~0); 19469#L1021-1 assume !(0 == ~E_9~0); 18393#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18394#L452 assume !(1 == ~m_pc~0); 18773#L452-2 is_master_triggered_~__retres1~0 := 0; 18774#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19158#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 19224#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19380#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19268#L471 assume 1 == ~t1_pc~0; 19269#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18789#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18790#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 19214#L1167 assume !(0 != activate_threads_~tmp___0~0); 19016#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19017#L490 assume !(1 == ~t2_pc~0); 19124#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 19125#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19163#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 18724#L1175 assume !(0 != activate_threads_~tmp___1~0); 18725#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19002#L509 assume 1 == ~t3_pc~0; 19003#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18739#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18740#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19325#L1183 assume !(0 != activate_threads_~tmp___2~0); 19263#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19264#L528 assume !(1 == ~t4_pc~0); 19054#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 19011#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19012#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18775#L1191 assume !(0 != activate_threads_~tmp___3~0); 18776#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19309#L547 assume 1 == ~t5_pc~0; 19389#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19101#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18751#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18752#L1199 assume !(0 != activate_threads_~tmp___4~0); 19044#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19350#L566 assume !(1 == ~t6_pc~0); 18469#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 18468#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18794#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18706#L1207 assume !(0 != activate_threads_~tmp___5~0); 18573#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18574#L585 assume 1 == ~t7_pc~0; 18579#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18580#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19482#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 19321#L1215 assume !(0 != activate_threads_~tmp___6~0); 19322#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19398#L604 assume 1 == ~t8_pc~0; 19399#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19374#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19219#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 19220#L1223 assume !(0 != activate_threads_~tmp___7~0); 19456#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 19451#L623 assume !(1 == ~t9_pc~0); 18422#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 18423#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 19266#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 19267#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 19128#L1231-2 assume !(1 == ~M_E~0); 19129#L1039-1 assume !(1 == ~T1_E~0); 19459#L1044-1 assume !(1 == ~T2_E~0); 19018#L1049-1 assume !(1 == ~T3_E~0); 19019#L1054-1 assume !(1 == ~T4_E~0); 19185#L1059-1 assume !(1 == ~T5_E~0); 18771#L1064-1 assume !(1 == ~T6_E~0); 18772#L1069-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19358#L1074-1 assume !(1 == ~T8_E~0); 19396#L1079-1 assume !(1 == ~T9_E~0); 19378#L1084-1 assume !(1 == ~E_M~0); 19379#L1089-1 assume !(1 == ~E_1~0); 19412#L1094-1 assume !(1 == ~E_2~0); 19082#L1099-1 assume !(1 == ~E_3~0); 19083#L1104-1 assume !(1 == ~E_4~0); 19271#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18909#L1114-1 assume !(1 == ~E_6~0); 18910#L1119-1 assume !(1 == ~E_7~0); 18963#L1124-1 assume !(1 == ~E_8~0); 18431#L1129-1 assume !(1 == ~E_9~0); 18432#L1420-1 [2021-11-02 23:01:43,572 INFO L793 eck$LassoCheckResult]: Loop: 18432#L1420-1 assume !false; 18985#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 18861#L906 assume !false; 18862#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 19259#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18403#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 19056#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 19057#L775 assume !(0 != eval_~tmp~0); 19351#L921 start_simulation_~kernel_st~0 := 2; 19352#L643-1 start_simulation_~kernel_st~0 := 3; 19467#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 19308#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18938#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18939#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19081#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18829#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18830#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19161#L961-3 assume !(0 == ~T7_E~0); 18948#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18949#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19205#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18453#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18454#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18433#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18434#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19289#L1001-3 assume !(0 == ~E_5~0); 18923#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18924#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19320#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19365#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19097#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19098#L452-33 assume 1 == ~m_pc~0; 19047#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 18718#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18719#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 19329#L1159-33 assume !(0 != activate_threads_~tmp~1); 19330#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19394#L471-33 assume 1 == ~t1_pc~0; 18826#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18827#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19432#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18368#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18369#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18883#L490-33 assume !(1 == ~t2_pc~0); 18884#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 18980#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19473#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 19441#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19442#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18375#L509-33 assume 1 == ~t3_pc~0; 18376#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18539#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19188#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19113#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18587#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18588#L528-33 assume 1 == ~t4_pc~0; 19331#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18635#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18636#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18659#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19209#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18932#L547-33 assume 1 == ~t5_pc~0; 18933#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18874#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19183#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19238#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19357#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18518#L566-33 assume !(1 == ~t6_pc~0); 18519#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 18418#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18419#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19000#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19180#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18656#L585-33 assume 1 == ~t7_pc~0; 18657#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18717#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18966#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 19223#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18997#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18998#L604-33 assume 1 == ~t8_pc~0; 18564#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18565#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18613#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 18614#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 19234#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 19344#L623-33 assume 1 == ~t9_pc~0; 19489#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 18504#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 19228#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 19283#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 18559#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 18560#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19301#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18699#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18700#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18493#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18494#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19024#L1069-3 assume !(1 == ~T7_E~0); 19025#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19279#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19192#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19116#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19117#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19042#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19043#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19296#L1109-3 assume !(1 == ~E_5~0); 19281#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19282#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19488#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19494#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18781#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 18782#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18616#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 19359#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 19360#L1439 assume !(0 == start_simulation_~tmp~3); 19407#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 18898#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18681#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 19078#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 18936#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18937#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 18799#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 18800#L1452 assume !(0 != start_simulation_~tmp___0~1); 18432#L1420-1 [2021-11-02 23:01:43,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,573 INFO L85 PathProgramCache]: Analyzing trace with hash 503945200, now seen corresponding path program 1 times [2021-11-02 23:01:43,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750659281] [2021-11-02 23:01:43,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,630 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [750659281] [2021-11-02 23:01:43,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [750659281] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,631 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:01:43,631 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064183730] [2021-11-02 23:01:43,632 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:43,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1260005662, now seen corresponding path program 2 times [2021-11-02 23:01:43,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,633 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225533123] [2021-11-02 23:01:43,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,633 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,676 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,677 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225533123] [2021-11-02 23:01:43,677 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225533123] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,677 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,677 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,677 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112148732] [2021-11-02 23:01:43,678 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:43,678 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:43,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:43,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:43,679 INFO L87 Difference]: Start difference. First operand 1143 states and 1708 transitions. cyclomatic complexity: 566 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 2 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:43,749 INFO L93 Difference]: Finished difference Result 1143 states and 1703 transitions. [2021-11-02 23:01:43,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:43,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1703 transitions. [2021-11-02 23:01:43,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1703 transitions. [2021-11-02 23:01:43,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:43,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:43,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1703 transitions. [2021-11-02 23:01:43,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:43,775 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-02 23:01:43,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1703 transitions. [2021-11-02 23:01:43,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:43,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4899387576552932) internal successors, (1703), 1142 states have internal predecessors, (1703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:43,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1703 transitions. [2021-11-02 23:01:43,805 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-02 23:01:43,805 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-02 23:01:43,805 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-02 23:01:43,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1703 transitions. [2021-11-02 23:01:43,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:43,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:43,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:43,814 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,815 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:43,815 INFO L791 eck$LassoCheckResult]: Stem: 21525#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 21526#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21785#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20728#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 20729#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20968#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21684#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21254#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21255#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21714#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21715#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21753#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21747#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21748#L695-1 assume !(0 == ~M_E~0); 21778#L931-1 assume !(0 == ~T1_E~0); 21779#L936-1 assume !(0 == ~T2_E~0); 21783#L941-1 assume !(0 == ~T3_E~0); 21333#L946-1 assume !(0 == ~T4_E~0); 21334#L951-1 assume !(0 == ~T5_E~0); 21025#L956-1 assume !(0 == ~T6_E~0); 21026#L961-1 assume !(0 == ~T7_E~0); 21471#L966-1 assume !(0 == ~T8_E~0); 21472#L971-1 assume !(0 == ~T9_E~0); 21595#L976-1 assume !(0 == ~E_M~0); 21570#L981-1 assume !(0 == ~E_1~0); 21342#L986-1 assume !(0 == ~E_2~0); 21084#L991-1 assume !(0 == ~E_3~0); 21085#L996-1 assume !(0 == ~E_4~0); 21769#L1001-1 assume 0 == ~E_5~0;~E_5~0 := 1; 21523#L1006-1 assume !(0 == ~E_6~0); 21524#L1011-1 assume !(0 == ~E_7~0); 21754#L1016-1 assume !(0 == ~E_8~0); 21762#L1021-1 assume !(0 == ~E_9~0); 20686#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20687#L452 assume !(1 == ~m_pc~0); 21066#L452-2 is_master_triggered_~__retres1~0 := 0; 21067#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21451#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21517#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21673#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21561#L471 assume 1 == ~t1_pc~0; 21562#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21082#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21083#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21507#L1167 assume !(0 != activate_threads_~tmp___0~0); 21309#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21310#L490 assume !(1 == ~t2_pc~0); 21417#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 21418#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21456#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21017#L1175 assume !(0 != activate_threads_~tmp___1~0); 21018#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21295#L509 assume 1 == ~t3_pc~0; 21296#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 21032#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21033#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21618#L1183 assume !(0 != activate_threads_~tmp___2~0); 21556#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21557#L528 assume !(1 == ~t4_pc~0); 21348#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 21304#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21305#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21068#L1191 assume !(0 != activate_threads_~tmp___3~0); 21069#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21602#L547 assume 1 == ~t5_pc~0; 21682#L548 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21394#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21044#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21045#L1199 assume !(0 != activate_threads_~tmp___4~0); 21337#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21643#L566 assume !(1 == ~t6_pc~0); 20762#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 20761#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21087#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20999#L1207 assume !(0 != activate_threads_~tmp___5~0); 20868#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20869#L585 assume 1 == ~t7_pc~0; 20872#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20873#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21775#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21614#L1215 assume !(0 != activate_threads_~tmp___6~0); 21615#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21691#L604 assume 1 == ~t8_pc~0; 21692#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21667#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21512#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21513#L1223 assume !(0 != activate_threads_~tmp___7~0); 21749#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21744#L623 assume !(1 == ~t9_pc~0); 20715#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 20716#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21559#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21560#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 21421#L1231-2 assume !(1 == ~M_E~0); 21422#L1039-1 assume !(1 == ~T1_E~0); 21752#L1044-1 assume !(1 == ~T2_E~0); 21311#L1049-1 assume !(1 == ~T3_E~0); 21312#L1054-1 assume !(1 == ~T4_E~0); 21478#L1059-1 assume !(1 == ~T5_E~0); 21064#L1064-1 assume !(1 == ~T6_E~0); 21065#L1069-1 assume !(1 == ~T7_E~0); 21651#L1074-1 assume !(1 == ~T8_E~0); 21689#L1079-1 assume !(1 == ~T9_E~0); 21671#L1084-1 assume !(1 == ~E_M~0); 21672#L1089-1 assume !(1 == ~E_1~0); 21705#L1094-1 assume !(1 == ~E_2~0); 21375#L1099-1 assume !(1 == ~E_3~0); 21376#L1104-1 assume !(1 == ~E_4~0); 21564#L1109-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21202#L1114-1 assume !(1 == ~E_6~0); 21203#L1119-1 assume !(1 == ~E_7~0); 21256#L1124-1 assume !(1 == ~E_8~0); 20724#L1129-1 assume !(1 == ~E_9~0); 20725#L1420-1 [2021-11-02 23:01:43,816 INFO L793 eck$LassoCheckResult]: Loop: 20725#L1420-1 assume !false; 21278#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 21154#L906 assume !false; 21155#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 21552#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20696#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 21349#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 21350#L775 assume !(0 != eval_~tmp~0); 21644#L921 start_simulation_~kernel_st~0 := 2; 21645#L643-1 start_simulation_~kernel_st~0 := 3; 21760#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21601#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21231#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21232#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21374#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21122#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21123#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21454#L961-3 assume !(0 == ~T7_E~0); 21241#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21242#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21498#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20746#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20747#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20726#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20727#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21582#L1001-3 assume !(0 == ~E_5~0); 21216#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21217#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21613#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21658#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21390#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21391#L452-33 assume 1 == ~m_pc~0; 21340#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 21011#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21012#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21622#L1159-33 assume !(0 != activate_threads_~tmp~1); 21623#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21687#L471-33 assume !(1 == ~t1_pc~0); 21121#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 21120#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21725#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20661#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20662#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21176#L490-33 assume !(1 == ~t2_pc~0); 21177#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 21273#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21766#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21734#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21735#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20668#L509-33 assume 1 == ~t3_pc~0; 20669#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20832#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21481#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21406#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20880#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20881#L528-33 assume 1 == ~t4_pc~0; 21624#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20928#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20929#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 20952#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21502#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21225#L547-33 assume 1 == ~t5_pc~0; 21226#L548-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21167#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21476#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21531#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21650#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20811#L566-33 assume !(1 == ~t6_pc~0); 20812#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 20711#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20712#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21293#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21473#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20949#L585-33 assume 1 == ~t7_pc~0; 20950#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21010#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21259#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21516#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21290#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21291#L604-33 assume 1 == ~t8_pc~0; 20854#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 20855#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20904#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20905#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21527#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21637#L623-33 assume !(1 == ~t9_pc~0); 20790#L623-35 is_transmit9_triggered_~__retres1~9 := 0; 20791#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21521#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21576#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 20852#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 20853#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21594#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20990#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20991#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20786#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20787#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21317#L1069-3 assume !(1 == ~T7_E~0); 21318#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21572#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21482#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21407#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21408#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21335#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21336#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21588#L1109-3 assume !(1 == ~E_5~0); 21574#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21575#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21781#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21787#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21074#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 21075#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20909#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 21652#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 21653#L1439 assume !(0 == start_simulation_~tmp~3); 21700#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 21191#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20974#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 21370#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 21229#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21230#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 21092#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 21093#L1452 assume !(0 != start_simulation_~tmp___0~1); 20725#L1420-1 [2021-11-02 23:01:43,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,816 INFO L85 PathProgramCache]: Analyzing trace with hash -966369804, now seen corresponding path program 1 times [2021-11-02 23:01:43,817 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,817 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486298302] [2021-11-02 23:01:43,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,874 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486298302] [2021-11-02 23:01:43,874 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486298302] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,874 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,874 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:01:43,874 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395362534] [2021-11-02 23:01:43,876 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:43,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:43,876 INFO L85 PathProgramCache]: Analyzing trace with hash 185235360, now seen corresponding path program 1 times [2021-11-02 23:01:43,877 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:43,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927032484] [2021-11-02 23:01:43,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:43,877 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:43,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:43,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:43,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:43,941 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927032484] [2021-11-02 23:01:43,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927032484] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:43,941 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:43,942 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:43,942 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908882387] [2021-11-02 23:01:43,942 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:43,943 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:43,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:01:43,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:01:43,944 INFO L87 Difference]: Start difference. First operand 1143 states and 1703 transitions. cyclomatic complexity: 561 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 2 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:44,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:44,020 INFO L93 Difference]: Finished difference Result 1143 states and 1686 transitions. [2021-11-02 23:01:44,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:01:44,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1686 transitions. [2021-11-02 23:01:44,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:44,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1686 transitions. [2021-11-02 23:01:44,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-02 23:01:44,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-02 23:01:44,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1686 transitions. [2021-11-02 23:01:44,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:44,048 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-02 23:01:44,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1686 transitions. [2021-11-02 23:01:44,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-02 23:01:44,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4750656167979002) internal successors, (1686), 1142 states have internal predecessors, (1686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:44,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1686 transitions. [2021-11-02 23:01:44,091 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-02 23:01:44,091 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-02 23:01:44,091 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-02 23:01:44,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1686 transitions. [2021-11-02 23:01:44,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-02 23:01:44,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:44,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:44,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:44,101 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:44,101 INFO L791 eck$LassoCheckResult]: Stem: 23817#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23818#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 24078#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23021#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 23022#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23263#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23976#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23547#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23548#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24006#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24007#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24045#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24039#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24040#L695-1 assume !(0 == ~M_E~0); 24071#L931-1 assume !(0 == ~T1_E~0); 24072#L936-1 assume !(0 == ~T2_E~0); 24076#L941-1 assume !(0 == ~T3_E~0); 23625#L946-1 assume !(0 == ~T4_E~0); 23626#L951-1 assume !(0 == ~T5_E~0); 23317#L956-1 assume !(0 == ~T6_E~0); 23318#L961-1 assume !(0 == ~T7_E~0); 23765#L966-1 assume !(0 == ~T8_E~0); 23766#L971-1 assume !(0 == ~T9_E~0); 23887#L976-1 assume !(0 == ~E_M~0); 23862#L981-1 assume !(0 == ~E_1~0); 23635#L986-1 assume !(0 == ~E_2~0); 23376#L991-1 assume !(0 == ~E_3~0); 23377#L996-1 assume !(0 == ~E_4~0); 24062#L1001-1 assume !(0 == ~E_5~0); 23815#L1006-1 assume !(0 == ~E_6~0); 23816#L1011-1 assume !(0 == ~E_7~0); 24046#L1016-1 assume !(0 == ~E_8~0); 24054#L1021-1 assume !(0 == ~E_9~0); 22979#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22980#L452 assume !(1 == ~m_pc~0); 23358#L452-2 is_master_triggered_~__retres1~0 := 0; 23359#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23744#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 23810#L1159 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23965#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23853#L471 assume 1 == ~t1_pc~0; 23854#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23374#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23375#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23800#L1167 assume !(0 != activate_threads_~tmp___0~0); 23601#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23602#L490 assume !(1 == ~t2_pc~0); 23710#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 23711#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23749#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23309#L1175 assume !(0 != activate_threads_~tmp___1~0); 23310#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23587#L509 assume 1 == ~t3_pc~0; 23588#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23324#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23325#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23910#L1183 assume !(0 != activate_threads_~tmp___2~0); 23848#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23849#L528 assume !(1 == ~t4_pc~0); 23641#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 23596#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23597#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23360#L1191 assume !(0 != activate_threads_~tmp___3~0); 23361#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23894#L547 assume !(1 == ~t5_pc~0); 23975#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 23687#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23336#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23337#L1199 assume !(0 != activate_threads_~tmp___4~0); 23629#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23935#L566 assume !(1 == ~t6_pc~0); 23055#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 23054#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23379#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23290#L1207 assume !(0 != activate_threads_~tmp___5~0); 23159#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23160#L585 assume 1 == ~t7_pc~0; 23163#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23164#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24068#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23906#L1215 assume !(0 != activate_threads_~tmp___6~0); 23907#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23983#L604 assume 1 == ~t8_pc~0; 23984#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 23959#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23804#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 23805#L1223 assume !(0 != activate_threads_~tmp___7~0); 24041#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24036#L623 assume !(1 == ~t9_pc~0); 23008#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 23009#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23851#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23852#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 23715#L1231-2 assume !(1 == ~M_E~0); 23716#L1039-1 assume !(1 == ~T1_E~0); 24044#L1044-1 assume !(1 == ~T2_E~0); 23603#L1049-1 assume !(1 == ~T3_E~0); 23604#L1054-1 assume !(1 == ~T4_E~0); 23771#L1059-1 assume !(1 == ~T5_E~0); 23356#L1064-1 assume !(1 == ~T6_E~0); 23357#L1069-1 assume !(1 == ~T7_E~0); 23943#L1074-1 assume !(1 == ~T8_E~0); 23981#L1079-1 assume !(1 == ~T9_E~0); 23963#L1084-1 assume !(1 == ~E_M~0); 23964#L1089-1 assume !(1 == ~E_1~0); 23997#L1094-1 assume !(1 == ~E_2~0); 23668#L1099-1 assume !(1 == ~E_3~0); 23669#L1104-1 assume !(1 == ~E_4~0); 23856#L1109-1 assume !(1 == ~E_5~0); 23494#L1114-1 assume !(1 == ~E_6~0); 23495#L1119-1 assume !(1 == ~E_7~0); 23549#L1124-1 assume !(1 == ~E_8~0); 23017#L1129-1 assume !(1 == ~E_9~0); 23018#L1420-1 [2021-11-02 23:01:44,102 INFO L793 eck$LassoCheckResult]: Loop: 23018#L1420-1 assume !false; 23572#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 23446#L906 assume !false; 23447#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23844#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 22989#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 23643#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 23644#L775 assume !(0 != eval_~tmp~0); 23936#L921 start_simulation_~kernel_st~0 := 2; 23937#L643-1 start_simulation_~kernel_st~0 := 3; 24052#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23893#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23523#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23524#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23667#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23414#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23415#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23747#L961-3 assume !(0 == ~T7_E~0); 23533#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23534#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23790#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23039#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23040#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23019#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23020#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23874#L1001-3 assume !(0 == ~E_5~0); 23507#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23508#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23905#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23950#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23683#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23684#L452-33 assume 1 == ~m_pc~0; 23633#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 23302#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23303#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 23914#L1159-33 assume !(0 != activate_threads_~tmp~1); 23915#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23979#L471-33 assume 1 == ~t1_pc~0; 23411#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23412#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24018#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 22954#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22955#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23469#L490-33 assume !(1 == ~t2_pc~0); 23470#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 23565#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24059#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 24026#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 24027#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22961#L509-33 assume 1 == ~t3_pc~0; 22962#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23124#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23774#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23699#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23171#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23172#L528-33 assume 1 == ~t4_pc~0; 23916#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23216#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23220#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23243#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23794#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23514#L547-33 assume !(1 == ~t5_pc~0); 23455#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 23456#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23769#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23823#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23941#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23100#L566-33 assume !(1 == ~t6_pc~0); 23101#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 23002#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23003#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23585#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23764#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23238#L585-33 assume 1 == ~t7_pc~0; 23239#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23301#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23546#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23808#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23582#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23583#L604-33 assume 1 == ~t8_pc~0; 23145#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 23146#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23195#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 23196#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 23819#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 23929#L623-33 assume 1 == ~t9_pc~0; 24075#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 23086#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23813#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23868#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 23143#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 23144#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23886#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23281#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23282#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23078#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23079#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23609#L1069-3 assume !(1 == ~T7_E~0); 23610#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23864#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23775#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23702#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23703#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23627#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23628#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23880#L1109-3 assume !(1 == ~E_5~0); 23866#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23867#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24074#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24080#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23366#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23367#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 23200#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 23944#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 23945#L1439 assume !(0 == start_simulation_~tmp~3); 23992#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23482#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 23265#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 23663#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 23521#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23522#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 23384#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 23385#L1452 assume !(0 != start_simulation_~tmp___0~1); 23018#L1420-1 [2021-11-02 23:01:44,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:44,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1914803911, now seen corresponding path program 1 times [2021-11-02 23:01:44,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:44,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191487325] [2021-11-02 23:01:44,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:44,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:44,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:44,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:44,173 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:44,173 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191487325] [2021-11-02 23:01:44,174 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191487325] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:44,174 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:44,174 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:44,174 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213434449] [2021-11-02 23:01:44,175 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:44,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:44,176 INFO L85 PathProgramCache]: Analyzing trace with hash 559720257, now seen corresponding path program 1 times [2021-11-02 23:01:44,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:44,176 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641257950] [2021-11-02 23:01:44,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:44,177 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:44,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:44,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:44,228 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:44,228 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641257950] [2021-11-02 23:01:44,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641257950] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:44,228 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:44,228 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:44,229 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838678734] [2021-11-02 23:01:44,229 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:44,229 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:44,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:01:44,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:01:44,230 INFO L87 Difference]: Start difference. First operand 1143 states and 1686 transitions. cyclomatic complexity: 544 Second operand has 5 states, 5 states have (on average 22.6) internal successors, (113), 5 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:44,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:44,605 INFO L93 Difference]: Finished difference Result 3244 states and 4755 transitions. [2021-11-02 23:01:44,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 23:01:44,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3244 states and 4755 transitions. [2021-11-02 23:01:44,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2952 [2021-11-02 23:01:44,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3244 states to 3244 states and 4755 transitions. [2021-11-02 23:01:44,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3244 [2021-11-02 23:01:44,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3244 [2021-11-02 23:01:44,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3244 states and 4755 transitions. [2021-11-02 23:01:44,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:44,720 INFO L681 BuchiCegarLoop]: Abstraction has 3244 states and 4755 transitions. [2021-11-02 23:01:44,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3244 states and 4755 transitions. [2021-11-02 23:01:44,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3244 to 1182. [2021-11-02 23:01:44,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1182 states, 1182 states have (on average 1.4593908629441625) internal successors, (1725), 1181 states have internal predecessors, (1725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:44,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1182 states to 1182 states and 1725 transitions. [2021-11-02 23:01:44,770 INFO L704 BuchiCegarLoop]: Abstraction has 1182 states and 1725 transitions. [2021-11-02 23:01:44,770 INFO L587 BuchiCegarLoop]: Abstraction has 1182 states and 1725 transitions. [2021-11-02 23:01:44,770 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-02 23:01:44,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1182 states and 1725 transitions. [2021-11-02 23:01:44,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2021-11-02 23:01:44,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:44,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:44,781 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:44,781 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:44,782 INFO L791 eck$LassoCheckResult]: Stem: 28231#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 28232#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28516#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27423#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 27424#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27666#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28402#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27954#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27955#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28432#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28433#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28474#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28467#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28468#L695-1 assume !(0 == ~M_E~0); 28509#L931-1 assume !(0 == ~T1_E~0); 28510#L936-1 assume !(0 == ~T2_E~0); 28514#L941-1 assume !(0 == ~T3_E~0); 28031#L946-1 assume !(0 == ~T4_E~0); 28032#L951-1 assume !(0 == ~T5_E~0); 27720#L956-1 assume !(0 == ~T6_E~0); 27721#L961-1 assume !(0 == ~T7_E~0); 28178#L966-1 assume !(0 == ~T8_E~0); 28179#L971-1 assume !(0 == ~T9_E~0); 28302#L976-1 assume !(0 == ~E_M~0); 28277#L981-1 assume !(0 == ~E_1~0); 28042#L986-1 assume !(0 == ~E_2~0); 27779#L991-1 assume !(0 == ~E_3~0); 27780#L996-1 assume !(0 == ~E_4~0); 28499#L1001-1 assume !(0 == ~E_5~0); 28229#L1006-1 assume !(0 == ~E_6~0); 28230#L1011-1 assume !(0 == ~E_7~0); 28475#L1016-1 assume !(0 == ~E_8~0); 28487#L1021-1 assume !(0 == ~E_9~0); 27381#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27382#L452 assume !(1 == ~m_pc~0); 27761#L452-2 is_master_triggered_~__retres1~0 := 0; 27762#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28156#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 28389#L1159 assume !(0 != activate_threads_~tmp~1); 28390#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28267#L471 assume 1 == ~t1_pc~0; 28268#L472 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27777#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27778#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 28213#L1167 assume !(0 != activate_threads_~tmp___0~0); 28007#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28008#L490 assume !(1 == ~t2_pc~0); 28119#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 28120#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28162#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 27712#L1175 assume !(0 != activate_threads_~tmp___1~0); 27713#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27992#L509 assume 1 == ~t3_pc~0; 27993#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 27731#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27732#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 28325#L1183 assume !(0 != activate_threads_~tmp___2~0); 28262#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28263#L528 assume !(1 == ~t4_pc~0); 28048#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 28001#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28002#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27763#L1191 assume !(0 != activate_threads_~tmp___3~0); 27764#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28309#L547 assume !(1 == ~t5_pc~0); 28401#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 28095#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27739#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27740#L1199 assume !(0 != activate_threads_~tmp___4~0); 28035#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28353#L566 assume !(1 == ~t6_pc~0); 27462#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 27461#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27783#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27695#L1207 assume !(0 != activate_threads_~tmp___5~0); 27562#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27563#L585 assume 1 == ~t7_pc~0; 27566#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 27567#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28505#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28321#L1215 assume !(0 != activate_threads_~tmp___6~0); 28322#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28411#L604 assume 1 == ~t8_pc~0; 28412#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 28383#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28217#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28218#L1223 assume !(0 != activate_threads_~tmp___7~0); 28469#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28464#L623 assume !(1 == ~t9_pc~0); 27410#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 27411#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28265#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28266#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 28124#L1231-2 assume !(1 == ~M_E~0); 28125#L1039-1 assume !(1 == ~T1_E~0); 28472#L1044-1 assume !(1 == ~T2_E~0); 28011#L1049-1 assume !(1 == ~T3_E~0); 28012#L1054-1 assume !(1 == ~T4_E~0); 28185#L1059-1 assume !(1 == ~T5_E~0); 27759#L1064-1 assume !(1 == ~T6_E~0); 27760#L1069-1 assume !(1 == ~T7_E~0); 28362#L1074-1 assume !(1 == ~T8_E~0); 28407#L1079-1 assume !(1 == ~T9_E~0); 28387#L1084-1 assume !(1 == ~E_M~0); 28388#L1089-1 assume !(1 == ~E_1~0); 28423#L1094-1 assume !(1 == ~E_2~0); 28076#L1099-1 assume !(1 == ~E_3~0); 28077#L1104-1 assume !(1 == ~E_4~0); 28270#L1109-1 assume !(1 == ~E_5~0); 27899#L1114-1 assume !(1 == ~E_6~0); 27900#L1119-1 assume !(1 == ~E_7~0); 27956#L1124-1 assume !(1 == ~E_8~0); 27421#L1129-1 assume !(1 == ~E_9~0); 27422#L1420-1 [2021-11-02 23:01:44,782 INFO L793 eck$LassoCheckResult]: Loop: 27422#L1420-1 assume !false; 27977#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 27850#L906 assume !false; 27851#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 28258#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27396#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 28050#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 28051#L775 assume !(0 != eval_~tmp~0); 28354#L921 start_simulation_~kernel_st~0 := 2; 28355#L643-1 start_simulation_~kernel_st~0 := 3; 28485#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28308#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27928#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27929#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28075#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27818#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27819#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28160#L961-3 assume !(0 == ~T7_E~0); 27938#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27939#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28203#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27441#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27442#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27419#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27420#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28288#L1001-3 assume !(0 == ~E_5~0); 27912#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27913#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28320#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28371#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28091#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28092#L452-33 assume 1 == ~m_pc~0; 28039#L453-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28040#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28367#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 28368#L1159-33 assume !(0 != activate_threads_~tmp~1); 28330#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28405#L471-33 assume 1 == ~t1_pc~0; 27815#L472-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27816#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28444#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27356#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27357#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27872#L490-33 assume !(1 == ~t2_pc~0); 27873#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 27970#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28494#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 28453#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28454#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27363#L509-33 assume 1 == ~t3_pc~0; 27364#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 27527#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28187#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 28107#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27574#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27575#L528-33 assume !(1 == ~t4_pc~0); 27621#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 27622#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27623#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27646#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28207#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27921#L547-33 assume !(1 == ~t5_pc~0); 27862#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 27863#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28182#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 28237#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 28361#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 27506#L566-33 assume !(1 == ~t6_pc~0); 27507#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 27406#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27407#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27990#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 28177#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27643#L585-33 assume 1 == ~t7_pc~0; 27644#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 27704#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27953#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28221#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 27987#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 27988#L604-33 assume !(1 == ~t8_pc~0); 27553#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 27552#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 27600#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 27601#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28233#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28345#L623-33 assume 1 == ~t9_pc~0; 28513#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 27492#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28227#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28282#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 27546#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 27547#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28301#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27686#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27687#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27481#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27482#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28015#L1069-3 assume !(1 == ~T7_E~0); 28016#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28278#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28191#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28110#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28111#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28033#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28034#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28295#L1109-3 assume !(1 == ~E_5~0); 28280#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28281#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28511#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28518#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27769#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 27770#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27603#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 28363#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 28364#L1439 assume !(0 == start_simulation_~tmp~3); 28418#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 27887#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27668#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 28072#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 27926#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27927#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 27788#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 27789#L1452 assume !(0 != start_simulation_~tmp___0~1); 27422#L1420-1 [2021-11-02 23:01:44,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:44,784 INFO L85 PathProgramCache]: Analyzing trace with hash -180699461, now seen corresponding path program 1 times [2021-11-02 23:01:44,784 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:44,784 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791116574] [2021-11-02 23:01:44,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:44,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:44,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:44,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:44,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:44,834 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791116574] [2021-11-02 23:01:44,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791116574] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:44,835 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:44,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:44,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242202336] [2021-11-02 23:01:44,838 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:44,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:44,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1122430591, now seen corresponding path program 1 times [2021-11-02 23:01:44,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:44,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158662113] [2021-11-02 23:01:44,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:44,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:44,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:44,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:44,892 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:44,892 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158662113] [2021-11-02 23:01:44,892 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158662113] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:44,893 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:44,893 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:44,893 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025520482] [2021-11-02 23:01:44,894 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:44,894 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:44,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:01:44,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:01:44,896 INFO L87 Difference]: Start difference. First operand 1182 states and 1725 transitions. cyclomatic complexity: 544 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:45,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:45,235 INFO L93 Difference]: Finished difference Result 3135 states and 4511 transitions. [2021-11-02 23:01:45,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:01:45,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3135 states and 4511 transitions. [2021-11-02 23:01:45,265 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2938 [2021-11-02 23:01:45,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3135 states to 3135 states and 4511 transitions. [2021-11-02 23:01:45,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3135 [2021-11-02 23:01:45,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3135 [2021-11-02 23:01:45,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3135 states and 4511 transitions. [2021-11-02 23:01:45,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:45,309 INFO L681 BuchiCegarLoop]: Abstraction has 3135 states and 4511 transitions. [2021-11-02 23:01:45,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3135 states and 4511 transitions. [2021-11-02 23:01:45,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3135 to 3001. [2021-11-02 23:01:45,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3001 states, 3001 states have (on average 1.4421859380206599) internal successors, (4328), 3000 states have internal predecessors, (4328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:45,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3001 states to 3001 states and 4328 transitions. [2021-11-02 23:01:45,406 INFO L704 BuchiCegarLoop]: Abstraction has 3001 states and 4328 transitions. [2021-11-02 23:01:45,406 INFO L587 BuchiCegarLoop]: Abstraction has 3001 states and 4328 transitions. [2021-11-02 23:01:45,407 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-02 23:01:45,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3001 states and 4328 transitions. [2021-11-02 23:01:45,425 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2875 [2021-11-02 23:01:45,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:45,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:45,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:45,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:45,429 INFO L791 eck$LassoCheckResult]: Stem: 32572#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 32573#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 32872#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 31752#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 31753#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31987#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32748#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32277#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32278#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32779#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32780#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32826#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32816#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32817#L695-1 assume !(0 == ~M_E~0); 32860#L931-1 assume !(0 == ~T1_E~0); 32861#L936-1 assume !(0 == ~T2_E~0); 32868#L941-1 assume !(0 == ~T3_E~0); 32365#L946-1 assume !(0 == ~T4_E~0); 32366#L951-1 assume !(0 == ~T5_E~0); 32043#L956-1 assume !(0 == ~T6_E~0); 32044#L961-1 assume !(0 == ~T7_E~0); 32519#L966-1 assume !(0 == ~T8_E~0); 32520#L971-1 assume !(0 == ~T9_E~0); 32643#L976-1 assume !(0 == ~E_M~0); 32617#L981-1 assume !(0 == ~E_1~0); 32376#L986-1 assume !(0 == ~E_2~0); 32103#L991-1 assume !(0 == ~E_3~0); 32104#L996-1 assume !(0 == ~E_4~0); 32849#L1001-1 assume !(0 == ~E_5~0); 32570#L1006-1 assume !(0 == ~E_6~0); 32571#L1011-1 assume !(0 == ~E_7~0); 32827#L1016-1 assume !(0 == ~E_8~0); 32840#L1021-1 assume !(0 == ~E_9~0); 31710#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31711#L452 assume !(1 == ~m_pc~0); 32085#L452-2 is_master_triggered_~__retres1~0 := 0; 32086#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32499#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32564#L1159 assume !(0 != activate_threads_~tmp~1); 32735#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32609#L471 assume !(1 == ~t1_pc~0); 32610#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 32101#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32102#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32554#L1167 assume !(0 != activate_threads_~tmp___0~0); 32336#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32337#L490 assume !(1 == ~t2_pc~0); 32465#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 32466#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32504#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32037#L1175 assume !(0 != activate_threads_~tmp___1~0); 32038#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32321#L509 assume 1 == ~t3_pc~0; 32322#L510 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32052#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32053#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32669#L1183 assume !(0 != activate_threads_~tmp___2~0); 32604#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32605#L528 assume !(1 == ~t4_pc~0); 32381#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 32330#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32331#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32087#L1191 assume !(0 != activate_threads_~tmp___3~0); 32088#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32650#L547 assume !(1 == ~t5_pc~0); 32747#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 32436#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32063#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32064#L1199 assume !(0 != activate_threads_~tmp___4~0); 32369#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32702#L566 assume !(1 == ~t6_pc~0); 31785#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 31784#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32106#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32018#L1207 assume !(0 != activate_threads_~tmp___5~0); 31885#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31886#L585 assume 1 == ~t7_pc~0; 31891#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 31892#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32857#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32665#L1215 assume !(0 != activate_threads_~tmp___6~0); 32666#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32755#L604 assume 1 == ~t8_pc~0; 32756#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32729#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32559#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32560#L1223 assume !(0 != activate_threads_~tmp___7~0); 32818#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32813#L623 assume !(1 == ~t9_pc~0); 31739#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 31740#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32607#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32608#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 32469#L1231-2 assume !(1 == ~M_E~0); 32470#L1039-1 assume !(1 == ~T1_E~0); 32821#L1044-1 assume !(1 == ~T2_E~0); 32338#L1049-1 assume !(1 == ~T3_E~0); 32339#L1054-1 assume !(1 == ~T4_E~0); 32526#L1059-1 assume !(1 == ~T5_E~0); 32083#L1064-1 assume !(1 == ~T6_E~0); 32084#L1069-1 assume !(1 == ~T7_E~0); 32710#L1074-1 assume !(1 == ~T8_E~0); 32753#L1079-1 assume !(1 == ~T9_E~0); 32733#L1084-1 assume !(1 == ~E_M~0); 32734#L1089-1 assume !(1 == ~E_1~0); 32770#L1094-1 assume !(1 == ~E_2~0); 32412#L1099-1 assume !(1 == ~E_3~0); 32413#L1104-1 assume !(1 == ~E_4~0); 32611#L1109-1 assume !(1 == ~E_5~0); 32221#L1114-1 assume !(1 == ~E_6~0); 32222#L1119-1 assume !(1 == ~E_7~0); 32279#L1124-1 assume !(1 == ~E_8~0); 31748#L1129-1 assume !(1 == ~E_9~0); 31749#L1420-1 [2021-11-02 23:01:45,430 INFO L793 eck$LassoCheckResult]: Loop: 31749#L1420-1 assume !false; 32301#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 32173#L906 assume !false; 32174#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 32601#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 31720#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 32383#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 32384#L775 assume !(0 != eval_~tmp~0); 32869#L921 start_simulation_~kernel_st~0 := 2; 34677#L643-1 start_simulation_~kernel_st~0 := 3; 32837#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32838#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34420#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32410#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32411#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32141#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32142#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32502#L961-3 assume !(0 == ~T7_E~0); 32263#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32264#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32545#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31769#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31770#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31750#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31751#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32629#L1001-3 assume !(0 == ~E_5~0); 32235#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32236#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32664#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32720#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32432#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32433#L452-33 assume !(1 == ~m_pc~0); 32462#L452-35 is_master_triggered_~__retres1~0 := 0; 32787#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34457#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32673#L1159-33 assume !(0 != activate_threads_~tmp~1); 32674#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32750#L471-33 assume !(1 == ~t1_pc~0); 32420#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 32421#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32792#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 31685#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 31686#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32192#L490-33 assume !(1 == ~t2_pc~0); 32193#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 32296#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32845#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32803#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32804#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31689#L509-33 assume 1 == ~t3_pc~0; 31690#L510-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 31852#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32529#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32452#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31899#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31900#L528-33 assume 1 == ~t4_pc~0; 32675#L529-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 31947#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31948#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 31972#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32549#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32242#L547-33 assume !(1 == ~t5_pc~0); 32185#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 32186#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32524#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32579#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32709#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31828#L566-33 assume !(1 == ~t6_pc~0); 31829#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 31735#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31736#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32319#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32521#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31966#L585-33 assume !(1 == ~t7_pc~0); 31968#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 32029#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32282#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32563#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32316#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32317#L604-33 assume 1 == ~t8_pc~0; 31876#L605-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 31877#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31925#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 31926#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32574#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32695#L623-33 assume 1 == ~t9_pc~0; 32867#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 31818#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32568#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32623#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 31871#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 31872#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32642#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32011#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32012#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31808#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31809#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32346#L1069-3 assume !(1 == ~T7_E~0); 32347#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32619#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32533#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32455#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32456#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32367#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32368#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32636#L1109-3 assume !(1 == ~E_5~0); 32621#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32622#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32865#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32874#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32093#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 32094#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 31928#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 32711#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 32712#L1439 assume !(0 == start_simulation_~tmp~3); 32764#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 32210#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 31993#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 32407#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 32249#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 32250#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 32111#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 32112#L1452 assume !(0 != start_simulation_~tmp___0~1); 31749#L1420-1 [2021-11-02 23:01:45,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:45,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1951288572, now seen corresponding path program 1 times [2021-11-02 23:01:45,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:45,434 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929120029] [2021-11-02 23:01:45,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:45,435 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:45,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:45,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:45,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:45,512 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929120029] [2021-11-02 23:01:45,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929120029] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:45,513 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:45,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:45,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053907380] [2021-11-02 23:01:45,514 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:45,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:45,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1875226210, now seen corresponding path program 1 times [2021-11-02 23:01:45,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:45,516 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638512582] [2021-11-02 23:01:45,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:45,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:45,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:45,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:45,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:45,563 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638512582] [2021-11-02 23:01:45,563 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638512582] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:45,563 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:45,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:45,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660061882] [2021-11-02 23:01:45,564 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:45,565 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:45,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:01:45,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:01:45,566 INFO L87 Difference]: Start difference. First operand 3001 states and 4328 transitions. cyclomatic complexity: 1329 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:45,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:45,877 INFO L93 Difference]: Finished difference Result 8323 states and 11881 transitions. [2021-11-02 23:01:45,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:01:45,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8323 states and 11881 transitions. [2021-11-02 23:01:45,932 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8033 [2021-11-02 23:01:46,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8323 states to 8323 states and 11881 transitions. [2021-11-02 23:01:46,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8323 [2021-11-02 23:01:46,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8323 [2021-11-02 23:01:46,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8323 states and 11881 transitions. [2021-11-02 23:01:46,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:46,040 INFO L681 BuchiCegarLoop]: Abstraction has 8323 states and 11881 transitions. [2021-11-02 23:01:46,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8323 states and 11881 transitions. [2021-11-02 23:01:46,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8323 to 8021. [2021-11-02 23:01:46,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8021 states, 8021 states have (on average 1.4304949507542701) internal successors, (11474), 8020 states have internal predecessors, (11474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:46,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8021 states to 8021 states and 11474 transitions. [2021-11-02 23:01:46,300 INFO L704 BuchiCegarLoop]: Abstraction has 8021 states and 11474 transitions. [2021-11-02 23:01:46,301 INFO L587 BuchiCegarLoop]: Abstraction has 8021 states and 11474 transitions. [2021-11-02 23:01:46,301 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-02 23:01:46,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8021 states and 11474 transitions. [2021-11-02 23:01:46,337 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7886 [2021-11-02 23:01:46,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:46,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:46,340 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:46,340 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:46,341 INFO L791 eck$LassoCheckResult]: Stem: 43937#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 43938#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 44312#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43086#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 43087#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43325#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44146#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43624#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43625#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44186#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44187#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44247#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44235#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44236#L695-1 assume !(0 == ~M_E~0); 44295#L931-1 assume !(0 == ~T1_E~0); 44296#L936-1 assume !(0 == ~T2_E~0); 44307#L941-1 assume !(0 == ~T3_E~0); 43714#L946-1 assume !(0 == ~T4_E~0); 43715#L951-1 assume !(0 == ~T5_E~0); 43383#L956-1 assume !(0 == ~T6_E~0); 43384#L961-1 assume !(0 == ~T7_E~0); 43881#L966-1 assume !(0 == ~T8_E~0); 43882#L971-1 assume !(0 == ~T9_E~0); 44015#L976-1 assume !(0 == ~E_M~0); 43986#L981-1 assume !(0 == ~E_1~0); 43725#L986-1 assume !(0 == ~E_2~0); 43445#L991-1 assume !(0 == ~E_3~0); 43446#L996-1 assume !(0 == ~E_4~0); 44284#L1001-1 assume !(0 == ~E_5~0); 43935#L1006-1 assume !(0 == ~E_6~0); 43936#L1011-1 assume !(0 == ~E_7~0); 44248#L1016-1 assume !(0 == ~E_8~0); 44264#L1021-1 assume !(0 == ~E_9~0); 43045#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43046#L452 assume !(1 == ~m_pc~0); 43427#L452-2 is_master_triggered_~__retres1~0 := 0; 43428#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43861#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 43929#L1159 assume !(0 != activate_threads_~tmp~1); 44125#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43977#L471 assume !(1 == ~t1_pc~0); 43978#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 43443#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43444#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 43918#L1167 assume !(0 != activate_threads_~tmp___0~0); 43685#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43686#L490 assume !(1 == ~t2_pc~0); 43824#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 43825#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43866#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 43375#L1175 assume !(0 != activate_threads_~tmp___1~0); 43376#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43671#L509 assume !(1 == ~t3_pc~0); 43672#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 43392#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43393#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 44054#L1183 assume !(0 != activate_threads_~tmp___2~0); 43971#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43972#L528 assume !(1 == ~t4_pc~0); 43731#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 43679#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43680#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 43429#L1191 assume !(0 != activate_threads_~tmp___3~0); 43430#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44025#L547 assume !(1 == ~t5_pc~0); 44143#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 43793#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43403#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 43404#L1199 assume !(0 != activate_threads_~tmp___4~0); 43718#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44090#L566 assume !(1 == ~t6_pc~0); 43119#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 43118#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43448#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43356#L1207 assume !(0 != activate_threads_~tmp___5~0); 43219#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43220#L585 assume 1 == ~t7_pc~0; 43225#L586 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43226#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44292#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44046#L1215 assume !(0 != activate_threads_~tmp___6~0); 44047#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44155#L604 assume 1 == ~t8_pc~0; 44156#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 44119#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 43923#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43924#L1223 assume !(0 != activate_threads_~tmp___7~0); 44237#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 44231#L623 assume !(1 == ~t9_pc~0); 43073#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 43074#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 43975#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 43976#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 43827#L1231-2 assume !(1 == ~M_E~0); 43828#L1039-1 assume !(1 == ~T1_E~0); 44242#L1044-1 assume !(1 == ~T2_E~0); 43687#L1049-1 assume !(1 == ~T3_E~0); 43688#L1054-1 assume !(1 == ~T4_E~0); 43889#L1059-1 assume !(1 == ~T5_E~0); 43425#L1064-1 assume !(1 == ~T6_E~0); 43426#L1069-1 assume !(1 == ~T7_E~0); 44098#L1074-1 assume !(1 == ~T8_E~0); 44152#L1079-1 assume !(1 == ~T9_E~0); 44123#L1084-1 assume !(1 == ~E_M~0); 44124#L1089-1 assume !(1 == ~E_1~0); 44174#L1094-1 assume !(1 == ~E_2~0); 43766#L1099-1 assume !(1 == ~E_3~0); 43767#L1104-1 assume !(1 == ~E_4~0); 43979#L1109-1 assume !(1 == ~E_5~0); 43566#L1114-1 assume !(1 == ~E_6~0); 43567#L1119-1 assume !(1 == ~E_7~0); 43626#L1124-1 assume !(1 == ~E_8~0); 43082#L1129-1 assume !(1 == ~E_9~0); 43083#L1420-1 [2021-11-02 23:01:46,341 INFO L793 eck$LassoCheckResult]: Loop: 43083#L1420-1 assume !false; 43649#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 43517#L906 assume !false; 43518#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 43967#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 43055#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 43734#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 43735#L775 assume !(0 != eval_~tmp~0); 44308#L921 start_simulation_~kernel_st~0 := 2; 50909#L643-1 start_simulation_~kernel_st~0 := 3; 50908#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 50907#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50906#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50905#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50904#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50903#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50902#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50901#L961-3 assume !(0 == ~T7_E~0); 50900#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50899#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50898#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50897#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50896#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50895#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50894#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50893#L1001-3 assume !(0 == ~E_5~0); 50892#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50891#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50890#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50889#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50888#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50887#L452-33 assume !(1 == ~m_pc~0); 50886#L452-35 is_master_triggered_~__retres1~0 := 0; 50885#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50884#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 50883#L1159-33 assume !(0 != activate_threads_~tmp~1); 50882#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50881#L471-33 assume !(1 == ~t1_pc~0); 50880#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 50879#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50878#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 50877#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 50876#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50875#L490-33 assume 1 == ~t2_pc~0; 50873#L491-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 50872#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50871#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 50870#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 50869#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50868#L509-33 assume !(1 == ~t3_pc~0); 50867#L509-35 is_transmit3_triggered_~__retres1~3 := 0; 50866#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50865#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 50864#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 50863#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50862#L528-33 assume !(1 == ~t4_pc~0); 50860#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 50859#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50858#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 50857#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 50856#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50855#L547-33 assume !(1 == ~t5_pc~0); 50853#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 50852#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50851#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 50850#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 50849#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50848#L566-33 assume !(1 == ~t6_pc~0); 50846#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 50845#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 50844#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50843#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 50842#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50841#L585-33 assume 1 == ~t7_pc~0; 50839#L586-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 50838#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 50837#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50836#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 50835#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 50834#L604-33 assume !(1 == ~t8_pc~0); 50832#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 50831#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 50830#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50829#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 50828#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 50827#L623-33 assume 1 == ~t9_pc~0; 50825#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 50824#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 50823#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 50822#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 50821#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 50820#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50819#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50818#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50817#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50816#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50815#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50814#L1069-3 assume !(1 == ~T7_E~0); 50813#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50812#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50811#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50810#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50809#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50808#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50807#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50806#L1109-3 assume !(1 == ~E_5~0); 50805#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50804#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50803#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50802#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50801#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 50800#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 44255#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 44256#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 44166#L1439 assume !(0 == start_simulation_~tmp~3); 44168#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 43554#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 43331#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 43762#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 43595#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43596#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 43453#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 43454#L1452 assume !(0 != start_simulation_~tmp___0~1); 43083#L1420-1 [2021-11-02 23:01:46,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:46,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1315146563, now seen corresponding path program 1 times [2021-11-02 23:01:46,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:46,343 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151612567] [2021-11-02 23:01:46,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:46,343 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:46,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:46,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:46,390 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:46,390 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151612567] [2021-11-02 23:01:46,390 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151612567] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:46,390 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:46,391 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:46,391 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430541369] [2021-11-02 23:01:46,391 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:46,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:46,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1068012861, now seen corresponding path program 1 times [2021-11-02 23:01:46,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:46,393 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45713641] [2021-11-02 23:01:46,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:46,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:46,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:46,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:46,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:46,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45713641] [2021-11-02 23:01:46,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45713641] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:46,437 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:46,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:46,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117126234] [2021-11-02 23:01:46,438 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:46,438 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:46,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:01:46,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:01:46,439 INFO L87 Difference]: Start difference. First operand 8021 states and 11474 transitions. cyclomatic complexity: 3457 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:46,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:46,818 INFO L93 Difference]: Finished difference Result 22397 states and 31783 transitions. [2021-11-02 23:01:46,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:01:46,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22397 states and 31783 transitions. [2021-11-02 23:01:46,938 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21913 [2021-11-02 23:01:47,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22397 states to 22397 states and 31783 transitions. [2021-11-02 23:01:47,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22397 [2021-11-02 23:01:47,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22397 [2021-11-02 23:01:47,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22397 states and 31783 transitions. [2021-11-02 23:01:47,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:47,274 INFO L681 BuchiCegarLoop]: Abstraction has 22397 states and 31783 transitions. [2021-11-02 23:01:47,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22397 states and 31783 transitions. [2021-11-02 23:01:47,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22397 to 21878. [2021-11-02 23:01:47,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21878 states, 21878 states have (on average 1.4214279184568974) internal successors, (31098), 21877 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:47,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21878 states to 21878 states and 31098 transitions. [2021-11-02 23:01:47,833 INFO L704 BuchiCegarLoop]: Abstraction has 21878 states and 31098 transitions. [2021-11-02 23:01:47,833 INFO L587 BuchiCegarLoop]: Abstraction has 21878 states and 31098 transitions. [2021-11-02 23:01:47,833 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-02 23:01:47,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21878 states and 31098 transitions. [2021-11-02 23:01:47,925 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21724 [2021-11-02 23:01:47,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:47,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:48,050 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:48,050 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:48,051 INFO L791 eck$LassoCheckResult]: Stem: 74401#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 74402#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 74794#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 73515#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 73516#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73753#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74608#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74062#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74063#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74650#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74651#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74719#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74707#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74708#L695-1 assume !(0 == ~M_E~0); 74776#L931-1 assume !(0 == ~T1_E~0); 74777#L936-1 assume !(0 == ~T2_E~0); 74786#L941-1 assume !(0 == ~T3_E~0); 74165#L946-1 assume !(0 == ~T4_E~0); 74166#L951-1 assume !(0 == ~T5_E~0); 73810#L956-1 assume !(0 == ~T6_E~0); 73811#L961-1 assume !(0 == ~T7_E~0); 74342#L966-1 assume !(0 == ~T8_E~0); 74343#L971-1 assume !(0 == ~T9_E~0); 74483#L976-1 assume !(0 == ~E_M~0); 74453#L981-1 assume !(0 == ~E_1~0); 74176#L986-1 assume !(0 == ~E_2~0); 73870#L991-1 assume !(0 == ~E_3~0); 73871#L996-1 assume !(0 == ~E_4~0); 74756#L1001-1 assume !(0 == ~E_5~0); 74399#L1006-1 assume !(0 == ~E_6~0); 74400#L1011-1 assume !(0 == ~E_7~0); 74721#L1016-1 assume !(0 == ~E_8~0); 74737#L1021-1 assume !(0 == ~E_9~0); 73475#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 73476#L452 assume !(1 == ~m_pc~0); 73852#L452-2 is_master_triggered_~__retres1~0 := 0; 73853#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 74316#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 74392#L1159 assume !(0 != activate_threads_~tmp~1); 74591#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74442#L471 assume !(1 == ~t1_pc~0); 74443#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 73868#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73869#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 74381#L1167 assume !(0 != activate_threads_~tmp___0~0); 74123#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74124#L490 assume !(1 == ~t2_pc~0); 74276#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 74277#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74324#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 73801#L1175 assume !(0 != activate_threads_~tmp___1~0); 73802#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 74109#L509 assume !(1 == ~t3_pc~0); 74110#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 73819#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 73820#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 74519#L1183 assume !(0 != activate_threads_~tmp___2~0); 74437#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 74438#L528 assume !(1 == ~t4_pc~0); 74183#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 74117#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 74118#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 73854#L1191 assume !(0 != activate_threads_~tmp___3~0); 73855#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 74492#L547 assume !(1 == ~t5_pc~0); 74607#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 74246#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 73829#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 73830#L1199 assume !(0 != activate_threads_~tmp___4~0); 74169#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 74554#L566 assume !(1 == ~t6_pc~0); 73552#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 73551#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 73873#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 73781#L1207 assume !(0 != activate_threads_~tmp___5~0); 73649#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 73650#L585 assume !(1 == ~t7_pc~0); 74318#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 74319#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 74769#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 74512#L1215 assume !(0 != activate_threads_~tmp___6~0); 74513#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 74618#L604 assume 1 == ~t8_pc~0; 74619#L605 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 74585#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 74386#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 74387#L1223 assume !(0 != activate_threads_~tmp___7~0); 74710#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 74704#L623 assume !(1 == ~t9_pc~0); 73502#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 73503#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 74440#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 74441#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 74279#L1231-2 assume !(1 == ~M_E~0); 74280#L1039-1 assume !(1 == ~T1_E~0); 74713#L1044-1 assume !(1 == ~T2_E~0); 74127#L1049-1 assume !(1 == ~T3_E~0); 74128#L1054-1 assume !(1 == ~T4_E~0); 74351#L1059-1 assume !(1 == ~T5_E~0); 73850#L1064-1 assume !(1 == ~T6_E~0); 73851#L1069-1 assume !(1 == ~T7_E~0); 74565#L1074-1 assume !(1 == ~T8_E~0); 74614#L1079-1 assume !(1 == ~T9_E~0); 74589#L1084-1 assume !(1 == ~E_M~0); 74590#L1089-1 assume !(1 == ~E_1~0); 74631#L1094-1 assume !(1 == ~E_2~0); 74216#L1099-1 assume !(1 == ~E_3~0); 74217#L1104-1 assume !(1 == ~E_4~0); 74444#L1109-1 assume !(1 == ~E_5~0); 74002#L1114-1 assume !(1 == ~E_6~0); 74003#L1119-1 assume !(1 == ~E_7~0); 74064#L1124-1 assume !(1 == ~E_8~0); 73513#L1129-1 assume !(1 == ~E_9~0); 73514#L1420-1 [2021-11-02 23:01:48,051 INFO L793 eck$LassoCheckResult]: Loop: 73514#L1420-1 assume !false; 86696#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 86686#L906 assume !false; 86678#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 86037#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 85983#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 85980#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 85978#L775 assume !(0 != eval_~tmp~0); 85979#L921 start_simulation_~kernel_st~0 := 2; 93568#L643-1 start_simulation_~kernel_st~0 := 3; 93567#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 93566#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 93565#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93564#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93563#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93562#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 93561#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93560#L961-3 assume !(0 == ~T7_E~0); 93559#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93558#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 93557#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 93556#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93555#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93554#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93553#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 93552#L1001-3 assume !(0 == ~E_5~0); 93551#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 93550#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 93549#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93548#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 93547#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93546#L452-33 assume !(1 == ~m_pc~0); 93545#L452-35 is_master_triggered_~__retres1~0 := 0; 93544#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93543#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 93542#L1159-33 assume !(0 != activate_threads_~tmp~1); 93540#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93538#L471-33 assume !(1 == ~t1_pc~0); 93536#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 93534#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93532#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 93530#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 93528#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93526#L490-33 assume 1 == ~t2_pc~0; 93523#L491-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 93521#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93519#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 93517#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 93515#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93512#L509-33 assume !(1 == ~t3_pc~0); 93510#L509-35 is_transmit3_triggered_~__retres1~3 := 0; 93508#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93506#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 93504#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 93502#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93500#L528-33 assume !(1 == ~t4_pc~0); 93497#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 93495#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93493#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 93491#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 93489#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 93486#L547-33 assume !(1 == ~t5_pc~0); 93483#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 93481#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93479#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 93477#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 93474#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 93472#L566-33 assume !(1 == ~t6_pc~0); 93469#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 93467#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 93465#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 93463#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 93461#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 93458#L585-33 assume !(1 == ~t7_pc~0); 93456#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 93454#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 93452#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 93450#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 93448#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 93446#L604-33 assume !(1 == ~t8_pc~0); 93443#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 93441#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 93439#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 93437#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 93435#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 93432#L623-33 assume 1 == ~t9_pc~0; 93429#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 93427#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 93425#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 93423#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 93421#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 93418#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93416#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93414#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93412#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93410#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93408#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93406#L1069-3 assume !(1 == ~T7_E~0); 93404#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 93402#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 93400#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 93398#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93396#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93394#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 93392#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93390#L1109-3 assume !(1 == ~E_5~0); 93388#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 93386#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 93384#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93382#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 93380#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 93378#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 93367#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 93365#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 93363#L1439 assume !(0 == start_simulation_~tmp~3); 93361#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 93360#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 93350#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 93349#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 93348#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 93347#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 93346#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 93345#L1452 assume !(0 != start_simulation_~tmp___0~1); 73514#L1420-1 [2021-11-02 23:01:48,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:48,051 INFO L85 PathProgramCache]: Analyzing trace with hash -189886594, now seen corresponding path program 1 times [2021-11-02 23:01:48,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:48,052 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350892774] [2021-11-02 23:01:48,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:48,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:48,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:48,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:48,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:48,142 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350892774] [2021-11-02 23:01:48,143 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350892774] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:48,143 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:48,143 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:01:48,143 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131179115] [2021-11-02 23:01:48,144 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:48,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:48,145 INFO L85 PathProgramCache]: Analyzing trace with hash -662324196, now seen corresponding path program 1 times [2021-11-02 23:01:48,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:48,145 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451844239] [2021-11-02 23:01:48,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:48,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:48,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:48,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:48,188 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:48,188 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451844239] [2021-11-02 23:01:48,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451844239] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:48,188 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:48,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:48,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899466074] [2021-11-02 23:01:48,189 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:48,190 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:48,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:01:48,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:01:48,191 INFO L87 Difference]: Start difference. First operand 21878 states and 31098 transitions. cyclomatic complexity: 9228 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:48,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:48,976 INFO L93 Difference]: Finished difference Result 61223 states and 86451 transitions. [2021-11-02 23:01:48,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:01:48,977 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61223 states and 86451 transitions. [2021-11-02 23:01:49,391 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60328 [2021-11-02 23:01:49,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61223 states to 61223 states and 86451 transitions. [2021-11-02 23:01:49,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61223 [2021-11-02 23:01:49,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61223 [2021-11-02 23:01:49,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61223 states and 86451 transitions. [2021-11-02 23:01:49,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:49,908 INFO L681 BuchiCegarLoop]: Abstraction has 61223 states and 86451 transitions. [2021-11-02 23:01:49,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61223 states and 86451 transitions. [2021-11-02 23:01:50,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61223 to 60143. [2021-11-02 23:01:50,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60143 states, 60143 states have (on average 1.4141961658048319) internal successors, (85054), 60142 states have internal predecessors, (85054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:51,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60143 states to 60143 states and 85054 transitions. [2021-11-02 23:01:51,373 INFO L704 BuchiCegarLoop]: Abstraction has 60143 states and 85054 transitions. [2021-11-02 23:01:51,373 INFO L587 BuchiCegarLoop]: Abstraction has 60143 states and 85054 transitions. [2021-11-02 23:01:51,373 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-02 23:01:51,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60143 states and 85054 transitions. [2021-11-02 23:01:51,607 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59950 [2021-11-02 23:01:51,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:51,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:51,610 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:51,610 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:51,611 INFO L791 eck$LassoCheckResult]: Stem: 157511#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 157512#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 157911#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 156628#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 156629#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156865#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157720#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157163#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157164#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157768#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157769#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157835#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 157823#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 157824#L695-1 assume !(0 == ~M_E~0); 157881#L931-1 assume !(0 == ~T1_E~0); 157882#L936-1 assume !(0 == ~T2_E~0); 157898#L941-1 assume !(0 == ~T3_E~0); 157269#L946-1 assume !(0 == ~T4_E~0); 157270#L951-1 assume !(0 == ~T5_E~0); 156921#L956-1 assume !(0 == ~T6_E~0); 156922#L961-1 assume !(0 == ~T7_E~0); 157447#L966-1 assume !(0 == ~T8_E~0); 157448#L971-1 assume !(0 == ~T9_E~0); 157593#L976-1 assume !(0 == ~E_M~0); 157562#L981-1 assume !(0 == ~E_1~0); 157280#L986-1 assume !(0 == ~E_2~0); 156978#L991-1 assume !(0 == ~E_3~0); 156979#L996-1 assume !(0 == ~E_4~0); 157864#L1001-1 assume !(0 == ~E_5~0); 157508#L1006-1 assume !(0 == ~E_6~0); 157509#L1011-1 assume !(0 == ~E_7~0); 157836#L1016-1 assume !(0 == ~E_8~0); 157850#L1021-1 assume !(0 == ~E_9~0); 156588#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156589#L452 assume !(1 == ~m_pc~0); 156960#L452-2 is_master_triggered_~__retres1~0 := 0; 156961#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 157423#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 157500#L1159 assume !(0 != activate_threads_~tmp~1); 157701#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 157553#L471 assume !(1 == ~t1_pc~0); 157554#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 156976#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156977#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 157490#L1167 assume !(0 != activate_threads_~tmp___0~0); 157223#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157224#L490 assume !(1 == ~t2_pc~0); 157377#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 157378#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157431#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 156914#L1175 assume !(0 != activate_threads_~tmp___1~0); 156915#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157209#L509 assume !(1 == ~t3_pc~0); 157210#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 156932#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156933#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 157623#L1183 assume !(0 != activate_threads_~tmp___2~0); 157548#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 157549#L528 assume !(1 == ~t4_pc~0); 157287#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 157217#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157218#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 156962#L1191 assume !(0 != activate_threads_~tmp___3~0); 156963#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157601#L547 assume !(1 == ~t5_pc~0); 157719#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 157349#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156939#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 156940#L1199 assume !(0 != activate_threads_~tmp___4~0); 157273#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 157663#L566 assume !(1 == ~t6_pc~0); 156665#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 156664#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 156981#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 156895#L1207 assume !(0 != activate_threads_~tmp___5~0); 156761#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 156762#L585 assume !(1 == ~t7_pc~0); 157425#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 157426#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 157877#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 157617#L1215 assume !(0 != activate_threads_~tmp___6~0); 157618#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 157731#L604 assume !(1 == ~t8_pc~0); 157732#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 157693#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 157494#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 157495#L1223 assume !(0 != activate_threads_~tmp___7~0); 157826#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 157817#L623 assume !(1 == ~t9_pc~0); 156615#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 156616#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 157551#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 157552#L1231 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 157382#L1231-2 assume !(1 == ~M_E~0); 157383#L1039-1 assume !(1 == ~T1_E~0); 157830#L1044-1 assume !(1 == ~T2_E~0); 157227#L1049-1 assume !(1 == ~T3_E~0); 157228#L1054-1 assume !(1 == ~T4_E~0); 157455#L1059-1 assume !(1 == ~T5_E~0); 156958#L1064-1 assume !(1 == ~T6_E~0); 156959#L1069-1 assume !(1 == ~T7_E~0); 157672#L1074-1 assume !(1 == ~T8_E~0); 157727#L1079-1 assume !(1 == ~T9_E~0); 157699#L1084-1 assume !(1 == ~E_M~0); 157700#L1089-1 assume !(1 == ~E_1~0); 157748#L1094-1 assume !(1 == ~E_2~0); 157321#L1099-1 assume !(1 == ~E_3~0); 157322#L1104-1 assume !(1 == ~E_4~0); 157555#L1109-1 assume !(1 == ~E_5~0); 157107#L1114-1 assume !(1 == ~E_6~0); 157108#L1119-1 assume !(1 == ~E_7~0); 157165#L1124-1 assume !(1 == ~E_8~0); 156624#L1129-1 assume !(1 == ~E_9~0); 156625#L1420-1 [2021-11-02 23:01:51,611 INFO L793 eck$LassoCheckResult]: Loop: 156625#L1420-1 assume !false; 157188#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 157056#L906 assume !false; 157057#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 157544#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 156602#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 157290#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 157291#L775 assume !(0 != eval_~tmp~0); 157907#L921 start_simulation_~kernel_st~0 := 2; 215048#L643-1 start_simulation_~kernel_st~0 := 3; 215047#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 215046#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 215041#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 215040#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 215039#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 215038#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 215019#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 215016#L961-3 assume !(0 == ~T7_E~0); 215014#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 215012#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 215007#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 215006#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 215005#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 215003#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 214730#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 214727#L1001-3 assume !(0 == ~E_5~0); 214725#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 214723#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 214721#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 214718#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 214716#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 214715#L452-33 assume !(1 == ~m_pc~0); 214714#L452-35 is_master_triggered_~__retres1~0 := 0; 214712#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 214709#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 214703#L1159-33 assume !(0 != activate_threads_~tmp~1); 214701#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 214698#L471-33 assume !(1 == ~t1_pc~0); 214571#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 214570#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 214569#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 214509#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 214507#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 214505#L490-33 assume !(1 == ~t2_pc~0); 214503#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 214501#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 214500#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 214499#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 214498#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 214497#L509-33 assume !(1 == ~t3_pc~0); 156726#L509-35 is_transmit3_triggered_~__retres1~3 := 0; 156727#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 214375#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 157363#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 156770#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156771#L528-33 assume !(1 == ~t4_pc~0); 156822#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 156823#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156824#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 156846#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 157484#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157129#L547-33 assume !(1 == ~t5_pc~0); 157067#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 157068#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157451#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 157518#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 157671#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 156705#L566-33 assume !(1 == ~t6_pc~0); 156706#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 156884#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 214204#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 214203#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 157895#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 156842#L585-33 assume !(1 == ~t7_pc~0); 156843#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 157256#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 157498#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 157499#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 157203#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 157204#L604-33 assume !(1 == ~t8_pc~0); 157418#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 157419#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 156801#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 156802#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 157515#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 157654#L623-33 assume !(1 == ~t9_pc~0); 214686#L623-35 is_transmit9_triggered_~__retres1~9 := 0; 157505#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 157506#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 157569#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 156745#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 156746#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 157643#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 157644#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157526#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156683#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 156684#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 157233#L1069-3 assume !(1 == ~T7_E~0); 157234#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 157563#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 157461#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 157462#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 157523#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 157271#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 157272#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 157582#L1109-3 assume !(1 == ~E_5~0); 157567#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 157568#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 157887#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 157914#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 156968#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 156969#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 156804#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 157675#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 157676#L1439 assume !(0 == start_simulation_~tmp~3); 157742#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 214826#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 213851#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 213850#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 157134#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 157135#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 212957#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 157185#L1452 assume !(0 != start_simulation_~tmp___0~1); 156625#L1420-1 [2021-11-02 23:01:51,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:51,612 INFO L85 PathProgramCache]: Analyzing trace with hash -1961357569, now seen corresponding path program 1 times [2021-11-02 23:01:51,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:51,613 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828965467] [2021-11-02 23:01:51,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:51,613 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:51,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:51,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:51,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:51,673 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828965467] [2021-11-02 23:01:51,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828965467] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:51,674 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:51,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:51,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410631412] [2021-11-02 23:01:51,675 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:01:51,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:51,676 INFO L85 PathProgramCache]: Analyzing trace with hash 877924378, now seen corresponding path program 1 times [2021-11-02 23:01:51,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:51,676 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849057601] [2021-11-02 23:01:51,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:51,677 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:51,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:51,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:51,911 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:51,911 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849057601] [2021-11-02 23:01:51,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849057601] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:51,911 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:51,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:51,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958100805] [2021-11-02 23:01:51,912 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:51,913 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:51,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:01:51,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:01:51,914 INFO L87 Difference]: Start difference. First operand 60143 states and 85054 transitions. cyclomatic complexity: 24927 Second operand has 5 states, 5 states have (on average 22.6) internal successors, (113), 5 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:53,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:53,055 INFO L93 Difference]: Finished difference Result 132280 states and 189857 transitions. [2021-11-02 23:01:53,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 23:01:53,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132280 states and 189857 transitions. [2021-11-02 23:01:54,094 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 131909 [2021-11-02 23:01:54,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132280 states to 132280 states and 189857 transitions. [2021-11-02 23:01:54,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132280 [2021-11-02 23:01:54,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132280 [2021-11-02 23:01:54,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132280 states and 189857 transitions. [2021-11-02 23:01:54,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:54,930 INFO L681 BuchiCegarLoop]: Abstraction has 132280 states and 189857 transitions. [2021-11-02 23:01:55,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132280 states and 189857 transitions. [2021-11-02 23:01:56,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132280 to 62219. [2021-11-02 23:01:56,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62219 states, 62219 states have (on average 1.4003760909047076) internal successors, (87130), 62218 states have internal predecessors, (87130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:56,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62219 states to 62219 states and 87130 transitions. [2021-11-02 23:01:56,356 INFO L704 BuchiCegarLoop]: Abstraction has 62219 states and 87130 transitions. [2021-11-02 23:01:56,356 INFO L587 BuchiCegarLoop]: Abstraction has 62219 states and 87130 transitions. [2021-11-02 23:01:56,357 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-02 23:01:56,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62219 states and 87130 transitions. [2021-11-02 23:01:56,545 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62023 [2021-11-02 23:01:56,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:01:56,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:01:56,548 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:56,548 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:01:56,549 INFO L791 eck$LassoCheckResult]: Stem: 349943#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 349944#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 350338#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 349066#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 349067#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 349300#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350150#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349600#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349601#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 350197#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 350198#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 350260#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 350246#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350247#L695-1 assume !(0 == ~M_E~0); 350317#L931-1 assume !(0 == ~T1_E~0); 350318#L936-1 assume !(0 == ~T2_E~0); 350331#L941-1 assume !(0 == ~T3_E~0); 349703#L946-1 assume !(0 == ~T4_E~0); 349704#L951-1 assume !(0 == ~T5_E~0); 349356#L956-1 assume !(0 == ~T6_E~0); 349357#L961-1 assume !(0 == ~T7_E~0); 349882#L966-1 assume !(0 == ~T8_E~0); 349883#L971-1 assume !(0 == ~T9_E~0); 350028#L976-1 assume !(0 == ~E_M~0); 349993#L981-1 assume !(0 == ~E_1~0); 349716#L986-1 assume !(0 == ~E_2~0); 349412#L991-1 assume !(0 == ~E_3~0); 349413#L996-1 assume !(0 == ~E_4~0); 350301#L1001-1 assume !(0 == ~E_5~0); 349941#L1006-1 assume !(0 == ~E_6~0); 349942#L1011-1 assume !(0 == ~E_7~0); 350261#L1016-1 assume !(0 == ~E_8~0); 350281#L1021-1 assume !(0 == ~E_9~0); 349026#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 349027#L452 assume !(1 == ~m_pc~0); 349394#L452-2 is_master_triggered_~__retres1~0 := 0; 349395#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 349856#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 349935#L1159 assume !(0 != activate_threads_~tmp~1); 350137#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 349981#L471 assume !(1 == ~t1_pc~0); 349982#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 349410#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 349411#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 349924#L1167 assume !(0 != activate_threads_~tmp___0~0); 349662#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 349663#L490 assume !(1 == ~t2_pc~0); 349814#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 349815#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 349865#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 349349#L1175 assume !(0 != activate_threads_~tmp___1~0); 349350#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 349647#L509 assume !(1 == ~t3_pc~0); 349648#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 349367#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 349368#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 350061#L1183 assume !(0 != activate_threads_~tmp___2~0); 349976#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 349977#L528 assume !(1 == ~t4_pc~0); 349721#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 349656#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 349657#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 349396#L1191 assume !(0 != activate_threads_~tmp___3~0); 349397#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 350037#L547 assume !(1 == ~t5_pc~0); 350149#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 349784#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 349374#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 349375#L1199 assume !(0 != activate_threads_~tmp___4~0); 349707#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 350100#L566 assume !(1 == ~t6_pc~0); 349101#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 349100#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 349415#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 349329#L1207 assume !(0 != activate_threads_~tmp___5~0); 349199#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 349200#L585 assume !(1 == ~t7_pc~0); 349859#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 349860#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 350311#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 350053#L1215 assume !(0 != activate_threads_~tmp___6~0); 350054#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 350162#L604 assume !(1 == ~t8_pc~0); 350163#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 350131#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 349928#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 349929#L1223 assume !(0 != activate_threads_~tmp___7~0); 350249#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 350243#L623 assume !(1 == ~t9_pc~0); 349053#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 349054#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 350360#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 350175#L1231 assume !(0 != activate_threads_~tmp___8~0); 349820#L1231-2 assume !(1 == ~M_E~0); 349821#L1039-1 assume !(1 == ~T1_E~0); 350253#L1044-1 assume !(1 == ~T2_E~0); 349668#L1049-1 assume !(1 == ~T3_E~0); 349669#L1054-1 assume !(1 == ~T4_E~0); 349890#L1059-1 assume !(1 == ~T5_E~0); 349392#L1064-1 assume !(1 == ~T6_E~0); 349393#L1069-1 assume !(1 == ~T7_E~0); 350109#L1074-1 assume !(1 == ~T8_E~0); 350158#L1079-1 assume !(1 == ~T9_E~0); 350135#L1084-1 assume !(1 == ~E_M~0); 350136#L1089-1 assume !(1 == ~E_1~0); 350178#L1094-1 assume !(1 == ~E_2~0); 349754#L1099-1 assume !(1 == ~E_3~0); 349755#L1104-1 assume !(1 == ~E_4~0); 349983#L1109-1 assume !(1 == ~E_5~0); 349543#L1114-1 assume !(1 == ~E_6~0); 349544#L1119-1 assume !(1 == ~E_7~0); 349602#L1124-1 assume !(1 == ~E_8~0); 349064#L1129-1 assume !(1 == ~E_9~0); 349065#L1420-1 [2021-11-02 23:01:56,549 INFO L793 eck$LassoCheckResult]: Loop: 349065#L1420-1 assume !false; 394463#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 394461#L906 assume !false; 394455#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 394368#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 394361#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 394359#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 394356#L775 assume !(0 != eval_~tmp~0); 394357#L921 start_simulation_~kernel_st~0 := 2; 396031#L643-1 start_simulation_~kernel_st~0 := 3; 396029#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 396027#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396025#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 396023#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 396021#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 396019#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 396017#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 396015#L961-3 assume !(0 == ~T7_E~0); 396013#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 396011#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 396009#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 396007#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 396005#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 395992#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 395988#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 395987#L1001-3 assume !(0 == ~E_5~0); 395986#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 395985#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 395984#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 395983#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 395982#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 395981#L452-33 assume !(1 == ~m_pc~0); 395980#L452-35 is_master_triggered_~__retres1~0 := 0; 395979#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 395978#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 395977#L1159-33 assume !(0 != activate_threads_~tmp~1); 395976#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 395975#L471-33 assume !(1 == ~t1_pc~0); 395974#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 395973#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 395972#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 395971#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 395970#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 395969#L490-33 assume !(1 == ~t2_pc~0); 395968#L490-35 is_transmit2_triggered_~__retres1~2 := 0; 395966#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 395965#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 395964#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 395963#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 395962#L509-33 assume !(1 == ~t3_pc~0); 395961#L509-35 is_transmit3_triggered_~__retres1~3 := 0; 395960#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 395959#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 395958#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 395957#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 395956#L528-33 assume !(1 == ~t4_pc~0); 395954#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 395953#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 395952#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 395951#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 395950#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 395949#L547-33 assume !(1 == ~t5_pc~0); 395947#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 395946#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 395945#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 395944#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 395943#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 395942#L566-33 assume !(1 == ~t6_pc~0); 395940#L566-35 is_transmit6_triggered_~__retres1~6 := 0; 395939#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 395938#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 395937#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 395936#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 395935#L585-33 assume !(1 == ~t7_pc~0); 395934#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 395933#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 395932#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 395931#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 395930#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 395929#L604-33 assume !(1 == ~t8_pc~0); 395928#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 395927#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 395926#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 395925#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 395924#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 395923#L623-33 assume 1 == ~t9_pc~0; 395922#L624-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 395920#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 395918#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 395916#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 395914#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 395913#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 395911#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 395909#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 395907#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 395905#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 395903#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 395901#L1069-3 assume !(1 == ~T7_E~0); 395899#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 395897#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 395895#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 395893#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 395891#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 395889#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 395887#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 395885#L1109-3 assume !(1 == ~E_5~0); 395883#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 395881#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 395879#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 395427#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 395426#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 395288#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 395277#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 395276#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 395271#L1439 assume !(0 == start_simulation_~tmp~3); 395261#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 395111#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 395100#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 395098#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 395096#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 395094#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 395092#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 395090#L1452 assume !(0 != start_simulation_~tmp___0~1); 349065#L1420-1 [2021-11-02 23:01:56,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:56,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1538655743, now seen corresponding path program 1 times [2021-11-02 23:01:56,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:56,551 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023995589] [2021-11-02 23:01:56,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:56,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:56,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:01:56,568 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:01:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:01:56,675 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:01:56,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:01:56,676 INFO L85 PathProgramCache]: Analyzing trace with hash 354603707, now seen corresponding path program 1 times [2021-11-02 23:01:56,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:01:56,677 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569978401] [2021-11-02 23:01:56,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:01:56,677 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:01:56,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:01:56,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:01:56,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:01:56,723 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569978401] [2021-11-02 23:01:56,723 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569978401] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:01:56,724 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:01:56,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:01:56,724 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194023531] [2021-11-02 23:01:56,724 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:01:56,725 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:01:56,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:01:56,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:01:56,726 INFO L87 Difference]: Start difference. First operand 62219 states and 87130 transitions. cyclomatic complexity: 24927 Second operand has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:01:57,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:01:57,740 INFO L93 Difference]: Finished difference Result 114020 states and 157447 transitions. [2021-11-02 23:01:57,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-02 23:01:57,740 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114020 states and 157447 transitions. [2021-11-02 23:01:58,272 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 113749 [2021-11-02 23:01:59,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114020 states to 114020 states and 157447 transitions. [2021-11-02 23:01:59,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114020 [2021-11-02 23:01:59,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114020 [2021-11-02 23:01:59,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114020 states and 157447 transitions. [2021-11-02 23:01:59,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:01:59,291 INFO L681 BuchiCegarLoop]: Abstraction has 114020 states and 157447 transitions. [2021-11-02 23:01:59,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114020 states and 157447 transitions. [2021-11-02 23:02:00,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114020 to 62462. [2021-11-02 23:02:00,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62462 states, 62462 states have (on average 1.3988184816368352) internal successors, (87373), 62461 states have internal predecessors, (87373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:00,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62462 states to 62462 states and 87373 transitions. [2021-11-02 23:02:00,712 INFO L704 BuchiCegarLoop]: Abstraction has 62462 states and 87373 transitions. [2021-11-02 23:02:00,712 INFO L587 BuchiCegarLoop]: Abstraction has 62462 states and 87373 transitions. [2021-11-02 23:02:00,712 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-02 23:02:00,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62462 states and 87373 transitions. [2021-11-02 23:02:00,903 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62266 [2021-11-02 23:02:00,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:02:00,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:02:00,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:00,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:00,907 INFO L791 eck$LassoCheckResult]: Stem: 526197#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 526198#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 526593#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 525321#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 525322#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 525552#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 526402#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 525856#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 525857#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 526450#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 526451#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 526516#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 526503#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 526504#L695-1 assume !(0 == ~M_E~0); 526570#L931-1 assume !(0 == ~T1_E~0); 526571#L936-1 assume !(0 == ~T2_E~0); 526583#L941-1 assume !(0 == ~T3_E~0); 525960#L946-1 assume !(0 == ~T4_E~0); 525961#L951-1 assume !(0 == ~T5_E~0); 525611#L956-1 assume !(0 == ~T6_E~0); 525612#L961-1 assume !(0 == ~T7_E~0); 526139#L966-1 assume !(0 == ~T8_E~0); 526140#L971-1 assume !(0 == ~T9_E~0); 526277#L976-1 assume !(0 == ~E_M~0); 526244#L981-1 assume !(0 == ~E_1~0); 525971#L986-1 assume !(0 == ~E_2~0); 525668#L991-1 assume !(0 == ~E_3~0); 525669#L996-1 assume !(0 == ~E_4~0); 526554#L1001-1 assume !(0 == ~E_5~0); 526194#L1006-1 assume !(0 == ~E_6~0); 526195#L1011-1 assume !(0 == ~E_7~0); 526517#L1016-1 assume !(0 == ~E_8~0); 526534#L1021-1 assume !(0 == ~E_9~0); 525281#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 525282#L452 assume !(1 == ~m_pc~0); 525650#L452-2 is_master_triggered_~__retres1~0 := 0; 525651#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 526112#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 526189#L1159 assume !(0 != activate_threads_~tmp~1); 526385#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 526234#L471 assume !(1 == ~t1_pc~0); 526235#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 525666#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 525667#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 526179#L1167 assume !(0 != activate_threads_~tmp___0~0); 525921#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 525922#L490 assume !(1 == ~t2_pc~0); 526068#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 526069#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 526122#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 525604#L1175 assume !(0 != activate_threads_~tmp___1~0); 525605#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 525907#L509 assume !(1 == ~t3_pc~0); 525908#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 525618#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 525619#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 526311#L1183 assume !(0 != activate_threads_~tmp___2~0); 526229#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 526230#L528 assume !(1 == ~t4_pc~0); 525977#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 525915#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 525916#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 525652#L1191 assume !(0 != activate_threads_~tmp___3~0); 525653#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 526285#L547 assume !(1 == ~t5_pc~0); 526400#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 526038#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 525629#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 525630#L1199 assume !(0 != activate_threads_~tmp___4~0); 525964#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 526347#L566 assume !(1 == ~t6_pc~0); 525354#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 525353#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 525671#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 525583#L1207 assume !(0 != activate_threads_~tmp___5~0); 525454#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 525455#L585 assume !(1 == ~t7_pc~0); 526115#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 526116#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 526566#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 526302#L1215 assume !(0 != activate_threads_~tmp___6~0); 526303#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 526411#L604 assume !(1 == ~t8_pc~0); 526412#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 526379#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 526184#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 526185#L1223 assume !(0 != activate_threads_~tmp___7~0); 526505#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 526499#L623 assume !(1 == ~t9_pc~0); 525308#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 525309#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 526232#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 526233#L1231 assume !(0 != activate_threads_~tmp___8~0); 526071#L1231-2 assume !(1 == ~M_E~0); 526072#L1039-1 assume !(1 == ~T1_E~0); 526508#L1044-1 assume !(1 == ~T2_E~0); 525923#L1049-1 assume !(1 == ~T3_E~0); 525924#L1054-1 assume !(1 == ~T4_E~0); 526147#L1059-1 assume !(1 == ~T5_E~0); 525648#L1064-1 assume !(1 == ~T6_E~0); 525649#L1069-1 assume !(1 == ~T7_E~0); 526356#L1074-1 assume !(1 == ~T8_E~0); 526409#L1079-1 assume !(1 == ~T9_E~0); 526383#L1084-1 assume !(1 == ~E_M~0); 526384#L1089-1 assume !(1 == ~E_1~0); 526430#L1094-1 assume !(1 == ~E_2~0); 526008#L1099-1 assume !(1 == ~E_3~0); 526009#L1104-1 assume !(1 == ~E_4~0); 526236#L1109-1 assume !(1 == ~E_5~0); 525799#L1114-1 assume !(1 == ~E_6~0); 525800#L1119-1 assume !(1 == ~E_7~0); 525858#L1124-1 assume !(1 == ~E_8~0); 525317#L1129-1 assume !(1 == ~E_9~0); 525318#L1420-1 [2021-11-02 23:02:00,907 INFO L793 eck$LassoCheckResult]: Loop: 525318#L1420-1 assume !false; 565512#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 565500#L906 assume !false; 565499#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 565494#L708 assume !(0 == ~m_st~0); 565495#L712 assume !(0 == ~t1_st~0); 565498#L716 assume !(0 == ~t2_st~0); 565492#L720 assume !(0 == ~t3_st~0); 565493#L724 assume !(0 == ~t4_st~0); 565497#L728 assume !(0 == ~t5_st~0); 565490#L732 assume !(0 == ~t6_st~0); 565491#L736 assume !(0 == ~t7_st~0); 565496#L740 assume !(0 == ~t8_st~0); 565488#L744 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10 := 0; 565489#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 561167#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 561168#L775 assume !(0 != eval_~tmp~0); 565943#L921 start_simulation_~kernel_st~0 := 2; 565942#L643-1 start_simulation_~kernel_st~0 := 3; 565941#L931-2 assume 0 == ~M_E~0;~M_E~0 := 1; 565940#L931-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 565939#L936-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 565938#L941-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 565937#L946-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 565936#L951-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 565935#L956-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 565934#L961-3 assume !(0 == ~T7_E~0); 565933#L966-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 565932#L971-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 565931#L976-3 assume 0 == ~E_M~0;~E_M~0 := 1; 565930#L981-3 assume 0 == ~E_1~0;~E_1~0 := 1; 565929#L986-3 assume 0 == ~E_2~0;~E_2~0 := 1; 565928#L991-3 assume 0 == ~E_3~0;~E_3~0 := 1; 565927#L996-3 assume 0 == ~E_4~0;~E_4~0 := 1; 565926#L1001-3 assume !(0 == ~E_5~0); 565925#L1006-3 assume 0 == ~E_6~0;~E_6~0 := 1; 565924#L1011-3 assume 0 == ~E_7~0;~E_7~0 := 1; 565923#L1016-3 assume 0 == ~E_8~0;~E_8~0 := 1; 565922#L1021-3 assume 0 == ~E_9~0;~E_9~0 := 1; 565921#L1026-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 565920#L452-33 assume !(1 == ~m_pc~0); 565919#L452-35 is_master_triggered_~__retres1~0 := 0; 565918#L463-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 565917#L464-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 565916#L1159-33 assume !(0 != activate_threads_~tmp~1); 565915#L1159-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 565914#L471-33 assume !(1 == ~t1_pc~0); 565913#L471-35 is_transmit1_triggered_~__retres1~1 := 0; 565912#L482-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 565911#L483-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 565910#L1167-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 565909#L1167-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 565908#L490-33 assume 1 == ~t2_pc~0; 565906#L491-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 565905#L501-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 565904#L502-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 565903#L1175-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 565902#L1175-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 565901#L509-33 assume !(1 == ~t3_pc~0); 565900#L509-35 is_transmit3_triggered_~__retres1~3 := 0; 565899#L520-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 565898#L521-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 565897#L1183-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 565896#L1183-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 565895#L528-33 assume !(1 == ~t4_pc~0); 565893#L528-35 is_transmit4_triggered_~__retres1~4 := 0; 565892#L539-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 565891#L540-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 565890#L1191-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 565889#L1191-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 565888#L547-33 assume !(1 == ~t5_pc~0); 565886#L547-35 is_transmit5_triggered_~__retres1~5 := 0; 565885#L558-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 565884#L559-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 565883#L1199-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 565882#L1199-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 565881#L566-33 assume 1 == ~t6_pc~0; 565880#L567-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 565878#L577-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 565877#L578-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 565876#L1207-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 565875#L1207-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 565874#L585-33 assume !(1 == ~t7_pc~0); 565873#L585-35 is_transmit7_triggered_~__retres1~7 := 0; 565872#L596-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 565871#L597-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 565870#L1215-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 565869#L1215-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 565868#L604-33 assume !(1 == ~t8_pc~0); 565867#L604-35 is_transmit8_triggered_~__retres1~8 := 0; 565866#L615-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 565865#L616-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 565864#L1223-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 565863#L1223-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 565862#L623-33 assume !(1 == ~t9_pc~0); 565860#L623-35 is_transmit9_triggered_~__retres1~9 := 0; 565858#L634-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 565856#L635-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 565852#L1231-33 assume !(0 != activate_threads_~tmp___8~0); 565851#L1231-35 assume 1 == ~M_E~0;~M_E~0 := 2; 565850#L1039-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 565849#L1044-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 565848#L1049-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 565847#L1054-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 565846#L1059-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 565845#L1064-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 565844#L1069-3 assume !(1 == ~T7_E~0); 565843#L1074-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 565842#L1079-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 565841#L1084-3 assume 1 == ~E_M~0;~E_M~0 := 2; 565840#L1089-3 assume 1 == ~E_1~0;~E_1~0 := 2; 565839#L1094-3 assume 1 == ~E_2~0;~E_2~0 := 2; 565838#L1099-3 assume 1 == ~E_3~0;~E_3~0 := 2; 565837#L1104-3 assume 1 == ~E_4~0;~E_4~0 := 2; 565836#L1109-3 assume !(1 == ~E_5~0); 565835#L1114-3 assume 1 == ~E_6~0;~E_6~0 := 2; 565834#L1119-3 assume 1 == ~E_7~0;~E_7~0 := 2; 565833#L1124-3 assume 1 == ~E_8~0;~E_8~0 := 2; 565832#L1129-3 assume 1 == ~E_9~0;~E_9~0 := 2; 565831#L1134-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 565830#L708-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 565819#L760-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 565817#L761-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 565779#L1439 assume !(0 == start_simulation_~tmp~3); 565701#L1439-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 565700#L708-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 565689#L760-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 565687#L761-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 565685#L1394 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 565683#L1401 stop_simulation_#res := stop_simulation_~__retres2~0; 565681#L1402 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 565679#L1452 assume !(0 != start_simulation_~tmp___0~1); 525318#L1420-1 [2021-11-02 23:02:00,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:00,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1538655743, now seen corresponding path program 2 times [2021-11-02 23:02:00,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:00,909 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833320539] [2021-11-02 23:02:00,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:00,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:00,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:00,927 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:00,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:01,002 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:01,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:01,003 INFO L85 PathProgramCache]: Analyzing trace with hash 113545259, now seen corresponding path program 1 times [2021-11-02 23:02:01,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:01,003 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320087820] [2021-11-02 23:02:01,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:01,003 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:01,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:02:01,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:02:01,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:02:01,052 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320087820] [2021-11-02 23:02:01,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320087820] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:02:01,052 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:02:01,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:02:01,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449166529] [2021-11-02 23:02:01,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:02:01,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:02:01,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:02:01,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:02:01,054 INFO L87 Difference]: Start difference. First operand 62462 states and 87373 transitions. cyclomatic complexity: 24927 Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 3 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:01,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:02:01,565 INFO L93 Difference]: Finished difference Result 107486 states and 147734 transitions. [2021-11-02 23:02:01,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:02:01,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107486 states and 147734 transitions. [2021-11-02 23:02:02,183 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 107288 [2021-11-02 23:02:03,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107486 states to 107486 states and 147734 transitions. [2021-11-02 23:02:03,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107486 [2021-11-02 23:02:03,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107486 [2021-11-02 23:02:03,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107486 states and 147734 transitions. [2021-11-02 23:02:03,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:02:03,272 INFO L681 BuchiCegarLoop]: Abstraction has 107486 states and 147734 transitions. [2021-11-02 23:02:03,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107486 states and 147734 transitions. [2021-11-02 23:02:04,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107486 to 106446. [2021-11-02 23:02:04,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106446 states, 106446 states have (on average 1.3748003682618417) internal successors, (146342), 106445 states have internal predecessors, (146342), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:04,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106446 states to 106446 states and 146342 transitions. [2021-11-02 23:02:04,989 INFO L704 BuchiCegarLoop]: Abstraction has 106446 states and 146342 transitions. [2021-11-02 23:02:04,989 INFO L587 BuchiCegarLoop]: Abstraction has 106446 states and 146342 transitions. [2021-11-02 23:02:04,989 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-02 23:02:04,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106446 states and 146342 transitions. [2021-11-02 23:02:05,261 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 106248 [2021-11-02 23:02:05,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:02:05,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:02:05,262 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:05,262 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:05,263 INFO L791 eck$LassoCheckResult]: Stem: 696161#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 696162#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 696559#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 695275#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 695276#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 695509#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 696368#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 695815#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 695816#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 696422#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 696423#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 696487#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 696473#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 696474#L695-1 assume !(0 == ~M_E~0); 696538#L931-1 assume !(0 == ~T1_E~0); 696539#L936-1 assume !(0 == ~T2_E~0); 696549#L941-1 assume !(0 == ~T3_E~0); 695917#L946-1 assume !(0 == ~T4_E~0); 695918#L951-1 assume !(0 == ~T5_E~0); 695566#L956-1 assume !(0 == ~T6_E~0); 695567#L961-1 assume !(0 == ~T7_E~0); 696099#L966-1 assume !(0 == ~T8_E~0); 696100#L971-1 assume !(0 == ~T9_E~0); 696248#L976-1 assume !(0 == ~E_M~0); 696215#L981-1 assume !(0 == ~E_1~0); 695928#L986-1 assume !(0 == ~E_2~0); 695627#L991-1 assume !(0 == ~E_3~0); 695628#L996-1 assume !(0 == ~E_4~0); 696521#L1001-1 assume !(0 == ~E_5~0); 696159#L1006-1 assume !(0 == ~E_6~0); 696160#L1011-1 assume !(0 == ~E_7~0); 696488#L1016-1 assume !(0 == ~E_8~0); 696503#L1021-1 assume !(0 == ~E_9~0); 695235#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 695236#L452 assume !(1 == ~m_pc~0); 695608#L452-2 is_master_triggered_~__retres1~0 := 0; 695609#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 696074#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 696150#L1159 assume !(0 != activate_threads_~tmp~1); 696352#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 696204#L471 assume !(1 == ~t1_pc~0); 696205#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 695625#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 695626#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 696140#L1167 assume !(0 != activate_threads_~tmp___0~0); 695879#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 695880#L490 assume !(1 == ~t2_pc~0); 696026#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 696027#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 696083#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 695560#L1175 assume !(0 != activate_threads_~tmp___1~0); 695561#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 695865#L509 assume !(1 == ~t3_pc~0); 695866#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 695575#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 695576#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 696282#L1183 assume !(0 != activate_threads_~tmp___2~0); 696199#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 696200#L528 assume !(1 == ~t4_pc~0); 695933#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 695873#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 695874#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 695610#L1191 assume !(0 != activate_threads_~tmp___3~0); 695611#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 696256#L547 assume !(1 == ~t5_pc~0); 696367#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 695995#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 695586#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 695587#L1199 assume !(0 != activate_threads_~tmp___4~0); 695921#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 696316#L566 assume !(1 == ~t6_pc~0); 695308#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 695307#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 695630#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 695539#L1207 assume !(0 != activate_threads_~tmp___5~0); 695406#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 695407#L585 assume !(1 == ~t7_pc~0); 696077#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 696078#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 696533#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 696274#L1215 assume !(0 != activate_threads_~tmp___6~0); 696275#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 696378#L604 assume !(1 == ~t8_pc~0); 696379#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 696346#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 696145#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 696146#L1223 assume !(0 != activate_threads_~tmp___7~0); 696475#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 696470#L623 assume !(1 == ~t9_pc~0); 695262#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 695263#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 696202#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 696203#L1231 assume !(0 != activate_threads_~tmp___8~0); 696029#L1231-2 assume !(1 == ~M_E~0); 696030#L1039-1 assume !(1 == ~T1_E~0); 696479#L1044-1 assume !(1 == ~T2_E~0); 695881#L1049-1 assume !(1 == ~T3_E~0); 695882#L1054-1 assume !(1 == ~T4_E~0); 696108#L1059-1 assume !(1 == ~T5_E~0); 695606#L1064-1 assume !(1 == ~T6_E~0); 695607#L1069-1 assume !(1 == ~T7_E~0); 696326#L1074-1 assume !(1 == ~T8_E~0); 696374#L1079-1 assume !(1 == ~T9_E~0); 696350#L1084-1 assume !(1 == ~E_M~0); 696351#L1089-1 assume !(1 == ~E_1~0); 696398#L1094-1 assume !(1 == ~E_2~0); 695965#L1099-1 assume !(1 == ~E_3~0); 695966#L1104-1 assume !(1 == ~E_4~0); 696206#L1109-1 assume !(1 == ~E_5~0); 695755#L1114-1 assume !(1 == ~E_6~0); 695756#L1119-1 assume !(1 == ~E_7~0); 695817#L1124-1 assume !(1 == ~E_8~0); 695271#L1129-1 assume !(1 == ~E_9~0); 695272#L1420-1 assume !false; 738657#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 738655#L906 [2021-11-02 23:02:05,263 INFO L793 eck$LassoCheckResult]: Loop: 738655#L906 assume !false; 738653#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 738650#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 738648#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 738637#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 738627#L775 assume 0 != eval_~tmp~0; 738618#L775-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 738607#L783 assume !(0 != eval_~tmp_ndt_1~0); 738598#L780 assume !(0 == ~t1_st~0); 738587#L794 assume !(0 == ~t2_st~0); 738577#L808 assume !(0 == ~t3_st~0); 737435#L822 assume !(0 == ~t4_st~0); 738750#L836 assume !(0 == ~t5_st~0); 738739#L850 assume !(0 == ~t6_st~0); 738730#L864 assume !(0 == ~t7_st~0); 738721#L878 assume !(0 == ~t8_st~0); 738661#L892 assume !(0 == ~t9_st~0); 738655#L906 [2021-11-02 23:02:05,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:05,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1179401661, now seen corresponding path program 1 times [2021-11-02 23:02:05,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:05,264 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668882953] [2021-11-02 23:02:05,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:05,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:05,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:05,279 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:05,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:05,336 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:05,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:05,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1564251751, now seen corresponding path program 1 times [2021-11-02 23:02:05,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:05,337 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909893556] [2021-11-02 23:02:05,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:05,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:05,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:05,341 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:05,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:05,346 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:05,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:05,347 INFO L85 PathProgramCache]: Analyzing trace with hash 450977893, now seen corresponding path program 1 times [2021-11-02 23:02:05,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:05,347 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424849702] [2021-11-02 23:02:05,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:05,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:05,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:02:05,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:02:05,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:02:05,387 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424849702] [2021-11-02 23:02:05,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424849702] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:02:05,388 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:02:05,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:02:05,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412644352] [2021-11-02 23:02:05,544 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:02:05,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:02:05,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:02:05,546 INFO L87 Difference]: Start difference. First operand 106446 states and 146342 transitions. cyclomatic complexity: 39927 Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 3 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:06,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:02:06,787 INFO L93 Difference]: Finished difference Result 206607 states and 281761 transitions. [2021-11-02 23:02:06,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:02:06,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 206607 states and 281761 transitions. [2021-11-02 23:02:07,542 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 201275 [2021-11-02 23:02:08,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 206607 states to 206607 states and 281761 transitions. [2021-11-02 23:02:08,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 206607 [2021-11-02 23:02:08,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 206607 [2021-11-02 23:02:08,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 206607 states and 281761 transitions. [2021-11-02 23:02:08,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:02:08,998 INFO L681 BuchiCegarLoop]: Abstraction has 206607 states and 281761 transitions. [2021-11-02 23:02:09,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206607 states and 281761 transitions. [2021-11-02 23:02:11,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206607 to 203367. [2021-11-02 23:02:11,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203367 states, 203367 states have (on average 1.3645035821937679) internal successors, (277495), 203366 states have internal predecessors, (277495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:11,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203367 states to 203367 states and 277495 transitions. [2021-11-02 23:02:11,654 INFO L704 BuchiCegarLoop]: Abstraction has 203367 states and 277495 transitions. [2021-11-02 23:02:11,654 INFO L587 BuchiCegarLoop]: Abstraction has 203367 states and 277495 transitions. [2021-11-02 23:02:11,654 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-02 23:02:11,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203367 states and 277495 transitions. [2021-11-02 23:02:13,245 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 198035 [2021-11-02 23:02:13,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:02:13,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:02:13,247 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:13,248 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:13,248 INFO L791 eck$LassoCheckResult]: Stem: 1009221#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1009222#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1009648#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1008337#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 1008338#L650-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1008569#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1009439#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1008870#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1008871#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1009494#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1009495#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1009564#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1009548#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1009549#L695-1 assume !(0 == ~M_E~0); 1009621#L931-1 assume !(0 == ~T1_E~0); 1009622#L936-1 assume !(0 == ~T2_E~0); 1009635#L941-1 assume !(0 == ~T3_E~0); 1008971#L946-1 assume !(0 == ~T4_E~0); 1008972#L951-1 assume !(0 == ~T5_E~0); 1008627#L956-1 assume !(0 == ~T6_E~0); 1008628#L961-1 assume !(0 == ~T7_E~0); 1009158#L966-1 assume !(0 == ~T8_E~0); 1009159#L971-1 assume !(0 == ~T9_E~0); 1009307#L976-1 assume !(0 == ~E_M~0); 1009275#L981-1 assume !(0 == ~E_1~0); 1008982#L986-1 assume !(0 == ~E_2~0); 1008686#L991-1 assume !(0 == ~E_3~0); 1008687#L996-1 assume !(0 == ~E_4~0); 1009604#L1001-1 assume !(0 == ~E_5~0); 1009219#L1006-1 assume !(0 == ~E_6~0); 1009220#L1011-1 assume !(0 == ~E_7~0); 1009565#L1016-1 assume !(0 == ~E_8~0); 1009587#L1021-1 assume !(0 == ~E_9~0); 1008297#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1008298#L452 assume !(1 == ~m_pc~0); 1008668#L452-2 is_master_triggered_~__retres1~0 := 0; 1008669#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1009131#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1009212#L1159 assume !(0 != activate_threads_~tmp~1); 1009416#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1009263#L471 assume !(1 == ~t1_pc~0); 1009264#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 1008684#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1008685#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1009201#L1167 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1009630#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1009641#L490 assume !(1 == ~t2_pc~0); 1009642#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 1108674#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1108673#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1108672#L1175 assume !(0 != activate_threads_~tmp___1~0); 1108671#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1108670#L509 assume !(1 == ~t3_pc~0); 1108669#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 1108668#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1108667#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1108666#L1183 assume !(0 != activate_threads_~tmp___2~0); 1108665#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1009657#L528 assume !(1 == ~t4_pc~0); 1009658#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 1108661#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1108660#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1008670#L1191 assume !(0 != activate_threads_~tmp___3~0); 1008671#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1009434#L547 assume !(1 == ~t5_pc~0); 1009436#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 1108648#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1108646#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1108644#L1199 assume !(0 != activate_threads_~tmp___4~0); 1009667#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1009668#L566 assume !(1 == ~t6_pc~0); 1008370#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 1008369#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1008689#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1008601#L1207 assume !(0 != activate_threads_~tmp___5~0); 1008470#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1008471#L585 assume !(1 == ~t7_pc~0); 1009134#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 1009135#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1009618#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1009334#L1215 assume !(0 != activate_threads_~tmp___6~0); 1009335#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1009680#L604 assume !(1 == ~t8_pc~0); 1009673#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 1009674#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1009207#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1009208#L1223 assume !(0 != activate_threads_~tmp___7~0); 1009550#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1009551#L623 assume !(1 == ~t9_pc~0); 1008324#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 1008325#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1009261#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1009262#L1231 assume !(0 != activate_threads_~tmp___8~0); 1009090#L1231-2 assume !(1 == ~M_E~0); 1009091#L1039-1 assume !(1 == ~T1_E~0); 1009554#L1044-1 assume !(1 == ~T2_E~0); 1009555#L1049-1 assume !(1 == ~T3_E~0); 1009695#L1054-1 assume !(1 == ~T4_E~0); 1009696#L1059-1 assume !(1 == ~T5_E~0); 1008666#L1064-1 assume !(1 == ~T6_E~0); 1008667#L1069-1 assume !(1 == ~T7_E~0); 1009653#L1074-1 assume !(1 == ~T8_E~0); 1009654#L1079-1 assume !(1 == ~T9_E~0); 1009414#L1084-1 assume !(1 == ~E_M~0); 1009415#L1089-1 assume !(1 == ~E_1~0); 1009472#L1094-1 assume !(1 == ~E_2~0); 1009473#L1099-1 assume !(1 == ~E_3~0); 1009576#L1104-1 assume !(1 == ~E_4~0); 1009577#L1109-1 assume !(1 == ~E_5~0); 1008813#L1114-1 assume !(1 == ~E_6~0); 1008814#L1119-1 assume !(1 == ~E_7~0); 1008872#L1124-1 assume !(1 == ~E_8~0); 1008333#L1129-1 assume !(1 == ~E_9~0); 1008334#L1420-1 assume !false; 1117414#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 1117415#L906 [2021-11-02 23:02:13,249 INFO L793 eck$LassoCheckResult]: Loop: 1117415#L906 assume !false; 1131401#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 1131398#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 1131396#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 1131394#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1131392#L775 assume 0 != eval_~tmp~0; 1131390#L775-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1131388#L783 assume !(0 != eval_~tmp_ndt_1~0); 1131385#L780 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1108281#L797 assume !(0 != eval_~tmp_ndt_2~0); 1131337#L794 assume !(0 == ~t2_st~0); 1131333#L808 assume !(0 == ~t3_st~0); 1131331#L822 assume !(0 == ~t4_st~0); 1131326#L836 assume !(0 == ~t5_st~0); 1117552#L850 assume !(0 == ~t6_st~0); 1117549#L864 assume !(0 == ~t7_st~0); 1117439#L878 assume !(0 == ~t8_st~0); 1117441#L892 assume !(0 == ~t9_st~0); 1117415#L906 [2021-11-02 23:02:13,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:13,249 INFO L85 PathProgramCache]: Analyzing trace with hash -1859413949, now seen corresponding path program 1 times [2021-11-02 23:02:13,249 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:13,250 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785203702] [2021-11-02 23:02:13,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:13,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:13,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:02:13,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:02:13,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:02:13,280 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785203702] [2021-11-02 23:02:13,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785203702] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:02:13,280 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:02:13,281 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:02:13,281 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899451318] [2021-11-02 23:02:13,281 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:02:13,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:13,282 INFO L85 PathProgramCache]: Analyzing trace with hash -74726741, now seen corresponding path program 1 times [2021-11-02 23:02:13,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:13,282 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49283267] [2021-11-02 23:02:13,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:13,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:13,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:13,287 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:13,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:13,293 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:13,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:02:13,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:02:13,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:02:13,454 INFO L87 Difference]: Start difference. First operand 203367 states and 277495 transitions. cyclomatic complexity: 74175 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:13,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:02:13,969 INFO L93 Difference]: Finished difference Result 166245 states and 226582 transitions. [2021-11-02 23:02:13,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:02:13,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166245 states and 226582 transitions. [2021-11-02 23:02:15,387 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 165977 [2021-11-02 23:02:15,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166245 states to 166245 states and 226582 transitions. [2021-11-02 23:02:15,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 166245 [2021-11-02 23:02:15,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 166245 [2021-11-02 23:02:15,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166245 states and 226582 transitions. [2021-11-02 23:02:15,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:02:15,922 INFO L681 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-02 23:02:15,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166245 states and 226582 transitions. [2021-11-02 23:02:17,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166245 to 166245. [2021-11-02 23:02:17,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166245 states, 166245 states have (on average 1.3629402388041745) internal successors, (226582), 166244 states have internal predecessors, (226582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:18,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166245 states to 166245 states and 226582 transitions. [2021-11-02 23:02:18,106 INFO L704 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-02 23:02:18,107 INFO L587 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-02 23:02:18,107 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-02 23:02:18,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 166245 states and 226582 transitions. [2021-11-02 23:02:19,377 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 165977 [2021-11-02 23:02:19,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:02:19,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:02:19,393 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:19,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:02:19,394 INFO L791 eck$LassoCheckResult]: Stem: 1378834#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1378835#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1379223#L1383 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1377955#L643 assume 1 == ~m_i~0;~m_st~0 := 0; 1377956#L650-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1378187#L655-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1379031#L660-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1378496#L665-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1378497#L670-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1379081#L675-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1379082#L680-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1379149#L685-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1379137#L690-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1379138#L695-1 assume !(0 == ~M_E~0); 1379204#L931-1 assume !(0 == ~T1_E~0); 1379205#L936-1 assume !(0 == ~T2_E~0); 1379214#L941-1 assume !(0 == ~T3_E~0); 1378595#L946-1 assume !(0 == ~T4_E~0); 1378596#L951-1 assume !(0 == ~T5_E~0); 1378242#L956-1 assume !(0 == ~T6_E~0); 1378243#L961-1 assume !(0 == ~T7_E~0); 1378777#L966-1 assume !(0 == ~T8_E~0); 1378778#L971-1 assume !(0 == ~T9_E~0); 1378912#L976-1 assume !(0 == ~E_M~0); 1378885#L981-1 assume !(0 == ~E_1~0); 1378606#L986-1 assume !(0 == ~E_2~0); 1378299#L991-1 assume !(0 == ~E_3~0); 1378300#L996-1 assume !(0 == ~E_4~0); 1379181#L1001-1 assume !(0 == ~E_5~0); 1378832#L1006-1 assume !(0 == ~E_6~0); 1378833#L1011-1 assume !(0 == ~E_7~0); 1379150#L1016-1 assume !(0 == ~E_8~0); 1379166#L1021-1 assume !(0 == ~E_9~0); 1377915#L1026-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1377916#L452 assume !(1 == ~m_pc~0); 1378281#L452-2 is_master_triggered_~__retres1~0 := 0; 1378282#L463 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1378752#L464 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1378825#L1159 assume !(0 != activate_threads_~tmp~1); 1379015#L1159-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1378873#L471 assume !(1 == ~t1_pc~0); 1378874#L471-2 is_transmit1_triggered_~__retres1~1 := 0; 1378297#L482 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1378298#L483 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1378816#L1167 assume !(0 != activate_threads_~tmp___0~0); 1378557#L1167-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1378558#L490 assume !(1 == ~t2_pc~0); 1378706#L490-2 is_transmit2_triggered_~__retres1~2 := 0; 1378707#L501 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1378761#L502 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1378234#L1175 assume !(0 != activate_threads_~tmp___1~0); 1378235#L1175-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1378543#L509 assume !(1 == ~t3_pc~0); 1378544#L509-2 is_transmit3_triggered_~__retres1~3 := 0; 1378253#L520 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1378254#L521 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1378943#L1183 assume !(0 != activate_threads_~tmp___2~0); 1378868#L1183-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1378869#L528 assume !(1 == ~t4_pc~0); 1378613#L528-2 is_transmit4_triggered_~__retres1~4 := 0; 1378551#L539 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1378552#L540 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1378283#L1191 assume !(0 != activate_threads_~tmp___3~0); 1378284#L1191-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1378920#L547 assume !(1 == ~t5_pc~0); 1379029#L547-2 is_transmit5_triggered_~__retres1~5 := 0; 1378676#L558 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1378260#L559 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1378261#L1199 assume !(0 != activate_threads_~tmp___4~0); 1378599#L1199-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1378976#L566 assume !(1 == ~t6_pc~0); 1377990#L566-2 is_transmit6_triggered_~__retres1~6 := 0; 1377989#L577 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1378303#L578 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1378215#L1207 assume !(0 != activate_threads_~tmp___5~0); 1378088#L1207-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1378089#L585 assume !(1 == ~t7_pc~0); 1378755#L585-2 is_transmit7_triggered_~__retres1~7 := 0; 1378756#L596 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1379198#L597 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1378937#L1215 assume !(0 != activate_threads_~tmp___6~0); 1378938#L1215-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1379041#L604 assume !(1 == ~t8_pc~0); 1379042#L604-2 is_transmit8_triggered_~__retres1~8 := 0; 1379008#L615 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1378820#L616 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1378821#L1223 assume !(0 != activate_threads_~tmp___7~0); 1379140#L1223-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1379131#L623 assume !(1 == ~t9_pc~0); 1377942#L623-2 is_transmit9_triggered_~__retres1~9 := 0; 1377943#L634 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1378871#L635 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1378872#L1231 assume !(0 != activate_threads_~tmp___8~0); 1378712#L1231-2 assume !(1 == ~M_E~0); 1378713#L1039-1 assume !(1 == ~T1_E~0); 1379144#L1044-1 assume !(1 == ~T2_E~0); 1378561#L1049-1 assume !(1 == ~T3_E~0); 1378562#L1054-1 assume !(1 == ~T4_E~0); 1378785#L1059-1 assume !(1 == ~T5_E~0); 1378279#L1064-1 assume !(1 == ~T6_E~0); 1378280#L1069-1 assume !(1 == ~T7_E~0); 1378986#L1074-1 assume !(1 == ~T8_E~0); 1379037#L1079-1 assume !(1 == ~T9_E~0); 1379013#L1084-1 assume !(1 == ~E_M~0); 1379014#L1089-1 assume !(1 == ~E_1~0); 1379057#L1094-1 assume !(1 == ~E_2~0); 1378644#L1099-1 assume !(1 == ~E_3~0); 1378645#L1104-1 assume !(1 == ~E_4~0); 1378875#L1109-1 assume !(1 == ~E_5~0); 1378438#L1114-1 assume !(1 == ~E_6~0); 1378439#L1119-1 assume !(1 == ~E_7~0); 1378498#L1124-1 assume !(1 == ~E_8~0); 1377953#L1129-1 assume !(1 == ~E_9~0); 1377954#L1420-1 assume !false; 1484201#L1421 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 1484199#L906 [2021-11-02 23:02:19,394 INFO L793 eck$LassoCheckResult]: Loop: 1484199#L906 assume !false; 1484197#L771 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 1484194#L708 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 1484192#L760 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 1484188#L761 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1484186#L775 assume 0 != eval_~tmp~0; 1484184#L775-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1484182#L783 assume !(0 != eval_~tmp_ndt_1~0); 1484179#L780 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1484178#L797 assume !(0 != eval_~tmp_ndt_2~0); 1484170#L794 assume !(0 == ~t2_st~0); 1484167#L808 assume !(0 == ~t3_st~0); 1484163#L822 assume !(0 == ~t4_st~0); 1484158#L836 assume !(0 == ~t5_st~0); 1484154#L850 assume !(0 == ~t6_st~0); 1484150#L864 assume !(0 == ~t7_st~0); 1467662#L878 assume !(0 == ~t8_st~0); 1484149#L892 assume !(0 == ~t9_st~0); 1484199#L906 [2021-11-02 23:02:19,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:19,395 INFO L85 PathProgramCache]: Analyzing trace with hash -1179401661, now seen corresponding path program 2 times [2021-11-02 23:02:19,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:19,408 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219140506] [2021-11-02 23:02:19,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:19,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:19,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:19,452 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:19,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:19,535 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:19,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:19,536 INFO L85 PathProgramCache]: Analyzing trace with hash -74726741, now seen corresponding path program 2 times [2021-11-02 23:02:19,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:19,537 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899622061] [2021-11-02 23:02:19,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:19,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:19,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:19,547 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-02 23:02:19,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-02 23:02:19,553 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-02 23:02:19,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:02:19,554 INFO L85 PathProgramCache]: Analyzing trace with hash -226477971, now seen corresponding path program 1 times [2021-11-02 23:02:19,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:02:19,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119582474] [2021-11-02 23:02:19,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:02:19,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:02:19,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:02:19,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:02:19,599 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:02:19,599 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119582474] [2021-11-02 23:02:19,599 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119582474] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:02:19,599 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:02:19,599 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:02:19,600 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698699927] [2021-11-02 23:02:19,775 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:02:19,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:02:19,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:02:19,775 INFO L87 Difference]: Start difference. First operand 166245 states and 226582 transitions. cyclomatic complexity: 60368 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:02:20,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:02:20,812 INFO L93 Difference]: Finished difference Result 321756 states and 436877 transitions. [2021-11-02 23:02:20,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:02:20,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 321756 states and 436877 transitions. [2021-11-02 23:02:23,061 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 321343 [2021-11-02 23:02:23,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 321756 states to 321756 states and 436877 transitions. [2021-11-02 23:02:23,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 321756 [2021-11-02 23:02:24,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 321756 [2021-11-02 23:02:24,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 321756 states and 436877 transitions. [2021-11-02 23:02:24,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:02:24,627 INFO L681 BuchiCegarLoop]: Abstraction has 321756 states and 436877 transitions. [2021-11-02 23:02:24,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321756 states and 436877 transitions.