./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9ad7fb26 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8636ce8641966242d4b565897af6099a657e8070649e2d99611dba3f37a77b1c --- Real Ultimate output --- This is Ultimate 0.2.1-dev-9ad7fb2 [2021-11-02 23:16:56,980 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-02 23:16:56,982 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-02 23:16:57,014 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-02 23:16:57,015 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-02 23:16:57,016 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-02 23:16:57,018 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-02 23:16:57,021 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-02 23:16:57,023 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-02 23:16:57,024 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-02 23:16:57,026 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-02 23:16:57,027 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-02 23:16:57,028 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-02 23:16:57,030 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-02 23:16:57,032 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-02 23:16:57,034 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-02 23:16:57,035 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-02 23:16:57,037 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-02 23:16:57,039 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-02 23:16:57,042 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-02 23:16:57,044 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-02 23:16:57,046 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-02 23:16:57,048 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-02 23:16:57,049 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-02 23:16:57,053 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-02 23:16:57,054 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-02 23:16:57,054 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-02 23:16:57,056 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-02 23:16:57,056 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-02 23:16:57,058 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-02 23:16:57,058 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-02 23:16:57,059 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-02 23:16:57,060 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-02 23:16:57,062 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-02 23:16:57,063 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-02 23:16:57,064 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-02 23:16:57,064 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-02 23:16:57,065 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-02 23:16:57,065 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-02 23:16:57,066 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-02 23:16:57,067 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-02 23:16:57,068 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-02 23:16:57,095 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-02 23:16:57,096 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-02 23:16:57,096 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-02 23:16:57,096 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-02 23:16:57,098 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-02 23:16:57,098 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-02 23:16:57,098 INFO L138 SettingsManager]: * Use SBE=true [2021-11-02 23:16:57,098 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-02 23:16:57,099 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-02 23:16:57,099 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-02 23:16:57,099 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-02 23:16:57,099 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-02 23:16:57,100 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-02 23:16:57,100 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-02 23:16:57,100 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-02 23:16:57,100 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-02 23:16:57,101 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-02 23:16:57,101 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-02 23:16:57,101 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-02 23:16:57,101 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-02 23:16:57,102 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-02 23:16:57,102 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-02 23:16:57,102 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-02 23:16:57,102 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-02 23:16:57,103 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-02 23:16:57,103 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-02 23:16:57,103 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-02 23:16:57,103 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-02 23:16:57,104 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-02 23:16:57,104 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-02 23:16:57,104 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-02 23:16:57,104 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-02 23:16:57,106 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-02 23:16:57,106 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8636ce8641966242d4b565897af6099a657e8070649e2d99611dba3f37a77b1c [2021-11-02 23:16:57,358 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-02 23:16:57,399 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-02 23:16:57,401 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-02 23:16:57,403 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-02 23:16:57,404 INFO L275 PluginConnector]: CDTParser initialized [2021-11-02 23:16:57,405 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/../../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-02 23:16:57,512 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/data/c13e5d0f1/defa7a091b6e4c43bacb8d49395c7331/FLAGf67618eca [2021-11-02 23:16:58,091 INFO L306 CDTParser]: Found 1 translation units. [2021-11-02 23:16:58,092 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2021-11-02 23:16:58,118 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/data/c13e5d0f1/defa7a091b6e4c43bacb8d49395c7331/FLAGf67618eca [2021-11-02 23:16:58,377 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/data/c13e5d0f1/defa7a091b6e4c43bacb8d49395c7331 [2021-11-02 23:16:58,379 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-02 23:16:58,381 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-02 23:16:58,394 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-02 23:16:58,394 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-02 23:16:58,398 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-02 23:16:58,399 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:58,400 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@730cc25a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58, skipping insertion in model container [2021-11-02 23:16:58,400 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:58,407 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-02 23:16:58,485 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-02 23:16:58,659 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[366,379] [2021-11-02 23:16:58,797 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:16:58,809 INFO L203 MainTranslator]: Completed pre-run [2021-11-02 23:16:58,821 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[366,379] [2021-11-02 23:16:58,906 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:16:58,937 INFO L208 MainTranslator]: Completed translation [2021-11-02 23:16:58,938 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58 WrapperNode [2021-11-02 23:16:58,939 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-02 23:16:58,940 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-02 23:16:58,940 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-02 23:16:58,940 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-02 23:16:58,948 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:58,962 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,105 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-02 23:16:59,106 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-02 23:16:59,106 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-02 23:16:59,106 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-02 23:16:59,115 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,115 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,131 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,131 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,189 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,244 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,253 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,291 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-02 23:16:59,292 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-02 23:16:59,292 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-02 23:16:59,293 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-02 23:16:59,304 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (1/1) ... [2021-11-02 23:16:59,315 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-02 23:16:59,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/z3 [2021-11-02 23:16:59,345 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-02 23:16:59,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_17fef3db-95ca-460e-8836-28462abc2a90/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-02 23:16:59,410 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-02 23:16:59,410 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-02 23:16:59,411 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-02 23:16:59,411 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-02 23:17:01,995 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-02 23:17:01,995 INFO L299 CfgBuilder]: Removed 555 assume(true) statements. [2021-11-02 23:17:02,000 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:17:02 BoogieIcfgContainer [2021-11-02 23:17:02,001 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-02 23:17:02,003 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-02 23:17:02,004 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-02 23:17:02,008 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-02 23:17:02,009 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:17:02,010 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 11:16:58" (1/3) ... [2021-11-02 23:17:02,011 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c216d67 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:17:02, skipping insertion in model container [2021-11-02 23:17:02,011 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:17:02,012 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:16:58" (2/3) ... [2021-11-02 23:17:02,012 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c216d67 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:17:02, skipping insertion in model container [2021-11-02 23:17:02,012 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:17:02,012 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:17:02" (3/3) ... [2021-11-02 23:17:02,014 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2021-11-02 23:17:02,069 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-02 23:17:02,069 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-02 23:17:02,070 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-02 23:17:02,070 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-02 23:17:02,070 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-02 23:17:02,070 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-02 23:17:02,070 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-02 23:17:02,070 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-02 23:17:02,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1763 states, 1762 states have (on average 1.5096481271282634) internal successors, (2660), 1762 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:02,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1600 [2021-11-02 23:17:02,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:02,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:02,269 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:02,269 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:02,270 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-02 23:17:02,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1763 states, 1762 states have (on average 1.5096481271282634) internal successors, (2660), 1762 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:02,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1600 [2021-11-02 23:17:02,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:02,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:02,310 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:02,310 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:02,328 INFO L791 eck$LassoCheckResult]: Stem: 432#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1706#L-1true havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1380#L1770true havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1585#L838true assume !(1 == ~m_i~0);~m_st~0 := 2; 1268#L845-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1046#L850-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1676#L855-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 84#L860-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 871#L865-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 816#L870-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1233#L875-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 981#L880-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 442#L885-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 403#L890-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 195#L895-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 473#L900-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 271#L905-1true assume !(0 == ~M_E~0); 731#L1198-1true assume !(0 == ~T1_E~0); 616#L1203-1true assume !(0 == ~T2_E~0); 1203#L1208-1true assume !(0 == ~T3_E~0); 1415#L1213-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1477#L1218-1true assume !(0 == ~T5_E~0); 19#L1223-1true assume !(0 == ~T6_E~0); 1174#L1228-1true assume !(0 == ~T7_E~0); 1642#L1233-1true assume !(0 == ~T8_E~0); 891#L1238-1true assume !(0 == ~T9_E~0); 1356#L1243-1true assume !(0 == ~T10_E~0); 1725#L1248-1true assume !(0 == ~T11_E~0); 1379#L1253-1true assume 0 == ~T12_E~0;~T12_E~0 := 1; 660#L1258-1true assume !(0 == ~E_M~0); 468#L1263-1true assume !(0 == ~E_1~0); 693#L1268-1true assume !(0 == ~E_2~0); 1282#L1273-1true assume !(0 == ~E_3~0); 1633#L1278-1true assume !(0 == ~E_4~0); 1104#L1283-1true assume !(0 == ~E_5~0); 1661#L1288-1true assume !(0 == ~E_6~0); 1462#L1293-1true assume 0 == ~E_7~0;~E_7~0 := 1; 1430#L1298-1true assume !(0 == ~E_8~0); 1298#L1303-1true assume !(0 == ~E_9~0); 198#L1308-1true assume !(0 == ~E_10~0); 159#L1313-1true assume !(0 == ~E_11~0); 1708#L1318-1true assume !(0 == ~E_12~0); 161#L1323-1true havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 949#L590true assume 1 == ~m_pc~0; 1227#L591true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 848#L601true is_master_triggered_#res := is_master_triggered_~__retres1~0; 452#L602true activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 371#L1489true assume !(0 != activate_threads_~tmp~1); 933#L1489-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1206#L609true assume !(1 == ~t1_pc~0); 913#L609-2true is_transmit1_triggered_~__retres1~1 := 0; 721#L620true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42#L621true activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1424#L1497true assume !(0 != activate_threads_~tmp___0~0); 1659#L1497-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1713#L628true assume 1 == ~t2_pc~0; 253#L629true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 830#L639true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 698#L640true activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1459#L1505true assume !(0 != activate_threads_~tmp___1~0); 714#L1505-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 555#L647true assume !(1 == ~t3_pc~0); 765#L647-2true is_transmit3_triggered_~__retres1~3 := 0; 587#L658true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 359#L659true activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1450#L1513true assume !(0 != activate_threads_~tmp___2~0); 749#L1513-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1678#L666true assume 1 == ~t4_pc~0; 147#L667true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 224#L677true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1426#L678true activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1754#L1521true assume !(0 != activate_threads_~tmp___3~0); 1549#L1521-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1629#L685true assume 1 == ~t5_pc~0; 858#L686true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1487#L696true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 592#L697true activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 220#L1529true assume !(0 != activate_threads_~tmp___4~0); 480#L1529-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 380#L704true assume !(1 == ~t6_pc~0); 1592#L704-2true is_transmit6_triggered_~__retres1~6 := 0; 686#L715true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1381#L716true activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1074#L1537true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 424#L1537-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 673#L723true assume 1 == ~t7_pc~0; 931#L724true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 990#L734true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1346#L735true activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1641#L1545true assume !(0 != activate_threads_~tmp___6~0); 772#L1545-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 245#L742true assume !(1 == ~t8_pc~0); 1406#L742-2true is_transmit8_triggered_~__retres1~8 := 0; 329#L753true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 794#L754true activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1086#L1553true assume !(0 != activate_threads_~tmp___7~0); 984#L1553-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 291#L761true assume 1 == ~t9_pc~0; 1733#L762true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 223#L772true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1710#L773true activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1105#L1561true assume !(0 != activate_threads_~tmp___8~0); 361#L1561-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 121#L780true assume !(1 == ~t10_pc~0); 1312#L780-2true is_transmit10_triggered_~__retres1~10 := 0; 236#L791true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 804#L792true activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 901#L1569true assume !(0 != activate_threads_~tmp___9~0); 1361#L1569-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1242#L799true assume 1 == ~t11_pc~0; 808#L800true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 122#L810true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 740#L811true activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1136#L1577true assume !(0 != activate_threads_~tmp___10~0); 200#L1577-2true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 752#L818true assume !(1 == ~t12_pc~0); 22#L818-2true is_transmit12_triggered_~__retres1~12 := 0; 801#L829true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1540#L830true activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1762#L1585true assume !(0 != activate_threads_~tmp___11~0); 1748#L1585-2true assume !(1 == ~M_E~0); 3#L1336-1true assume !(1 == ~T1_E~0); 973#L1341-1true assume !(1 == ~T2_E~0); 32#L1346-1true assume !(1 == ~T3_E~0); 1328#L1351-1true assume !(1 == ~T4_E~0); 181#L1356-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1717#L1361-1true assume !(1 == ~T6_E~0); 1452#L1366-1true assume !(1 == ~T7_E~0); 205#L1371-1true assume !(1 == ~T8_E~0); 1305#L1376-1true assume !(1 == ~T9_E~0); 696#L1381-1true assume !(1 == ~T10_E~0); 1539#L1386-1true assume !(1 == ~T11_E~0); 1649#L1391-1true assume !(1 == ~T12_E~0); 1583#L1396-1true assume 1 == ~E_M~0;~E_M~0 := 2; 613#L1401-1true assume !(1 == ~E_1~0); 1159#L1406-1true assume !(1 == ~E_2~0); 831#L1411-1true assume !(1 == ~E_3~0); 1503#L1416-1true assume !(1 == ~E_4~0); 572#L1421-1true assume !(1 == ~E_5~0); 277#L1426-1true assume !(1 == ~E_6~0); 977#L1431-1true assume !(1 == ~E_7~0); 55#L1436-1true assume 1 == ~E_8~0;~E_8~0 := 2; 723#L1441-1true assume !(1 == ~E_9~0); 463#L1446-1true assume !(1 == ~E_10~0); 1652#L1451-1true assume !(1 == ~E_11~0); 1048#L1456-1true assume !(1 == ~E_12~0); 1761#L1807-1true [2021-11-02 23:17:02,334 INFO L793 eck$LassoCheckResult]: Loop: 1761#L1807-1true assume !false; 576#L1808true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 1301#L1173true assume !true; 1082#L1188true start_simulation_~kernel_st~0 := 2; 229#L838-1true start_simulation_~kernel_st~0 := 3; 559#L1198-2true assume 0 == ~M_E~0;~M_E~0 := 1; 897#L1198-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1153#L1203-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 149#L1208-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1555#L1213-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 427#L1218-3true assume !(0 == ~T5_E~0); 135#L1223-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1360#L1228-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1117#L1233-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 776#L1238-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1214#L1243-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 631#L1248-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 865#L1253-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1528#L1258-3true assume !(0 == ~E_M~0); 132#L1263-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1497#L1268-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1511#L1273-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1749#L1278-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1512#L1283-3true assume 0 == ~E_5~0;~E_5~0 := 1; 240#L1288-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1666#L1293-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1114#L1298-3true assume !(0 == ~E_8~0); 1576#L1303-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1325#L1308-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1112#L1313-3true assume 0 == ~E_11~0;~E_11~0 := 1; 633#L1318-3true assume 0 == ~E_12~0;~E_12~0 := 1; 133#L1323-3true havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1632#L590-42true assume !(1 == ~m_pc~0); 1289#L590-44true is_master_triggered_~__retres1~0 := 0; 1376#L601-14true is_master_triggered_#res := is_master_triggered_~__retres1~0; 639#L602-14true activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 797#L1489-42true assume !(0 != activate_threads_~tmp~1); 900#L1489-44true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1419#L609-42true assume !(1 == ~t1_pc~0); 131#L609-44true is_transmit1_triggered_~__retres1~1 := 0; 1764#L620-14true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 496#L621-14true activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1434#L1497-42true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1677#L1497-44true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 712#L628-42true assume !(1 == ~t2_pc~0); 619#L628-44true is_transmit2_triggered_~__retres1~2 := 0; 484#L639-14true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1342#L640-14true activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1429#L1505-42true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 278#L1505-44true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1703#L647-42true assume !(1 == ~t3_pc~0); 1514#L647-44true is_transmit3_triggered_~__retres1~3 := 0; 1475#L658-14true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 242#L659-14true activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1103#L1513-42true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 993#L1513-44true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 346#L666-42true assume 1 == ~t4_pc~0; 303#L667-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1306#L677-14true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 350#L678-14true activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1728#L1521-42true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1216#L1521-44true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1045#L685-42true assume !(1 == ~t5_pc~0); 846#L685-44true is_transmit5_triggered_~__retres1~5 := 0; 1581#L696-14true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 279#L697-14true activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 964#L1529-42true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 607#L1529-44true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1066#L704-42true assume !(1 == ~t6_pc~0); 1349#L704-44true is_transmit6_triggered_~__retres1~6 := 0; 385#L715-14true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 211#L716-14true activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 856#L1537-42true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1151#L1537-44true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 462#L723-42true assume !(1 == ~t7_pc~0); 1140#L723-44true is_transmit7_triggered_~__retres1~7 := 0; 412#L734-14true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 331#L735-14true activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1751#L1545-42true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 417#L1545-44true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 416#L742-42true assume !(1 == ~t8_pc~0); 1004#L742-44true is_transmit8_triggered_~__retres1~8 := 0; 1707#L753-14true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1042#L754-14true activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 373#L1553-42true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1049#L1553-44true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 78#L761-42true assume !(1 == ~t9_pc~0); 90#L761-44true is_transmit9_triggered_~__retres1~9 := 0; 998#L772-14true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 353#L773-14true activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 163#L1561-42true assume !(0 != activate_threads_~tmp___8~0); 1668#L1561-44true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1506#L780-42true assume 1 == ~t10_pc~0; 1238#L781-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 276#L791-14true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1247#L792-14true activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1571#L1569-42true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 280#L1569-44true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 927#L799-42true assume !(1 == ~t11_pc~0); 9#L799-44true is_transmit11_triggered_~__retres1~11 := 0; 1192#L810-14true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 160#L811-14true activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1647#L1577-42true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1600#L1577-44true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 52#L818-42true assume 1 == ~t12_pc~0; 136#L819-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 326#L829-14true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1692#L830-14true activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 138#L1585-42true assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1150#L1585-44true assume 1 == ~M_E~0;~M_E~0 := 2; 813#L1336-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1359#L1341-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 358#L1346-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 348#L1351-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 306#L1356-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 682#L1361-3true assume !(1 == ~T6_E~0); 708#L1366-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 25#L1371-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1157#L1376-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1385#L1381-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 974#L1386-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1491#L1391-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1194#L1396-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1719#L1401-3true assume !(1 == ~E_1~0); 179#L1406-3true assume 1 == ~E_2~0;~E_2~0 := 2; 125#L1411-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1560#L1416-3true assume 1 == ~E_4~0;~E_4~0 := 2; 436#L1421-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1005#L1426-3true assume 1 == ~E_6~0;~E_6~0 := 2; 207#L1431-3true assume 1 == ~E_7~0;~E_7~0 := 2; 269#L1436-3true assume 1 == ~E_8~0;~E_8~0 := 2; 18#L1441-3true assume !(1 == ~E_9~0); 1092#L1446-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1080#L1451-3true assume 1 == ~E_11~0;~E_11~0 := 2; 499#L1456-3true assume 1 == ~E_12~0;~E_12~0 := 2; 281#L1461-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 939#L918-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1343#L985-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1211#L986-1true start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 1596#L1826true assume !(0 == start_simulation_~tmp~3); 1073#L1826-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1370#L918-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 206#L985-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 889#L986-2true stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 1251#L1781true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 172#L1788true stop_simulation_#res := stop_simulation_~__retres2~0; 1256#L1789true start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1655#L1839true assume !(0 != start_simulation_~tmp___0~1); 1761#L1807-1true [2021-11-02 23:17:02,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:02,341 INFO L85 PathProgramCache]: Analyzing trace with hash 372785729, now seen corresponding path program 1 times [2021-11-02 23:17:02,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:02,374 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29052377] [2021-11-02 23:17:02,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:02,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:02,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:02,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:02,716 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:02,716 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29052377] [2021-11-02 23:17:02,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29052377] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:02,717 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:02,717 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:02,719 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461069288] [2021-11-02 23:17:02,725 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:02,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:02,726 INFO L85 PathProgramCache]: Analyzing trace with hash 113025386, now seen corresponding path program 1 times [2021-11-02 23:17:02,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:02,727 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332172320] [2021-11-02 23:17:02,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:02,728 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:02,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:02,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:02,821 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:02,822 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332172320] [2021-11-02 23:17:02,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332172320] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:02,823 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:02,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:02,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665849648] [2021-11-02 23:17:02,827 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:02,836 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:02,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:02,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:02,858 INFO L87 Difference]: Start difference. First operand has 1763 states, 1762 states have (on average 1.5096481271282634) internal successors, (2660), 1762 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:02,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:02,963 INFO L93 Difference]: Finished difference Result 1763 states and 2627 transitions. [2021-11-02 23:17:02,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:02,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1763 states and 2627 transitions. [2021-11-02 23:17:02,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1763 states to 1757 states and 2621 transitions. [2021-11-02 23:17:03,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:03,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:03,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2621 transitions. [2021-11-02 23:17:03,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:03,024 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2621 transitions. [2021-11-02 23:17:03,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2621 transitions. [2021-11-02 23:17:03,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:03,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.491747296528173) internal successors, (2621), 1756 states have internal predecessors, (2621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:03,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2621 transitions. [2021-11-02 23:17:03,134 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2621 transitions. [2021-11-02 23:17:03,135 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2621 transitions. [2021-11-02 23:17:03,135 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-02 23:17:03,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2621 transitions. [2021-11-02 23:17:03,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:03,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:03,152 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,152 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,153 INFO L791 eck$LassoCheckResult]: Stem: 4350#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4351#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5222#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5223#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 5174#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5048#L850-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5049#L855-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3713#L860-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3714#L865-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4842#L870-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4843#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4999#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4366#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4297#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3931#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3932#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4068#L905-1 assume !(0 == ~M_E~0); 4069#L1198-1 assume !(0 == ~T1_E~0); 4612#L1203-1 assume !(0 == ~T2_E~0); 4613#L1208-1 assume !(0 == ~T3_E~0); 5143#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5236#L1218-1 assume !(0 == ~T5_E~0); 3573#L1223-1 assume !(0 == ~T6_E~0); 3574#L1228-1 assume !(0 == ~T7_E~0); 5123#L1233-1 assume !(0 == ~T8_E~0); 4916#L1238-1 assume !(0 == ~T9_E~0); 4917#L1243-1 assume !(0 == ~T10_E~0); 5214#L1248-1 assume !(0 == ~T11_E~0); 5221#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4668#L1258-1 assume !(0 == ~E_M~0); 4407#L1263-1 assume !(0 == ~E_1~0); 4408#L1268-1 assume !(0 == ~E_2~0); 4708#L1273-1 assume !(0 == ~E_3~0); 5181#L1278-1 assume !(0 == ~E_4~0); 5086#L1283-1 assume !(0 == ~E_5~0); 5087#L1288-1 assume !(0 == ~E_6~0); 5249#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 5242#L1298-1 assume !(0 == ~E_8~0); 5185#L1303-1 assume !(0 == ~E_9~0); 3937#L1308-1 assume !(0 == ~E_10~0); 3867#L1313-1 assume !(0 == ~E_11~0); 3868#L1318-1 assume !(0 == ~E_12~0); 3871#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3872#L590 assume 1 == ~m_pc~0; 4970#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4153#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4379#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4244#L1489 assume !(0 != activate_threads_~tmp~1); 4245#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4954#L609 assume !(1 == ~t1_pc~0); 4941#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 4744#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3622#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3623#L1497 assume !(0 != activate_threads_~tmp___0~0); 5240#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5288#L628 assume 1 == ~t2_pc~0; 4037#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4038#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4715#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4716#L1505 assume !(0 != activate_threads_~tmp___1~0); 4735#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4534#L647 assume !(1 == ~t3_pc~0); 3977#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 3976#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4226#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4227#L1513 assume !(0 != activate_threads_~tmp___2~0); 4766#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4767#L666 assume 1 == ~t4_pc~0; 3843#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3844#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3986#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5241#L1521 assume !(0 != activate_threads_~tmp___3~0); 5270#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5271#L685 assume 1 == ~t5_pc~0; 4880#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4881#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4582#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3978#L1529 assume !(0 != activate_threads_~tmp___4~0); 3979#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4257#L704 assume !(1 == ~t6_pc~0); 4258#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 4697#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4698#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 5069#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4336#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4337#L723 assume 1 == ~t7_pc~0; 4682#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4860#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5004#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5207#L1545 assume !(0 != activate_threads_~tmp___6~0); 4796#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4023#L742 assume !(1 == ~t8_pc~0); 4024#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 4179#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4180#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 4818#L1553 assume !(0 != activate_threads_~tmp___7~0); 5000#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4108#L761 assume 1 == ~t9_pc~0; 4109#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 3984#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3985#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 5088#L1561 assume !(0 != activate_threads_~tmp___8~0); 4229#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 3791#L780 assume !(1 == ~t10_pc~0); 3792#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 4008#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4009#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4826#L1569 assume !(0 != activate_threads_~tmp___9~0); 4928#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5162#L799 assume 1 == ~t11_pc~0; 4833#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 3794#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3795#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4760#L1577 assume !(0 != activate_threads_~tmp___10~0); 3940#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 3941#L818 assume !(1 == ~t12_pc~0); 3579#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 3580#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4824#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 5269#L1585 assume !(0 != activate_threads_~tmp___11~0); 5291#L1585-2 assume !(1 == ~M_E~0); 3535#L1336-1 assume !(1 == ~T1_E~0); 3536#L1341-1 assume !(1 == ~T2_E~0); 3599#L1346-1 assume !(1 == ~T3_E~0); 3600#L1351-1 assume !(1 == ~T4_E~0); 3904#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3905#L1361-1 assume !(1 == ~T6_E~0); 5247#L1366-1 assume !(1 == ~T7_E~0); 3948#L1371-1 assume !(1 == ~T8_E~0); 3949#L1376-1 assume !(1 == ~T9_E~0); 4712#L1381-1 assume !(1 == ~T10_E~0); 4713#L1386-1 assume !(1 == ~T11_E~0); 5268#L1391-1 assume !(1 == ~T12_E~0); 5280#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 4608#L1401-1 assume !(1 == ~E_1~0); 4609#L1406-1 assume !(1 == ~E_2~0); 4855#L1411-1 assume !(1 == ~E_3~0); 4856#L1416-1 assume !(1 == ~E_4~0); 4554#L1421-1 assume !(1 == ~E_5~0); 4078#L1426-1 assume !(1 == ~E_6~0); 4079#L1431-1 assume !(1 == ~E_7~0); 3652#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 3653#L1441-1 assume !(1 == ~E_9~0); 4400#L1446-1 assume !(1 == ~E_10~0); 4401#L1451-1 assume !(1 == ~E_11~0); 5052#L1456-1 assume !(1 == ~E_12~0); 5053#L1807-1 [2021-11-02 23:17:03,154 INFO L793 eck$LassoCheckResult]: Loop: 5053#L1807-1 assume !false; 4559#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 4560#L1173 assume !false; 5109#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 5110#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 3538#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 4717#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5204#L1000 assume !(0 != eval_~tmp~0); 5075#L1188 start_simulation_~kernel_st~0 := 2; 3995#L838-1 start_simulation_~kernel_st~0 := 3; 3996#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4538#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4926#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3848#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3849#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4342#L1218-3 assume !(0 == ~T5_E~0); 3819#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3820#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5096#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4799#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4800#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4628#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4629#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4890#L1258-3 assume !(0 == ~E_M~0); 3812#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3813#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5256#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5260#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5261#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4015#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4016#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5093#L1298-3 assume !(0 == ~E_8~0); 5094#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5197#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5092#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4630#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 3814#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3815#L590-42 assume 1 == ~m_pc~0; 5257#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5184#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4641#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4642#L1489-42 assume !(0 != activate_threads_~tmp~1); 4822#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4927#L609-42 assume !(1 == ~t1_pc~0); 3810#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 3811#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4452#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4453#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5243#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4733#L628-42 assume 1 == ~t2_pc~0; 4725#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4432#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4433#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5205#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4080#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4081#L647-42 assume 1 == ~t3_pc~0; 4829#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4830#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4018#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4019#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5007#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4207#L666-42 assume 1 == ~t4_pc~0; 4131#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4133#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4212#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4213#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5149#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5047#L685-42 assume 1 == ~t5_pc~0; 3725#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3726#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4082#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4083#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4599#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4600#L704-42 assume !(1 == ~t6_pc~0); 5062#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 4267#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3960#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3961#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4879#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4397#L723-42 assume 1 == ~t7_pc~0; 4398#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4313#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4184#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4185#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4323#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4320#L742-42 assume 1 == ~t8_pc~0; 4321#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5016#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5043#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 4247#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4248#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3700#L761-42 assume !(1 == ~t9_pc~0); 3701#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 3724#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4217#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 3875#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 3876#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5258#L780-42 assume 1 == ~t10_pc~0; 5159#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 4076#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4077#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 5163#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 4084#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4085#L799-42 assume 1 == ~t11_pc~0; 4561#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 3551#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3869#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 3870#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5282#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 3645#L818-42 assume 1 == ~t12_pc~0; 3646#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 3821#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4174#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 3825#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 3826#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 4837#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4838#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4225#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4209#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4139#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4140#L1361-3 assume !(1 == ~T6_E~0); 4693#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3585#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3586#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5117#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4994#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4995#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5134#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5135#L1401-3 assume !(1 == ~E_1~0); 3901#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3799#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3800#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4356#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4357#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3952#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3953#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3571#L1441-3 assume !(1 == ~E_9~0); 3572#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5074#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4456#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4086#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 4087#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 4091#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 5146#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 5147#L1826 assume !(0 == start_simulation_~tmp~3); 5067#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 5068#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 3950#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 3951#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 4914#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3885#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 3886#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 5166#L1839 assume !(0 != start_simulation_~tmp___0~1); 5053#L1807-1 [2021-11-02 23:17:03,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:03,156 INFO L85 PathProgramCache]: Analyzing trace with hash -53768769, now seen corresponding path program 1 times [2021-11-02 23:17:03,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:03,156 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946044746] [2021-11-02 23:17:03,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:03,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:03,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:03,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:03,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:03,287 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946044746] [2021-11-02 23:17:03,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946044746] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:03,288 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:03,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:03,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305879873] [2021-11-02 23:17:03,289 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:03,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:03,289 INFO L85 PathProgramCache]: Analyzing trace with hash 582081517, now seen corresponding path program 1 times [2021-11-02 23:17:03,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:03,290 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995803698] [2021-11-02 23:17:03,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:03,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:03,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:03,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:03,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:03,420 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995803698] [2021-11-02 23:17:03,421 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995803698] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:03,421 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:03,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:03,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775660858] [2021-11-02 23:17:03,422 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:03,422 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:03,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:03,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:03,424 INFO L87 Difference]: Start difference. First operand 1757 states and 2621 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:03,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:03,512 INFO L93 Difference]: Finished difference Result 1757 states and 2620 transitions. [2021-11-02 23:17:03,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:03,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2620 transitions. [2021-11-02 23:17:03,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2620 transitions. [2021-11-02 23:17:03,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:03,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:03,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2620 transitions. [2021-11-02 23:17:03,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:03,551 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2620 transitions. [2021-11-02 23:17:03,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2620 transitions. [2021-11-02 23:17:03,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:03,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4911781445645989) internal successors, (2620), 1756 states have internal predecessors, (2620), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:03,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2620 transitions. [2021-11-02 23:17:03,596 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2620 transitions. [2021-11-02 23:17:03,596 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2620 transitions. [2021-11-02 23:17:03,596 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-02 23:17:03,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2620 transitions. [2021-11-02 23:17:03,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:03,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:03,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,611 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,613 INFO L791 eck$LassoCheckResult]: Stem: 7871#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7872#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8743#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8744#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 8695#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8569#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8570#L855-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7234#L860-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7235#L865-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8363#L870-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8364#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8520#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7887#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7818#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7452#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7453#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7589#L905-1 assume !(0 == ~M_E~0); 7590#L1198-1 assume !(0 == ~T1_E~0); 8133#L1203-1 assume !(0 == ~T2_E~0); 8134#L1208-1 assume !(0 == ~T3_E~0); 8664#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8757#L1218-1 assume !(0 == ~T5_E~0); 7094#L1223-1 assume !(0 == ~T6_E~0); 7095#L1228-1 assume !(0 == ~T7_E~0); 8644#L1233-1 assume !(0 == ~T8_E~0); 8437#L1238-1 assume !(0 == ~T9_E~0); 8438#L1243-1 assume !(0 == ~T10_E~0); 8735#L1248-1 assume !(0 == ~T11_E~0); 8742#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8189#L1258-1 assume !(0 == ~E_M~0); 7928#L1263-1 assume !(0 == ~E_1~0); 7929#L1268-1 assume !(0 == ~E_2~0); 8229#L1273-1 assume !(0 == ~E_3~0); 8702#L1278-1 assume !(0 == ~E_4~0); 8607#L1283-1 assume !(0 == ~E_5~0); 8608#L1288-1 assume !(0 == ~E_6~0); 8770#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 8763#L1298-1 assume !(0 == ~E_8~0); 8706#L1303-1 assume !(0 == ~E_9~0); 7458#L1308-1 assume !(0 == ~E_10~0); 7388#L1313-1 assume !(0 == ~E_11~0); 7389#L1318-1 assume !(0 == ~E_12~0); 7392#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7393#L590 assume 1 == ~m_pc~0; 8491#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7674#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7900#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7765#L1489 assume !(0 != activate_threads_~tmp~1); 7766#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8475#L609 assume !(1 == ~t1_pc~0); 8462#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 8265#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7143#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7144#L1497 assume !(0 != activate_threads_~tmp___0~0); 8761#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8809#L628 assume 1 == ~t2_pc~0; 7558#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7559#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8236#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8237#L1505 assume !(0 != activate_threads_~tmp___1~0); 8256#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8055#L647 assume !(1 == ~t3_pc~0); 7498#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 7497#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7747#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7748#L1513 assume !(0 != activate_threads_~tmp___2~0); 8287#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8288#L666 assume 1 == ~t4_pc~0; 7364#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7365#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7507#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8762#L1521 assume !(0 != activate_threads_~tmp___3~0); 8791#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8792#L685 assume 1 == ~t5_pc~0; 8401#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8402#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8103#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7499#L1529 assume !(0 != activate_threads_~tmp___4~0); 7500#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7778#L704 assume !(1 == ~t6_pc~0); 7779#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 8218#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8219#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8590#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7857#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7858#L723 assume 1 == ~t7_pc~0; 8203#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8381#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8525#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8728#L1545 assume !(0 != activate_threads_~tmp___6~0); 8317#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7544#L742 assume !(1 == ~t8_pc~0); 7545#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 7700#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7701#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8339#L1553 assume !(0 != activate_threads_~tmp___7~0); 8521#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7629#L761 assume 1 == ~t9_pc~0; 7630#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 7505#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7506#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 8609#L1561 assume !(0 != activate_threads_~tmp___8~0); 7750#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 7312#L780 assume !(1 == ~t10_pc~0); 7313#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 7529#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 7530#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8347#L1569 assume !(0 != activate_threads_~tmp___9~0); 8449#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8683#L799 assume 1 == ~t11_pc~0; 8354#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 7315#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 7316#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 8281#L1577 assume !(0 != activate_threads_~tmp___10~0); 7461#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 7462#L818 assume !(1 == ~t12_pc~0); 7100#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 7101#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8345#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 8790#L1585 assume !(0 != activate_threads_~tmp___11~0); 8812#L1585-2 assume !(1 == ~M_E~0); 7056#L1336-1 assume !(1 == ~T1_E~0); 7057#L1341-1 assume !(1 == ~T2_E~0); 7120#L1346-1 assume !(1 == ~T3_E~0); 7121#L1351-1 assume !(1 == ~T4_E~0); 7425#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7426#L1361-1 assume !(1 == ~T6_E~0); 8768#L1366-1 assume !(1 == ~T7_E~0); 7469#L1371-1 assume !(1 == ~T8_E~0); 7470#L1376-1 assume !(1 == ~T9_E~0); 8233#L1381-1 assume !(1 == ~T10_E~0); 8234#L1386-1 assume !(1 == ~T11_E~0); 8789#L1391-1 assume !(1 == ~T12_E~0); 8801#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 8129#L1401-1 assume !(1 == ~E_1~0); 8130#L1406-1 assume !(1 == ~E_2~0); 8376#L1411-1 assume !(1 == ~E_3~0); 8377#L1416-1 assume !(1 == ~E_4~0); 8075#L1421-1 assume !(1 == ~E_5~0); 7599#L1426-1 assume !(1 == ~E_6~0); 7600#L1431-1 assume !(1 == ~E_7~0); 7173#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 7174#L1441-1 assume !(1 == ~E_9~0); 7921#L1446-1 assume !(1 == ~E_10~0); 7922#L1451-1 assume !(1 == ~E_11~0); 8573#L1456-1 assume !(1 == ~E_12~0); 8574#L1807-1 [2021-11-02 23:17:03,614 INFO L793 eck$LassoCheckResult]: Loop: 8574#L1807-1 assume !false; 8080#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 8081#L1173 assume !false; 8630#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 8631#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 7059#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 8238#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 8725#L1000 assume !(0 != eval_~tmp~0); 8596#L1188 start_simulation_~kernel_st~0 := 2; 7516#L838-1 start_simulation_~kernel_st~0 := 3; 7517#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8059#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8447#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7369#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7370#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7863#L1218-3 assume !(0 == ~T5_E~0); 7340#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7341#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8617#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8320#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8321#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8149#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8150#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8411#L1258-3 assume !(0 == ~E_M~0); 7333#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7334#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8777#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8781#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8782#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7536#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7537#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8614#L1298-3 assume !(0 == ~E_8~0); 8615#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8718#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8613#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8151#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7335#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7336#L590-42 assume !(1 == ~m_pc~0); 8704#L590-44 is_master_triggered_~__retres1~0 := 0; 8705#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8162#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8163#L1489-42 assume !(0 != activate_threads_~tmp~1); 8343#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8448#L609-42 assume !(1 == ~t1_pc~0); 7331#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 7332#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7973#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7974#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8764#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8254#L628-42 assume 1 == ~t2_pc~0; 8246#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7953#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7954#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8726#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7601#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7602#L647-42 assume !(1 == ~t3_pc~0); 8352#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 8351#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7539#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7540#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8528#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7728#L666-42 assume 1 == ~t4_pc~0; 7652#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7654#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7733#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7734#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8670#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8568#L685-42 assume !(1 == ~t5_pc~0); 7248#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 7247#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7603#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7604#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8120#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8121#L704-42 assume !(1 == ~t6_pc~0); 8583#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 7788#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7481#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 7482#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8400#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7918#L723-42 assume !(1 == ~t7_pc~0); 7920#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 7834#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7705#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 7706#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7844#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7841#L742-42 assume 1 == ~t8_pc~0; 7842#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8537#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8564#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 7768#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 7769#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7221#L761-42 assume !(1 == ~t9_pc~0); 7222#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 7245#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7738#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 7396#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 7397#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8779#L780-42 assume 1 == ~t10_pc~0; 8680#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 7597#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 7598#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8684#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 7605#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 7606#L799-42 assume 1 == ~t11_pc~0; 8082#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 7072#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 7390#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 7391#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 8803#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 7166#L818-42 assume !(1 == ~t12_pc~0); 7168#L818-44 is_transmit12_triggered_~__retres1~12 := 0; 7342#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 7695#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 7346#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 7347#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 8358#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8359#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7746#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7730#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7660#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7661#L1361-3 assume !(1 == ~T6_E~0); 8214#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7106#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7107#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8638#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8515#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8516#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8655#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8656#L1401-3 assume !(1 == ~E_1~0); 7422#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7320#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7321#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7877#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7878#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7473#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7474#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7092#L1441-3 assume !(1 == ~E_9~0); 7093#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8595#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7977#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7607#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 7608#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 7612#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 8667#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 8668#L1826 assume !(0 == start_simulation_~tmp~3); 8588#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 8589#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 7471#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 7472#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 8435#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7406#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 7407#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 8687#L1839 assume !(0 != start_simulation_~tmp___0~1); 8574#L1807-1 [2021-11-02 23:17:03,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:03,615 INFO L85 PathProgramCache]: Analyzing trace with hash 102211773, now seen corresponding path program 1 times [2021-11-02 23:17:03,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:03,615 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124882708] [2021-11-02 23:17:03,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:03,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:03,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:03,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:03,705 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:03,705 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124882708] [2021-11-02 23:17:03,706 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124882708] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:03,706 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:03,706 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:03,706 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153579683] [2021-11-02 23:17:03,707 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:03,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:03,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1793084600, now seen corresponding path program 1 times [2021-11-02 23:17:03,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:03,711 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953269392] [2021-11-02 23:17:03,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:03,712 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:03,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:03,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:03,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:03,792 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953269392] [2021-11-02 23:17:03,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [953269392] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:03,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:03,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:03,793 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52614723] [2021-11-02 23:17:03,793 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:03,794 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:03,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:03,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:03,795 INFO L87 Difference]: Start difference. First operand 1757 states and 2620 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:03,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:03,831 INFO L93 Difference]: Finished difference Result 1757 states and 2619 transitions. [2021-11-02 23:17:03,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:03,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2619 transitions. [2021-11-02 23:17:03,846 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2619 transitions. [2021-11-02 23:17:03,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:03,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:03,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2619 transitions. [2021-11-02 23:17:03,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:03,866 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2619 transitions. [2021-11-02 23:17:03,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2619 transitions. [2021-11-02 23:17:03,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:03,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4906089926010244) internal successors, (2619), 1756 states have internal predecessors, (2619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:03,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2619 transitions. [2021-11-02 23:17:03,913 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2619 transitions. [2021-11-02 23:17:03,913 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2619 transitions. [2021-11-02 23:17:03,914 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-02 23:17:03,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2619 transitions. [2021-11-02 23:17:03,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:03,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:03,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:03,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:03,956 INFO L791 eck$LassoCheckResult]: Stem: 11392#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11393#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 12264#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12265#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 12216#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12090#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12091#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10755#L860-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10756#L865-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11884#L870-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11885#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12041#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11408#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11339#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10973#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10974#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11110#L905-1 assume !(0 == ~M_E~0); 11111#L1198-1 assume !(0 == ~T1_E~0); 11654#L1203-1 assume !(0 == ~T2_E~0); 11655#L1208-1 assume !(0 == ~T3_E~0); 12185#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12278#L1218-1 assume !(0 == ~T5_E~0); 10615#L1223-1 assume !(0 == ~T6_E~0); 10616#L1228-1 assume !(0 == ~T7_E~0); 12165#L1233-1 assume !(0 == ~T8_E~0); 11958#L1238-1 assume !(0 == ~T9_E~0); 11959#L1243-1 assume !(0 == ~T10_E~0); 12256#L1248-1 assume !(0 == ~T11_E~0); 12263#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11710#L1258-1 assume !(0 == ~E_M~0); 11449#L1263-1 assume !(0 == ~E_1~0); 11450#L1268-1 assume !(0 == ~E_2~0); 11750#L1273-1 assume !(0 == ~E_3~0); 12223#L1278-1 assume !(0 == ~E_4~0); 12128#L1283-1 assume !(0 == ~E_5~0); 12129#L1288-1 assume !(0 == ~E_6~0); 12291#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12284#L1298-1 assume !(0 == ~E_8~0); 12227#L1303-1 assume !(0 == ~E_9~0); 10979#L1308-1 assume !(0 == ~E_10~0); 10909#L1313-1 assume !(0 == ~E_11~0); 10910#L1318-1 assume !(0 == ~E_12~0); 10913#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10914#L590 assume 1 == ~m_pc~0; 12012#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11195#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11421#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 11286#L1489 assume !(0 != activate_threads_~tmp~1); 11287#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11996#L609 assume !(1 == ~t1_pc~0); 11983#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 11786#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10664#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10665#L1497 assume !(0 != activate_threads_~tmp___0~0); 12282#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12330#L628 assume 1 == ~t2_pc~0; 11079#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11080#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11757#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 11758#L1505 assume !(0 != activate_threads_~tmp___1~0); 11777#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11576#L647 assume !(1 == ~t3_pc~0); 11019#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 11018#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11268#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11269#L1513 assume !(0 != activate_threads_~tmp___2~0); 11808#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11809#L666 assume 1 == ~t4_pc~0; 10885#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10886#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11028#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12283#L1521 assume !(0 != activate_threads_~tmp___3~0); 12312#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12313#L685 assume 1 == ~t5_pc~0; 11922#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11923#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11624#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 11020#L1529 assume !(0 != activate_threads_~tmp___4~0); 11021#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11299#L704 assume !(1 == ~t6_pc~0); 11300#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 11739#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11740#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12111#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11378#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11379#L723 assume 1 == ~t7_pc~0; 11724#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11902#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12046#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12249#L1545 assume !(0 != activate_threads_~tmp___6~0); 11838#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11065#L742 assume !(1 == ~t8_pc~0); 11066#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 11221#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11222#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 11860#L1553 assume !(0 != activate_threads_~tmp___7~0); 12042#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 11150#L761 assume 1 == ~t9_pc~0; 11151#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 11026#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11027#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 12130#L1561 assume !(0 != activate_threads_~tmp___8~0); 11271#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 10833#L780 assume !(1 == ~t10_pc~0); 10834#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 11050#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 11051#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 11868#L1569 assume !(0 != activate_threads_~tmp___9~0); 11970#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12204#L799 assume 1 == ~t11_pc~0; 11875#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 10836#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 10837#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 11802#L1577 assume !(0 != activate_threads_~tmp___10~0); 10982#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 10983#L818 assume !(1 == ~t12_pc~0); 10621#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 10622#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 11866#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 12311#L1585 assume !(0 != activate_threads_~tmp___11~0); 12333#L1585-2 assume !(1 == ~M_E~0); 10577#L1336-1 assume !(1 == ~T1_E~0); 10578#L1341-1 assume !(1 == ~T2_E~0); 10641#L1346-1 assume !(1 == ~T3_E~0); 10642#L1351-1 assume !(1 == ~T4_E~0); 10946#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10947#L1361-1 assume !(1 == ~T6_E~0); 12289#L1366-1 assume !(1 == ~T7_E~0); 10990#L1371-1 assume !(1 == ~T8_E~0); 10991#L1376-1 assume !(1 == ~T9_E~0); 11754#L1381-1 assume !(1 == ~T10_E~0); 11755#L1386-1 assume !(1 == ~T11_E~0); 12310#L1391-1 assume !(1 == ~T12_E~0); 12322#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 11650#L1401-1 assume !(1 == ~E_1~0); 11651#L1406-1 assume !(1 == ~E_2~0); 11897#L1411-1 assume !(1 == ~E_3~0); 11898#L1416-1 assume !(1 == ~E_4~0); 11596#L1421-1 assume !(1 == ~E_5~0); 11120#L1426-1 assume !(1 == ~E_6~0); 11121#L1431-1 assume !(1 == ~E_7~0); 10694#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 10695#L1441-1 assume !(1 == ~E_9~0); 11442#L1446-1 assume !(1 == ~E_10~0); 11443#L1451-1 assume !(1 == ~E_11~0); 12094#L1456-1 assume !(1 == ~E_12~0); 12095#L1807-1 [2021-11-02 23:17:03,957 INFO L793 eck$LassoCheckResult]: Loop: 12095#L1807-1 assume !false; 11601#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 11602#L1173 assume !false; 12151#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 12152#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 10580#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 11759#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12246#L1000 assume !(0 != eval_~tmp~0); 12117#L1188 start_simulation_~kernel_st~0 := 2; 11037#L838-1 start_simulation_~kernel_st~0 := 3; 11038#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11580#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11968#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10890#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10891#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11384#L1218-3 assume !(0 == ~T5_E~0); 10861#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10862#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12138#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11841#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11842#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11670#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11671#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11932#L1258-3 assume !(0 == ~E_M~0); 10854#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10855#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12298#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12302#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12303#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11057#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11058#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12135#L1298-3 assume !(0 == ~E_8~0); 12136#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12239#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12134#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11672#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 10856#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10857#L590-42 assume !(1 == ~m_pc~0); 12225#L590-44 is_master_triggered_~__retres1~0 := 0; 12226#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11683#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 11684#L1489-42 assume !(0 != activate_threads_~tmp~1); 11864#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11969#L609-42 assume !(1 == ~t1_pc~0); 10852#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 10853#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11494#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11495#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12285#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11775#L628-42 assume 1 == ~t2_pc~0; 11767#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11474#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11475#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12247#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11122#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11123#L647-42 assume !(1 == ~t3_pc~0); 11873#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 11872#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11060#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11061#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12049#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11249#L666-42 assume 1 == ~t4_pc~0; 11173#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11175#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11254#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 11255#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12191#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12089#L685-42 assume !(1 == ~t5_pc~0); 10769#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 10768#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11124#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 11125#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11641#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11642#L704-42 assume !(1 == ~t6_pc~0); 12104#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 11309#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11002#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 11003#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11921#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11439#L723-42 assume 1 == ~t7_pc~0; 11440#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11355#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11226#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 11227#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11365#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11362#L742-42 assume 1 == ~t8_pc~0; 11363#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12058#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12085#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 11289#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11290#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 10742#L761-42 assume !(1 == ~t9_pc~0); 10743#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 10766#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11259#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 10917#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 10918#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12300#L780-42 assume !(1 == ~t10_pc~0); 11312#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 11118#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 11119#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 12205#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 11126#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 11127#L799-42 assume !(1 == ~t11_pc~0); 10592#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 10593#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 10911#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 10912#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 12324#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 10687#L818-42 assume 1 == ~t12_pc~0; 10688#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 10863#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 11216#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 10867#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 10868#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 11879#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11880#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11267#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11251#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11181#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11182#L1361-3 assume !(1 == ~T6_E~0); 11735#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10627#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10628#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12159#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12036#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12037#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12176#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12177#L1401-3 assume !(1 == ~E_1~0); 10943#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10841#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10842#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11398#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11399#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10994#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10995#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10613#L1441-3 assume !(1 == ~E_9~0); 10614#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12116#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11498#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11128#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 11129#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 11133#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 12188#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 12189#L1826 assume !(0 == start_simulation_~tmp~3); 12109#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 12110#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 10992#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 10993#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 11956#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10927#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 10928#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 12208#L1839 assume !(0 != start_simulation_~tmp___0~1); 12095#L1807-1 [2021-11-02 23:17:03,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:03,957 INFO L85 PathProgramCache]: Analyzing trace with hash -308398593, now seen corresponding path program 1 times [2021-11-02 23:17:03,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:03,958 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934439387] [2021-11-02 23:17:03,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:03,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:03,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,002 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934439387] [2021-11-02 23:17:04,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934439387] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,003 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831864481] [2021-11-02 23:17:04,004 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:04,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,004 INFO L85 PathProgramCache]: Analyzing trace with hash 387279304, now seen corresponding path program 1 times [2021-11-02 23:17:04,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,005 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339167324] [2021-11-02 23:17:04,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,059 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,060 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339167324] [2021-11-02 23:17:04,060 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339167324] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,060 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,060 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,061 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253950568] [2021-11-02 23:17:04,061 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:04,061 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:04,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:04,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:04,062 INFO L87 Difference]: Start difference. First operand 1757 states and 2619 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:04,104 INFO L93 Difference]: Finished difference Result 1757 states and 2618 transitions. [2021-11-02 23:17:04,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:04,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2618 transitions. [2021-11-02 23:17:04,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2618 transitions. [2021-11-02 23:17:04,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:04,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:04,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2618 transitions. [2021-11-02 23:17:04,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:04,144 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2618 transitions. [2021-11-02 23:17:04,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2618 transitions. [2021-11-02 23:17:04,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:04,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4900398406374502) internal successors, (2618), 1756 states have internal predecessors, (2618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2618 transitions. [2021-11-02 23:17:04,193 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2618 transitions. [2021-11-02 23:17:04,193 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2618 transitions. [2021-11-02 23:17:04,193 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-02 23:17:04,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2618 transitions. [2021-11-02 23:17:04,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:04,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:04,208 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,208 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,208 INFO L791 eck$LassoCheckResult]: Stem: 14913#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14914#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15785#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15786#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 15737#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15611#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15612#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14276#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14277#L865-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15405#L870-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15406#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15562#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14929#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14860#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14494#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14495#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14631#L905-1 assume !(0 == ~M_E~0); 14632#L1198-1 assume !(0 == ~T1_E~0); 15175#L1203-1 assume !(0 == ~T2_E~0); 15176#L1208-1 assume !(0 == ~T3_E~0); 15706#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15799#L1218-1 assume !(0 == ~T5_E~0); 14136#L1223-1 assume !(0 == ~T6_E~0); 14137#L1228-1 assume !(0 == ~T7_E~0); 15686#L1233-1 assume !(0 == ~T8_E~0); 15479#L1238-1 assume !(0 == ~T9_E~0); 15480#L1243-1 assume !(0 == ~T10_E~0); 15777#L1248-1 assume !(0 == ~T11_E~0); 15784#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15231#L1258-1 assume !(0 == ~E_M~0); 14970#L1263-1 assume !(0 == ~E_1~0); 14971#L1268-1 assume !(0 == ~E_2~0); 15271#L1273-1 assume !(0 == ~E_3~0); 15744#L1278-1 assume !(0 == ~E_4~0); 15649#L1283-1 assume !(0 == ~E_5~0); 15650#L1288-1 assume !(0 == ~E_6~0); 15812#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15805#L1298-1 assume !(0 == ~E_8~0); 15748#L1303-1 assume !(0 == ~E_9~0); 14500#L1308-1 assume !(0 == ~E_10~0); 14430#L1313-1 assume !(0 == ~E_11~0); 14431#L1318-1 assume !(0 == ~E_12~0); 14434#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14435#L590 assume 1 == ~m_pc~0; 15533#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14716#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14942#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14807#L1489 assume !(0 != activate_threads_~tmp~1); 14808#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15517#L609 assume !(1 == ~t1_pc~0); 15504#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 15307#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14185#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14186#L1497 assume !(0 != activate_threads_~tmp___0~0); 15803#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15851#L628 assume 1 == ~t2_pc~0; 14600#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14601#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15278#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 15279#L1505 assume !(0 != activate_threads_~tmp___1~0); 15298#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15097#L647 assume !(1 == ~t3_pc~0); 14540#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 14539#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14789#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14790#L1513 assume !(0 != activate_threads_~tmp___2~0); 15329#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15330#L666 assume 1 == ~t4_pc~0; 14406#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14407#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14549#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 15804#L1521 assume !(0 != activate_threads_~tmp___3~0); 15833#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15834#L685 assume 1 == ~t5_pc~0; 15443#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15444#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15145#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 14541#L1529 assume !(0 != activate_threads_~tmp___4~0); 14542#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14820#L704 assume !(1 == ~t6_pc~0); 14821#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 15260#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15261#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 15632#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14899#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14900#L723 assume 1 == ~t7_pc~0; 15245#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15423#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15567#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 15770#L1545 assume !(0 != activate_threads_~tmp___6~0); 15359#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14586#L742 assume !(1 == ~t8_pc~0); 14587#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 14742#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14743#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 15381#L1553 assume !(0 != activate_threads_~tmp___7~0); 15563#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 14671#L761 assume 1 == ~t9_pc~0; 14672#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 14547#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 14548#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 15651#L1561 assume !(0 != activate_threads_~tmp___8~0); 14792#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 14354#L780 assume !(1 == ~t10_pc~0); 14355#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 14571#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 14572#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 15389#L1569 assume !(0 != activate_threads_~tmp___9~0); 15491#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 15725#L799 assume 1 == ~t11_pc~0; 15396#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 14357#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 14358#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 15323#L1577 assume !(0 != activate_threads_~tmp___10~0); 14503#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 14504#L818 assume !(1 == ~t12_pc~0); 14142#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 14143#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 15387#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 15832#L1585 assume !(0 != activate_threads_~tmp___11~0); 15854#L1585-2 assume !(1 == ~M_E~0); 14098#L1336-1 assume !(1 == ~T1_E~0); 14099#L1341-1 assume !(1 == ~T2_E~0); 14162#L1346-1 assume !(1 == ~T3_E~0); 14163#L1351-1 assume !(1 == ~T4_E~0); 14467#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14468#L1361-1 assume !(1 == ~T6_E~0); 15810#L1366-1 assume !(1 == ~T7_E~0); 14511#L1371-1 assume !(1 == ~T8_E~0); 14512#L1376-1 assume !(1 == ~T9_E~0); 15275#L1381-1 assume !(1 == ~T10_E~0); 15276#L1386-1 assume !(1 == ~T11_E~0); 15831#L1391-1 assume !(1 == ~T12_E~0); 15843#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 15171#L1401-1 assume !(1 == ~E_1~0); 15172#L1406-1 assume !(1 == ~E_2~0); 15418#L1411-1 assume !(1 == ~E_3~0); 15419#L1416-1 assume !(1 == ~E_4~0); 15117#L1421-1 assume !(1 == ~E_5~0); 14641#L1426-1 assume !(1 == ~E_6~0); 14642#L1431-1 assume !(1 == ~E_7~0); 14215#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 14216#L1441-1 assume !(1 == ~E_9~0); 14963#L1446-1 assume !(1 == ~E_10~0); 14964#L1451-1 assume !(1 == ~E_11~0); 15615#L1456-1 assume !(1 == ~E_12~0); 15616#L1807-1 [2021-11-02 23:17:04,209 INFO L793 eck$LassoCheckResult]: Loop: 15616#L1807-1 assume !false; 15122#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 15123#L1173 assume !false; 15672#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 15673#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 14101#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 15280#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 15767#L1000 assume !(0 != eval_~tmp~0); 15638#L1188 start_simulation_~kernel_st~0 := 2; 14558#L838-1 start_simulation_~kernel_st~0 := 3; 14559#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15101#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15489#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14411#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14412#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14905#L1218-3 assume !(0 == ~T5_E~0); 14382#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14383#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15659#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15362#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15363#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15191#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15192#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15453#L1258-3 assume !(0 == ~E_M~0); 14375#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14376#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15819#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15823#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15824#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14578#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14579#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15656#L1298-3 assume !(0 == ~E_8~0); 15657#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15760#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15655#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 15193#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14377#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14378#L590-42 assume !(1 == ~m_pc~0); 15746#L590-44 is_master_triggered_~__retres1~0 := 0; 15747#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15204#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15205#L1489-42 assume !(0 != activate_threads_~tmp~1); 15385#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15490#L609-42 assume !(1 == ~t1_pc~0); 14373#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 14374#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15015#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15016#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15806#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15296#L628-42 assume 1 == ~t2_pc~0; 15288#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14995#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14996#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 15768#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14643#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14644#L647-42 assume 1 == ~t3_pc~0; 15392#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15393#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14581#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14582#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15570#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14770#L666-42 assume 1 == ~t4_pc~0; 14694#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14696#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14775#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14776#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15712#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15610#L685-42 assume 1 == ~t5_pc~0; 14288#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14289#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14645#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 14646#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15162#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15163#L704-42 assume !(1 == ~t6_pc~0); 15625#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 14830#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14523#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 14524#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 15442#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14960#L723-42 assume 1 == ~t7_pc~0; 14961#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14876#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14747#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 14748#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14886#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14883#L742-42 assume 1 == ~t8_pc~0; 14884#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15579#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15606#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 14810#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 14811#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 14263#L761-42 assume !(1 == ~t9_pc~0); 14264#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 14287#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 14780#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 14438#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 14439#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 15821#L780-42 assume !(1 == ~t10_pc~0); 14833#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 14639#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 14640#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 15726#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 14647#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 14648#L799-42 assume !(1 == ~t11_pc~0); 14113#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 14114#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 14432#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 14433#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 15845#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 14208#L818-42 assume 1 == ~t12_pc~0; 14209#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 14384#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 14737#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 14388#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 14389#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 15400#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15401#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14788#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14772#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14702#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14703#L1361-3 assume !(1 == ~T6_E~0); 15256#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14148#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14149#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15680#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15557#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15558#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15697#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15698#L1401-3 assume !(1 == ~E_1~0); 14464#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14362#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14363#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14919#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14920#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14515#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14516#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14134#L1441-3 assume !(1 == ~E_9~0); 14135#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15637#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15019#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14649#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 14650#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 14654#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 15709#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 15710#L1826 assume !(0 == start_simulation_~tmp~3); 15630#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 15631#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 14513#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 14514#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 15477#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14448#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 14449#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 15729#L1839 assume !(0 != start_simulation_~tmp___0~1); 15616#L1807-1 [2021-11-02 23:17:04,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1479471229, now seen corresponding path program 1 times [2021-11-02 23:17:04,210 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,210 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882042156] [2021-11-02 23:17:04,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,211 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,253 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,253 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882042156] [2021-11-02 23:17:04,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882042156] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,254 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,254 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,254 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224283063] [2021-11-02 23:17:04,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:04,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1334557066, now seen corresponding path program 1 times [2021-11-02 23:17:04,255 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,256 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112063375] [2021-11-02 23:17:04,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,256 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,311 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112063375] [2021-11-02 23:17:04,311 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112063375] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,311 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342371346] [2021-11-02 23:17:04,312 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:04,313 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:04,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:04,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:04,314 INFO L87 Difference]: Start difference. First operand 1757 states and 2618 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:04,357 INFO L93 Difference]: Finished difference Result 1757 states and 2617 transitions. [2021-11-02 23:17:04,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:04,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2617 transitions. [2021-11-02 23:17:04,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2617 transitions. [2021-11-02 23:17:04,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:04,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:04,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2617 transitions. [2021-11-02 23:17:04,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:04,399 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2617 transitions. [2021-11-02 23:17:04,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2617 transitions. [2021-11-02 23:17:04,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:04,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.489470688673876) internal successors, (2617), 1756 states have internal predecessors, (2617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2617 transitions. [2021-11-02 23:17:04,447 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2617 transitions. [2021-11-02 23:17:04,447 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2617 transitions. [2021-11-02 23:17:04,447 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-02 23:17:04,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2617 transitions. [2021-11-02 23:17:04,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:04,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:04,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,460 INFO L791 eck$LassoCheckResult]: Stem: 18436#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18437#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19306#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19307#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 19258#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19132#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19133#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17797#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17798#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18928#L870-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18929#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19083#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18450#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18381#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18015#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18016#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18152#L905-1 assume !(0 == ~M_E~0); 18153#L1198-1 assume !(0 == ~T1_E~0); 18696#L1203-1 assume !(0 == ~T2_E~0); 18697#L1208-1 assume !(0 == ~T3_E~0); 19228#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19320#L1218-1 assume !(0 == ~T5_E~0); 17657#L1223-1 assume !(0 == ~T6_E~0); 17658#L1228-1 assume !(0 == ~T7_E~0); 19207#L1233-1 assume !(0 == ~T8_E~0); 19000#L1238-1 assume !(0 == ~T9_E~0); 19001#L1243-1 assume !(0 == ~T10_E~0); 19298#L1248-1 assume !(0 == ~T11_E~0); 19305#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18753#L1258-1 assume !(0 == ~E_M~0); 18491#L1263-1 assume !(0 == ~E_1~0); 18492#L1268-1 assume !(0 == ~E_2~0); 18792#L1273-1 assume !(0 == ~E_3~0); 19265#L1278-1 assume !(0 == ~E_4~0); 19170#L1283-1 assume !(0 == ~E_5~0); 19171#L1288-1 assume !(0 == ~E_6~0); 19333#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 19326#L1298-1 assume !(0 == ~E_8~0); 19269#L1303-1 assume !(0 == ~E_9~0); 18021#L1308-1 assume !(0 == ~E_10~0); 17951#L1313-1 assume !(0 == ~E_11~0); 17952#L1318-1 assume !(0 == ~E_12~0); 17959#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17960#L590 assume 1 == ~m_pc~0; 19054#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 18237#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18469#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18328#L1489 assume !(0 != activate_threads_~tmp~1); 18329#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19038#L609 assume !(1 == ~t1_pc~0); 19025#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 18828#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17708#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 17709#L1497 assume !(0 != activate_threads_~tmp___0~0); 19324#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19372#L628 assume 1 == ~t2_pc~0; 18121#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 18122#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18799#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18800#L1505 assume !(0 != activate_threads_~tmp___1~0); 18819#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18618#L647 assume !(1 == ~t3_pc~0); 18061#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 18060#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18311#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18312#L1513 assume !(0 != activate_threads_~tmp___2~0); 18850#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18851#L666 assume 1 == ~t4_pc~0; 17927#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17928#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18070#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 19325#L1521 assume !(0 != activate_threads_~tmp___3~0); 19354#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19355#L685 assume 1 == ~t5_pc~0; 18965#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18966#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18666#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 18062#L1529 assume !(0 != activate_threads_~tmp___4~0); 18063#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18343#L704 assume !(1 == ~t6_pc~0); 18344#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 18781#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18782#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 19153#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 18420#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18421#L723 assume 1 == ~t7_pc~0; 18766#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18944#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19088#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 19291#L1545 assume !(0 != activate_threads_~tmp___6~0); 18880#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18110#L742 assume !(1 == ~t8_pc~0); 18111#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 18263#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18264#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 18902#L1553 assume !(0 != activate_threads_~tmp___7~0); 19084#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 18194#L761 assume 1 == ~t9_pc~0; 18195#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 18068#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18069#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 19172#L1561 assume !(0 != activate_threads_~tmp___8~0); 18313#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 17875#L780 assume !(1 == ~t10_pc~0); 17876#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 18093#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 18094#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 18912#L1569 assume !(0 != activate_threads_~tmp___9~0); 19012#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 19246#L799 assume 1 == ~t11_pc~0; 18919#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 17878#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 17879#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 18844#L1577 assume !(0 != activate_threads_~tmp___10~0); 18027#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 18028#L818 assume !(1 == ~t12_pc~0); 17665#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 17666#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 18909#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 19353#L1585 assume !(0 != activate_threads_~tmp___11~0); 19375#L1585-2 assume !(1 == ~M_E~0); 17619#L1336-1 assume !(1 == ~T1_E~0); 17620#L1341-1 assume !(1 == ~T2_E~0); 17683#L1346-1 assume !(1 == ~T3_E~0); 17684#L1351-1 assume !(1 == ~T4_E~0); 17988#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17989#L1361-1 assume !(1 == ~T6_E~0); 19331#L1366-1 assume !(1 == ~T7_E~0); 18034#L1371-1 assume !(1 == ~T8_E~0); 18035#L1376-1 assume !(1 == ~T9_E~0); 18796#L1381-1 assume !(1 == ~T10_E~0); 18797#L1386-1 assume !(1 == ~T11_E~0); 19352#L1391-1 assume !(1 == ~T12_E~0); 19364#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 18692#L1401-1 assume !(1 == ~E_1~0); 18693#L1406-1 assume !(1 == ~E_2~0); 18939#L1411-1 assume !(1 == ~E_3~0); 18940#L1416-1 assume !(1 == ~E_4~0); 18638#L1421-1 assume !(1 == ~E_5~0); 18164#L1426-1 assume !(1 == ~E_6~0); 18165#L1431-1 assume !(1 == ~E_7~0); 17736#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 17737#L1441-1 assume !(1 == ~E_9~0); 18485#L1446-1 assume !(1 == ~E_10~0); 18486#L1451-1 assume !(1 == ~E_11~0); 19136#L1456-1 assume !(1 == ~E_12~0); 19137#L1807-1 [2021-11-02 23:17:04,461 INFO L793 eck$LassoCheckResult]: Loop: 19137#L1807-1 assume !false; 18643#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 18644#L1173 assume !false; 19193#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 19194#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 17622#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 18801#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 19288#L1000 assume !(0 != eval_~tmp~0); 19159#L1188 start_simulation_~kernel_st~0 := 2; 18079#L838-1 start_simulation_~kernel_st~0 := 3; 18080#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18622#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19010#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17932#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17933#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18426#L1218-3 assume !(0 == ~T5_E~0); 17903#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17904#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19180#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18883#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18884#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18712#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18713#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18974#L1258-3 assume !(0 == ~E_M~0); 17898#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17899#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19340#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19344#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19345#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18100#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18101#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19177#L1298-3 assume !(0 == ~E_8~0); 19178#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19281#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19176#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18714#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17896#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17897#L590-42 assume !(1 == ~m_pc~0); 19267#L590-44 is_master_triggered_~__retres1~0 := 0; 19268#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18725#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18726#L1489-42 assume !(0 != activate_threads_~tmp~1); 18906#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19011#L609-42 assume !(1 == ~t1_pc~0); 17893#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 17894#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18536#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18537#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19327#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18817#L628-42 assume 1 == ~t2_pc~0; 18809#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 18516#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18517#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19289#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18162#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18163#L647-42 assume 1 == ~t3_pc~0; 18913#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18914#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18102#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18103#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19091#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18291#L666-42 assume 1 == ~t4_pc~0; 18215#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18217#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18296#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 18297#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19233#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19131#L685-42 assume 1 == ~t5_pc~0; 17809#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17810#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18166#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 18167#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 18683#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18684#L704-42 assume !(1 == ~t6_pc~0); 19145#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 18349#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18044#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 18045#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 18963#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18481#L723-42 assume 1 == ~t7_pc~0; 18482#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18397#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18268#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 18269#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18407#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18404#L742-42 assume 1 == ~t8_pc~0; 18405#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19100#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19127#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 18331#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18332#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17784#L761-42 assume !(1 == ~t9_pc~0); 17785#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 17808#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18301#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 17957#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 17958#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 19342#L780-42 assume !(1 == ~t10_pc~0); 18352#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 18160#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 18161#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 19247#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 18168#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 18169#L799-42 assume !(1 == ~t11_pc~0); 17634#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 17635#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 17953#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 17954#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 19366#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 17729#L818-42 assume 1 == ~t12_pc~0; 17730#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 17905#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 18258#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 17909#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 17910#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 18921#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18922#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18309#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18293#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18223#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18224#L1361-3 assume !(1 == ~T6_E~0); 18777#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17669#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17670#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19201#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19078#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19079#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19218#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19219#L1401-3 assume !(1 == ~E_1~0); 17985#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17883#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17884#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18440#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18441#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18036#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18037#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17652#L1441-3 assume !(1 == ~E_9~0); 17653#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19158#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18540#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 18170#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 18171#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 18175#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 19230#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 19231#L1826 assume !(0 == start_simulation_~tmp~3); 19151#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 19152#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 18032#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 18033#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 18998#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17969#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 17970#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 19250#L1839 assume !(0 != start_simulation_~tmp___0~1); 19137#L1807-1 [2021-11-02 23:17:04,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,462 INFO L85 PathProgramCache]: Analyzing trace with hash -679612865, now seen corresponding path program 1 times [2021-11-02 23:17:04,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,462 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955662162] [2021-11-02 23:17:04,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,463 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,520 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,521 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955662162] [2021-11-02 23:17:04,521 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955662162] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,521 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,521 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,522 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030414883] [2021-11-02 23:17:04,522 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:04,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,523 INFO L85 PathProgramCache]: Analyzing trace with hash 1334557066, now seen corresponding path program 2 times [2021-11-02 23:17:04,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,523 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992677636] [2021-11-02 23:17:04,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,581 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992677636] [2021-11-02 23:17:04,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992677636] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,581 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,582 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384488107] [2021-11-02 23:17:04,582 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:04,583 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:04,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:04,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:04,584 INFO L87 Difference]: Start difference. First operand 1757 states and 2617 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:04,628 INFO L93 Difference]: Finished difference Result 1757 states and 2616 transitions. [2021-11-02 23:17:04,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:04,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2616 transitions. [2021-11-02 23:17:04,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2616 transitions. [2021-11-02 23:17:04,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:04,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:04,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2616 transitions. [2021-11-02 23:17:04,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:04,672 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2616 transitions. [2021-11-02 23:17:04,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2616 transitions. [2021-11-02 23:17:04,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:04,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4889015367103016) internal successors, (2616), 1756 states have internal predecessors, (2616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2616 transitions. [2021-11-02 23:17:04,726 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2616 transitions. [2021-11-02 23:17:04,726 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2616 transitions. [2021-11-02 23:17:04,726 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-02 23:17:04,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2616 transitions. [2021-11-02 23:17:04,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:04,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:04,741 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,741 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:04,742 INFO L791 eck$LassoCheckResult]: Stem: 21955#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21956#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22827#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22828#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 22779#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22653#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22654#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21318#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21319#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22447#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22448#L875-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22604#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21971#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21902#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21536#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21537#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21673#L905-1 assume !(0 == ~M_E~0); 21674#L1198-1 assume !(0 == ~T1_E~0); 22217#L1203-1 assume !(0 == ~T2_E~0); 22218#L1208-1 assume !(0 == ~T3_E~0); 22749#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22841#L1218-1 assume !(0 == ~T5_E~0); 21178#L1223-1 assume !(0 == ~T6_E~0); 21179#L1228-1 assume !(0 == ~T7_E~0); 22728#L1233-1 assume !(0 == ~T8_E~0); 22521#L1238-1 assume !(0 == ~T9_E~0); 22522#L1243-1 assume !(0 == ~T10_E~0); 22819#L1248-1 assume !(0 == ~T11_E~0); 22826#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22274#L1258-1 assume !(0 == ~E_M~0); 22012#L1263-1 assume !(0 == ~E_1~0); 22013#L1268-1 assume !(0 == ~E_2~0); 22313#L1273-1 assume !(0 == ~E_3~0); 22786#L1278-1 assume !(0 == ~E_4~0); 22691#L1283-1 assume !(0 == ~E_5~0); 22692#L1288-1 assume !(0 == ~E_6~0); 22854#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 22847#L1298-1 assume !(0 == ~E_8~0); 22790#L1303-1 assume !(0 == ~E_9~0); 21542#L1308-1 assume !(0 == ~E_10~0); 21472#L1313-1 assume !(0 == ~E_11~0); 21473#L1318-1 assume !(0 == ~E_12~0); 21478#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21479#L590 assume 1 == ~m_pc~0; 22575#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 21758#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21986#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21849#L1489 assume !(0 != activate_threads_~tmp~1); 21850#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22559#L609 assume !(1 == ~t1_pc~0); 22546#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 22349#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21229#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21230#L1497 assume !(0 != activate_threads_~tmp___0~0); 22845#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22893#L628 assume 1 == ~t2_pc~0; 21642#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21643#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22320#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 22321#L1505 assume !(0 != activate_threads_~tmp___1~0); 22340#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22139#L647 assume !(1 == ~t3_pc~0); 21582#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 21581#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21832#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21833#L1513 assume !(0 != activate_threads_~tmp___2~0); 22371#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22372#L666 assume 1 == ~t4_pc~0; 21448#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 21449#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21591#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 22846#L1521 assume !(0 != activate_threads_~tmp___3~0); 22875#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22876#L685 assume 1 == ~t5_pc~0; 22485#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22486#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22187#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21583#L1529 assume !(0 != activate_threads_~tmp___4~0); 21584#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21864#L704 assume !(1 == ~t6_pc~0); 21865#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 22302#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22303#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 22674#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21941#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21942#L723 assume 1 == ~t7_pc~0; 22287#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 22465#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22609#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 22812#L1545 assume !(0 != activate_threads_~tmp___6~0); 22401#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21630#L742 assume !(1 == ~t8_pc~0); 21631#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 21784#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21785#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 22423#L1553 assume !(0 != activate_threads_~tmp___7~0); 22605#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21715#L761 assume 1 == ~t9_pc~0; 21716#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 21589#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21590#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 22693#L1561 assume !(0 != activate_threads_~tmp___8~0); 21834#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 21396#L780 assume !(1 == ~t10_pc~0); 21397#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 21613#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21614#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 22433#L1569 assume !(0 != activate_threads_~tmp___9~0); 22533#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 22767#L799 assume 1 == ~t11_pc~0; 22438#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 21399#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 21400#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 22365#L1577 assume !(0 != activate_threads_~tmp___10~0); 21545#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 21546#L818 assume !(1 == ~t12_pc~0); 21184#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 21185#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 22429#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 22874#L1585 assume !(0 != activate_threads_~tmp___11~0); 22896#L1585-2 assume !(1 == ~M_E~0); 21140#L1336-1 assume !(1 == ~T1_E~0); 21141#L1341-1 assume !(1 == ~T2_E~0); 21204#L1346-1 assume !(1 == ~T3_E~0); 21205#L1351-1 assume !(1 == ~T4_E~0); 21509#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21510#L1361-1 assume !(1 == ~T6_E~0); 22852#L1366-1 assume !(1 == ~T7_E~0); 21555#L1371-1 assume !(1 == ~T8_E~0); 21556#L1376-1 assume !(1 == ~T9_E~0); 22317#L1381-1 assume !(1 == ~T10_E~0); 22318#L1386-1 assume !(1 == ~T11_E~0); 22873#L1391-1 assume !(1 == ~T12_E~0); 22885#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 22213#L1401-1 assume !(1 == ~E_1~0); 22214#L1406-1 assume !(1 == ~E_2~0); 22460#L1411-1 assume !(1 == ~E_3~0); 22461#L1416-1 assume !(1 == ~E_4~0); 22159#L1421-1 assume !(1 == ~E_5~0); 21683#L1426-1 assume !(1 == ~E_6~0); 21684#L1431-1 assume !(1 == ~E_7~0); 21257#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 21258#L1441-1 assume !(1 == ~E_9~0); 22005#L1446-1 assume !(1 == ~E_10~0); 22006#L1451-1 assume !(1 == ~E_11~0); 22657#L1456-1 assume !(1 == ~E_12~0); 22658#L1807-1 [2021-11-02 23:17:04,743 INFO L793 eck$LassoCheckResult]: Loop: 22658#L1807-1 assume !false; 22164#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 22165#L1173 assume !false; 22714#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 22715#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 21143#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 22322#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 22809#L1000 assume !(0 != eval_~tmp~0); 22680#L1188 start_simulation_~kernel_st~0 := 2; 21600#L838-1 start_simulation_~kernel_st~0 := 3; 21601#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22143#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22531#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21453#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21454#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21947#L1218-3 assume !(0 == ~T5_E~0); 21424#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21425#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22701#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22404#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22405#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22233#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22234#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22495#L1258-3 assume !(0 == ~E_M~0); 21417#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21418#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22861#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22865#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22866#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21621#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21622#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22698#L1298-3 assume !(0 == ~E_8~0); 22699#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22802#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22697#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22237#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21419#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21420#L590-42 assume !(1 == ~m_pc~0); 22788#L590-44 is_master_triggered_~__retres1~0 := 0; 22789#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22246#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22247#L1489-42 assume !(0 != activate_threads_~tmp~1); 22427#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22532#L609-42 assume 1 == ~t1_pc~0; 21633#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21416#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22057#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 22058#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22848#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22338#L628-42 assume 1 == ~t2_pc~0; 22331#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22037#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22038#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 22810#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21685#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21686#L647-42 assume 1 == ~t3_pc~0; 22435#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22436#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21623#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21624#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22612#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21812#L666-42 assume 1 == ~t4_pc~0; 21739#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 21741#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21817#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21818#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22754#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22652#L685-42 assume 1 == ~t5_pc~0; 21330#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21331#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21687#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21688#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22204#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22205#L704-42 assume !(1 == ~t6_pc~0); 22666#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 21870#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21565#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 21566#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22481#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22000#L723-42 assume 1 == ~t7_pc~0; 22001#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21918#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21789#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 21790#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21928#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21924#L742-42 assume 1 == ~t8_pc~0; 21925#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 22621#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 22648#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 21852#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21853#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21305#L761-42 assume !(1 == ~t9_pc~0); 21306#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 21329#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21822#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 21476#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 21477#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 22862#L780-42 assume !(1 == ~t10_pc~0); 21873#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 21681#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21682#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 22768#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 21689#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 21690#L799-42 assume !(1 == ~t11_pc~0); 21155#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 21156#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 21474#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 21475#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 22887#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 21245#L818-42 assume 1 == ~t12_pc~0; 21246#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 21426#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 21779#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 21430#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 21431#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 22442#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22443#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21830#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21814#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21744#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21745#L1361-3 assume !(1 == ~T6_E~0); 22298#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21190#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21191#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22722#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22599#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22600#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22739#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22740#L1401-3 assume !(1 == ~E_1~0); 21506#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21404#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21405#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21961#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21962#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21557#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21558#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21173#L1441-3 assume !(1 == ~E_9~0); 21174#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22679#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22061#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21691#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 21692#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 21696#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 22751#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 22752#L1826 assume !(0 == start_simulation_~tmp~3); 22672#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 22673#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 21553#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 21554#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 22519#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21490#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 21491#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 22771#L1839 assume !(0 != start_simulation_~tmp___0~1); 22658#L1807-1 [2021-11-02 23:17:04,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,744 INFO L85 PathProgramCache]: Analyzing trace with hash -749260739, now seen corresponding path program 1 times [2021-11-02 23:17:04,744 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,745 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113522498] [2021-11-02 23:17:04,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,747 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,792 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113522498] [2021-11-02 23:17:04,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113522498] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,793 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178993593] [2021-11-02 23:17:04,793 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:04,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:04,794 INFO L85 PathProgramCache]: Analyzing trace with hash 1172620075, now seen corresponding path program 1 times [2021-11-02 23:17:04,794 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:04,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342859092] [2021-11-02 23:17:04,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:04,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:04,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:04,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:04,877 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:04,877 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342859092] [2021-11-02 23:17:04,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342859092] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:04,877 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:04,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:04,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414731175] [2021-11-02 23:17:04,878 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:04,879 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:04,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:04,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:04,880 INFO L87 Difference]: Start difference. First operand 1757 states and 2616 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:04,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:04,925 INFO L93 Difference]: Finished difference Result 1757 states and 2615 transitions. [2021-11-02 23:17:04,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:04,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2615 transitions. [2021-11-02 23:17:04,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:04,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2615 transitions. [2021-11-02 23:17:04,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:04,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:04,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2615 transitions. [2021-11-02 23:17:04,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:04,966 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2615 transitions. [2021-11-02 23:17:04,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2615 transitions. [2021-11-02 23:17:05,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:05,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4883323847467274) internal successors, (2615), 1756 states have internal predecessors, (2615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2615 transitions. [2021-11-02 23:17:05,017 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2615 transitions. [2021-11-02 23:17:05,017 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2615 transitions. [2021-11-02 23:17:05,017 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-02 23:17:05,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2615 transitions. [2021-11-02 23:17:05,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:05,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:05,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,031 INFO L791 eck$LassoCheckResult]: Stem: 25476#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25477#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26348#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26349#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 26300#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26174#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26175#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24839#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24840#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25968#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25969#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26125#L880-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25492#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25423#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25057#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25058#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25194#L905-1 assume !(0 == ~M_E~0); 25195#L1198-1 assume !(0 == ~T1_E~0); 25738#L1203-1 assume !(0 == ~T2_E~0); 25739#L1208-1 assume !(0 == ~T3_E~0); 26269#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26362#L1218-1 assume !(0 == ~T5_E~0); 24699#L1223-1 assume !(0 == ~T6_E~0); 24700#L1228-1 assume !(0 == ~T7_E~0); 26249#L1233-1 assume !(0 == ~T8_E~0); 26042#L1238-1 assume !(0 == ~T9_E~0); 26043#L1243-1 assume !(0 == ~T10_E~0); 26340#L1248-1 assume !(0 == ~T11_E~0); 26347#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25794#L1258-1 assume !(0 == ~E_M~0); 25533#L1263-1 assume !(0 == ~E_1~0); 25534#L1268-1 assume !(0 == ~E_2~0); 25834#L1273-1 assume !(0 == ~E_3~0); 26307#L1278-1 assume !(0 == ~E_4~0); 26212#L1283-1 assume !(0 == ~E_5~0); 26213#L1288-1 assume !(0 == ~E_6~0); 26375#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 26368#L1298-1 assume !(0 == ~E_8~0); 26311#L1303-1 assume !(0 == ~E_9~0); 25063#L1308-1 assume !(0 == ~E_10~0); 24993#L1313-1 assume !(0 == ~E_11~0); 24994#L1318-1 assume !(0 == ~E_12~0); 24997#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24998#L590 assume 1 == ~m_pc~0; 26096#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 25279#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25505#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25370#L1489 assume !(0 != activate_threads_~tmp~1); 25371#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26080#L609 assume !(1 == ~t1_pc~0); 26067#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 25870#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24748#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 24749#L1497 assume !(0 != activate_threads_~tmp___0~0); 26366#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26414#L628 assume 1 == ~t2_pc~0; 25163#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25164#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25841#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 25842#L1505 assume !(0 != activate_threads_~tmp___1~0); 25861#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25660#L647 assume !(1 == ~t3_pc~0); 25103#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 25102#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25352#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25353#L1513 assume !(0 != activate_threads_~tmp___2~0); 25892#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25893#L666 assume 1 == ~t4_pc~0; 24969#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 24970#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25112#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 26367#L1521 assume !(0 != activate_threads_~tmp___3~0); 26396#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26397#L685 assume 1 == ~t5_pc~0; 26006#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26007#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25708#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 25104#L1529 assume !(0 != activate_threads_~tmp___4~0); 25105#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25383#L704 assume !(1 == ~t6_pc~0); 25384#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 25823#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25824#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 26195#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25462#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25463#L723 assume 1 == ~t7_pc~0; 25808#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 25986#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26130#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 26333#L1545 assume !(0 != activate_threads_~tmp___6~0); 25922#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25149#L742 assume !(1 == ~t8_pc~0); 25150#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 25305#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25306#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 25944#L1553 assume !(0 != activate_threads_~tmp___7~0); 26126#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 25234#L761 assume 1 == ~t9_pc~0; 25235#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 25110#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 25111#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 26214#L1561 assume !(0 != activate_threads_~tmp___8~0); 25355#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24917#L780 assume !(1 == ~t10_pc~0); 24918#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 25134#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 25135#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 25952#L1569 assume !(0 != activate_threads_~tmp___9~0); 26054#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 26288#L799 assume 1 == ~t11_pc~0; 25959#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 24920#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24921#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 25886#L1577 assume !(0 != activate_threads_~tmp___10~0); 25066#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 25067#L818 assume !(1 == ~t12_pc~0); 24705#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 24706#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 25950#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 26395#L1585 assume !(0 != activate_threads_~tmp___11~0); 26417#L1585-2 assume !(1 == ~M_E~0); 24661#L1336-1 assume !(1 == ~T1_E~0); 24662#L1341-1 assume !(1 == ~T2_E~0); 24725#L1346-1 assume !(1 == ~T3_E~0); 24726#L1351-1 assume !(1 == ~T4_E~0); 25030#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25031#L1361-1 assume !(1 == ~T6_E~0); 26373#L1366-1 assume !(1 == ~T7_E~0); 25074#L1371-1 assume !(1 == ~T8_E~0); 25075#L1376-1 assume !(1 == ~T9_E~0); 25838#L1381-1 assume !(1 == ~T10_E~0); 25839#L1386-1 assume !(1 == ~T11_E~0); 26394#L1391-1 assume !(1 == ~T12_E~0); 26406#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 25734#L1401-1 assume !(1 == ~E_1~0); 25735#L1406-1 assume !(1 == ~E_2~0); 25981#L1411-1 assume !(1 == ~E_3~0); 25982#L1416-1 assume !(1 == ~E_4~0); 25680#L1421-1 assume !(1 == ~E_5~0); 25204#L1426-1 assume !(1 == ~E_6~0); 25205#L1431-1 assume !(1 == ~E_7~0); 24778#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 24779#L1441-1 assume !(1 == ~E_9~0); 25526#L1446-1 assume !(1 == ~E_10~0); 25527#L1451-1 assume !(1 == ~E_11~0); 26178#L1456-1 assume !(1 == ~E_12~0); 26179#L1807-1 [2021-11-02 23:17:05,031 INFO L793 eck$LassoCheckResult]: Loop: 26179#L1807-1 assume !false; 25685#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 25686#L1173 assume !false; 26235#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 26236#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 24664#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 25843#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 26330#L1000 assume !(0 != eval_~tmp~0); 26201#L1188 start_simulation_~kernel_st~0 := 2; 25121#L838-1 start_simulation_~kernel_st~0 := 3; 25122#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25664#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26052#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24974#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24975#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25468#L1218-3 assume !(0 == ~T5_E~0); 24945#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24946#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26222#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25925#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25926#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25754#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25755#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26016#L1258-3 assume !(0 == ~E_M~0); 24938#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24939#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26382#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26386#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26387#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25141#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25142#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26219#L1298-3 assume !(0 == ~E_8~0); 26220#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26323#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26218#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25756#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24940#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24941#L590-42 assume !(1 == ~m_pc~0); 26309#L590-44 is_master_triggered_~__retres1~0 := 0; 26310#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25767#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 25768#L1489-42 assume !(0 != activate_threads_~tmp~1); 25948#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26053#L609-42 assume 1 == ~t1_pc~0; 25152#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24937#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25578#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 25579#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26369#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25859#L628-42 assume 1 == ~t2_pc~0; 25851#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25558#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25559#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26331#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25206#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25207#L647-42 assume 1 == ~t3_pc~0; 25955#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25956#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25144#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25145#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26133#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25333#L666-42 assume 1 == ~t4_pc~0; 25257#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25259#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25338#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25339#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 26275#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26173#L685-42 assume 1 == ~t5_pc~0; 24854#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 24855#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25208#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 25209#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25725#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25726#L704-42 assume !(1 == ~t6_pc~0); 26188#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 25393#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25086#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 25087#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 26005#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25523#L723-42 assume 1 == ~t7_pc~0; 25524#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 25439#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 25310#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 25311#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25449#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25446#L742-42 assume 1 == ~t8_pc~0; 25447#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26142#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 26169#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 25373#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25374#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24826#L761-42 assume !(1 == ~t9_pc~0); 24827#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 24850#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 25343#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 25001#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 25002#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 26384#L780-42 assume !(1 == ~t10_pc~0); 25396#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 25202#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 25203#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 26289#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 25210#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 25211#L799-42 assume !(1 == ~t11_pc~0); 24676#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 24677#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24995#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 24996#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 26408#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 24771#L818-42 assume 1 == ~t12_pc~0; 24772#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 24950#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 25300#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 24951#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 24952#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 25963#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25964#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25351#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25335#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25265#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25266#L1361-3 assume !(1 == ~T6_E~0); 25819#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24711#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24712#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26243#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26120#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26121#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26260#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26261#L1401-3 assume !(1 == ~E_1~0); 25027#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24925#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24926#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25482#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25483#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25078#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25079#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24697#L1441-3 assume !(1 == ~E_9~0); 24698#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26200#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25582#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25212#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 25213#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 25217#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 26272#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 26273#L1826 assume !(0 == start_simulation_~tmp~3); 26193#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 26194#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 25076#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 25077#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 26041#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25011#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 25012#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 26292#L1839 assume !(0 != start_simulation_~tmp___0~1); 26179#L1807-1 [2021-11-02 23:17:05,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1167149441, now seen corresponding path program 1 times [2021-11-02 23:17:05,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,033 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824600399] [2021-11-02 23:17:05,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,077 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,078 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824600399] [2021-11-02 23:17:05,078 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824600399] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,078 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,078 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,079 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341674658] [2021-11-02 23:17:05,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:05,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,080 INFO L85 PathProgramCache]: Analyzing trace with hash 1172620075, now seen corresponding path program 2 times [2021-11-02 23:17:05,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,080 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822044436] [2021-11-02 23:17:05,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,182 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,184 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822044436] [2021-11-02 23:17:05,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822044436] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,191 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,191 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881521438] [2021-11-02 23:17:05,192 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:05,192 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:05,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:05,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:05,193 INFO L87 Difference]: Start difference. First operand 1757 states and 2615 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:05,243 INFO L93 Difference]: Finished difference Result 1757 states and 2614 transitions. [2021-11-02 23:17:05,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:05,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2614 transitions. [2021-11-02 23:17:05,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2614 transitions. [2021-11-02 23:17:05,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:05,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:05,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2614 transitions. [2021-11-02 23:17:05,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:05,291 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2614 transitions. [2021-11-02 23:17:05,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2614 transitions. [2021-11-02 23:17:05,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:05,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4877632327831531) internal successors, (2614), 1756 states have internal predecessors, (2614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2614 transitions. [2021-11-02 23:17:05,346 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2614 transitions. [2021-11-02 23:17:05,346 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2614 transitions. [2021-11-02 23:17:05,346 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-02 23:17:05,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2614 transitions. [2021-11-02 23:17:05,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:05,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:05,361 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,362 INFO L791 eck$LassoCheckResult]: Stem: 28997#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 28998#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 29869#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29870#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 29821#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29695#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29696#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28360#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28361#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29489#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29490#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29646#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29013#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28944#L890-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28578#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28579#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28715#L905-1 assume !(0 == ~M_E~0); 28716#L1198-1 assume !(0 == ~T1_E~0); 29259#L1203-1 assume !(0 == ~T2_E~0); 29260#L1208-1 assume !(0 == ~T3_E~0); 29790#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29883#L1218-1 assume !(0 == ~T5_E~0); 28220#L1223-1 assume !(0 == ~T6_E~0); 28221#L1228-1 assume !(0 == ~T7_E~0); 29770#L1233-1 assume !(0 == ~T8_E~0); 29563#L1238-1 assume !(0 == ~T9_E~0); 29564#L1243-1 assume !(0 == ~T10_E~0); 29861#L1248-1 assume !(0 == ~T11_E~0); 29868#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29315#L1258-1 assume !(0 == ~E_M~0); 29054#L1263-1 assume !(0 == ~E_1~0); 29055#L1268-1 assume !(0 == ~E_2~0); 29355#L1273-1 assume !(0 == ~E_3~0); 29828#L1278-1 assume !(0 == ~E_4~0); 29733#L1283-1 assume !(0 == ~E_5~0); 29734#L1288-1 assume !(0 == ~E_6~0); 29896#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 29889#L1298-1 assume !(0 == ~E_8~0); 29832#L1303-1 assume !(0 == ~E_9~0); 28584#L1308-1 assume !(0 == ~E_10~0); 28514#L1313-1 assume !(0 == ~E_11~0); 28515#L1318-1 assume !(0 == ~E_12~0); 28518#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28519#L590 assume 1 == ~m_pc~0; 29617#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28800#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29026#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 28891#L1489 assume !(0 != activate_threads_~tmp~1); 28892#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29601#L609 assume !(1 == ~t1_pc~0); 29588#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 29391#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28269#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 28270#L1497 assume !(0 != activate_threads_~tmp___0~0); 29887#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29935#L628 assume 1 == ~t2_pc~0; 28684#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28685#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29362#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29363#L1505 assume !(0 != activate_threads_~tmp___1~0); 29382#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29181#L647 assume !(1 == ~t3_pc~0); 28624#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 28623#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28873#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28874#L1513 assume !(0 != activate_threads_~tmp___2~0); 29413#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29414#L666 assume 1 == ~t4_pc~0; 28490#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28491#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28633#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29888#L1521 assume !(0 != activate_threads_~tmp___3~0); 29917#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29918#L685 assume 1 == ~t5_pc~0; 29527#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 29528#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29229#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28625#L1529 assume !(0 != activate_threads_~tmp___4~0); 28626#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28904#L704 assume !(1 == ~t6_pc~0); 28905#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 29344#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29345#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 29716#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 28983#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28984#L723 assume 1 == ~t7_pc~0; 29329#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 29507#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 29651#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 29854#L1545 assume !(0 != activate_threads_~tmp___6~0); 29443#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28670#L742 assume !(1 == ~t8_pc~0); 28671#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 28826#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28827#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 29465#L1553 assume !(0 != activate_threads_~tmp___7~0); 29647#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28755#L761 assume 1 == ~t9_pc~0; 28756#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 28631#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28632#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 29735#L1561 assume !(0 != activate_threads_~tmp___8~0); 28876#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 28438#L780 assume !(1 == ~t10_pc~0); 28439#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 28655#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28656#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 29473#L1569 assume !(0 != activate_threads_~tmp___9~0); 29575#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29809#L799 assume 1 == ~t11_pc~0; 29480#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 28441#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28442#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 29407#L1577 assume !(0 != activate_threads_~tmp___10~0); 28587#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 28588#L818 assume !(1 == ~t12_pc~0); 28226#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 28227#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 29471#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 29916#L1585 assume !(0 != activate_threads_~tmp___11~0); 29938#L1585-2 assume !(1 == ~M_E~0); 28182#L1336-1 assume !(1 == ~T1_E~0); 28183#L1341-1 assume !(1 == ~T2_E~0); 28246#L1346-1 assume !(1 == ~T3_E~0); 28247#L1351-1 assume !(1 == ~T4_E~0); 28551#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28552#L1361-1 assume !(1 == ~T6_E~0); 29894#L1366-1 assume !(1 == ~T7_E~0); 28595#L1371-1 assume !(1 == ~T8_E~0); 28596#L1376-1 assume !(1 == ~T9_E~0); 29359#L1381-1 assume !(1 == ~T10_E~0); 29360#L1386-1 assume !(1 == ~T11_E~0); 29915#L1391-1 assume !(1 == ~T12_E~0); 29927#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 29255#L1401-1 assume !(1 == ~E_1~0); 29256#L1406-1 assume !(1 == ~E_2~0); 29502#L1411-1 assume !(1 == ~E_3~0); 29503#L1416-1 assume !(1 == ~E_4~0); 29201#L1421-1 assume !(1 == ~E_5~0); 28725#L1426-1 assume !(1 == ~E_6~0); 28726#L1431-1 assume !(1 == ~E_7~0); 28299#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 28300#L1441-1 assume !(1 == ~E_9~0); 29047#L1446-1 assume !(1 == ~E_10~0); 29048#L1451-1 assume !(1 == ~E_11~0); 29699#L1456-1 assume !(1 == ~E_12~0); 29700#L1807-1 [2021-11-02 23:17:05,362 INFO L793 eck$LassoCheckResult]: Loop: 29700#L1807-1 assume !false; 29206#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 29207#L1173 assume !false; 29756#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 29757#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 28185#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 29364#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 29851#L1000 assume !(0 != eval_~tmp~0); 29722#L1188 start_simulation_~kernel_st~0 := 2; 28642#L838-1 start_simulation_~kernel_st~0 := 3; 28643#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29185#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29573#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28495#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28496#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28989#L1218-3 assume !(0 == ~T5_E~0); 28466#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28467#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29743#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29446#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29447#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29275#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29276#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29537#L1258-3 assume !(0 == ~E_M~0); 28459#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28460#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29903#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29907#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29908#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28662#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28663#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29740#L1298-3 assume !(0 == ~E_8~0); 29741#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29844#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29739#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29277#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28461#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28462#L590-42 assume 1 == ~m_pc~0; 29904#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 29831#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29288#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 29289#L1489-42 assume !(0 != activate_threads_~tmp~1); 29469#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29574#L609-42 assume 1 == ~t1_pc~0; 28673#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 28458#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29099#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 29100#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29890#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29380#L628-42 assume 1 == ~t2_pc~0; 29372#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 29079#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29080#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29852#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28727#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28728#L647-42 assume 1 == ~t3_pc~0; 29476#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 29477#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28665#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28666#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29654#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28854#L666-42 assume 1 == ~t4_pc~0; 28778#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28780#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28859#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28860#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29796#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29694#L685-42 assume 1 == ~t5_pc~0; 28372#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 28373#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28729#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28730#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29246#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29247#L704-42 assume !(1 == ~t6_pc~0); 29709#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 28914#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28607#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 28608#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 29526#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29044#L723-42 assume 1 == ~t7_pc~0; 29045#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 28960#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28831#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 28832#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 28970#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28967#L742-42 assume 1 == ~t8_pc~0; 28968#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 29663#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 29690#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 28894#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28895#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28347#L761-42 assume !(1 == ~t9_pc~0); 28348#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 28371#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28864#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 28522#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 28523#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 29905#L780-42 assume !(1 == ~t10_pc~0); 28917#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 28723#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28724#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 29810#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 28731#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 28732#L799-42 assume !(1 == ~t11_pc~0); 28197#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 28198#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28516#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 28517#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 29929#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 28292#L818-42 assume 1 == ~t12_pc~0; 28293#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 28468#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 28821#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 28472#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 28473#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 29484#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29485#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28872#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28856#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28786#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28787#L1361-3 assume !(1 == ~T6_E~0); 29340#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28232#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28233#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29764#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29641#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29642#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29781#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29782#L1401-3 assume !(1 == ~E_1~0); 28548#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28446#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28447#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29003#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29004#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28599#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28600#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28218#L1441-3 assume !(1 == ~E_9~0); 28219#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29721#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29103#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28733#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 28734#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 28738#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 29793#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 29794#L1826 assume !(0 == start_simulation_~tmp~3); 29714#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 29715#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 28597#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 28598#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 29561#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28532#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 28533#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 29813#L1839 assume !(0 != start_simulation_~tmp___0~1); 29700#L1807-1 [2021-11-02 23:17:05,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1728864253, now seen corresponding path program 1 times [2021-11-02 23:17:05,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,364 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908328169] [2021-11-02 23:17:05,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908328169] [2021-11-02 23:17:05,419 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908328169] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,419 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777958650] [2021-11-02 23:17:05,421 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:05,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,421 INFO L85 PathProgramCache]: Analyzing trace with hash -1302441972, now seen corresponding path program 1 times [2021-11-02 23:17:05,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,422 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577217574] [2021-11-02 23:17:05,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,481 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577217574] [2021-11-02 23:17:05,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577217574] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,482 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961492931] [2021-11-02 23:17:05,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:05,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:05,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:05,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:05,484 INFO L87 Difference]: Start difference. First operand 1757 states and 2614 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:05,538 INFO L93 Difference]: Finished difference Result 1757 states and 2613 transitions. [2021-11-02 23:17:05,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:05,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2613 transitions. [2021-11-02 23:17:05,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2613 transitions. [2021-11-02 23:17:05,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:05,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:05,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2613 transitions. [2021-11-02 23:17:05,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:05,575 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2613 transitions. [2021-11-02 23:17:05,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2613 transitions. [2021-11-02 23:17:05,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:05,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.487194080819579) internal successors, (2613), 1756 states have internal predecessors, (2613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2613 transitions. [2021-11-02 23:17:05,624 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2613 transitions. [2021-11-02 23:17:05,624 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2613 transitions. [2021-11-02 23:17:05,624 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-02 23:17:05,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2613 transitions. [2021-11-02 23:17:05,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:05,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:05,636 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,636 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,637 INFO L791 eck$LassoCheckResult]: Stem: 32518#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32519#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33390#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33391#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 33342#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33216#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33217#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31881#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31882#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33010#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33011#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33167#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32534#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32465#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 32099#L895-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32100#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32236#L905-1 assume !(0 == ~M_E~0); 32237#L1198-1 assume !(0 == ~T1_E~0); 32780#L1203-1 assume !(0 == ~T2_E~0); 32781#L1208-1 assume !(0 == ~T3_E~0); 33311#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33404#L1218-1 assume !(0 == ~T5_E~0); 31741#L1223-1 assume !(0 == ~T6_E~0); 31742#L1228-1 assume !(0 == ~T7_E~0); 33291#L1233-1 assume !(0 == ~T8_E~0); 33084#L1238-1 assume !(0 == ~T9_E~0); 33085#L1243-1 assume !(0 == ~T10_E~0); 33382#L1248-1 assume !(0 == ~T11_E~0); 33389#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32836#L1258-1 assume !(0 == ~E_M~0); 32575#L1263-1 assume !(0 == ~E_1~0); 32576#L1268-1 assume !(0 == ~E_2~0); 32876#L1273-1 assume !(0 == ~E_3~0); 33349#L1278-1 assume !(0 == ~E_4~0); 33254#L1283-1 assume !(0 == ~E_5~0); 33255#L1288-1 assume !(0 == ~E_6~0); 33417#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33410#L1298-1 assume !(0 == ~E_8~0); 33353#L1303-1 assume !(0 == ~E_9~0); 32105#L1308-1 assume !(0 == ~E_10~0); 32035#L1313-1 assume !(0 == ~E_11~0); 32036#L1318-1 assume !(0 == ~E_12~0); 32039#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32040#L590 assume 1 == ~m_pc~0; 33138#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 32321#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32547#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32412#L1489 assume !(0 != activate_threads_~tmp~1); 32413#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33122#L609 assume !(1 == ~t1_pc~0); 33109#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 32912#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31790#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 31791#L1497 assume !(0 != activate_threads_~tmp___0~0); 33408#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33456#L628 assume 1 == ~t2_pc~0; 32205#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32206#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32883#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32884#L1505 assume !(0 != activate_threads_~tmp___1~0); 32903#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32702#L647 assume !(1 == ~t3_pc~0); 32145#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 32144#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32394#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32395#L1513 assume !(0 != activate_threads_~tmp___2~0); 32934#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32935#L666 assume 1 == ~t4_pc~0; 32011#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32012#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32154#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 33409#L1521 assume !(0 != activate_threads_~tmp___3~0); 33438#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33439#L685 assume 1 == ~t5_pc~0; 33048#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 33049#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32750#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32146#L1529 assume !(0 != activate_threads_~tmp___4~0); 32147#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32425#L704 assume !(1 == ~t6_pc~0); 32426#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 32865#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32866#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 33237#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32504#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32505#L723 assume 1 == ~t7_pc~0; 32850#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 33028#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33172#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 33375#L1545 assume !(0 != activate_threads_~tmp___6~0); 32964#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32191#L742 assume !(1 == ~t8_pc~0); 32192#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 32347#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32348#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 32986#L1553 assume !(0 != activate_threads_~tmp___7~0); 33168#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32276#L761 assume 1 == ~t9_pc~0; 32277#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 32152#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32153#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 33256#L1561 assume !(0 != activate_threads_~tmp___8~0); 32397#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 31959#L780 assume !(1 == ~t10_pc~0); 31960#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 32176#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32177#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 32994#L1569 assume !(0 != activate_threads_~tmp___9~0); 33096#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 33330#L799 assume 1 == ~t11_pc~0; 33001#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 31962#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 31963#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 32928#L1577 assume !(0 != activate_threads_~tmp___10~0); 32108#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 32109#L818 assume !(1 == ~t12_pc~0); 31747#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 31748#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32992#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 33437#L1585 assume !(0 != activate_threads_~tmp___11~0); 33459#L1585-2 assume !(1 == ~M_E~0); 31703#L1336-1 assume !(1 == ~T1_E~0); 31704#L1341-1 assume !(1 == ~T2_E~0); 31767#L1346-1 assume !(1 == ~T3_E~0); 31768#L1351-1 assume !(1 == ~T4_E~0); 32072#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32073#L1361-1 assume !(1 == ~T6_E~0); 33415#L1366-1 assume !(1 == ~T7_E~0); 32116#L1371-1 assume !(1 == ~T8_E~0); 32117#L1376-1 assume !(1 == ~T9_E~0); 32880#L1381-1 assume !(1 == ~T10_E~0); 32881#L1386-1 assume !(1 == ~T11_E~0); 33436#L1391-1 assume !(1 == ~T12_E~0); 33448#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 32776#L1401-1 assume !(1 == ~E_1~0); 32777#L1406-1 assume !(1 == ~E_2~0); 33023#L1411-1 assume !(1 == ~E_3~0); 33024#L1416-1 assume !(1 == ~E_4~0); 32722#L1421-1 assume !(1 == ~E_5~0); 32246#L1426-1 assume !(1 == ~E_6~0); 32247#L1431-1 assume !(1 == ~E_7~0); 31820#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 31821#L1441-1 assume !(1 == ~E_9~0); 32568#L1446-1 assume !(1 == ~E_10~0); 32569#L1451-1 assume !(1 == ~E_11~0); 33220#L1456-1 assume !(1 == ~E_12~0); 33221#L1807-1 [2021-11-02 23:17:05,637 INFO L793 eck$LassoCheckResult]: Loop: 33221#L1807-1 assume !false; 32727#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 32728#L1173 assume !false; 33277#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 33278#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 31706#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 32885#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 33372#L1000 assume !(0 != eval_~tmp~0); 33243#L1188 start_simulation_~kernel_st~0 := 2; 32163#L838-1 start_simulation_~kernel_st~0 := 3; 32164#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32706#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33094#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32016#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32017#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32510#L1218-3 assume !(0 == ~T5_E~0); 31987#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31988#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33264#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32967#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32968#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32796#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32797#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33058#L1258-3 assume !(0 == ~E_M~0); 31980#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31981#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33424#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33428#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33429#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32183#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32184#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33261#L1298-3 assume !(0 == ~E_8~0); 33262#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33365#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33260#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32798#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 31982#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31983#L590-42 assume 1 == ~m_pc~0; 33425#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 33352#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32809#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32810#L1489-42 assume !(0 != activate_threads_~tmp~1); 32990#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33095#L609-42 assume 1 == ~t1_pc~0; 32194#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 31979#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32620#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32621#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33411#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32901#L628-42 assume !(1 == ~t2_pc~0); 32784#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 32600#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32601#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 33373#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32248#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32249#L647-42 assume 1 == ~t3_pc~0; 32997#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32998#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32186#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32187#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33175#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32375#L666-42 assume 1 == ~t4_pc~0; 32299#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32301#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32380#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32381#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33317#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33215#L685-42 assume 1 == ~t5_pc~0; 31893#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 31894#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32250#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32251#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32767#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32768#L704-42 assume !(1 == ~t6_pc~0); 33230#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 32435#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32128#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32129#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 33047#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32565#L723-42 assume 1 == ~t7_pc~0; 32566#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32481#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32352#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32353#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32491#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32488#L742-42 assume 1 == ~t8_pc~0; 32489#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 33184#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 33211#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 32415#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32416#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 31868#L761-42 assume !(1 == ~t9_pc~0); 31869#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 31892#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32385#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 32043#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 32044#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 33426#L780-42 assume !(1 == ~t10_pc~0); 32438#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 32244#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32245#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 33331#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 32252#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32253#L799-42 assume !(1 == ~t11_pc~0); 31718#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 31719#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32037#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 32038#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 33450#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 31813#L818-42 assume 1 == ~t12_pc~0; 31814#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 31989#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32342#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 31993#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 31994#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 33005#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33006#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32393#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32377#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32307#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32308#L1361-3 assume !(1 == ~T6_E~0); 32861#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31753#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31754#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33285#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33162#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33163#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33302#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33303#L1401-3 assume !(1 == ~E_1~0); 32069#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31967#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31968#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32524#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32525#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32120#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32121#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31739#L1441-3 assume !(1 == ~E_9~0); 31740#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33242#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32624#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32254#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 32255#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 32259#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 33314#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 33315#L1826 assume !(0 == start_simulation_~tmp~3); 33235#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 33236#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 32118#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 32119#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 33082#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 32053#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 32054#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 33334#L1839 assume !(0 != start_simulation_~tmp___0~1); 33221#L1807-1 [2021-11-02 23:17:05,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1365397755, now seen corresponding path program 1 times [2021-11-02 23:17:05,638 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,639 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024930794] [2021-11-02 23:17:05,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,639 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,679 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,679 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024930794] [2021-11-02 23:17:05,679 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024930794] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,679 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,679 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,680 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261645218] [2021-11-02 23:17:05,681 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:05,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1754872235, now seen corresponding path program 1 times [2021-11-02 23:17:05,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,682 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050129221] [2021-11-02 23:17:05,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,743 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,744 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050129221] [2021-11-02 23:17:05,749 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050129221] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,749 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,749 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927513475] [2021-11-02 23:17:05,750 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:05,750 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:05,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:05,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:05,752 INFO L87 Difference]: Start difference. First operand 1757 states and 2613 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:05,784 INFO L93 Difference]: Finished difference Result 1757 states and 2612 transitions. [2021-11-02 23:17:05,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:05,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2612 transitions. [2021-11-02 23:17:05,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2612 transitions. [2021-11-02 23:17:05,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:05,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:05,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2612 transitions. [2021-11-02 23:17:05,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:05,817 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2612 transitions. [2021-11-02 23:17:05,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2612 transitions. [2021-11-02 23:17:05,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:05,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4866249288560045) internal successors, (2612), 1756 states have internal predecessors, (2612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:05,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2612 transitions. [2021-11-02 23:17:05,862 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2612 transitions. [2021-11-02 23:17:05,862 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2612 transitions. [2021-11-02 23:17:05,862 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-02 23:17:05,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2612 transitions. [2021-11-02 23:17:05,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:05,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:05,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:05,874 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,875 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:05,875 INFO L791 eck$LassoCheckResult]: Stem: 36039#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36040#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36911#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36912#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 36863#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36737#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36738#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35402#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35403#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36531#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36532#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36688#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36055#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35986#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35620#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 35621#L900-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35757#L905-1 assume !(0 == ~M_E~0); 35758#L1198-1 assume !(0 == ~T1_E~0); 36301#L1203-1 assume !(0 == ~T2_E~0); 36302#L1208-1 assume !(0 == ~T3_E~0); 36832#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36925#L1218-1 assume !(0 == ~T5_E~0); 35262#L1223-1 assume !(0 == ~T6_E~0); 35263#L1228-1 assume !(0 == ~T7_E~0); 36812#L1233-1 assume !(0 == ~T8_E~0); 36605#L1238-1 assume !(0 == ~T9_E~0); 36606#L1243-1 assume !(0 == ~T10_E~0); 36903#L1248-1 assume !(0 == ~T11_E~0); 36910#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36357#L1258-1 assume !(0 == ~E_M~0); 36096#L1263-1 assume !(0 == ~E_1~0); 36097#L1268-1 assume !(0 == ~E_2~0); 36397#L1273-1 assume !(0 == ~E_3~0); 36870#L1278-1 assume !(0 == ~E_4~0); 36775#L1283-1 assume !(0 == ~E_5~0); 36776#L1288-1 assume !(0 == ~E_6~0); 36938#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36931#L1298-1 assume !(0 == ~E_8~0); 36874#L1303-1 assume !(0 == ~E_9~0); 35626#L1308-1 assume !(0 == ~E_10~0); 35556#L1313-1 assume !(0 == ~E_11~0); 35557#L1318-1 assume !(0 == ~E_12~0); 35560#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35561#L590 assume 1 == ~m_pc~0; 36659#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 35842#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36068#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 35933#L1489 assume !(0 != activate_threads_~tmp~1); 35934#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36643#L609 assume !(1 == ~t1_pc~0); 36630#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 36433#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35311#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 35312#L1497 assume !(0 != activate_threads_~tmp___0~0); 36929#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36977#L628 assume 1 == ~t2_pc~0; 35726#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 35727#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36404#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36405#L1505 assume !(0 != activate_threads_~tmp___1~0); 36424#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36223#L647 assume !(1 == ~t3_pc~0); 35666#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 35665#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35915#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35916#L1513 assume !(0 != activate_threads_~tmp___2~0); 36455#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36456#L666 assume 1 == ~t4_pc~0; 35532#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 35533#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35675#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 36930#L1521 assume !(0 != activate_threads_~tmp___3~0); 36959#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36960#L685 assume 1 == ~t5_pc~0; 36569#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36570#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36271#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 35667#L1529 assume !(0 != activate_threads_~tmp___4~0); 35668#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 35946#L704 assume !(1 == ~t6_pc~0); 35947#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 36386#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 36387#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 36758#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 36025#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 36026#L723 assume 1 == ~t7_pc~0; 36371#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 36549#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36693#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 36896#L1545 assume !(0 != activate_threads_~tmp___6~0); 36485#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35712#L742 assume !(1 == ~t8_pc~0); 35713#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 35868#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35869#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 36507#L1553 assume !(0 != activate_threads_~tmp___7~0); 36689#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 35797#L761 assume 1 == ~t9_pc~0; 35798#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 35673#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35674#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 36777#L1561 assume !(0 != activate_threads_~tmp___8~0); 35918#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 35480#L780 assume !(1 == ~t10_pc~0); 35481#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 35697#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 35698#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36515#L1569 assume !(0 != activate_threads_~tmp___9~0); 36617#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 36851#L799 assume 1 == ~t11_pc~0; 36522#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 35483#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 35484#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 36449#L1577 assume !(0 != activate_threads_~tmp___10~0); 35629#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 35630#L818 assume !(1 == ~t12_pc~0); 35268#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 35269#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 36513#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 36958#L1585 assume !(0 != activate_threads_~tmp___11~0); 36980#L1585-2 assume !(1 == ~M_E~0); 35224#L1336-1 assume !(1 == ~T1_E~0); 35225#L1341-1 assume !(1 == ~T2_E~0); 35288#L1346-1 assume !(1 == ~T3_E~0); 35289#L1351-1 assume !(1 == ~T4_E~0); 35593#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35594#L1361-1 assume !(1 == ~T6_E~0); 36936#L1366-1 assume !(1 == ~T7_E~0); 35637#L1371-1 assume !(1 == ~T8_E~0); 35638#L1376-1 assume !(1 == ~T9_E~0); 36401#L1381-1 assume !(1 == ~T10_E~0); 36402#L1386-1 assume !(1 == ~T11_E~0); 36957#L1391-1 assume !(1 == ~T12_E~0); 36969#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 36297#L1401-1 assume !(1 == ~E_1~0); 36298#L1406-1 assume !(1 == ~E_2~0); 36544#L1411-1 assume !(1 == ~E_3~0); 36545#L1416-1 assume !(1 == ~E_4~0); 36243#L1421-1 assume !(1 == ~E_5~0); 35767#L1426-1 assume !(1 == ~E_6~0); 35768#L1431-1 assume !(1 == ~E_7~0); 35341#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 35342#L1441-1 assume !(1 == ~E_9~0); 36089#L1446-1 assume !(1 == ~E_10~0); 36090#L1451-1 assume !(1 == ~E_11~0); 36741#L1456-1 assume !(1 == ~E_12~0); 36742#L1807-1 [2021-11-02 23:17:05,876 INFO L793 eck$LassoCheckResult]: Loop: 36742#L1807-1 assume !false; 36248#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 36249#L1173 assume !false; 36798#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 36799#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 35227#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 36406#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 36893#L1000 assume !(0 != eval_~tmp~0); 36764#L1188 start_simulation_~kernel_st~0 := 2; 35684#L838-1 start_simulation_~kernel_st~0 := 3; 35685#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36227#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36615#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35537#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35538#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36031#L1218-3 assume !(0 == ~T5_E~0); 35508#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35509#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36785#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36488#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36489#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36317#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36318#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36579#L1258-3 assume !(0 == ~E_M~0); 35501#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35502#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36945#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36949#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36950#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35704#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35705#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36782#L1298-3 assume !(0 == ~E_8~0); 36783#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36886#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36781#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36319#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 35503#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35504#L590-42 assume 1 == ~m_pc~0; 36946#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 36873#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36330#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 36331#L1489-42 assume !(0 != activate_threads_~tmp~1); 36511#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36616#L609-42 assume 1 == ~t1_pc~0; 35715#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35500#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36141#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36142#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36932#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36422#L628-42 assume !(1 == ~t2_pc~0); 36305#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 36121#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36122#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36894#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35769#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35770#L647-42 assume 1 == ~t3_pc~0; 36518#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 36519#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35707#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35708#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36696#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35896#L666-42 assume 1 == ~t4_pc~0; 35820#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 35822#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35901#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 35902#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36838#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36736#L685-42 assume 1 == ~t5_pc~0; 35414#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 35415#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35771#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 35772#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36288#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36289#L704-42 assume 1 == ~t6_pc~0; 36752#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 35956#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 35649#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 35650#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 36568#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 36086#L723-42 assume 1 == ~t7_pc~0; 36087#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 36002#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 35873#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 35874#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 36012#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 36009#L742-42 assume 1 == ~t8_pc~0; 36010#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 36705#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36732#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 35936#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 35937#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 35389#L761-42 assume !(1 == ~t9_pc~0); 35390#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 35413#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35906#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 35564#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 35565#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 36947#L780-42 assume 1 == ~t10_pc~0; 36848#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 35765#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 35766#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36852#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 35773#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 35774#L799-42 assume !(1 == ~t11_pc~0); 35239#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 35240#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 35558#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 35559#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 36971#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 35334#L818-42 assume 1 == ~t12_pc~0; 35335#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 35510#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 35863#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 35514#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 35515#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 36526#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36527#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35914#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35898#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35828#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35829#L1361-3 assume !(1 == ~T6_E~0); 36382#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35274#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35275#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36806#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36683#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36684#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36823#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36824#L1401-3 assume !(1 == ~E_1~0); 35590#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35488#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35489#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36045#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36046#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35641#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35642#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35260#L1441-3 assume !(1 == ~E_9~0); 35261#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36763#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36145#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35775#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 35776#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 35780#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 36835#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 36836#L1826 assume !(0 == start_simulation_~tmp~3); 36756#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 36757#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 35639#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 35640#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 36603#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35574#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 35575#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 36855#L1839 assume !(0 != start_simulation_~tmp___0~1); 36742#L1807-1 [2021-11-02 23:17:05,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1076578365, now seen corresponding path program 1 times [2021-11-02 23:17:05,877 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671739065] [2021-11-02 23:17:05,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:05,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:05,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:05,931 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671739065] [2021-11-02 23:17:05,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671739065] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:05,931 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:05,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:05,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204246687] [2021-11-02 23:17:05,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:05,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:05,933 INFO L85 PathProgramCache]: Analyzing trace with hash 730193773, now seen corresponding path program 1 times [2021-11-02 23:17:05,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:05,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473908659] [2021-11-02 23:17:05,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:05,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:05,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,022 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473908659] [2021-11-02 23:17:06,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473908659] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,022 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,022 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:06,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131062240] [2021-11-02 23:17:06,023 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:06,023 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:06,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:06,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:06,024 INFO L87 Difference]: Start difference. First operand 1757 states and 2612 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:06,059 INFO L93 Difference]: Finished difference Result 1757 states and 2611 transitions. [2021-11-02 23:17:06,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:06,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2611 transitions. [2021-11-02 23:17:06,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:06,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2611 transitions. [2021-11-02 23:17:06,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:06,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:06,095 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2611 transitions. [2021-11-02 23:17:06,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:06,099 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2611 transitions. [2021-11-02 23:17:06,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2611 transitions. [2021-11-02 23:17:06,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:06,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4860557768924303) internal successors, (2611), 1756 states have internal predecessors, (2611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2611 transitions. [2021-11-02 23:17:06,159 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2611 transitions. [2021-11-02 23:17:06,159 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2611 transitions. [2021-11-02 23:17:06,159 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-02 23:17:06,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2611 transitions. [2021-11-02 23:17:06,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:06,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:06,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:06,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,171 INFO L791 eck$LassoCheckResult]: Stem: 39560#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39561#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40432#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40433#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 40384#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40258#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40259#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38923#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38924#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40052#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40053#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40209#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39576#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39507#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39141#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39142#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 39278#L905-1 assume !(0 == ~M_E~0); 39279#L1198-1 assume !(0 == ~T1_E~0); 39822#L1203-1 assume !(0 == ~T2_E~0); 39823#L1208-1 assume !(0 == ~T3_E~0); 40353#L1213-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40446#L1218-1 assume !(0 == ~T5_E~0); 38783#L1223-1 assume !(0 == ~T6_E~0); 38784#L1228-1 assume !(0 == ~T7_E~0); 40333#L1233-1 assume !(0 == ~T8_E~0); 40126#L1238-1 assume !(0 == ~T9_E~0); 40127#L1243-1 assume !(0 == ~T10_E~0); 40424#L1248-1 assume !(0 == ~T11_E~0); 40431#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39878#L1258-1 assume !(0 == ~E_M~0); 39617#L1263-1 assume !(0 == ~E_1~0); 39618#L1268-1 assume !(0 == ~E_2~0); 39918#L1273-1 assume !(0 == ~E_3~0); 40391#L1278-1 assume !(0 == ~E_4~0); 40296#L1283-1 assume !(0 == ~E_5~0); 40297#L1288-1 assume !(0 == ~E_6~0); 40459#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 40452#L1298-1 assume !(0 == ~E_8~0); 40395#L1303-1 assume !(0 == ~E_9~0); 39147#L1308-1 assume !(0 == ~E_10~0); 39077#L1313-1 assume !(0 == ~E_11~0); 39078#L1318-1 assume !(0 == ~E_12~0); 39081#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39082#L590 assume 1 == ~m_pc~0; 40180#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 39363#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39589#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 39454#L1489 assume !(0 != activate_threads_~tmp~1); 39455#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40164#L609 assume !(1 == ~t1_pc~0); 40151#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 39954#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38832#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 38833#L1497 assume !(0 != activate_threads_~tmp___0~0); 40450#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40498#L628 assume 1 == ~t2_pc~0; 39247#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 39248#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39925#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 39926#L1505 assume !(0 != activate_threads_~tmp___1~0); 39945#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39744#L647 assume !(1 == ~t3_pc~0); 39187#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 39186#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39436#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39437#L1513 assume !(0 != activate_threads_~tmp___2~0); 39976#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39977#L666 assume 1 == ~t4_pc~0; 39053#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 39054#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39196#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 40451#L1521 assume !(0 != activate_threads_~tmp___3~0); 40480#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40481#L685 assume 1 == ~t5_pc~0; 40090#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 40091#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39792#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 39188#L1529 assume !(0 != activate_threads_~tmp___4~0); 39189#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39467#L704 assume !(1 == ~t6_pc~0); 39468#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 39907#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39908#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 40279#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 39546#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 39547#L723 assume 1 == ~t7_pc~0; 39892#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 40070#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40214#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 40417#L1545 assume !(0 != activate_threads_~tmp___6~0); 40006#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 39233#L742 assume !(1 == ~t8_pc~0); 39234#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 39389#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 39390#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 40028#L1553 assume !(0 != activate_threads_~tmp___7~0); 40210#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 39318#L761 assume 1 == ~t9_pc~0; 39319#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 39194#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 39195#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 40298#L1561 assume !(0 != activate_threads_~tmp___8~0); 39439#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 39001#L780 assume !(1 == ~t10_pc~0); 39002#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 39218#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 39219#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40036#L1569 assume !(0 != activate_threads_~tmp___9~0); 40138#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 40372#L799 assume 1 == ~t11_pc~0; 40043#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 39004#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 39005#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 39970#L1577 assume !(0 != activate_threads_~tmp___10~0); 39150#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 39151#L818 assume !(1 == ~t12_pc~0); 38789#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 38790#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 40034#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 40479#L1585 assume !(0 != activate_threads_~tmp___11~0); 40501#L1585-2 assume !(1 == ~M_E~0); 38745#L1336-1 assume !(1 == ~T1_E~0); 38746#L1341-1 assume !(1 == ~T2_E~0); 38809#L1346-1 assume !(1 == ~T3_E~0); 38810#L1351-1 assume !(1 == ~T4_E~0); 39114#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39115#L1361-1 assume !(1 == ~T6_E~0); 40457#L1366-1 assume !(1 == ~T7_E~0); 39158#L1371-1 assume !(1 == ~T8_E~0); 39159#L1376-1 assume !(1 == ~T9_E~0); 39922#L1381-1 assume !(1 == ~T10_E~0); 39923#L1386-1 assume !(1 == ~T11_E~0); 40478#L1391-1 assume !(1 == ~T12_E~0); 40490#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 39818#L1401-1 assume !(1 == ~E_1~0); 39819#L1406-1 assume !(1 == ~E_2~0); 40065#L1411-1 assume !(1 == ~E_3~0); 40066#L1416-1 assume !(1 == ~E_4~0); 39764#L1421-1 assume !(1 == ~E_5~0); 39288#L1426-1 assume !(1 == ~E_6~0); 39289#L1431-1 assume !(1 == ~E_7~0); 38862#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 38863#L1441-1 assume !(1 == ~E_9~0); 39610#L1446-1 assume !(1 == ~E_10~0); 39611#L1451-1 assume !(1 == ~E_11~0); 40262#L1456-1 assume !(1 == ~E_12~0); 40263#L1807-1 [2021-11-02 23:17:06,172 INFO L793 eck$LassoCheckResult]: Loop: 40263#L1807-1 assume !false; 39769#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 39770#L1173 assume !false; 40319#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 40320#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 38748#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 39927#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 40414#L1000 assume !(0 != eval_~tmp~0); 40285#L1188 start_simulation_~kernel_st~0 := 2; 39205#L838-1 start_simulation_~kernel_st~0 := 3; 39206#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 39748#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40136#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39058#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39059#L1213-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39552#L1218-3 assume !(0 == ~T5_E~0); 39029#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39030#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40306#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40009#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40010#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39838#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39839#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40100#L1258-3 assume !(0 == ~E_M~0); 39022#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39023#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40466#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40470#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40471#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39225#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39226#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40303#L1298-3 assume !(0 == ~E_8~0); 40304#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40407#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40302#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39840#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39024#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39025#L590-42 assume 1 == ~m_pc~0; 40467#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 40394#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39851#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 39852#L1489-42 assume !(0 != activate_threads_~tmp~1); 40032#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40137#L609-42 assume 1 == ~t1_pc~0; 39236#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 39021#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39662#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 39663#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40453#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39943#L628-42 assume !(1 == ~t2_pc~0); 39826#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 39642#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39643#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 40415#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39290#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39291#L647-42 assume 1 == ~t3_pc~0; 40039#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 40040#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39228#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39229#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 40217#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39417#L666-42 assume 1 == ~t4_pc~0; 39341#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 39343#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39422#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 39423#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40359#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40257#L685-42 assume 1 == ~t5_pc~0; 38935#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 38936#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39292#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 39293#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39809#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39810#L704-42 assume !(1 == ~t6_pc~0); 40272#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 39477#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 39170#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 39171#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 40089#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 39607#L723-42 assume 1 == ~t7_pc~0; 39608#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 39523#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 39394#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 39395#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 39533#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 39530#L742-42 assume 1 == ~t8_pc~0; 39531#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 40226#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40253#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 39457#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 39458#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 38910#L761-42 assume 1 == ~t9_pc~0; 38912#L762-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 38934#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 39427#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 39085#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 39086#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 40468#L780-42 assume 1 == ~t10_pc~0; 40369#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 39286#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 39287#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40373#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 39294#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 39295#L799-42 assume !(1 == ~t11_pc~0); 38760#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 38761#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 39079#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 39080#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 40492#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 38855#L818-42 assume 1 == ~t12_pc~0; 38856#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 39031#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 39384#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 39035#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 39036#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 40047#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40048#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39435#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39419#L1351-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39349#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39350#L1361-3 assume !(1 == ~T6_E~0); 39903#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38795#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38796#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40327#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40204#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40205#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40344#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40345#L1401-3 assume !(1 == ~E_1~0); 39111#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39009#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39010#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39566#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39567#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39162#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39163#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38781#L1441-3 assume !(1 == ~E_9~0); 38782#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40284#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39666#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39296#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 39297#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 39301#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 40356#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 40357#L1826 assume !(0 == start_simulation_~tmp~3); 40277#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 40278#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 39160#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 39161#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 40124#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39095#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 39096#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 40376#L1839 assume !(0 != start_simulation_~tmp___0~1); 40263#L1807-1 [2021-11-02 23:17:06,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,173 INFO L85 PathProgramCache]: Analyzing trace with hash 1621450939, now seen corresponding path program 1 times [2021-11-02 23:17:06,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,174 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940406985] [2021-11-02 23:17:06,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940406985] [2021-11-02 23:17:06,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940406985] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,222 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:06,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336910285] [2021-11-02 23:17:06,225 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:06,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,225 INFO L85 PathProgramCache]: Analyzing trace with hash -72604243, now seen corresponding path program 1 times [2021-11-02 23:17:06,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,226 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181604126] [2021-11-02 23:17:06,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,287 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181604126] [2021-11-02 23:17:06,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181604126] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,287 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:06,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048140598] [2021-11-02 23:17:06,288 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:06,288 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:06,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:06,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:06,290 INFO L87 Difference]: Start difference. First operand 1757 states and 2611 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:06,328 INFO L93 Difference]: Finished difference Result 1757 states and 2606 transitions. [2021-11-02 23:17:06,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:06,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1757 states and 2606 transitions. [2021-11-02 23:17:06,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:06,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1757 states to 1757 states and 2606 transitions. [2021-11-02 23:17:06,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1757 [2021-11-02 23:17:06,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1757 [2021-11-02 23:17:06,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1757 states and 2606 transitions. [2021-11-02 23:17:06,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:06,357 INFO L681 BuchiCegarLoop]: Abstraction has 1757 states and 2606 transitions. [2021-11-02 23:17:06,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1757 states and 2606 transitions. [2021-11-02 23:17:06,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1757 to 1757. [2021-11-02 23:17:06,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.483210017074559) internal successors, (2606), 1756 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2606 transitions. [2021-11-02 23:17:06,401 INFO L704 BuchiCegarLoop]: Abstraction has 1757 states and 2606 transitions. [2021-11-02 23:17:06,401 INFO L587 BuchiCegarLoop]: Abstraction has 1757 states and 2606 transitions. [2021-11-02 23:17:06,401 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-02 23:17:06,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2606 transitions. [2021-11-02 23:17:06,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1598 [2021-11-02 23:17:06,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:06,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:06,413 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,414 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,414 INFO L791 eck$LassoCheckResult]: Stem: 43083#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43084#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43953#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43954#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 43905#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43781#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43782#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42444#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42445#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43575#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43576#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43730#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43097#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43028#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42662#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 42663#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 42799#L905-1 assume !(0 == ~M_E~0); 42800#L1198-1 assume !(0 == ~T1_E~0); 43343#L1203-1 assume !(0 == ~T2_E~0); 43344#L1208-1 assume !(0 == ~T3_E~0); 43875#L1213-1 assume !(0 == ~T4_E~0); 43967#L1218-1 assume !(0 == ~T5_E~0); 42304#L1223-1 assume !(0 == ~T6_E~0); 42305#L1228-1 assume !(0 == ~T7_E~0); 43854#L1233-1 assume !(0 == ~T8_E~0); 43647#L1238-1 assume !(0 == ~T9_E~0); 43648#L1243-1 assume !(0 == ~T10_E~0); 43945#L1248-1 assume !(0 == ~T11_E~0); 43952#L1253-1 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43400#L1258-1 assume !(0 == ~E_M~0); 43138#L1263-1 assume !(0 == ~E_1~0); 43139#L1268-1 assume !(0 == ~E_2~0); 43439#L1273-1 assume !(0 == ~E_3~0); 43912#L1278-1 assume !(0 == ~E_4~0); 43817#L1283-1 assume !(0 == ~E_5~0); 43818#L1288-1 assume !(0 == ~E_6~0); 43980#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 43973#L1298-1 assume !(0 == ~E_8~0); 43916#L1303-1 assume !(0 == ~E_9~0); 42668#L1308-1 assume !(0 == ~E_10~0); 42598#L1313-1 assume !(0 == ~E_11~0); 42599#L1318-1 assume !(0 == ~E_12~0); 42606#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42607#L590 assume 1 == ~m_pc~0; 43702#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 42884#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43116#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 42975#L1489 assume !(0 != activate_threads_~tmp~1); 42976#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43685#L609 assume !(1 == ~t1_pc~0); 43672#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 43475#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42355#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 42356#L1497 assume !(0 != activate_threads_~tmp___0~0); 43971#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44019#L628 assume 1 == ~t2_pc~0; 42768#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 42769#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43446#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43447#L1505 assume !(0 != activate_threads_~tmp___1~0); 43466#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43265#L647 assume !(1 == ~t3_pc~0); 42708#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 42707#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42958#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 42959#L1513 assume !(0 != activate_threads_~tmp___2~0); 43497#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43498#L666 assume 1 == ~t4_pc~0; 42574#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 42575#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42717#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43972#L1521 assume !(0 != activate_threads_~tmp___3~0); 44001#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44002#L685 assume 1 == ~t5_pc~0; 43612#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 43613#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43313#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 42709#L1529 assume !(0 != activate_threads_~tmp___4~0); 42710#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 42990#L704 assume !(1 == ~t6_pc~0); 42991#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 43428#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43429#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 43800#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 43067#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43068#L723 assume 1 == ~t7_pc~0; 43413#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43591#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 43735#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 43938#L1545 assume !(0 != activate_threads_~tmp___6~0); 43527#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 42757#L742 assume !(1 == ~t8_pc~0); 42758#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 42910#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 42911#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 43549#L1553 assume !(0 != activate_threads_~tmp___7~0); 43731#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 42841#L761 assume 1 == ~t9_pc~0; 42842#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 42715#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 42716#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 43819#L1561 assume !(0 != activate_threads_~tmp___8~0); 42960#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 42522#L780 assume !(1 == ~t10_pc~0); 42523#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 42740#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 42741#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 43559#L1569 assume !(0 != activate_threads_~tmp___9~0); 43659#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 43893#L799 assume 1 == ~t11_pc~0; 43566#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 42525#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 42526#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 43491#L1577 assume !(0 != activate_threads_~tmp___10~0); 42674#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 42675#L818 assume !(1 == ~t12_pc~0); 42312#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 42313#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 43556#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 44000#L1585 assume !(0 != activate_threads_~tmp___11~0); 44022#L1585-2 assume !(1 == ~M_E~0); 42266#L1336-1 assume !(1 == ~T1_E~0); 42267#L1341-1 assume !(1 == ~T2_E~0); 42330#L1346-1 assume !(1 == ~T3_E~0); 42331#L1351-1 assume !(1 == ~T4_E~0); 42635#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42636#L1361-1 assume !(1 == ~T6_E~0); 43978#L1366-1 assume !(1 == ~T7_E~0); 42681#L1371-1 assume !(1 == ~T8_E~0); 42682#L1376-1 assume !(1 == ~T9_E~0); 43443#L1381-1 assume !(1 == ~T10_E~0); 43444#L1386-1 assume !(1 == ~T11_E~0); 43999#L1391-1 assume !(1 == ~T12_E~0); 44011#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 43339#L1401-1 assume !(1 == ~E_1~0); 43340#L1406-1 assume !(1 == ~E_2~0); 43586#L1411-1 assume !(1 == ~E_3~0); 43587#L1416-1 assume !(1 == ~E_4~0); 43285#L1421-1 assume !(1 == ~E_5~0); 42811#L1426-1 assume !(1 == ~E_6~0); 42812#L1431-1 assume !(1 == ~E_7~0); 42383#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 42384#L1441-1 assume !(1 == ~E_9~0); 43132#L1446-1 assume !(1 == ~E_10~0); 43133#L1451-1 assume !(1 == ~E_11~0); 43783#L1456-1 assume !(1 == ~E_12~0); 43784#L1807-1 [2021-11-02 23:17:06,415 INFO L793 eck$LassoCheckResult]: Loop: 43784#L1807-1 assume !false; 43290#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 43291#L1173 assume !false; 43840#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 43841#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 42269#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 43448#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 43935#L1000 assume !(0 != eval_~tmp~0); 43806#L1188 start_simulation_~kernel_st~0 := 2; 42726#L838-1 start_simulation_~kernel_st~0 := 3; 42727#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 43269#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43657#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42579#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42580#L1213-3 assume !(0 == ~T4_E~0); 43073#L1218-3 assume !(0 == ~T5_E~0); 42550#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42551#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43827#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43530#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43531#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43359#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43360#L1253-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43621#L1258-3 assume !(0 == ~E_M~0); 42545#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42546#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43987#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43991#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43992#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42746#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42747#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43824#L1298-3 assume !(0 == ~E_8~0); 43825#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43928#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43823#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43361#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42543#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42544#L590-42 assume 1 == ~m_pc~0; 43988#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 43915#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43372#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 43373#L1489-42 assume !(0 != activate_threads_~tmp~1); 43553#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43658#L609-42 assume 1 == ~t1_pc~0; 42754#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 42542#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43183#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 43184#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43974#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43464#L628-42 assume 1 == ~t2_pc~0; 43456#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 43163#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43164#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43936#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42809#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42810#L647-42 assume 1 == ~t3_pc~0; 43560#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43561#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42749#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 42750#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43738#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42938#L666-42 assume 1 == ~t4_pc~0; 42862#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 42864#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42943#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 42944#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 43880#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43778#L685-42 assume 1 == ~t5_pc~0; 42456#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 42457#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42813#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 42814#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 43330#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 43331#L704-42 assume !(1 == ~t6_pc~0); 43792#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 42998#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 42691#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 42692#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 43610#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43128#L723-42 assume 1 == ~t7_pc~0; 43129#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43044#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 42915#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 42916#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 43054#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 43051#L742-42 assume 1 == ~t8_pc~0; 43052#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 43747#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 43774#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 42978#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 42979#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 42431#L761-42 assume !(1 == ~t9_pc~0); 42432#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 42455#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 42948#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 42604#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 42605#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 43989#L780-42 assume 1 == ~t10_pc~0; 43890#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 42807#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 42808#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 43894#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 42815#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 42816#L799-42 assume !(1 == ~t11_pc~0); 42281#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 42282#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 42600#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 42601#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 44013#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 42376#L818-42 assume 1 == ~t12_pc~0; 42377#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 42552#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 42905#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 42556#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 42557#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 43568#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43569#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42956#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42940#L1351-3 assume !(1 == ~T4_E~0); 42870#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42871#L1361-3 assume !(1 == ~T6_E~0); 43424#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42316#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42317#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43848#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43725#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43726#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43865#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 43866#L1401-3 assume !(1 == ~E_1~0); 42632#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42530#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42531#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43087#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43088#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42683#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42684#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42302#L1441-3 assume !(1 == ~E_9~0); 42303#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43805#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43187#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42817#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 42818#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 42822#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 43877#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 43878#L1826 assume !(0 == start_simulation_~tmp~3); 43798#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 43799#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 42679#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 42680#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 43645#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 42616#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 42617#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 43897#L1839 assume !(0 != start_simulation_~tmp___0~1); 43784#L1807-1 [2021-11-02 23:17:06,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1191792633, now seen corresponding path program 1 times [2021-11-02 23:17:06,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,418 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441844565] [2021-11-02 23:17:06,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,467 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441844565] [2021-11-02 23:17:06,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441844565] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,467 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,468 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:06,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798081917] [2021-11-02 23:17:06,469 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:06,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,471 INFO L85 PathProgramCache]: Analyzing trace with hash 352899441, now seen corresponding path program 1 times [2021-11-02 23:17:06,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,471 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783436709] [2021-11-02 23:17:06,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,524 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,524 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783436709] [2021-11-02 23:17:06,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783436709] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,525 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,525 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:06,525 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695308789] [2021-11-02 23:17:06,526 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:06,526 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:06,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:06,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:06,527 INFO L87 Difference]: Start difference. First operand 1757 states and 2606 transitions. cyclomatic complexity: 850 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:06,684 INFO L93 Difference]: Finished difference Result 3372 states and 4991 transitions. [2021-11-02 23:17:06,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:06,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3372 states and 4991 transitions. [2021-11-02 23:17:06,704 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3196 [2021-11-02 23:17:06,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3372 states to 3372 states and 4991 transitions. [2021-11-02 23:17:06,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3372 [2021-11-02 23:17:06,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3372 [2021-11-02 23:17:06,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3372 states and 4991 transitions. [2021-11-02 23:17:06,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:06,748 INFO L681 BuchiCegarLoop]: Abstraction has 3372 states and 4991 transitions. [2021-11-02 23:17:06,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3372 states and 4991 transitions. [2021-11-02 23:17:06,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3372 to 3372. [2021-11-02 23:17:06,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3372 states, 3372 states have (on average 1.4801304863582443) internal successors, (4991), 3371 states have internal predecessors, (4991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:06,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3372 states to 3372 states and 4991 transitions. [2021-11-02 23:17:06,881 INFO L704 BuchiCegarLoop]: Abstraction has 3372 states and 4991 transitions. [2021-11-02 23:17:06,881 INFO L587 BuchiCegarLoop]: Abstraction has 3372 states and 4991 transitions. [2021-11-02 23:17:06,881 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-02 23:17:06,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3372 states and 4991 transitions. [2021-11-02 23:17:06,897 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3196 [2021-11-02 23:17:06,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:06,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:06,900 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,900 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:06,901 INFO L791 eck$LassoCheckResult]: Stem: 48221#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 48222#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 49150#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49151#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 49090#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48943#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48944#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47583#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47584#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48721#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48722#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48884#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48237#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48168#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47801#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47802#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47939#L905-1 assume !(0 == ~M_E~0); 47940#L1198-1 assume !(0 == ~T1_E~0); 48487#L1203-1 assume !(0 == ~T2_E~0); 48488#L1208-1 assume !(0 == ~T3_E~0); 49055#L1213-1 assume !(0 == ~T4_E~0); 49168#L1218-1 assume !(0 == ~T5_E~0); 47443#L1223-1 assume !(0 == ~T6_E~0); 47444#L1228-1 assume !(0 == ~T7_E~0); 49032#L1233-1 assume !(0 == ~T8_E~0); 48798#L1238-1 assume !(0 == ~T9_E~0); 48799#L1243-1 assume !(0 == ~T10_E~0); 49139#L1248-1 assume !(0 == ~T11_E~0); 49149#L1253-1 assume !(0 == ~T12_E~0); 48544#L1258-1 assume !(0 == ~E_M~0); 48278#L1263-1 assume !(0 == ~E_1~0); 48279#L1268-1 assume !(0 == ~E_2~0); 48584#L1273-1 assume !(0 == ~E_3~0); 49098#L1278-1 assume !(0 == ~E_4~0); 48988#L1283-1 assume !(0 == ~E_5~0); 48989#L1288-1 assume !(0 == ~E_6~0); 49188#L1293-1 assume 0 == ~E_7~0;~E_7~0 := 1; 49174#L1298-1 assume !(0 == ~E_8~0); 49102#L1303-1 assume !(0 == ~E_9~0); 47807#L1308-1 assume !(0 == ~E_10~0); 47737#L1313-1 assume !(0 == ~E_11~0); 47738#L1318-1 assume !(0 == ~E_12~0); 47741#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47742#L590 assume 1 == ~m_pc~0; 48853#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 48024#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48250#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 48115#L1489 assume !(0 != activate_threads_~tmp~1); 48116#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48837#L609 assume !(1 == ~t1_pc~0); 48824#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 48621#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47492#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 47493#L1497 assume !(0 != activate_threads_~tmp___0~0); 49172#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49247#L628 assume 1 == ~t2_pc~0; 47908#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 47909#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48591#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 48592#L1505 assume !(0 != activate_threads_~tmp___1~0); 48612#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48408#L647 assume !(1 == ~t3_pc~0); 47848#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 47847#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48097#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 48098#L1513 assume !(0 != activate_threads_~tmp___2~0); 48644#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48645#L666 assume 1 == ~t4_pc~0; 47713#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 47714#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47857#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49173#L1521 assume !(0 != activate_threads_~tmp___3~0); 49219#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49220#L685 assume 1 == ~t5_pc~0; 48761#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 48762#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48456#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 47849#L1529 assume !(0 != activate_threads_~tmp___4~0); 47850#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48128#L704 assume !(1 == ~t6_pc~0); 48129#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 48573#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 48574#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 48965#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 48207#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48208#L723 assume 1 == ~t7_pc~0; 48558#L724 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 48740#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48889#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 49131#L1545 assume !(0 != activate_threads_~tmp___6~0); 48675#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 47894#L742 assume !(1 == ~t8_pc~0); 47895#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 48050#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 48051#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 48697#L1553 assume !(0 != activate_threads_~tmp___7~0); 48885#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 47979#L761 assume 1 == ~t9_pc~0; 47980#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 47855#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 47856#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 48990#L1561 assume !(0 != activate_threads_~tmp___8~0); 48100#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 47661#L780 assume !(1 == ~t10_pc~0); 47662#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 47879#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 47880#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 48705#L1569 assume !(0 != activate_threads_~tmp___9~0); 48811#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 49074#L799 assume 1 == ~t11_pc~0; 48712#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 47664#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 47665#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 48638#L1577 assume !(0 != activate_threads_~tmp___10~0); 47810#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 47811#L818 assume !(1 == ~t12_pc~0); 47449#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 47450#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48703#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 49216#L1585 assume !(0 != activate_threads_~tmp___11~0); 49255#L1585-2 assume !(1 == ~M_E~0); 47405#L1336-1 assume !(1 == ~T1_E~0); 47406#L1341-1 assume !(1 == ~T2_E~0); 47469#L1346-1 assume !(1 == ~T3_E~0); 47470#L1351-1 assume !(1 == ~T4_E~0); 47774#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47775#L1361-1 assume !(1 == ~T6_E~0); 49186#L1366-1 assume !(1 == ~T7_E~0); 47818#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47819#L1376-1 assume !(1 == ~T9_E~0); 48588#L1381-1 assume !(1 == ~T10_E~0); 48589#L1386-1 assume !(1 == ~T11_E~0); 49215#L1391-1 assume !(1 == ~T12_E~0); 49232#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 49233#L1401-1 assume !(1 == ~E_1~0); 49306#L1406-1 assume !(1 == ~E_2~0); 49305#L1411-1 assume !(1 == ~E_3~0); 49303#L1416-1 assume !(1 == ~E_4~0); 49301#L1421-1 assume !(1 == ~E_5~0); 49299#L1426-1 assume !(1 == ~E_6~0); 49297#L1431-1 assume !(1 == ~E_7~0); 49296#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 49295#L1441-1 assume !(1 == ~E_9~0); 49294#L1446-1 assume !(1 == ~E_10~0); 49293#L1451-1 assume !(1 == ~E_11~0); 48947#L1456-1 assume !(1 == ~E_12~0); 48948#L1807-1 [2021-11-02 23:17:06,902 INFO L793 eck$LassoCheckResult]: Loop: 48948#L1807-1 assume !false; 48433#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 48434#L1173 assume !false; 49015#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 49016#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 49264#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 49127#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 49128#L1000 assume !(0 != eval_~tmp~0); 49243#L1188 start_simulation_~kernel_st~0 := 2; 49261#L838-1 start_simulation_~kernel_st~0 := 3; 49260#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48808#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48809#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49259#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49221#L1213-3 assume !(0 == ~T4_E~0); 49222#L1218-3 assume !(0 == ~T5_E~0); 49258#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49141#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49142#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48678#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48679#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48504#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48505#L1253-3 assume !(0 == ~T12_E~0); 48771#L1258-3 assume !(0 == ~E_M~0); 47682#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47683#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49200#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49206#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49207#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47886#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47887#L1293-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48996#L1298-3 assume !(0 == ~E_8~0); 48997#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49119#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48995#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48506#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47684#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47685#L590-42 assume 1 == ~m_pc~0; 49201#L591-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 49101#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48517#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 48518#L1489-42 assume !(0 != activate_threads_~tmp~1); 48701#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48810#L609-42 assume !(1 == ~t1_pc~0); 47680#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 47681#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48324#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 48325#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 49177#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48610#L628-42 assume 1 == ~t2_pc~0; 48602#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 48304#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48305#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 49129#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 47951#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47952#L647-42 assume 1 == ~t3_pc~0; 49251#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 50737#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50736#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50735#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 50734#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50733#L666-42 assume !(1 == ~t4_pc~0); 50731#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 50730#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50729#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50728#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 50727#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50726#L685-42 assume 1 == ~t5_pc~0; 47595#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 47596#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 47953#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 47954#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 48473#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48474#L704-42 assume !(1 == ~t6_pc~0); 48957#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 48138#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 47831#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 47832#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 48760#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48268#L723-42 assume 1 == ~t7_pc~0; 48269#L724-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 48184#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48055#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 48056#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 48194#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 48191#L742-42 assume 1 == ~t8_pc~0; 48192#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 48902#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 48936#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 48118#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 48119#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 47570#L761-42 assume !(1 == ~t9_pc~0); 47571#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 47594#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 48088#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 47745#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 47746#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 49202#L780-42 assume !(1 == ~t10_pc~0); 48141#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 47947#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 47948#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 49076#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 47955#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 47956#L799-42 assume 1 == ~t11_pc~0; 48435#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 47421#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 47739#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 47740#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49236#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 47515#L818-42 assume 1 == ~t12_pc~0; 47516#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 47691#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48045#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 47695#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 47696#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 48716#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48717#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48096#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48080#L1351-3 assume !(1 == ~T4_E~0); 48010#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48011#L1361-3 assume !(1 == ~T6_E~0); 48569#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47455#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47456#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49024#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48879#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48880#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49046#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49047#L1401-3 assume !(1 == ~E_1~0); 47771#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47669#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47670#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48227#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48228#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48903#L1431-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49627#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49625#L1441-3 assume !(1 == ~E_9~0); 48978#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48979#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49617#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49615#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 49612#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 49600#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 49599#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 49235#L1826 assume !(0 == start_simulation_~tmp~3); 48963#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 48964#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 47821#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 47822#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 48796#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47755#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 47756#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 49079#L1839 assume !(0 != start_simulation_~tmp___0~1); 48948#L1807-1 [2021-11-02 23:17:06,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,902 INFO L85 PathProgramCache]: Analyzing trace with hash 1343461625, now seen corresponding path program 1 times [2021-11-02 23:17:06,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853604934] [2021-11-02 23:17:06,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:06,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:06,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:06,954 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853604934] [2021-11-02 23:17:06,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853604934] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:06,954 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:06,954 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:06,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067530798] [2021-11-02 23:17:06,955 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:06,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:06,956 INFO L85 PathProgramCache]: Analyzing trace with hash 81521713, now seen corresponding path program 1 times [2021-11-02 23:17:06,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:06,956 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775237704] [2021-11-02 23:17:06,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:06,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:06,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:07,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:07,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:07,007 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775237704] [2021-11-02 23:17:07,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775237704] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:07,008 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:07,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:07,008 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206248124] [2021-11-02 23:17:07,009 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:07,009 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:07,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:07,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:07,012 INFO L87 Difference]: Start difference. First operand 3372 states and 4991 transitions. cyclomatic complexity: 1621 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:07,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:07,098 INFO L93 Difference]: Finished difference Result 3372 states and 4953 transitions. [2021-11-02 23:17:07,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:07,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3372 states and 4953 transitions. [2021-11-02 23:17:07,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3196 [2021-11-02 23:17:07,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3372 states to 3372 states and 4953 transitions. [2021-11-02 23:17:07,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3372 [2021-11-02 23:17:07,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3372 [2021-11-02 23:17:07,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3372 states and 4953 transitions. [2021-11-02 23:17:07,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:07,144 INFO L681 BuchiCegarLoop]: Abstraction has 3372 states and 4953 transitions. [2021-11-02 23:17:07,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3372 states and 4953 transitions. [2021-11-02 23:17:07,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3372 to 3372. [2021-11-02 23:17:07,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3372 states, 3372 states have (on average 1.4688612099644127) internal successors, (4953), 3371 states have internal predecessors, (4953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:07,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3372 states to 3372 states and 4953 transitions. [2021-11-02 23:17:07,238 INFO L704 BuchiCegarLoop]: Abstraction has 3372 states and 4953 transitions. [2021-11-02 23:17:07,239 INFO L587 BuchiCegarLoop]: Abstraction has 3372 states and 4953 transitions. [2021-11-02 23:17:07,239 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-02 23:17:07,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3372 states and 4953 transitions. [2021-11-02 23:17:07,255 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3196 [2021-11-02 23:17:07,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:07,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:07,258 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:07,259 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:07,259 INFO L791 eck$LassoCheckResult]: Stem: 54972#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 54973#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 55899#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55900#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 55840#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55695#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55696#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54333#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54334#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55470#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55471#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55638#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54988#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54919#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54552#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54553#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54690#L905-1 assume !(0 == ~M_E~0); 54691#L1198-1 assume !(0 == ~T1_E~0); 55236#L1203-1 assume !(0 == ~T2_E~0); 55237#L1208-1 assume !(0 == ~T3_E~0); 55804#L1213-1 assume !(0 == ~T4_E~0); 55918#L1218-1 assume !(0 == ~T5_E~0); 54193#L1223-1 assume !(0 == ~T6_E~0); 54194#L1228-1 assume !(0 == ~T7_E~0); 55782#L1233-1 assume !(0 == ~T8_E~0); 55547#L1238-1 assume !(0 == ~T9_E~0); 55548#L1243-1 assume !(0 == ~T10_E~0); 55888#L1248-1 assume !(0 == ~T11_E~0); 55898#L1253-1 assume !(0 == ~T12_E~0); 55293#L1258-1 assume !(0 == ~E_M~0); 55029#L1263-1 assume !(0 == ~E_1~0); 55030#L1268-1 assume !(0 == ~E_2~0); 55333#L1273-1 assume !(0 == ~E_3~0); 55849#L1278-1 assume !(0 == ~E_4~0); 55741#L1283-1 assume !(0 == ~E_5~0); 55742#L1288-1 assume !(0 == ~E_6~0); 55938#L1293-1 assume !(0 == ~E_7~0); 55924#L1298-1 assume !(0 == ~E_8~0); 55853#L1303-1 assume !(0 == ~E_9~0); 54558#L1308-1 assume !(0 == ~E_10~0); 54488#L1313-1 assume !(0 == ~E_11~0); 54489#L1318-1 assume !(0 == ~E_12~0); 54492#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54493#L590 assume 1 == ~m_pc~0; 55605#L591 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 54775#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55001#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 54866#L1489 assume !(0 != activate_threads_~tmp~1); 54867#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55589#L609 assume !(1 == ~t1_pc~0); 55576#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 55369#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54242#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 54243#L1497 assume !(0 != activate_threads_~tmp___0~0); 55922#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55997#L628 assume 1 == ~t2_pc~0; 54659#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 54660#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55340#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 55341#L1505 assume !(0 != activate_threads_~tmp___1~0); 55360#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55158#L647 assume !(1 == ~t3_pc~0); 54599#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 54598#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54848#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 54849#L1513 assume !(0 != activate_threads_~tmp___2~0); 55392#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55393#L666 assume 1 == ~t4_pc~0; 54464#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 54465#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54608#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 55923#L1521 assume !(0 != activate_threads_~tmp___3~0); 55968#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55969#L685 assume 1 == ~t5_pc~0; 55510#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 55511#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55205#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 54600#L1529 assume !(0 != activate_threads_~tmp___4~0); 54601#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 54879#L704 assume !(1 == ~t6_pc~0); 54880#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 55322#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 55323#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 55718#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 54958#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 54959#L723 assume !(1 == ~t7_pc~0); 55308#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 55489#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 55643#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 55880#L1545 assume !(0 != activate_threads_~tmp___6~0); 55423#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 54645#L742 assume !(1 == ~t8_pc~0); 54646#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 54801#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 54802#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 55445#L1553 assume !(0 != activate_threads_~tmp___7~0); 55639#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 54730#L761 assume 1 == ~t9_pc~0; 54731#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 54606#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 54607#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 55743#L1561 assume !(0 != activate_threads_~tmp___8~0); 54851#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 54412#L780 assume !(1 == ~t10_pc~0); 54413#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 54630#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 54631#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 55454#L1569 assume !(0 != activate_threads_~tmp___9~0); 55562#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 55824#L799 assume 1 == ~t11_pc~0; 55461#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 54415#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 54416#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 55386#L1577 assume !(0 != activate_threads_~tmp___10~0); 54561#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 54562#L818 assume !(1 == ~t12_pc~0); 54199#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 54200#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 55451#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 55964#L1585 assume !(0 != activate_threads_~tmp___11~0); 56005#L1585-2 assume !(1 == ~M_E~0); 54156#L1336-1 assume !(1 == ~T1_E~0); 54157#L1341-1 assume !(1 == ~T2_E~0); 54219#L1346-1 assume !(1 == ~T3_E~0); 54220#L1351-1 assume !(1 == ~T4_E~0); 54525#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54526#L1361-1 assume !(1 == ~T6_E~0); 55935#L1366-1 assume !(1 == ~T7_E~0); 54569#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54570#L1376-1 assume !(1 == ~T9_E~0); 55337#L1381-1 assume !(1 == ~T10_E~0); 55338#L1386-1 assume !(1 == ~T11_E~0); 55963#L1391-1 assume !(1 == ~T12_E~0); 55983#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 55984#L1401-1 assume !(1 == ~E_1~0); 56055#L1406-1 assume !(1 == ~E_2~0); 56054#L1411-1 assume !(1 == ~E_3~0); 56052#L1416-1 assume !(1 == ~E_4~0); 56050#L1421-1 assume !(1 == ~E_5~0); 56048#L1426-1 assume !(1 == ~E_6~0); 56046#L1431-1 assume !(1 == ~E_7~0); 56045#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 56044#L1441-1 assume !(1 == ~E_9~0); 56043#L1446-1 assume !(1 == ~E_10~0); 56042#L1451-1 assume !(1 == ~E_11~0); 55699#L1456-1 assume !(1 == ~E_12~0); 55700#L1807-1 [2021-11-02 23:17:07,260 INFO L793 eck$LassoCheckResult]: Loop: 55700#L1807-1 assume !false; 55182#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 55183#L1173 assume !false; 55766#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 55767#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 56013#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 55876#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 55877#L1000 assume !(0 != eval_~tmp~0); 55993#L1188 start_simulation_~kernel_st~0 := 2; 56010#L838-1 start_simulation_~kernel_st~0 := 3; 56009#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 55559#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55560#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56008#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55970#L1213-3 assume !(0 == ~T4_E~0); 55971#L1218-3 assume !(0 == ~T5_E~0); 56007#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55890#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55891#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55426#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55427#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55253#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55254#L1253-3 assume !(0 == ~T12_E~0); 55520#L1258-3 assume !(0 == ~E_M~0); 54433#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54434#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55949#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55954#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55955#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54637#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54638#L1293-3 assume !(0 == ~E_7~0); 55749#L1298-3 assume !(0 == ~E_8~0); 55750#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55868#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55748#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55255#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54435#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54436#L590-42 assume !(1 == ~m_pc~0); 55851#L590-44 is_master_triggered_~__retres1~0 := 0; 55852#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55266#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 55267#L1489-42 assume !(0 != activate_threads_~tmp~1); 55449#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55561#L609-42 assume 1 == ~t1_pc~0; 54648#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 54432#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55075#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 55076#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55926#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55358#L628-42 assume 1 == ~t2_pc~0; 55350#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 55055#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55056#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 55878#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 54702#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54703#L647-42 assume 1 == ~t3_pc~0; 55457#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 55458#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54640#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 54641#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 55646#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54829#L666-42 assume 1 == ~t4_pc~0; 54753#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 54755#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54834#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 54835#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 55811#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55694#L685-42 assume 1 == ~t5_pc~0; 54346#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 54347#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54704#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 54705#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 55222#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 55223#L704-42 assume !(1 == ~t6_pc~0); 55710#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 54889#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 54582#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 54583#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 55509#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 55019#L723-42 assume !(1 == ~t7_pc~0); 55021#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 54935#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 54806#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 54807#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 54945#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 54942#L742-42 assume !(1 == ~t8_pc~0); 54944#L742-44 is_transmit8_triggered_~__retres1~8 := 0; 55656#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 55690#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 54869#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 54870#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 54320#L761-42 assume !(1 == ~t9_pc~0); 54321#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 54345#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 54839#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 54496#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 54497#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 55951#L780-42 assume !(1 == ~t10_pc~0); 54892#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 54698#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 54699#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 55826#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 54706#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 54707#L799-42 assume 1 == ~t11_pc~0; 55184#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 54172#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 54490#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 54491#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 55987#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 54265#L818-42 assume 1 == ~t12_pc~0; 54266#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 54442#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 54796#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 54446#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 54447#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 55465#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55466#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54847#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54831#L1351-3 assume !(1 == ~T4_E~0); 54761#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54762#L1361-3 assume !(1 == ~T6_E~0); 55318#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54205#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54206#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55775#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55633#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55634#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55794#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55795#L1401-3 assume !(1 == ~E_1~0); 54522#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54420#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54421#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54978#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54979#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55657#L1431-3 assume !(1 == ~E_7~0); 56375#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56373#L1441-3 assume !(1 == ~E_9~0); 55731#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 55732#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56365#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56363#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 56360#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 56348#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 56347#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 55986#L1826 assume !(0 == start_simulation_~tmp~3); 55716#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 55717#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 54572#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 54573#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 55545#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54506#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 54507#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 55829#L1839 assume !(0 != start_simulation_~tmp___0~1); 55700#L1807-1 [2021-11-02 23:17:07,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:07,262 INFO L85 PathProgramCache]: Analyzing trace with hash 240643064, now seen corresponding path program 1 times [2021-11-02 23:17:07,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:07,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141441440] [2021-11-02 23:17:07,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:07,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:07,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:07,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:07,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:07,302 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141441440] [2021-11-02 23:17:07,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141441440] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:07,302 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:07,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:07,302 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490277795] [2021-11-02 23:17:07,303 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:07,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:07,304 INFO L85 PathProgramCache]: Analyzing trace with hash -1890935596, now seen corresponding path program 1 times [2021-11-02 23:17:07,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:07,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263426522] [2021-11-02 23:17:07,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:07,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:07,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:07,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:07,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:07,350 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263426522] [2021-11-02 23:17:07,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263426522] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:07,351 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:07,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:07,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550533272] [2021-11-02 23:17:07,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:07,352 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:07,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:07,353 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:07,353 INFO L87 Difference]: Start difference. First operand 3372 states and 4953 transitions. cyclomatic complexity: 1583 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:07,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:07,527 INFO L93 Difference]: Finished difference Result 6523 states and 9509 transitions. [2021-11-02 23:17:07,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:07,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6523 states and 9509 transitions. [2021-11-02 23:17:07,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6346 [2021-11-02 23:17:07,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6523 states to 6523 states and 9509 transitions. [2021-11-02 23:17:07,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6523 [2021-11-02 23:17:07,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6523 [2021-11-02 23:17:07,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6523 states and 9509 transitions. [2021-11-02 23:17:07,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:07,672 INFO L681 BuchiCegarLoop]: Abstraction has 6523 states and 9509 transitions. [2021-11-02 23:17:07,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6523 states and 9509 transitions. [2021-11-02 23:17:07,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6523 to 6345. [2021-11-02 23:17:07,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6345 states, 6345 states have (on average 1.4592592592592593) internal successors, (9259), 6344 states have internal predecessors, (9259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:07,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6345 states to 6345 states and 9259 transitions. [2021-11-02 23:17:07,818 INFO L704 BuchiCegarLoop]: Abstraction has 6345 states and 9259 transitions. [2021-11-02 23:17:07,818 INFO L587 BuchiCegarLoop]: Abstraction has 6345 states and 9259 transitions. [2021-11-02 23:17:07,818 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-02 23:17:07,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6345 states and 9259 transitions. [2021-11-02 23:17:07,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6168 [2021-11-02 23:17:07,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:07,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:07,851 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:07,851 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:07,851 INFO L791 eck$LassoCheckResult]: Stem: 64880#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 64881#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 65853#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65854#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 65792#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65636#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65637#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64236#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64237#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65410#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65411#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65584#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64896#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64827#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64455#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64456#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64594#L905-1 assume !(0 == ~M_E~0); 64595#L1198-1 assume !(0 == ~T1_E~0); 65161#L1203-1 assume !(0 == ~T2_E~0); 65162#L1208-1 assume !(0 == ~T3_E~0); 65752#L1213-1 assume !(0 == ~T4_E~0); 65875#L1218-1 assume !(0 == ~T5_E~0); 64095#L1223-1 assume !(0 == ~T6_E~0); 64096#L1228-1 assume !(0 == ~T7_E~0); 65726#L1233-1 assume !(0 == ~T8_E~0); 65489#L1238-1 assume !(0 == ~T9_E~0); 65490#L1243-1 assume !(0 == ~T10_E~0); 65843#L1248-1 assume !(0 == ~T11_E~0); 65852#L1253-1 assume !(0 == ~T12_E~0); 65219#L1258-1 assume !(0 == ~E_M~0); 64939#L1263-1 assume !(0 == ~E_1~0); 64940#L1268-1 assume !(0 == ~E_2~0); 65259#L1273-1 assume !(0 == ~E_3~0); 65800#L1278-1 assume !(0 == ~E_4~0); 65681#L1283-1 assume !(0 == ~E_5~0); 65682#L1288-1 assume !(0 == ~E_6~0); 65892#L1293-1 assume !(0 == ~E_7~0); 65882#L1298-1 assume !(0 == ~E_8~0); 65808#L1303-1 assume !(0 == ~E_9~0); 64461#L1308-1 assume !(0 == ~E_10~0); 64391#L1313-1 assume !(0 == ~E_11~0); 64392#L1318-1 assume !(0 == ~E_12~0); 64395#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64396#L590 assume !(1 == ~m_pc~0); 64678#L590-2 is_master_triggered_~__retres1~0 := 0; 64679#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64911#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 64772#L1489 assume !(0 != activate_threads_~tmp~1); 64773#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65532#L609 assume !(1 == ~t1_pc~0); 65516#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 65297#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64145#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 64146#L1497 assume !(0 != activate_threads_~tmp___0~0); 65880#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65979#L628 assume 1 == ~t2_pc~0; 64564#L629 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 64565#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65267#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 65268#L1505 assume !(0 != activate_threads_~tmp___1~0); 65288#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65077#L647 assume !(1 == ~t3_pc~0); 64502#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 64501#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64754#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 64755#L1513 assume !(0 != activate_threads_~tmp___2~0); 65328#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65329#L666 assume 1 == ~t4_pc~0; 64367#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64368#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64511#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 65881#L1521 assume !(0 != activate_threads_~tmp___3~0); 65935#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65936#L685 assume 1 == ~t5_pc~0; 65449#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 65450#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65129#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 64503#L1529 assume !(0 != activate_threads_~tmp___4~0); 64504#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64786#L704 assume !(1 == ~t6_pc~0); 64787#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 65248#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65249#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 65659#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 64866#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 64867#L723 assume !(1 == ~t7_pc~0); 65234#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 65429#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 65589#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 65836#L1545 assume !(0 != activate_threads_~tmp___6~0); 65361#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 64549#L742 assume !(1 == ~t8_pc~0); 64550#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 64707#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 64708#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 65385#L1553 assume !(0 != activate_threads_~tmp___7~0); 65585#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 64634#L761 assume 1 == ~t9_pc~0; 64635#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 64509#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 64510#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 65683#L1561 assume !(0 != activate_threads_~tmp___8~0); 64757#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 64315#L780 assume !(1 == ~t10_pc~0); 64316#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 64534#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 64535#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 65394#L1569 assume !(0 != activate_threads_~tmp___9~0); 65502#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 65776#L799 assume 1 == ~t11_pc~0; 65401#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 64318#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 64319#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 65320#L1577 assume !(0 != activate_threads_~tmp___10~0); 64464#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 64465#L818 assume !(1 == ~t12_pc~0); 64101#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 64102#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 65392#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 65934#L1585 assume !(0 != activate_threads_~tmp___11~0); 65992#L1585-2 assume !(1 == ~M_E~0); 64058#L1336-1 assume !(1 == ~T1_E~0); 64059#L1341-1 assume !(1 == ~T2_E~0); 64122#L1346-1 assume !(1 == ~T3_E~0); 64123#L1351-1 assume !(1 == ~T4_E~0); 64428#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64429#L1361-1 assume !(1 == ~T6_E~0); 65890#L1366-1 assume !(1 == ~T7_E~0); 64472#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64473#L1376-1 assume !(1 == ~T9_E~0); 65264#L1381-1 assume !(1 == ~T10_E~0); 65265#L1386-1 assume !(1 == ~T11_E~0); 65973#L1391-1 assume !(1 == ~T12_E~0); 65974#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 65157#L1401-1 assume !(1 == ~E_1~0); 65158#L1406-1 assume !(1 == ~E_2~0); 68027#L1411-1 assume !(1 == ~E_3~0); 68026#L1416-1 assume !(1 == ~E_4~0); 65099#L1421-1 assume !(1 == ~E_5~0); 64604#L1426-1 assume !(1 == ~E_6~0); 64605#L1431-1 assume !(1 == ~E_7~0); 64175#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 64176#L1441-1 assume !(1 == ~E_9~0); 67131#L1446-1 assume !(1 == ~E_10~0); 65975#L1451-1 assume !(1 == ~E_11~0); 65976#L1456-1 assume !(1 == ~E_12~0); 67106#L1807-1 [2021-11-02 23:17:07,852 INFO L793 eck$LassoCheckResult]: Loop: 67106#L1807-1 assume !false; 67103#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 67100#L1173 assume !false; 67099#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 67095#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 67085#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 67084#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 67082#L1000 assume !(0 != eval_~tmp~0); 67081#L1188 start_simulation_~kernel_st~0 := 2; 67079#L838-1 start_simulation_~kernel_st~0 := 3; 67077#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 67075#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67073#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67071#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67069#L1213-3 assume !(0 == ~T4_E~0); 67067#L1218-3 assume !(0 == ~T5_E~0); 67065#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67063#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67060#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67057#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67055#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67052#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67050#L1253-3 assume !(0 == ~T12_E~0); 65926#L1258-3 assume !(0 == ~E_M~0); 64336#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64337#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65908#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65917#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65918#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64541#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64542#L1293-3 assume !(0 == ~E_7~0); 65688#L1298-3 assume !(0 == ~E_8~0); 65689#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65824#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65687#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65180#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64338#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64339#L590-42 assume !(1 == ~m_pc~0); 65802#L590-44 is_master_triggered_~__retres1~0 := 0; 65803#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65191#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 65192#L1489-42 assume !(0 != activate_threads_~tmp~1); 65389#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65501#L609-42 assume 1 == ~t1_pc~0; 64552#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 64335#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64984#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 64985#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 65884#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65285#L628-42 assume 1 == ~t2_pc~0; 65277#L629-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 64964#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64965#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 65832#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 64606#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64607#L647-42 assume 1 == ~t3_pc~0; 65397#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 65398#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64544#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 64545#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65592#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64735#L666-42 assume 1 == ~t4_pc~0; 64657#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64659#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64740#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 64741#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 65761#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65635#L685-42 assume 1 == ~t5_pc~0; 64248#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 64249#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67820#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 67818#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 67816#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 67814#L704-42 assume 1 == ~t6_pc~0; 67811#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 67808#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 67806#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 67804#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 67801#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 67799#L723-42 assume !(1 == ~t7_pc~0); 67796#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 67794#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 67792#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 67790#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 67787#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 67785#L742-42 assume 1 == ~t8_pc~0; 67783#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 67780#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 67778#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 67776#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 67773#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 67771#L761-42 assume !(1 == ~t9_pc~0); 67769#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 67766#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 67764#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 67762#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 67759#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 67754#L780-42 assume 1 == ~t10_pc~0; 67747#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 67745#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 67743#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 67741#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 67738#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 67736#L799-42 assume !(1 == ~t11_pc~0); 67733#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 67731#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 67730#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 67729#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 67728#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 67727#L818-42 assume 1 == ~t12_pc~0; 67725#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 67724#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 67723#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 67722#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 67721#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 67720#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67719#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67718#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67712#L1351-3 assume !(1 == ~T4_E~0); 67709#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67707#L1361-3 assume !(1 == ~T6_E~0); 67705#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 67703#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64108#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67700#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67697#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67695#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65906#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 67692#L1401-3 assume !(1 == ~E_1~0); 67690#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67689#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 67688#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 67687#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67684#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67682#L1431-3 assume !(1 == ~E_7~0); 67680#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67678#L1441-3 assume !(1 == ~E_9~0); 67676#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 67674#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 67671#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 67670#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 67276#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 67262#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 67260#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 67258#L1826 assume !(0 == start_simulation_~tmp~3); 67252#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 67236#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 67228#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 67226#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 67158#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 67132#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 67121#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 67112#L1839 assume !(0 != start_simulation_~tmp___0~1); 67106#L1807-1 [2021-11-02 23:17:07,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:07,853 INFO L85 PathProgramCache]: Analyzing trace with hash -1738943879, now seen corresponding path program 1 times [2021-11-02 23:17:07,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:07,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445496708] [2021-11-02 23:17:07,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:07,854 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:07,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:07,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:07,906 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:07,906 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445496708] [2021-11-02 23:17:07,906 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445496708] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:07,906 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:07,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:07,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653591505] [2021-11-02 23:17:07,907 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:07,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:07,908 INFO L85 PathProgramCache]: Analyzing trace with hash 2106170454, now seen corresponding path program 1 times [2021-11-02 23:17:07,908 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:07,908 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815980973] [2021-11-02 23:17:07,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:07,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:07,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:07,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:07,963 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:07,963 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815980973] [2021-11-02 23:17:07,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815980973] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:07,963 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:07,964 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:07,964 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351855862] [2021-11-02 23:17:07,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:07,965 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:07,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:07,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:07,966 INFO L87 Difference]: Start difference. First operand 6345 states and 9259 transitions. cyclomatic complexity: 2918 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:08,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:08,379 INFO L93 Difference]: Finished difference Result 15336 states and 22199 transitions. [2021-11-02 23:17:08,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:08,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15336 states and 22199 transitions. [2021-11-02 23:17:08,543 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 14966 [2021-11-02 23:17:08,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15336 states to 15336 states and 22199 transitions. [2021-11-02 23:17:08,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15336 [2021-11-02 23:17:08,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15336 [2021-11-02 23:17:08,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15336 states and 22199 transitions. [2021-11-02 23:17:08,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:08,657 INFO L681 BuchiCegarLoop]: Abstraction has 15336 states and 22199 transitions. [2021-11-02 23:17:08,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15336 states and 22199 transitions. [2021-11-02 23:17:08,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15336 to 12086. [2021-11-02 23:17:08,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12086 states, 12086 states have (on average 1.4522588118484197) internal successors, (17552), 12085 states have internal predecessors, (17552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:08,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12086 states to 12086 states and 17552 transitions. [2021-11-02 23:17:08,952 INFO L704 BuchiCegarLoop]: Abstraction has 12086 states and 17552 transitions. [2021-11-02 23:17:08,952 INFO L587 BuchiCegarLoop]: Abstraction has 12086 states and 17552 transitions. [2021-11-02 23:17:08,952 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-02 23:17:08,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12086 states and 17552 transitions. [2021-11-02 23:17:09,008 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11908 [2021-11-02 23:17:09,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:09,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:09,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:09,014 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:09,015 INFO L791 eck$LassoCheckResult]: Stem: 86565#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 86566#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 87543#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87544#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 87486#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87317#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87318#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85927#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85928#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87087#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87088#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87256#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86581#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86512#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86146#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86147#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86282#L905-1 assume !(0 == ~M_E~0); 86283#L1198-1 assume !(0 == ~T1_E~0); 86837#L1203-1 assume !(0 == ~T2_E~0); 86838#L1208-1 assume !(0 == ~T3_E~0); 87442#L1213-1 assume !(0 == ~T4_E~0); 87559#L1218-1 assume !(0 == ~T5_E~0); 85785#L1223-1 assume !(0 == ~T6_E~0); 85786#L1228-1 assume !(0 == ~T7_E~0); 87414#L1233-1 assume !(0 == ~T8_E~0); 87170#L1238-1 assume !(0 == ~T9_E~0); 87171#L1243-1 assume !(0 == ~T10_E~0); 87533#L1248-1 assume !(0 == ~T11_E~0); 87542#L1253-1 assume !(0 == ~T12_E~0); 86896#L1258-1 assume !(0 == ~E_M~0); 86623#L1263-1 assume !(0 == ~E_1~0); 86624#L1268-1 assume !(0 == ~E_2~0); 86938#L1273-1 assume !(0 == ~E_3~0); 87493#L1278-1 assume !(0 == ~E_4~0); 87367#L1283-1 assume !(0 == ~E_5~0); 87368#L1288-1 assume !(0 == ~E_6~0); 87583#L1293-1 assume !(0 == ~E_7~0); 87571#L1298-1 assume !(0 == ~E_8~0); 87499#L1303-1 assume !(0 == ~E_9~0); 86152#L1308-1 assume !(0 == ~E_10~0); 86083#L1313-1 assume !(0 == ~E_11~0); 86084#L1318-1 assume !(0 == ~E_12~0); 86087#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86088#L590 assume !(1 == ~m_pc~0); 86366#L590-2 is_master_triggered_~__retres1~0 := 0; 86367#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86594#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 86459#L1489 assume !(0 != activate_threads_~tmp~1); 86460#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87210#L609 assume !(1 == ~t1_pc~0); 87197#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 86979#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85835#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 85836#L1497 assume !(0 != activate_threads_~tmp___0~0); 87569#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87654#L628 assume !(1 == ~t2_pc~0); 87475#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 87100#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86946#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 86947#L1505 assume !(0 != activate_threads_~tmp___1~0); 86970#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86758#L647 assume !(1 == ~t3_pc~0); 86193#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 86192#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86439#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 86440#L1513 assume !(0 != activate_threads_~tmp___2~0); 87006#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87007#L666 assume 1 == ~t4_pc~0; 86059#L667 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 86060#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86202#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 87570#L1521 assume !(0 != activate_threads_~tmp___3~0); 87619#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87620#L685 assume 1 == ~t5_pc~0; 87128#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 87129#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86806#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 86194#L1529 assume !(0 != activate_threads_~tmp___4~0); 86195#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 86472#L704 assume !(1 == ~t6_pc~0); 86473#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 86928#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 86929#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 87347#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 86551#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 86552#L723 assume !(1 == ~t7_pc~0); 86912#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 87106#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 87261#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 87523#L1545 assume !(0 != activate_threads_~tmp___6~0); 87038#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 86242#L742 assume !(1 == ~t8_pc~0); 86243#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 86392#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 86393#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 87060#L1553 assume !(0 != activate_threads_~tmp___7~0); 87257#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 86322#L761 assume 1 == ~t9_pc~0; 86323#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 86200#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 86201#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 87369#L1561 assume !(0 != activate_threads_~tmp___8~0); 86442#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 86007#L780 assume !(1 == ~t10_pc~0); 86008#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 86227#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 86228#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 87070#L1569 assume !(0 != activate_threads_~tmp___9~0); 87184#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 87469#L799 assume 1 == ~t11_pc~0; 87077#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 86010#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 86011#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 87000#L1577 assume !(0 != activate_threads_~tmp___10~0); 86155#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 86156#L818 assume !(1 == ~t12_pc~0); 85791#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 85792#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 87068#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 87616#L1585 assume !(0 != activate_threads_~tmp___11~0); 87672#L1585-2 assume !(1 == ~M_E~0); 85749#L1336-1 assume !(1 == ~T1_E~0); 85750#L1341-1 assume !(1 == ~T2_E~0); 85812#L1346-1 assume !(1 == ~T3_E~0); 85813#L1351-1 assume !(1 == ~T4_E~0); 86120#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86121#L1361-1 assume !(1 == ~T6_E~0); 87581#L1366-1 assume !(1 == ~T7_E~0); 86163#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86164#L1376-1 assume !(1 == ~T9_E~0); 86943#L1381-1 assume !(1 == ~T10_E~0); 86944#L1386-1 assume !(1 == ~T11_E~0); 87648#L1391-1 assume !(1 == ~T12_E~0); 87649#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 86833#L1401-1 assume !(1 == ~E_1~0); 86834#L1406-1 assume !(1 == ~E_2~0); 87101#L1411-1 assume !(1 == ~E_3~0); 87102#L1416-1 assume !(1 == ~E_4~0); 86777#L1421-1 assume !(1 == ~E_5~0); 86778#L1426-1 assume !(1 == ~E_6~0); 87252#L1431-1 assume !(1 == ~E_7~0); 87253#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 86981#L1441-1 assume !(1 == ~E_9~0); 86982#L1446-1 assume !(1 == ~E_10~0); 87650#L1451-1 assume !(1 == ~E_11~0); 87651#L1456-1 assume !(1 == ~E_12~0); 93573#L1807-1 [2021-11-02 23:17:09,015 INFO L793 eck$LassoCheckResult]: Loop: 93573#L1807-1 assume !false; 93567#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 93562#L1173 assume !false; 93560#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 93506#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 93494#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 93491#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 93487#L1000 assume !(0 != eval_~tmp~0); 93488#L1188 start_simulation_~kernel_st~0 := 2; 95035#L838-1 start_simulation_~kernel_st~0 := 3; 95032#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 95029#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95028#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95027#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95026#L1213-3 assume !(0 == ~T4_E~0); 95024#L1218-3 assume !(0 == ~T5_E~0); 95022#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95020#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95018#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 95016#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 95014#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 95012#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 95009#L1253-3 assume !(0 == ~T12_E~0); 95007#L1258-3 assume !(0 == ~E_M~0); 95005#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95004#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95003#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95002#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95001#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95000#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94999#L1293-3 assume !(0 == ~E_7~0); 94998#L1298-3 assume !(0 == ~E_8~0); 94997#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94996#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 94995#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 94667#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 94666#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 94665#L590-42 assume !(1 == ~m_pc~0); 94664#L590-44 is_master_triggered_~__retres1~0 := 0; 94663#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94662#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 94661#L1489-42 assume !(0 != activate_threads_~tmp~1); 94660#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94659#L609-42 assume 1 == ~t1_pc~0; 94657#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 94656#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94655#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 94654#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 94653#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 94652#L628-42 assume !(1 == ~t2_pc~0); 91176#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 94651#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 94650#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 94649#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 94648#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 94647#L647-42 assume 1 == ~t3_pc~0; 94645#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 94644#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 94643#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 94642#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 94641#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94640#L666-42 assume 1 == ~t4_pc~0; 94639#L667-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 94637#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94636#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 94635#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 94634#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 94633#L685-42 assume 1 == ~t5_pc~0; 94631#L686-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 94630#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 94629#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 94628#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 94627#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 87338#L704-42 assume !(1 == ~t6_pc~0); 87339#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 86482#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 86176#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 86177#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 87127#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 86613#L723-42 assume !(1 == ~t7_pc~0); 86615#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 86528#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 86397#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 86398#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 86538#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 86535#L742-42 assume !(1 == ~t8_pc~0); 86537#L742-44 is_transmit8_triggered_~__retres1~8 := 0; 87274#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 87312#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 86462#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 86463#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 85914#L761-42 assume !(1 == ~t9_pc~0); 85915#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 94487#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 94484#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 94483#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 94482#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 94481#L780-42 assume !(1 == ~t10_pc~0); 94480#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 94478#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 94477#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 94475#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 94473#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 94471#L799-42 assume 1 == ~t11_pc~0; 94469#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 94466#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 94464#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 94462#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 94459#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 94457#L818-42 assume !(1 == ~t12_pc~0); 94455#L818-44 is_transmit12_triggered_~__retres1~12 := 0; 94452#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 94450#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 94448#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 94447#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 94445#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94443#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94442#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94441#L1351-3 assume !(1 == ~T4_E~0); 94439#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94437#L1361-3 assume !(1 == ~T6_E~0); 94435#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94433#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85798#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94430#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94428#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94425#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87596#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94318#L1401-3 assume !(1 == ~E_1~0); 94315#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94313#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94311#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94309#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94307#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94305#L1431-3 assume !(1 == ~E_7~0); 94302#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 94300#L1441-3 assume !(1 == ~E_9~0); 94298#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 94296#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 94294#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 94292#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 94288#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 94260#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 94144#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 94108#L1826 assume !(0 == start_simulation_~tmp~3); 94104#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 93645#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 93636#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 93634#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 93633#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 93604#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 93592#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 93581#L1839 assume !(0 != start_simulation_~tmp___0~1); 93573#L1807-1 [2021-11-02 23:17:09,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:09,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1395176058, now seen corresponding path program 1 times [2021-11-02 23:17:09,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:09,017 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528828333] [2021-11-02 23:17:09,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:09,017 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:09,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:09,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:09,079 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:09,079 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528828333] [2021-11-02 23:17:09,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528828333] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:09,080 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:09,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:09,080 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489403497] [2021-11-02 23:17:09,081 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:09,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:09,082 INFO L85 PathProgramCache]: Analyzing trace with hash -108724078, now seen corresponding path program 1 times [2021-11-02 23:17:09,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:09,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841723985] [2021-11-02 23:17:09,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:09,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:09,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:09,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:09,134 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:09,134 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841723985] [2021-11-02 23:17:09,134 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841723985] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:09,135 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:09,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:09,135 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564630587] [2021-11-02 23:17:09,136 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:09,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:09,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:09,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:09,137 INFO L87 Difference]: Start difference. First operand 12086 states and 17552 transitions. cyclomatic complexity: 5470 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:09,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:09,374 INFO L93 Difference]: Finished difference Result 23165 states and 33493 transitions. [2021-11-02 23:17:09,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:09,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23165 states and 33493 transitions. [2021-11-02 23:17:09,592 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22968 [2021-11-02 23:17:09,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23165 states to 23165 states and 33493 transitions. [2021-11-02 23:17:09,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23165 [2021-11-02 23:17:09,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23165 [2021-11-02 23:17:09,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23165 states and 33493 transitions. [2021-11-02 23:17:09,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:09,723 INFO L681 BuchiCegarLoop]: Abstraction has 23165 states and 33493 transitions. [2021-11-02 23:17:09,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23165 states and 33493 transitions. [2021-11-02 23:17:10,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23165 to 23149. [2021-11-02 23:17:10,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23149 states, 23149 states have (on average 1.4461531815629185) internal successors, (33477), 23148 states have internal predecessors, (33477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:10,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23149 states to 23149 states and 33477 transitions. [2021-11-02 23:17:10,217 INFO L704 BuchiCegarLoop]: Abstraction has 23149 states and 33477 transitions. [2021-11-02 23:17:10,217 INFO L587 BuchiCegarLoop]: Abstraction has 23149 states and 33477 transitions. [2021-11-02 23:17:10,218 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-02 23:17:10,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23149 states and 33477 transitions. [2021-11-02 23:17:10,384 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22952 [2021-11-02 23:17:10,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:10,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:10,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:10,388 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:10,388 INFO L791 eck$LassoCheckResult]: Stem: 121823#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 121824#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 122786#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 122787#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 122725#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122571#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122572#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121183#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121184#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122340#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122341#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122504#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 121838#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 121768#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 121402#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 121403#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 121534#L905-1 assume !(0 == ~M_E~0); 121535#L1198-1 assume !(0 == ~T1_E~0); 122095#L1203-1 assume !(0 == ~T2_E~0); 122096#L1208-1 assume !(0 == ~T3_E~0); 122687#L1213-1 assume !(0 == ~T4_E~0); 122805#L1218-1 assume !(0 == ~T5_E~0); 121043#L1223-1 assume !(0 == ~T6_E~0); 121044#L1228-1 assume !(0 == ~T7_E~0); 122660#L1233-1 assume !(0 == ~T8_E~0); 122417#L1238-1 assume !(0 == ~T9_E~0); 122418#L1243-1 assume !(0 == ~T10_E~0); 122773#L1248-1 assume !(0 == ~T11_E~0); 122785#L1253-1 assume !(0 == ~T12_E~0); 122153#L1258-1 assume !(0 == ~E_M~0); 121878#L1263-1 assume !(0 == ~E_1~0); 121879#L1268-1 assume !(0 == ~E_2~0); 122192#L1273-1 assume !(0 == ~E_3~0); 122733#L1278-1 assume !(0 == ~E_4~0); 122616#L1283-1 assume !(0 == ~E_5~0); 122617#L1288-1 assume !(0 == ~E_6~0); 122830#L1293-1 assume !(0 == ~E_7~0); 122819#L1298-1 assume !(0 == ~E_8~0); 122741#L1303-1 assume !(0 == ~E_9~0); 121408#L1308-1 assume !(0 == ~E_10~0); 121336#L1313-1 assume !(0 == ~E_11~0); 121337#L1318-1 assume !(0 == ~E_12~0); 121344#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121345#L590 assume !(1 == ~m_pc~0); 121618#L590-2 is_master_triggered_~__retres1~0 := 0; 121619#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121856#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 121711#L1489 assume !(0 != activate_threads_~tmp~1); 121712#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 122459#L609 assume !(1 == ~t1_pc~0); 122445#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 122232#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121094#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 121095#L1497 assume !(0 != activate_threads_~tmp___0~0); 122815#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 122907#L628 assume !(1 == ~t2_pc~0); 122715#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 122351#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122200#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 122201#L1505 assume !(0 != activate_threads_~tmp___1~0); 122223#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 122013#L647 assume !(1 == ~t3_pc~0); 121447#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 121446#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121694#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 121695#L1513 assume !(0 != activate_threads_~tmp___2~0); 122258#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 122259#L666 assume !(1 == ~t4_pc~0); 122800#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 121456#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121457#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 122816#L1521 assume !(0 != activate_threads_~tmp___3~0); 122871#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 122872#L685 assume 1 == ~t5_pc~0; 122378#L686 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 122379#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 122061#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 121448#L1529 assume !(0 != activate_threads_~tmp___4~0); 121449#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 121727#L704 assume !(1 == ~t6_pc~0); 121728#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 122181#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 122182#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 122594#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 121807#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 121808#L723 assume !(1 == ~t7_pc~0); 122167#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 122357#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 122509#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 122765#L1545 assume !(0 != activate_threads_~tmp___6~0); 122289#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 121498#L742 assume !(1 == ~t8_pc~0); 121499#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 121647#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 121648#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 122312#L1553 assume !(0 != activate_threads_~tmp___7~0); 122505#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 121576#L761 assume 1 == ~t9_pc~0; 121577#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 121454#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 121455#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 122618#L1561 assume !(0 != activate_threads_~tmp___8~0); 121696#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 121262#L780 assume !(1 == ~t10_pc~0); 121263#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 121483#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 121484#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 122323#L1569 assume !(0 != activate_threads_~tmp___9~0); 122430#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 122707#L799 assume 1 == ~t11_pc~0; 122330#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 121265#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 121266#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 122250#L1577 assume !(0 != activate_threads_~tmp___10~0); 121412#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 121413#L818 assume !(1 == ~t12_pc~0); 121051#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 121052#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 122320#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 122870#L1585 assume !(0 != activate_threads_~tmp___11~0); 122929#L1585-2 assume !(1 == ~M_E~0); 121007#L1336-1 assume !(1 == ~T1_E~0); 121008#L1341-1 assume !(1 == ~T2_E~0); 121069#L1346-1 assume !(1 == ~T3_E~0); 121070#L1351-1 assume !(1 == ~T4_E~0); 121373#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121374#L1361-1 assume !(1 == ~T6_E~0); 122828#L1366-1 assume !(1 == ~T7_E~0); 121419#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 121420#L1376-1 assume !(1 == ~T9_E~0); 122196#L1381-1 assume !(1 == ~T10_E~0); 122197#L1386-1 assume !(1 == ~T11_E~0); 122868#L1391-1 assume !(1 == ~T12_E~0); 122884#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 122089#L1401-1 assume !(1 == ~E_1~0); 122090#L1406-1 assume !(1 == ~E_2~0); 122352#L1411-1 assume !(1 == ~E_3~0); 122353#L1416-1 assume !(1 == ~E_4~0); 122033#L1421-1 assume !(1 == ~E_5~0); 121546#L1426-1 assume !(1 == ~E_6~0); 121547#L1431-1 assume !(1 == ~E_7~0); 121124#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 121125#L1441-1 assume !(1 == ~E_9~0); 121872#L1446-1 assume !(1 == ~E_10~0); 121873#L1451-1 assume !(1 == ~E_11~0); 122904#L1456-1 assume !(1 == ~E_12~0); 127221#L1807-1 [2021-11-02 23:17:10,389 INFO L793 eck$LassoCheckResult]: Loop: 127221#L1807-1 assume !false; 127222#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 131043#L1173 assume !false; 131042#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 126113#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 126104#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 126097#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 126098#L1000 assume !(0 != eval_~tmp~0); 130994#L1188 start_simulation_~kernel_st~0 := 2; 132025#L838-1 start_simulation_~kernel_st~0 := 3; 132023#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 132022#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132021#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132020#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132019#L1213-3 assume !(0 == ~T4_E~0); 132017#L1218-3 assume !(0 == ~T5_E~0); 132016#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132015#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132014#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 132013#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 132012#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 132011#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 132010#L1253-3 assume !(0 == ~T12_E~0); 132009#L1258-3 assume !(0 == ~E_M~0); 132008#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132007#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132006#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132005#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132004#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132003#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 132002#L1293-3 assume !(0 == ~E_7~0); 132001#L1298-3 assume !(0 == ~E_8~0); 132000#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 131999#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 131998#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 131997#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 131996#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 131995#L590-42 assume !(1 == ~m_pc~0); 131994#L590-44 is_master_triggered_~__retres1~0 := 0; 131993#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 131992#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 131991#L1489-42 assume !(0 != activate_threads_~tmp~1); 131990#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 131989#L609-42 assume 1 == ~t1_pc~0; 131987#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 131984#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 131983#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 131981#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 131979#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 127465#L628-42 assume !(1 == ~t2_pc~0); 127464#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 127463#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 127462#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 127461#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 127460#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127459#L647-42 assume !(1 == ~t3_pc~0); 127457#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 127454#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 127452#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 127450#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 127448#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 127446#L666-42 assume !(1 == ~t4_pc~0); 127444#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 127441#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 127439#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 127437#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 127435#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 127433#L685-42 assume !(1 == ~t5_pc~0); 127431#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 127428#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 127426#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 127424#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 127422#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 127420#L704-42 assume !(1 == ~t6_pc~0); 127417#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 127414#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 127412#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 127410#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 127408#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 127406#L723-42 assume !(1 == ~t7_pc~0); 127403#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 127400#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 127398#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 127396#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 127394#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 127392#L742-42 assume 1 == ~t8_pc~0; 127389#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 127386#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 127384#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 127382#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 127380#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 127378#L761-42 assume !(1 == ~t9_pc~0); 127376#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 127372#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 127370#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 127368#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 127366#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 127364#L780-42 assume 1 == ~t10_pc~0; 127361#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 127358#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 127356#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 127354#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 127352#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 127350#L799-42 assume !(1 == ~t11_pc~0); 127347#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 127344#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 127342#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 127340#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 127338#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 127336#L818-42 assume 1 == ~t12_pc~0; 127333#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 127330#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 127328#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 127326#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 127324#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 127322#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 127320#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127317#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 127315#L1351-3 assume !(1 == ~T4_E~0); 127313#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 127311#L1361-3 assume !(1 == ~T6_E~0); 127309#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 127307#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 127305#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 127303#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 127301#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 127299#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 127297#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 127295#L1401-3 assume !(1 == ~E_1~0); 127293#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 127291#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 127289#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 127287#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 127285#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 127283#L1431-3 assume !(1 == ~E_7~0); 127281#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 127279#L1441-3 assume !(1 == ~E_9~0); 127277#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 127275#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 127273#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 127271#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 127266#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 127253#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 127251#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 127249#L1826 assume !(0 == start_simulation_~tmp~3); 127247#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 127241#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 127233#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 127232#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 127231#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 127229#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 127226#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 127227#L1839 assume !(0 != start_simulation_~tmp___0~1); 127221#L1807-1 [2021-11-02 23:17:10,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:10,389 INFO L85 PathProgramCache]: Analyzing trace with hash 458148859, now seen corresponding path program 1 times [2021-11-02 23:17:10,390 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:10,390 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413093965] [2021-11-02 23:17:10,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:10,390 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:10,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:10,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:10,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:10,434 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413093965] [2021-11-02 23:17:10,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413093965] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:10,434 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:10,434 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:10,434 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605965203] [2021-11-02 23:17:10,435 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:10,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:10,436 INFO L85 PathProgramCache]: Analyzing trace with hash -688362255, now seen corresponding path program 1 times [2021-11-02 23:17:10,436 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:10,436 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953117869] [2021-11-02 23:17:10,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:10,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:10,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:10,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:10,476 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:10,476 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953117869] [2021-11-02 23:17:10,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [953117869] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:10,477 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:10,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:10,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774524380] [2021-11-02 23:17:10,478 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:10,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:10,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:10,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:10,479 INFO L87 Difference]: Start difference. First operand 23149 states and 33477 transitions. cyclomatic complexity: 10336 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:11,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:11,061 INFO L93 Difference]: Finished difference Result 56272 states and 80818 transitions. [2021-11-02 23:17:11,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:11,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56272 states and 80818 transitions. [2021-11-02 23:17:11,381 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 55284 [2021-11-02 23:17:11,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56272 states to 56272 states and 80818 transitions. [2021-11-02 23:17:11,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56272 [2021-11-02 23:17:11,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56272 [2021-11-02 23:17:11,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56272 states and 80818 transitions. [2021-11-02 23:17:11,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:11,951 INFO L681 BuchiCegarLoop]: Abstraction has 56272 states and 80818 transitions. [2021-11-02 23:17:11,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56272 states and 80818 transitions. [2021-11-02 23:17:12,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56272 to 44444. [2021-11-02 23:17:12,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44444 states, 44444 states have (on average 1.44059940599406) internal successors, (64026), 44443 states have internal predecessors, (64026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:12,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44444 states to 44444 states and 64026 transitions. [2021-11-02 23:17:12,943 INFO L704 BuchiCegarLoop]: Abstraction has 44444 states and 64026 transitions. [2021-11-02 23:17:12,944 INFO L587 BuchiCegarLoop]: Abstraction has 44444 states and 64026 transitions. [2021-11-02 23:17:12,944 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-02 23:17:12,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44444 states and 64026 transitions. [2021-11-02 23:17:13,124 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 44224 [2021-11-02 23:17:13,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:13,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:13,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:13,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:13,130 INFO L791 eck$LassoCheckResult]: Stem: 201250#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 201251#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 202242#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 202243#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 202183#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 202016#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 202017#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 200614#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 200615#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 201779#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 201780#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 201953#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 201266#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 201196#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 200829#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 200830#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 200965#L905-1 assume !(0 == ~M_E~0); 200966#L1198-1 assume !(0 == ~T1_E~0); 201524#L1203-1 assume !(0 == ~T2_E~0); 201525#L1208-1 assume !(0 == ~T3_E~0); 202140#L1213-1 assume !(0 == ~T4_E~0); 202262#L1218-1 assume !(0 == ~T5_E~0); 200474#L1223-1 assume !(0 == ~T6_E~0); 200475#L1228-1 assume !(0 == ~T7_E~0); 202113#L1233-1 assume !(0 == ~T8_E~0); 201861#L1238-1 assume !(0 == ~T9_E~0); 201862#L1243-1 assume !(0 == ~T10_E~0); 202234#L1248-1 assume !(0 == ~T11_E~0); 202241#L1253-1 assume !(0 == ~T12_E~0); 201585#L1258-1 assume !(0 == ~E_M~0); 201308#L1263-1 assume !(0 == ~E_1~0); 201309#L1268-1 assume !(0 == ~E_2~0); 201625#L1273-1 assume !(0 == ~E_3~0); 202191#L1278-1 assume !(0 == ~E_4~0); 202068#L1283-1 assume !(0 == ~E_5~0); 202069#L1288-1 assume !(0 == ~E_6~0); 202284#L1293-1 assume !(0 == ~E_7~0); 202273#L1298-1 assume !(0 == ~E_8~0); 202199#L1303-1 assume !(0 == ~E_9~0); 200835#L1308-1 assume !(0 == ~E_10~0); 200766#L1313-1 assume !(0 == ~E_11~0); 200767#L1318-1 assume !(0 == ~E_12~0); 200770#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 200771#L590 assume !(1 == ~m_pc~0); 201049#L590-2 is_master_triggered_~__retres1~0 := 0; 201050#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 201279#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 201140#L1489 assume !(0 != activate_threads_~tmp~1); 201141#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 201905#L609 assume !(1 == ~t1_pc~0); 201890#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 201663#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 200523#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 200524#L1497 assume !(0 != activate_threads_~tmp___0~0); 202271#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 202364#L628 assume !(1 == ~t2_pc~0); 202171#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 201793#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 201632#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 201633#L1505 assume !(0 != activate_threads_~tmp___1~0); 201654#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 201443#L647 assume !(1 == ~t3_pc~0); 200876#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 200875#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 201122#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 201123#L1513 assume !(0 != activate_threads_~tmp___2~0); 201697#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 201698#L666 assume !(1 == ~t4_pc~0); 202252#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 200885#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 200886#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 202272#L1521 assume !(0 != activate_threads_~tmp___3~0); 202323#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 202324#L685 assume !(1 == ~t5_pc~0); 201886#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 201887#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 201490#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 200877#L1529 assume !(0 != activate_threads_~tmp___4~0); 200878#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 201156#L704 assume !(1 == ~t6_pc~0); 201157#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 201615#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 201616#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 202040#L1537 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 201235#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 201236#L723 assume !(1 == ~t7_pc~0); 201600#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 201799#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 201958#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 202226#L1545 assume !(0 != activate_threads_~tmp___6~0); 201728#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 200926#L742 assume !(1 == ~t8_pc~0); 200927#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 201075#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 201076#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 201753#L1553 assume !(0 != activate_threads_~tmp___7~0); 201954#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 201006#L761 assume 1 == ~t9_pc~0; 201007#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 200883#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 200884#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 202070#L1561 assume !(0 != activate_threads_~tmp___8~0); 201125#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 200692#L780 assume !(1 == ~t10_pc~0); 200693#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 200909#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 200910#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 201763#L1569 assume !(0 != activate_threads_~tmp___9~0); 201874#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 202166#L799 assume 1 == ~t11_pc~0; 201770#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 200695#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 200696#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 201686#L1577 assume !(0 != activate_threads_~tmp___10~0); 200838#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 200839#L818 assume !(1 == ~t12_pc~0); 200480#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 200481#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 201760#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 202322#L1585 assume !(0 != activate_threads_~tmp___11~0); 202383#L1585-2 assume !(1 == ~M_E~0); 200438#L1336-1 assume !(1 == ~T1_E~0); 200439#L1341-1 assume !(1 == ~T2_E~0); 200500#L1346-1 assume !(1 == ~T3_E~0); 200501#L1351-1 assume !(1 == ~T4_E~0); 200803#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 200804#L1361-1 assume !(1 == ~T6_E~0); 202282#L1366-1 assume !(1 == ~T7_E~0); 200846#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 200847#L1376-1 assume !(1 == ~T9_E~0); 202201#L1381-1 assume !(1 == ~T10_E~0); 202320#L1386-1 assume !(1 == ~T11_E~0); 202321#L1391-1 assume !(1 == ~T12_E~0); 202336#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 202337#L1401-1 assume !(1 == ~E_1~0); 202107#L1406-1 assume !(1 == ~E_2~0); 202108#L1411-1 assume !(1 == ~E_3~0); 202303#L1416-1 assume !(1 == ~E_4~0); 202304#L1421-1 assume !(1 == ~E_5~0); 200976#L1426-1 assume !(1 == ~E_6~0); 200977#L1431-1 assume !(1 == ~E_7~0); 200553#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 200554#L1441-1 assume !(1 == ~E_9~0); 201300#L1446-1 assume !(1 == ~E_10~0); 201301#L1451-1 assume !(1 == ~E_11~0); 202019#L1456-1 assume !(1 == ~E_12~0); 202020#L1807-1 [2021-11-02 23:17:13,131 INFO L793 eck$LassoCheckResult]: Loop: 202020#L1807-1 assume !false; 239493#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 239490#L1173 assume !false; 236028#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 235806#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 235789#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 235783#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 235776#L1000 assume !(0 != eval_~tmp~0); 235777#L1188 start_simulation_~kernel_st~0 := 2; 244485#L838-1 start_simulation_~kernel_st~0 := 3; 244484#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 244483#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 244482#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 244481#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 244480#L1213-3 assume !(0 == ~T4_E~0); 244479#L1218-3 assume !(0 == ~T5_E~0); 244478#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 244477#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 244476#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 244475#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 244474#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 244473#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 244472#L1253-3 assume !(0 == ~T12_E~0); 244471#L1258-3 assume !(0 == ~E_M~0); 244470#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244469#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 244468#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 243977#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 243976#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 243975#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 243974#L1293-3 assume !(0 == ~E_7~0); 243973#L1298-3 assume !(0 == ~E_8~0); 243971#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 243969#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 243967#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 243965#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 243963#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 243961#L590-42 assume !(1 == ~m_pc~0); 243959#L590-44 is_master_triggered_~__retres1~0 := 0; 243957#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 243955#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 243953#L1489-42 assume !(0 != activate_threads_~tmp~1); 243951#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 202265#L609-42 assume 1 == ~t1_pc~0; 200929#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 200712#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 201353#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 201354#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 202274#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 202369#L628-42 assume !(1 == ~t2_pc~0); 240910#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 240908#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 240906#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 240904#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 240902#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 240899#L647-42 assume !(1 == ~t3_pc~0); 240897#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 240894#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 240892#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 240890#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 240888#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 240887#L666-42 assume !(1 == ~t4_pc~0); 240884#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 240882#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 240880#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 240878#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 240876#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 240874#L685-42 assume !(1 == ~t5_pc~0); 213294#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 240870#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 240868#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 240866#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 240864#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 240862#L704-42 assume !(1 == ~t6_pc~0); 240859#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 240857#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 240855#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 240800#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 240797#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 240795#L723-42 assume !(1 == ~t7_pc~0); 240792#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 240790#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 240571#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 240567#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 240565#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 240563#L742-42 assume 1 == ~t8_pc~0; 240561#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 240558#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 240556#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 240554#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 240552#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 240550#L761-42 assume 1 == ~t9_pc~0; 240547#L762-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 240545#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 240543#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 240541#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 240539#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 240537#L780-42 assume !(1 == ~t10_pc~0); 240535#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 240532#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 240530#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 240528#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 240526#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 240523#L799-42 assume 1 == ~t11_pc~0; 240521#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 240518#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 240516#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 240514#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 240512#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 240510#L818-42 assume 1 == ~t12_pc~0; 240507#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 240505#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 240503#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 240501#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 240499#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 240498#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 240496#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 240494#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 240492#L1351-3 assume !(1 == ~T4_E~0); 240490#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240488#L1361-3 assume !(1 == ~T6_E~0); 240485#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 240483#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 239238#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 240480#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 240478#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 240475#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 239229#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 240472#L1401-3 assume !(1 == ~E_1~0); 240470#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 240468#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 240466#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 240464#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 240461#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 240459#L1431-3 assume !(1 == ~E_7~0); 240457#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 240455#L1441-3 assume !(1 == ~E_9~0); 240453#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 240451#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 240448#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 240446#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 240441#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 240428#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 240425#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 240423#L1826 assume !(0 == start_simulation_~tmp~3); 240420#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 240405#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 240396#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 240393#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 240391#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 240389#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 240387#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 240386#L1839 assume !(0 != start_simulation_~tmp___0~1); 202020#L1807-1 [2021-11-02 23:17:13,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:13,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1704830404, now seen corresponding path program 1 times [2021-11-02 23:17:13,132 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:13,132 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507892298] [2021-11-02 23:17:13,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:13,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:13,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:13,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:13,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:13,394 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507892298] [2021-11-02 23:17:13,395 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507892298] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:13,395 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:13,395 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:17:13,395 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977531050] [2021-11-02 23:17:13,397 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:13,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:13,398 INFO L85 PathProgramCache]: Analyzing trace with hash -770000558, now seen corresponding path program 1 times [2021-11-02 23:17:13,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:13,398 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619208231] [2021-11-02 23:17:13,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:13,399 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:13,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:13,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:13,450 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:13,450 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619208231] [2021-11-02 23:17:13,450 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619208231] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:13,450 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:13,451 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:13,451 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401632969] [2021-11-02 23:17:13,452 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:13,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:13,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:17:13,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:17:13,454 INFO L87 Difference]: Start difference. First operand 44444 states and 64026 transitions. cyclomatic complexity: 19590 Second operand has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:14,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:14,345 INFO L93 Difference]: Finished difference Result 112729 states and 163017 transitions. [2021-11-02 23:17:14,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 23:17:14,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112729 states and 163017 transitions. [2021-11-02 23:17:15,060 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 112240 [2021-11-02 23:17:15,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112729 states to 112729 states and 163017 transitions. [2021-11-02 23:17:15,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112729 [2021-11-02 23:17:15,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112729 [2021-11-02 23:17:15,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112729 states and 163017 transitions. [2021-11-02 23:17:15,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:15,971 INFO L681 BuchiCegarLoop]: Abstraction has 112729 states and 163017 transitions. [2021-11-02 23:17:16,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112729 states and 163017 transitions. [2021-11-02 23:17:16,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112729 to 45695. [2021-11-02 23:17:16,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45695 states, 45695 states have (on average 1.428537039063355) internal successors, (65277), 45694 states have internal predecessors, (65277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:17,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45695 states to 45695 states and 65277 transitions. [2021-11-02 23:17:17,070 INFO L704 BuchiCegarLoop]: Abstraction has 45695 states and 65277 transitions. [2021-11-02 23:17:17,072 INFO L587 BuchiCegarLoop]: Abstraction has 45695 states and 65277 transitions. [2021-11-02 23:17:17,072 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-02 23:17:17,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45695 states and 65277 transitions. [2021-11-02 23:17:17,491 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 45472 [2021-11-02 23:17:17,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:17,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:17,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:17,496 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:17,497 INFO L791 eck$LassoCheckResult]: Stem: 358444#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 358445#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 359458#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 359459#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 359391#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 359210#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 359211#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 357801#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 357802#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 358971#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 358972#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 359146#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 358459#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 358385#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 358019#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 358020#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 358152#L905-1 assume !(0 == ~M_E~0); 358153#L1198-1 assume !(0 == ~T1_E~0); 358716#L1203-1 assume !(0 == ~T2_E~0); 358717#L1208-1 assume !(0 == ~T3_E~0); 359352#L1213-1 assume !(0 == ~T4_E~0); 359488#L1218-1 assume !(0 == ~T5_E~0); 357660#L1223-1 assume !(0 == ~T6_E~0); 357661#L1228-1 assume !(0 == ~T7_E~0); 359323#L1233-1 assume !(0 == ~T8_E~0); 359051#L1238-1 assume !(0 == ~T9_E~0); 359052#L1243-1 assume !(0 == ~T10_E~0); 359448#L1248-1 assume !(0 == ~T11_E~0); 359457#L1253-1 assume !(0 == ~T12_E~0); 358782#L1258-1 assume !(0 == ~E_M~0); 358500#L1263-1 assume !(0 == ~E_1~0); 358501#L1268-1 assume !(0 == ~E_2~0); 358823#L1273-1 assume !(0 == ~E_3~0); 359401#L1278-1 assume !(0 == ~E_4~0); 359265#L1283-1 assume !(0 == ~E_5~0); 359266#L1288-1 assume !(0 == ~E_6~0); 359512#L1293-1 assume !(0 == ~E_7~0); 359499#L1298-1 assume !(0 == ~E_8~0); 359407#L1303-1 assume !(0 == ~E_9~0); 358022#L1308-1 assume !(0 == ~E_10~0); 357953#L1313-1 assume !(0 == ~E_11~0); 357954#L1318-1 assume !(0 == ~E_12~0); 357961#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 357962#L590 assume !(1 == ~m_pc~0); 358236#L590-2 is_master_triggered_~__retres1~0 := 0; 358237#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 358477#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 358329#L1489 assume !(0 != activate_threads_~tmp~1); 358330#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 359097#L609 assume !(1 == ~t1_pc~0); 359081#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 358860#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 357712#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 357713#L1497 assume !(0 != activate_threads_~tmp___0~0); 359495#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 359611#L628 assume !(1 == ~t2_pc~0); 359381#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 358983#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 358829#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 358830#L1505 assume !(0 != activate_threads_~tmp___1~0); 358851#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 358636#L647 assume !(1 == ~t3_pc~0); 358063#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 358062#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 358312#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 358313#L1513 assume !(0 != activate_threads_~tmp___2~0); 358885#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 358886#L666 assume !(1 == ~t4_pc~0); 359479#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 358072#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 358073#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 359496#L1521 assume !(0 != activate_threads_~tmp___3~0); 359556#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 359557#L685 assume !(1 == ~t5_pc~0); 359078#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 359079#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 358683#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 358064#L1529 assume !(0 != activate_threads_~tmp___4~0); 358065#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 358344#L704 assume !(1 == ~t6_pc~0); 358345#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 358813#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 358814#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 359236#L1537 assume !(0 != activate_threads_~tmp___5~0); 358428#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 358429#L723 assume !(1 == ~t7_pc~0); 358797#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 358989#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 359151#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 359437#L1545 assume !(0 != activate_threads_~tmp___6~0); 358917#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 358114#L742 assume !(1 == ~t8_pc~0); 358115#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 358265#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 358266#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 358943#L1553 assume !(0 != activate_threads_~tmp___7~0); 359147#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 358194#L761 assume 1 == ~t9_pc~0; 358195#L762 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 358070#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 358071#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 359267#L1561 assume !(0 != activate_threads_~tmp___8~0); 358314#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 357879#L780 assume !(1 == ~t10_pc~0); 357880#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 358097#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 358098#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 358954#L1569 assume !(0 != activate_threads_~tmp___9~0); 359064#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 359374#L799 assume 1 == ~t11_pc~0; 358961#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 357882#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 357883#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 358879#L1577 assume !(0 != activate_threads_~tmp___10~0); 358028#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 358029#L818 assume !(1 == ~t12_pc~0); 357668#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 357669#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 358951#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 359555#L1585 assume !(0 != activate_threads_~tmp___11~0); 359638#L1585-2 assume !(1 == ~M_E~0); 357624#L1336-1 assume !(1 == ~T1_E~0); 357625#L1341-1 assume !(1 == ~T2_E~0); 357687#L1346-1 assume !(1 == ~T3_E~0); 357688#L1351-1 assume !(1 == ~T4_E~0); 357990#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 357991#L1361-1 assume !(1 == ~T6_E~0); 359507#L1366-1 assume !(1 == ~T7_E~0); 358035#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 358036#L1376-1 assume !(1 == ~T9_E~0); 380380#L1381-1 assume !(1 == ~T10_E~0); 380379#L1386-1 assume !(1 == ~T11_E~0); 380378#L1391-1 assume !(1 == ~T12_E~0); 359607#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 380377#L1401-1 assume !(1 == ~E_1~0); 380376#L1406-1 assume !(1 == ~E_2~0); 380375#L1411-1 assume !(1 == ~E_3~0); 380374#L1416-1 assume !(1 == ~E_4~0); 380373#L1421-1 assume !(1 == ~E_5~0); 380372#L1426-1 assume !(1 == ~E_6~0); 380358#L1431-1 assume !(1 == ~E_7~0); 380356#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 380354#L1441-1 assume !(1 == ~E_9~0); 380352#L1446-1 assume !(1 == ~E_10~0); 380350#L1451-1 assume !(1 == ~E_11~0); 380347#L1456-1 assume !(1 == ~E_12~0); 380342#L1807-1 [2021-11-02 23:17:17,497 INFO L793 eck$LassoCheckResult]: Loop: 380342#L1807-1 assume !false; 378778#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 378775#L1173 assume !false; 378774#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 378770#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 378760#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 378759#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 378757#L1000 assume !(0 != eval_~tmp~0); 378758#L1188 start_simulation_~kernel_st~0 := 2; 382668#L838-1 start_simulation_~kernel_st~0 := 3; 382663#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 382656#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 382605#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 382599#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 382593#L1213-3 assume !(0 == ~T4_E~0); 382587#L1218-3 assume !(0 == ~T5_E~0); 382582#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 382532#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 382525#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 382517#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 382511#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 382505#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 382500#L1253-3 assume !(0 == ~T12_E~0); 382494#L1258-3 assume !(0 == ~E_M~0); 382487#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 382480#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 382473#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 382466#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 382460#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 382454#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 382447#L1293-3 assume !(0 == ~E_7~0); 382440#L1298-3 assume !(0 == ~E_8~0); 382433#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 382426#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 382418#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 382413#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 382390#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 382388#L590-42 assume !(1 == ~m_pc~0); 382386#L590-44 is_master_triggered_~__retres1~0 := 0; 382383#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 382381#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 382379#L1489-42 assume !(0 != activate_threads_~tmp~1); 382377#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 382375#L609-42 assume !(1 == ~t1_pc~0); 382373#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 382370#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 382368#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 382366#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 382364#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 381969#L628-42 assume !(1 == ~t2_pc~0); 381968#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 381967#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 381966#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 381965#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 381964#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 381963#L647-42 assume 1 == ~t3_pc~0; 381961#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 381960#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 381959#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 381958#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 381957#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 381956#L666-42 assume !(1 == ~t4_pc~0); 381955#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 381954#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 381953#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 381952#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 381951#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 381950#L685-42 assume !(1 == ~t5_pc~0); 377501#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 381949#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 381948#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 381947#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 381946#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 381945#L704-42 assume 1 == ~t6_pc~0; 381943#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 381941#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 381939#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 381937#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 381925#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 381924#L723-42 assume !(1 == ~t7_pc~0); 381922#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 381921#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 381920#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 381919#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 380536#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 380534#L742-42 assume 1 == ~t8_pc~0; 380531#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 380528#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 380526#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 380524#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 380522#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 380520#L761-42 assume 1 == ~t9_pc~0; 380517#L762-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 380514#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 380512#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 380510#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 380508#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 380506#L780-42 assume 1 == ~t10_pc~0; 380503#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 380500#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 380498#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 380496#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 380494#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 380492#L799-42 assume !(1 == ~t11_pc~0); 380489#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 380486#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 380484#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 380482#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 380480#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 380478#L818-42 assume !(1 == ~t12_pc~0); 380476#L818-44 is_transmit12_triggered_~__retres1~12 := 0; 380472#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 380470#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 380468#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 380466#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 380464#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 380462#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 380459#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 380457#L1351-3 assume !(1 == ~T4_E~0); 380455#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 380453#L1361-3 assume !(1 == ~T6_E~0); 380451#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 380449#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 380445#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 380443#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 380441#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 380439#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 380435#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 380433#L1401-3 assume !(1 == ~E_1~0); 380429#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 380427#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 380425#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 380423#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 380419#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 380417#L1431-3 assume !(1 == ~E_7~0); 380415#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 380413#L1441-3 assume !(1 == ~E_9~0); 380411#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 380409#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 380407#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 380405#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 380400#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 380387#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 380385#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 380383#L1826 assume !(0 == start_simulation_~tmp~3); 380381#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 380366#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 380357#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 380355#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 380353#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 380351#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 380349#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 380348#L1839 assume !(0 != start_simulation_~tmp___0~1); 380342#L1807-1 [2021-11-02 23:17:17,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:17,498 INFO L85 PathProgramCache]: Analyzing trace with hash -2122227010, now seen corresponding path program 1 times [2021-11-02 23:17:17,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:17,499 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145926945] [2021-11-02 23:17:17,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:17,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:17,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:17,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:17,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:17,550 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145926945] [2021-11-02 23:17:17,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145926945] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:17,551 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:17,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:17,551 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559994388] [2021-11-02 23:17:17,552 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:17,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:17,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1525983634, now seen corresponding path program 1 times [2021-11-02 23:17:17,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:17,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021675533] [2021-11-02 23:17:17,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:17,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:17,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:17,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:17,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:17,594 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021675533] [2021-11-02 23:17:17,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021675533] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:17,594 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:17,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:17,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018401560] [2021-11-02 23:17:17,595 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:17,595 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:17,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:17,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:17,596 INFO L87 Difference]: Start difference. First operand 45695 states and 65277 transitions. cyclomatic complexity: 19590 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:18,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:18,658 INFO L93 Difference]: Finished difference Result 110326 states and 156626 transitions. [2021-11-02 23:17:18,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:18,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110326 states and 156626 transitions. [2021-11-02 23:17:19,444 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 108480 [2021-11-02 23:17:19,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110326 states to 110326 states and 156626 transitions. [2021-11-02 23:17:19,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110326 [2021-11-02 23:17:19,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110326 [2021-11-02 23:17:19,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110326 states and 156626 transitions. [2021-11-02 23:17:19,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:19,956 INFO L681 BuchiCegarLoop]: Abstraction has 110326 states and 156626 transitions. [2021-11-02 23:17:20,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110326 states and 156626 transitions. [2021-11-02 23:17:21,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110326 to 87790. [2021-11-02 23:17:21,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87790 states, 87790 states have (on average 1.4235106504157649) internal successors, (124970), 87789 states have internal predecessors, (124970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:21,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87790 states to 87790 states and 124970 transitions. [2021-11-02 23:17:21,442 INFO L704 BuchiCegarLoop]: Abstraction has 87790 states and 124970 transitions. [2021-11-02 23:17:21,442 INFO L587 BuchiCegarLoop]: Abstraction has 87790 states and 124970 transitions. [2021-11-02 23:17:21,442 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-02 23:17:21,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87790 states and 124970 transitions. [2021-11-02 23:17:21,663 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 87520 [2021-11-02 23:17:21,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:21,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:21,667 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:21,667 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:21,668 INFO L791 eck$LassoCheckResult]: Stem: 514468#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 514469#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 515495#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 515496#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 515436#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 515252#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 515253#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 513829#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 513830#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 515010#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 515011#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515189#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 514484#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 514415#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 514045#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 514046#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 514186#L905-1 assume !(0 == ~M_E~0); 514187#L1198-1 assume !(0 == ~T1_E~0); 514755#L1203-1 assume !(0 == ~T2_E~0); 514756#L1208-1 assume !(0 == ~T3_E~0); 515390#L1213-1 assume !(0 == ~T4_E~0); 515519#L1218-1 assume !(0 == ~T5_E~0); 513690#L1223-1 assume !(0 == ~T6_E~0); 513691#L1228-1 assume !(0 == ~T7_E~0); 515357#L1233-1 assume !(0 == ~T8_E~0); 515093#L1238-1 assume !(0 == ~T9_E~0); 515094#L1243-1 assume !(0 == ~T10_E~0); 515487#L1248-1 assume !(0 == ~T11_E~0); 515494#L1253-1 assume !(0 == ~T12_E~0); 514817#L1258-1 assume !(0 == ~E_M~0); 514529#L1263-1 assume !(0 == ~E_1~0); 514530#L1268-1 assume !(0 == ~E_2~0); 514860#L1273-1 assume !(0 == ~E_3~0); 515444#L1278-1 assume !(0 == ~E_4~0); 515310#L1283-1 assume !(0 == ~E_5~0); 515311#L1288-1 assume !(0 == ~E_6~0); 515541#L1293-1 assume !(0 == ~E_7~0); 515529#L1298-1 assume !(0 == ~E_8~0); 515451#L1303-1 assume !(0 == ~E_9~0); 514051#L1308-1 assume !(0 == ~E_10~0); 513982#L1313-1 assume !(0 == ~E_11~0); 513983#L1318-1 assume !(0 == ~E_12~0); 513986#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 513987#L590 assume !(1 == ~m_pc~0); 514271#L590-2 is_master_triggered_~__retres1~0 := 0; 514272#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 514498#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 514361#L1489 assume !(0 != activate_threads_~tmp~1); 514362#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 515141#L609 assume !(1 == ~t1_pc~0); 515124#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 514899#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 513739#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 513740#L1497 assume !(0 != activate_threads_~tmp___0~0); 515525#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 515629#L628 assume !(1 == ~t2_pc~0); 515423#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 515025#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 514866#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 514867#L1505 assume !(0 != activate_threads_~tmp___1~0); 514890#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 514668#L647 assume !(1 == ~t3_pc~0); 514094#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 514093#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 514343#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 514344#L1513 assume !(0 != activate_threads_~tmp___2~0); 514928#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 514929#L666 assume !(1 == ~t4_pc~0); 515509#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 514103#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 514104#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 515526#L1521 assume !(0 != activate_threads_~tmp___3~0); 515582#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 515583#L685 assume !(1 == ~t5_pc~0); 515119#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 515120#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 514720#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 514095#L1529 assume !(0 != activate_threads_~tmp___4~0); 514096#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 514374#L704 assume !(1 == ~t6_pc~0); 514375#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 514850#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 514851#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 515282#L1537 assume !(0 != activate_threads_~tmp___5~0); 514454#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 514455#L723 assume !(1 == ~t7_pc~0); 514833#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 515031#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 515194#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 515477#L1545 assume !(0 != activate_threads_~tmp___6~0); 514960#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 514144#L742 assume !(1 == ~t8_pc~0); 514145#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 514296#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 514297#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 514983#L1553 assume !(0 != activate_threads_~tmp___7~0); 515190#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 514226#L761 assume !(1 == ~t9_pc~0); 514227#L761-2 is_transmit9_triggered_~__retres1~9 := 0; 514101#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 514102#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 515312#L1561 assume !(0 != activate_threads_~tmp___8~0); 514346#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 513908#L780 assume !(1 == ~t10_pc~0); 513909#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 514127#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 514128#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 514993#L1569 assume !(0 != activate_threads_~tmp___9~0); 515106#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 515416#L799 assume 1 == ~t11_pc~0; 515000#L800 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 513911#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 513912#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 514919#L1577 assume !(0 != activate_threads_~tmp___10~0); 514054#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 514055#L818 assume !(1 == ~t12_pc~0); 513696#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 513697#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 514991#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 515581#L1585 assume !(0 != activate_threads_~tmp___11~0); 515646#L1585-2 assume !(1 == ~M_E~0); 513655#L1336-1 assume !(1 == ~T1_E~0); 513656#L1341-1 assume !(1 == ~T2_E~0); 513716#L1346-1 assume !(1 == ~T3_E~0); 513717#L1351-1 assume !(1 == ~T4_E~0); 514019#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 514020#L1361-1 assume !(1 == ~T6_E~0); 515538#L1366-1 assume !(1 == ~T7_E~0); 514064#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 514065#L1376-1 assume !(1 == ~T9_E~0); 515453#L1381-1 assume !(1 == ~T10_E~0); 515579#L1386-1 assume !(1 == ~T11_E~0); 515580#L1391-1 assume !(1 == ~T12_E~0); 515597#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 515598#L1401-1 assume !(1 == ~E_1~0); 515349#L1406-1 assume !(1 == ~E_2~0); 515350#L1411-1 assume !(1 == ~E_3~0); 515561#L1416-1 assume !(1 == ~E_4~0); 515562#L1421-1 assume !(1 == ~E_5~0); 514196#L1426-1 assume !(1 == ~E_6~0); 514197#L1431-1 assume !(1 == ~E_7~0); 513769#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 513770#L1441-1 assume !(1 == ~E_9~0); 514521#L1446-1 assume !(1 == ~E_10~0); 514522#L1451-1 assume !(1 == ~E_11~0); 515255#L1456-1 assume !(1 == ~E_12~0); 515256#L1807-1 [2021-11-02 23:17:21,669 INFO L793 eck$LassoCheckResult]: Loop: 515256#L1807-1 assume !false; 588887#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 588884#L1173 assume !false; 588882#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 588742#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 588731#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 588729#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 588726#L1000 assume !(0 != eval_~tmp~0); 588727#L1188 start_simulation_~kernel_st~0 := 2; 600979#L838-1 start_simulation_~kernel_st~0 := 3; 600977#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 600975#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 600973#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 600971#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 600969#L1213-3 assume !(0 == ~T4_E~0); 600967#L1218-3 assume !(0 == ~T5_E~0); 600965#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 600962#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 600960#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 600958#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 600956#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 600954#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 600953#L1253-3 assume !(0 == ~T12_E~0); 600952#L1258-3 assume !(0 == ~E_M~0); 600951#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 600949#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 600947#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 600945#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 600943#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 600941#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 600939#L1293-3 assume !(0 == ~E_7~0); 600937#L1298-3 assume !(0 == ~E_8~0); 600934#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 600932#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 600930#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 600928#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 600926#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 600924#L590-42 assume !(1 == ~m_pc~0); 600923#L590-44 is_master_triggered_~__retres1~0 := 0; 600922#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 600919#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 600917#L1489-42 assume !(0 != activate_threads_~tmp~1); 600903#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 600891#L609-42 assume !(1 == ~t1_pc~0); 600889#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 600886#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 600883#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 600881#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 600879#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 514887#L628-42 assume !(1 == ~t2_pc~0); 514888#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 600387#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 600386#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 600384#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 600382#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 600380#L647-42 assume 1 == ~t3_pc~0; 600377#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 600374#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 600372#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 600370#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 600368#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 600366#L666-42 assume !(1 == ~t4_pc~0); 600364#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 600362#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 600360#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 600358#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 515399#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 515400#L685-42 assume !(1 == ~t5_pc~0); 589801#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 589798#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 589796#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 589794#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 589792#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 589770#L704-42 assume !(1 == ~t6_pc~0); 589768#L704-44 is_transmit6_triggered_~__retres1~6 := 0; 589766#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 589752#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 589750#L1537-42 assume !(0 != activate_threads_~tmp___5~0); 589746#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 589744#L723-42 assume !(1 == ~t7_pc~0); 589741#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 589739#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 589737#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 589735#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 589733#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 589730#L742-42 assume !(1 == ~t8_pc~0); 589726#L742-44 is_transmit8_triggered_~__retres1~8 := 0; 589724#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 589722#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 589720#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 589719#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 589717#L761-42 assume !(1 == ~t9_pc~0); 531555#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 589714#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 589712#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 589710#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 589707#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 589705#L780-42 assume 1 == ~t10_pc~0; 589672#L781-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 589664#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 589658#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 589647#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 589578#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 589577#L799-42 assume 1 == ~t11_pc~0; 589576#L800-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 589573#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 589571#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 589569#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 589567#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 589565#L818-42 assume 1 == ~t12_pc~0; 589562#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 589560#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 589559#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 589558#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 589556#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 589554#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 589552#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 589550#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 589548#L1351-3 assume !(1 == ~T4_E~0); 589546#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 589544#L1361-3 assume !(1 == ~T6_E~0); 589542#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 589540#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 586408#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 589536#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 589534#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 589486#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 586370#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 589377#L1401-3 assume !(1 == ~E_1~0); 589374#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 589372#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 589370#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 589368#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 589366#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 589364#L1431-3 assume !(1 == ~E_7~0); 589339#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 589331#L1441-3 assume !(1 == ~E_9~0); 589323#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 589303#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 589299#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 589295#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 589138#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 589119#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 589040#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 589033#L1826 assume !(0 == start_simulation_~tmp~3); 589029#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 588947#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 588938#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 588936#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 588933#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 588931#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 588929#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 588901#L1839 assume !(0 != start_simulation_~tmp___0~1); 515256#L1807-1 [2021-11-02 23:17:21,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:21,670 INFO L85 PathProgramCache]: Analyzing trace with hash -654023681, now seen corresponding path program 1 times [2021-11-02 23:17:21,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:21,670 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611933236] [2021-11-02 23:17:21,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:21,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:21,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:21,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:21,720 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:21,720 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611933236] [2021-11-02 23:17:21,720 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611933236] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:21,720 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:21,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:21,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309209755] [2021-11-02 23:17:21,721 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:21,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:21,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1461381265, now seen corresponding path program 1 times [2021-11-02 23:17:21,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:21,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955722010] [2021-11-02 23:17:21,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:21,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:21,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:21,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:21,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:21,763 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955722010] [2021-11-02 23:17:21,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955722010] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:21,763 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:21,764 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:21,764 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083741473] [2021-11-02 23:17:21,764 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:21,765 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:21,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:21,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:21,766 INFO L87 Difference]: Start difference. First operand 87790 states and 124970 transitions. cyclomatic complexity: 37188 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:23,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:23,389 INFO L93 Difference]: Finished difference Result 211117 states and 298711 transitions. [2021-11-02 23:17:23,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:23,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211117 states and 298711 transitions. [2021-11-02 23:17:24,901 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 207616 [2021-11-02 23:17:25,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211117 states to 211117 states and 298711 transitions. [2021-11-02 23:17:25,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211117 [2021-11-02 23:17:25,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211117 [2021-11-02 23:17:25,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211117 states and 298711 transitions. [2021-11-02 23:17:25,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:25,545 INFO L681 BuchiCegarLoop]: Abstraction has 211117 states and 298711 transitions. [2021-11-02 23:17:25,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211117 states and 298711 transitions. [2021-11-02 23:17:27,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211117 to 168621. [2021-11-02 23:17:28,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168621 states, 168621 states have (on average 1.4187971842178613) internal successors, (239239), 168620 states have internal predecessors, (239239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:28,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168621 states to 168621 states and 239239 transitions. [2021-11-02 23:17:28,410 INFO L704 BuchiCegarLoop]: Abstraction has 168621 states and 239239 transitions. [2021-11-02 23:17:28,410 INFO L587 BuchiCegarLoop]: Abstraction has 168621 states and 239239 transitions. [2021-11-02 23:17:28,410 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-02 23:17:28,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168621 states and 239239 transitions. [2021-11-02 23:17:28,858 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 168256 [2021-11-02 23:17:28,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:28,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:28,863 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:28,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:28,864 INFO L791 eck$LassoCheckResult]: Stem: 813398#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 813399#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 814486#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 814487#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 814404#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 814203#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 814204#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 812745#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 812746#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 813955#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 813956#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 814138#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 813415#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 813345#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 812967#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 812968#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 813106#L905-1 assume !(0 == ~M_E~0); 813107#L1198-1 assume !(0 == ~T1_E~0); 813689#L1203-1 assume !(0 == ~T2_E~0); 813690#L1208-1 assume !(0 == ~T3_E~0); 814353#L1213-1 assume !(0 == ~T4_E~0); 814515#L1218-1 assume !(0 == ~T5_E~0); 812607#L1223-1 assume !(0 == ~T6_E~0); 812608#L1228-1 assume !(0 == ~T7_E~0); 814324#L1233-1 assume !(0 == ~T8_E~0); 814032#L1238-1 assume !(0 == ~T9_E~0); 814033#L1243-1 assume !(0 == ~T10_E~0); 814475#L1248-1 assume !(0 == ~T11_E~0); 814485#L1253-1 assume !(0 == ~T12_E~0); 813755#L1258-1 assume !(0 == ~E_M~0); 813459#L1263-1 assume !(0 == ~E_1~0); 813460#L1268-1 assume !(0 == ~E_2~0); 813800#L1273-1 assume !(0 == ~E_3~0); 814417#L1278-1 assume !(0 == ~E_4~0); 814266#L1283-1 assume !(0 == ~E_5~0); 814267#L1288-1 assume !(0 == ~E_6~0); 814542#L1293-1 assume !(0 == ~E_7~0); 814526#L1298-1 assume !(0 == ~E_8~0); 814423#L1303-1 assume !(0 == ~E_9~0); 812974#L1308-1 assume !(0 == ~E_10~0); 812901#L1313-1 assume !(0 == ~E_11~0); 812902#L1318-1 assume !(0 == ~E_12~0); 812905#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812906#L590 assume !(1 == ~m_pc~0); 813194#L590-2 is_master_triggered_~__retres1~0 := 0; 813195#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 813429#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 813289#L1489 assume !(0 != activate_threads_~tmp~1); 813290#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 814085#L609 assume !(1 == ~t1_pc~0); 814064#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 813840#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 812655#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 812656#L1497 assume !(0 != activate_threads_~tmp___0~0); 814523#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 814647#L628 assume !(1 == ~t2_pc~0); 814388#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 813967#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 813807#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 813808#L1505 assume !(0 != activate_threads_~tmp___1~0); 813831#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 813600#L647 assume !(1 == ~t3_pc~0); 813015#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 813014#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 813270#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 813271#L1513 assume !(0 != activate_threads_~tmp___2~0); 813873#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 813874#L666 assume !(1 == ~t4_pc~0); 814502#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 813024#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 813025#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 814524#L1521 assume !(0 != activate_threads_~tmp___3~0); 814596#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 814597#L685 assume !(1 == ~t5_pc~0); 814059#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 814060#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 813652#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 813016#L1529 assume !(0 != activate_threads_~tmp___4~0); 813017#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 813303#L704 assume !(1 == ~t6_pc~0); 813304#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 813789#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 813790#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 814237#L1537 assume !(0 != activate_threads_~tmp___5~0); 813384#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 813385#L723 assume !(1 == ~t7_pc~0); 813771#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 813973#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 814143#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 814463#L1545 assume !(0 != activate_threads_~tmp___6~0); 813904#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 813065#L742 assume !(1 == ~t8_pc~0); 813066#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 813221#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 813222#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 813931#L1553 assume !(0 != activate_threads_~tmp___7~0); 814139#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 813146#L761 assume !(1 == ~t9_pc~0); 813147#L761-2 is_transmit9_triggered_~__retres1~9 := 0; 813022#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 813023#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 814268#L1561 assume !(0 != activate_threads_~tmp___8~0); 813273#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 812824#L780 assume !(1 == ~t10_pc~0); 812825#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 813048#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 813049#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 813940#L1569 assume !(0 != activate_threads_~tmp___9~0); 814047#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 814379#L799 assume !(1 == ~t11_pc~0); 813283#L799-2 is_transmit11_triggered_~__retres1~11 := 0; 812827#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 812828#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 813866#L1577 assume !(0 != activate_threads_~tmp___10~0); 812977#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 812978#L818 assume !(1 == ~t12_pc~0); 812613#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 812614#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 813937#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 814593#L1585 assume !(0 != activate_threads_~tmp___11~0); 814681#L1585-2 assume !(1 == ~M_E~0); 812572#L1336-1 assume !(1 == ~T1_E~0); 812573#L1341-1 assume !(1 == ~T2_E~0); 812633#L1346-1 assume !(1 == ~T3_E~0); 812634#L1351-1 assume !(1 == ~T4_E~0); 812940#L1356-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 812941#L1361-1 assume !(1 == ~T6_E~0); 814537#L1366-1 assume !(1 == ~T7_E~0); 812985#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 812986#L1376-1 assume !(1 == ~T9_E~0); 813804#L1381-1 assume !(1 == ~T10_E~0); 813805#L1386-1 assume !(1 == ~T11_E~0); 814639#L1391-1 assume !(1 == ~T12_E~0); 814640#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 813685#L1401-1 assume !(1 == ~E_1~0); 813686#L1406-1 assume !(1 == ~E_2~0); 813968#L1411-1 assume !(1 == ~E_3~0); 813969#L1416-1 assume !(1 == ~E_4~0); 813620#L1421-1 assume !(1 == ~E_5~0); 813621#L1426-1 assume !(1 == ~E_6~0); 814132#L1431-1 assume !(1 == ~E_7~0); 814133#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 813841#L1441-1 assume !(1 == ~E_9~0); 813842#L1446-1 assume !(1 == ~E_10~0); 814641#L1451-1 assume !(1 == ~E_11~0); 814642#L1456-1 assume !(1 == ~E_12~0); 884639#L1807-1 [2021-11-02 23:17:28,865 INFO L793 eck$LassoCheckResult]: Loop: 884639#L1807-1 assume !false; 884630#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 884623#L1173 assume !false; 884621#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 884412#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 884396#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 884390#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 884383#L1000 assume !(0 != eval_~tmp~0); 884384#L1188 start_simulation_~kernel_st~0 := 2; 894957#L838-1 start_simulation_~kernel_st~0 := 3; 894956#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 894955#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 894954#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 894953#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 894952#L1213-3 assume !(0 == ~T4_E~0); 894951#L1218-3 assume !(0 == ~T5_E~0); 894950#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 894949#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 894948#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 894947#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 894946#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 894945#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 894944#L1253-3 assume !(0 == ~T12_E~0); 894943#L1258-3 assume !(0 == ~E_M~0); 894942#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 894941#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 894940#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 894939#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 894938#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 894937#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 894936#L1293-3 assume !(0 == ~E_7~0); 894935#L1298-3 assume !(0 == ~E_8~0); 894934#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 894932#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 894930#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 894928#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 894926#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 894924#L590-42 assume !(1 == ~m_pc~0); 894922#L590-44 is_master_triggered_~__retres1~0 := 0; 894919#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 894915#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 894912#L1489-42 assume !(0 != activate_threads_~tmp~1); 894909#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 894906#L609-42 assume !(1 == ~t1_pc~0); 894903#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 894900#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 894897#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 894895#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 894892#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 886706#L628-42 assume !(1 == ~t2_pc~0); 886655#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 886649#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 886642#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 886636#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 886627#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 886621#L647-42 assume 1 == ~t3_pc~0; 886613#L648-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 886608#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 886606#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 886605#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 886604#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 886603#L666-42 assume !(1 == ~t4_pc~0); 886601#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 886599#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 886597#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 886595#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 886593#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 886591#L685-42 assume !(1 == ~t5_pc~0); 872665#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 886587#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 886586#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 886585#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 886584#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 886583#L704-42 assume 1 == ~t6_pc~0; 886581#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 886579#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 886558#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 886551#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 886543#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 886392#L723-42 assume !(1 == ~t7_pc~0); 886388#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 886386#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 886384#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 886382#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 886380#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 886378#L742-42 assume 1 == ~t8_pc~0; 886229#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 886225#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 886223#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 886221#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 886219#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 886217#L761-42 assume !(1 == ~t9_pc~0); 884004#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 886206#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 886197#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 885634#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 885631#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 885629#L780-42 assume !(1 == ~t10_pc~0); 885627#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 885624#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 885622#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 885620#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 885619#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 885617#L799-42 assume !(1 == ~t11_pc~0); 838717#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 885614#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 885612#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 885296#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 885295#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 885294#L818-42 assume !(1 == ~t12_pc~0); 885292#L818-44 is_transmit12_triggered_~__retres1~12 := 0; 885289#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 885287#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 885285#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 885283#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 885281#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 885279#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 885277#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 885273#L1351-3 assume !(1 == ~T4_E~0); 885270#L1356-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 885266#L1361-3 assume !(1 == ~T6_E~0); 885261#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 885241#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 885233#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 885228#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 885223#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 885218#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 885211#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 885204#L1401-3 assume !(1 == ~E_1~0); 885197#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 885192#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 885186#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 885181#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 885164#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 885159#L1431-3 assume !(1 == ~E_7~0); 885145#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 885139#L1441-3 assume !(1 == ~E_9~0); 885131#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 885125#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 885121#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 885117#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 884982#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 884965#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 884962#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 884958#L1826 assume !(0 == start_simulation_~tmp~3); 884954#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 884741#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 884732#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 884731#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 884730#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 884729#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 884725#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 884667#L1839 assume !(0 != start_simulation_~tmp___0~1); 884639#L1807-1 [2021-11-02 23:17:28,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:28,866 INFO L85 PathProgramCache]: Analyzing trace with hash 471236288, now seen corresponding path program 1 times [2021-11-02 23:17:28,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:28,866 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103804467] [2021-11-02 23:17:28,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:28,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:28,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:28,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:28,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:28,916 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103804467] [2021-11-02 23:17:28,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103804467] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:28,916 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:28,916 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:28,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525785550] [2021-11-02 23:17:28,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:28,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:28,918 INFO L85 PathProgramCache]: Analyzing trace with hash -941507184, now seen corresponding path program 1 times [2021-11-02 23:17:28,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:28,918 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826039668] [2021-11-02 23:17:28,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:28,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:29,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:29,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:29,632 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:29,632 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826039668] [2021-11-02 23:17:29,632 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826039668] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:29,632 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:29,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:29,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144506613] [2021-11-02 23:17:29,633 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:29,633 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:29,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:29,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:29,648 INFO L87 Difference]: Start difference. First operand 168621 states and 239239 transitions. cyclomatic complexity: 70626 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:30,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:30,286 INFO L93 Difference]: Finished difference Result 168621 states and 238853 transitions. [2021-11-02 23:17:30,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:30,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168621 states and 238853 transitions. [2021-11-02 23:17:30,926 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 168256 [2021-11-02 23:17:32,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168621 states to 168621 states and 238853 transitions. [2021-11-02 23:17:32,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168621 [2021-11-02 23:17:32,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168621 [2021-11-02 23:17:32,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168621 states and 238853 transitions. [2021-11-02 23:17:32,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:32,244 INFO L681 BuchiCegarLoop]: Abstraction has 168621 states and 238853 transitions. [2021-11-02 23:17:32,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168621 states and 238853 transitions. [2021-11-02 23:17:33,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168621 to 168621. [2021-11-02 23:17:34,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168621 states, 168621 states have (on average 1.4165080268768422) internal successors, (238853), 168620 states have internal predecessors, (238853), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:34,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168621 states to 168621 states and 238853 transitions. [2021-11-02 23:17:34,519 INFO L704 BuchiCegarLoop]: Abstraction has 168621 states and 238853 transitions. [2021-11-02 23:17:34,519 INFO L587 BuchiCegarLoop]: Abstraction has 168621 states and 238853 transitions. [2021-11-02 23:17:34,519 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-02 23:17:34,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168621 states and 238853 transitions. [2021-11-02 23:17:35,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 168256 [2021-11-02 23:17:35,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:35,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:35,827 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:35,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:35,828 INFO L791 eck$LassoCheckResult]: Stem: 1150643#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1150644#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1151707#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1151708#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 1151623#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1151435#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1151436#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1149995#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1149996#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1151181#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1151182#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1151363#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1150658#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1150586#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1150217#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1150218#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1150353#L905-1 assume !(0 == ~M_E~0); 1150354#L1198-1 assume !(0 == ~T1_E~0); 1150925#L1203-1 assume !(0 == ~T2_E~0); 1150926#L1208-1 assume !(0 == ~T3_E~0); 1151576#L1213-1 assume !(0 == ~T4_E~0); 1151733#L1218-1 assume !(0 == ~T5_E~0); 1149856#L1223-1 assume !(0 == ~T6_E~0); 1149857#L1228-1 assume !(0 == ~T7_E~0); 1151546#L1233-1 assume !(0 == ~T8_E~0); 1151263#L1238-1 assume !(0 == ~T9_E~0); 1151264#L1243-1 assume !(0 == ~T10_E~0); 1151693#L1248-1 assume !(0 == ~T11_E~0); 1151706#L1253-1 assume !(0 == ~T12_E~0); 1150985#L1258-1 assume !(0 == ~E_M~0); 1150699#L1263-1 assume !(0 == ~E_1~0); 1150700#L1268-1 assume !(0 == ~E_2~0); 1151028#L1273-1 assume !(0 == ~E_3~0); 1151632#L1278-1 assume !(0 == ~E_4~0); 1151486#L1283-1 assume !(0 == ~E_5~0); 1151487#L1288-1 assume !(0 == ~E_6~0); 1151759#L1293-1 assume !(0 == ~E_7~0); 1151746#L1298-1 assume !(0 == ~E_8~0); 1151643#L1303-1 assume !(0 == ~E_9~0); 1150220#L1308-1 assume !(0 == ~E_10~0); 1150151#L1313-1 assume !(0 == ~E_11~0); 1150152#L1318-1 assume !(0 == ~E_12~0); 1150159#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1150160#L590 assume !(1 == ~m_pc~0); 1150436#L590-2 is_master_triggered_~__retres1~0 := 0; 1150437#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1150676#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1150530#L1489 assume !(0 != activate_threads_~tmp~1); 1150531#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1151315#L609 assume !(1 == ~t1_pc~0); 1151293#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 1151067#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1149907#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1149908#L1497 assume !(0 != activate_threads_~tmp___0~0); 1151742#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1151858#L628 assume !(1 == ~t2_pc~0); 1151611#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 1151193#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1151035#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1151036#L1505 assume !(0 != activate_threads_~tmp___1~0); 1151058#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1150840#L647 assume !(1 == ~t3_pc~0); 1150262#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 1150261#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1150513#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1150514#L1513 assume !(0 != activate_threads_~tmp___2~0); 1151094#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1151095#L666 assume !(1 == ~t4_pc~0); 1151727#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 1150271#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1150272#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1151744#L1521 assume !(0 != activate_threads_~tmp___3~0); 1151808#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1151809#L685 assume !(1 == ~t5_pc~0); 1151290#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 1151291#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1150891#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1150263#L1529 assume !(0 != activate_threads_~tmp___4~0); 1150264#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1150547#L704 assume !(1 == ~t6_pc~0); 1150548#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 1151017#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1151018#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1151461#L1537 assume !(0 != activate_threads_~tmp___5~0); 1150626#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1150627#L723 assume !(1 == ~t7_pc~0); 1150999#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 1151199#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1151368#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1151682#L1545 assume !(0 != activate_threads_~tmp___6~0); 1151128#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1150313#L742 assume !(1 == ~t8_pc~0); 1150314#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 1150467#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1150468#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1151154#L1553 assume !(0 != activate_threads_~tmp___7~0); 1151364#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1150395#L761 assume !(1 == ~t9_pc~0); 1150396#L761-2 is_transmit9_triggered_~__retres1~9 := 0; 1150269#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1150270#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1151488#L1561 assume !(0 != activate_threads_~tmp___8~0); 1150515#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1150076#L780 assume !(1 == ~t10_pc~0); 1150077#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 1150296#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1150297#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1151165#L1569 assume !(0 != activate_threads_~tmp___9~0); 1151276#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1151603#L799 assume !(1 == ~t11_pc~0); 1150524#L799-2 is_transmit11_triggered_~__retres1~11 := 0; 1150079#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1150080#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1151087#L1577 assume !(0 != activate_threads_~tmp___10~0); 1150223#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1150224#L818 assume !(1 == ~t12_pc~0); 1149864#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 1149865#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1151162#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1151805#L1585 assume !(0 != activate_threads_~tmp___11~0); 1151885#L1585-2 assume !(1 == ~M_E~0); 1149821#L1336-1 assume !(1 == ~T1_E~0); 1149822#L1341-1 assume !(1 == ~T2_E~0); 1149882#L1346-1 assume !(1 == ~T3_E~0); 1149883#L1351-1 assume !(1 == ~T4_E~0); 1150189#L1356-1 assume !(1 == ~T5_E~0); 1150190#L1361-1 assume !(1 == ~T6_E~0); 1151754#L1366-1 assume !(1 == ~T7_E~0); 1150233#L1371-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1150234#L1376-1 assume !(1 == ~T9_E~0); 1151032#L1381-1 assume !(1 == ~T10_E~0); 1151033#L1386-1 assume !(1 == ~T11_E~0); 1151804#L1391-1 assume !(1 == ~T12_E~0); 1151831#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 1150920#L1401-1 assume !(1 == ~E_1~0); 1150921#L1406-1 assume !(1 == ~E_2~0); 1151194#L1411-1 assume !(1 == ~E_3~0); 1151195#L1416-1 assume !(1 == ~E_4~0); 1150859#L1421-1 assume !(1 == ~E_5~0); 1150365#L1426-1 assume !(1 == ~E_6~0); 1150366#L1431-1 assume !(1 == ~E_7~0); 1149937#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1149938#L1441-1 assume !(1 == ~E_9~0); 1150692#L1446-1 assume !(1 == ~E_10~0); 1150693#L1451-1 assume !(1 == ~E_11~0); 1151437#L1456-1 assume !(1 == ~E_12~0); 1151438#L1807-1 [2021-11-02 23:17:35,830 INFO L793 eck$LassoCheckResult]: Loop: 1151438#L1807-1 assume !false; 1257164#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 1257161#L1173 assume !false; 1257160#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1257156#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1257146#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1257144#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1257140#L1000 assume !(0 != eval_~tmp~0); 1257141#L1188 start_simulation_~kernel_st~0 := 2; 1311035#L838-1 start_simulation_~kernel_st~0 := 3; 1311034#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1311033#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1311031#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1311029#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1311027#L1213-3 assume !(0 == ~T4_E~0); 1311024#L1218-3 assume !(0 == ~T5_E~0); 1311022#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1311020#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1311018#L1233-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1311016#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1311014#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1311011#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1311009#L1253-3 assume !(0 == ~T12_E~0); 1311007#L1258-3 assume !(0 == ~E_M~0); 1311005#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1311003#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1311001#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1310998#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1310996#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1310994#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1310992#L1293-3 assume !(0 == ~E_7~0); 1310990#L1298-3 assume !(0 == ~E_8~0); 1310899#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1310898#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1310897#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1310896#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1310895#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1310894#L590-42 assume !(1 == ~m_pc~0); 1310892#L590-44 is_master_triggered_~__retres1~0 := 0; 1310890#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1310887#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1310888#L1489-42 assume !(0 != activate_threads_~tmp~1); 1318344#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1318342#L609-42 assume 1 == ~t1_pc~0; 1318338#L610-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1318337#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1318336#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1318335#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1318334#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1305580#L628-42 assume !(1 == ~t2_pc~0); 1305578#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 1305576#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1305573#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1305571#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1305569#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1305567#L647-42 assume !(1 == ~t3_pc~0); 1305565#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 1305562#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1305559#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1305557#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1305555#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1305553#L666-42 assume !(1 == ~t4_pc~0); 1305551#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 1305546#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1305545#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1305542#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1305540#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1302123#L685-42 assume !(1 == ~t5_pc~0); 1302122#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 1302121#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1302119#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1302118#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1302117#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1302113#L704-42 assume 1 == ~t6_pc~0; 1302114#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1302115#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1302120#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1302103#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1302101#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1302099#L723-42 assume !(1 == ~t7_pc~0); 1302095#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 1302093#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1302091#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1302089#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1302087#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1302085#L742-42 assume 1 == ~t8_pc~0; 1302082#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1302079#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1302077#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1302075#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1302073#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1302071#L761-42 assume !(1 == ~t9_pc~0); 1262374#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 1302067#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1302065#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1302063#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 1302061#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1302059#L780-42 assume !(1 == ~t10_pc~0); 1302057#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 1302054#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1302052#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1302050#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1302048#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1262812#L799-42 assume !(1 == ~t11_pc~0); 1262811#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 1262810#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1262809#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1262808#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1262807#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1262806#L818-42 assume 1 == ~t12_pc~0; 1262803#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1262801#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1262799#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1262797#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1262795#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 1262793#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1262791#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1262788#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1262786#L1351-3 assume !(1 == ~T4_E~0); 1262784#L1356-3 assume !(1 == ~T5_E~0); 1262782#L1361-3 assume !(1 == ~T6_E~0); 1262780#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1262778#L1371-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1174685#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1262775#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1262773#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1262771#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1174676#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1262768#L1401-3 assume !(1 == ~E_1~0); 1262766#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1262765#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1262763#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1262761#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1262759#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1262758#L1431-3 assume !(1 == ~E_7~0); 1262756#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1262754#L1441-3 assume !(1 == ~E_9~0); 1262752#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1262750#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1262748#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1262746#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1262741#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1262728#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1262726#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 1262724#L1826 assume !(0 == start_simulation_~tmp~3); 1262722#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1262710#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1262701#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1262698#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 1262696#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1262694#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 1262692#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1262691#L1839 assume !(0 != start_simulation_~tmp___0~1); 1151438#L1807-1 [2021-11-02 23:17:35,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:35,841 INFO L85 PathProgramCache]: Analyzing trace with hash 893938114, now seen corresponding path program 1 times [2021-11-02 23:17:35,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:35,842 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641106799] [2021-11-02 23:17:35,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:35,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:35,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:35,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:35,939 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:35,940 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641106799] [2021-11-02 23:17:35,940 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641106799] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:35,940 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:35,940 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:17:35,940 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390079976] [2021-11-02 23:17:35,941 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:35,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:35,946 INFO L85 PathProgramCache]: Analyzing trace with hash 353444399, now seen corresponding path program 1 times [2021-11-02 23:17:35,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:35,946 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352455163] [2021-11-02 23:17:35,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:35,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:35,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:36,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:36,009 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:36,010 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352455163] [2021-11-02 23:17:36,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352455163] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:36,010 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:36,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:36,011 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103613199] [2021-11-02 23:17:36,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:36,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:36,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:17:36,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:17:36,012 INFO L87 Difference]: Start difference. First operand 168621 states and 238853 transitions. cyclomatic complexity: 70240 Second operand has 3 states, 3 states have (on average 48.666666666666664) internal successors, (146), 2 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:36,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:36,615 INFO L93 Difference]: Finished difference Result 168617 states and 238524 transitions. [2021-11-02 23:17:36,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:17:36,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168617 states and 238524 transitions. [2021-11-02 23:17:37,282 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 168256 [2021-11-02 23:17:38,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168617 states to 168617 states and 238524 transitions. [2021-11-02 23:17:38,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168617 [2021-11-02 23:17:38,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168617 [2021-11-02 23:17:38,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168617 states and 238524 transitions. [2021-11-02 23:17:38,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:38,646 INFO L681 BuchiCegarLoop]: Abstraction has 168617 states and 238524 transitions. [2021-11-02 23:17:38,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168617 states and 238524 transitions. [2021-11-02 23:17:39,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168617 to 84380. [2021-11-02 23:17:39,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84380 states, 84380 states have (on average 1.4145887651102156) internal successors, (119363), 84379 states have internal predecessors, (119363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:40,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84380 states to 84380 states and 119363 transitions. [2021-11-02 23:17:40,384 INFO L704 BuchiCegarLoop]: Abstraction has 84380 states and 119363 transitions. [2021-11-02 23:17:40,384 INFO L587 BuchiCegarLoop]: Abstraction has 84380 states and 119363 transitions. [2021-11-02 23:17:40,384 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-02 23:17:40,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84380 states and 119363 transitions. [2021-11-02 23:17:40,592 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 84128 [2021-11-02 23:17:40,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:40,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:40,595 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:40,595 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:40,596 INFO L791 eck$LassoCheckResult]: Stem: 1487894#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1487895#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1488971#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1488972#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 1488897#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1488687#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1488688#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1487239#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1487240#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1488438#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1488439#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1488617#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1487910#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1487840#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1487454#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1487455#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1487593#L905-1 assume !(0 == ~M_E~0); 1487594#L1198-1 assume !(0 == ~T1_E~0); 1488187#L1203-1 assume !(0 == ~T2_E~0); 1488188#L1208-1 assume !(0 == ~T3_E~0); 1488841#L1213-1 assume !(0 == ~T4_E~0); 1488995#L1218-1 assume !(0 == ~T5_E~0); 1487101#L1223-1 assume !(0 == ~T6_E~0); 1487102#L1228-1 assume !(0 == ~T7_E~0); 1488811#L1233-1 assume !(0 == ~T8_E~0); 1488521#L1238-1 assume !(0 == ~T9_E~0); 1488522#L1243-1 assume !(0 == ~T10_E~0); 1488959#L1248-1 assume !(0 == ~T11_E~0); 1488970#L1253-1 assume !(0 == ~T12_E~0); 1488248#L1258-1 assume !(0 == ~E_M~0); 1487955#L1263-1 assume !(0 == ~E_1~0); 1487956#L1268-1 assume !(0 == ~E_2~0); 1488290#L1273-1 assume !(0 == ~E_3~0); 1488907#L1278-1 assume !(0 == ~E_4~0); 1488752#L1283-1 assume !(0 == ~E_5~0); 1488753#L1288-1 assume !(0 == ~E_6~0); 1489022#L1293-1 assume !(0 == ~E_7~0); 1489005#L1298-1 assume !(0 == ~E_8~0); 1488915#L1303-1 assume !(0 == ~E_9~0); 1487460#L1308-1 assume !(0 == ~E_10~0); 1487391#L1313-1 assume !(0 == ~E_11~0); 1487392#L1318-1 assume !(0 == ~E_12~0); 1487395#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1487396#L590 assume !(1 == ~m_pc~0); 1487681#L590-2 is_master_triggered_~__retres1~0 := 0; 1487682#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1487925#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1487781#L1489 assume !(0 != activate_threads_~tmp~1); 1487782#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1488567#L609 assume !(1 == ~t1_pc~0); 1488550#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 1488329#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1487149#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1487150#L1497 assume !(0 != activate_threads_~tmp___0~0); 1489003#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1489124#L628 assume !(1 == ~t2_pc~0); 1488883#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 1488451#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1488296#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1488297#L1505 assume !(0 != activate_threads_~tmp___1~0); 1488320#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1488099#L647 assume !(1 == ~t3_pc~0); 1487502#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 1487501#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1487759#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1487760#L1513 assume !(0 != activate_threads_~tmp___2~0); 1488355#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1488356#L666 assume !(1 == ~t4_pc~0); 1488984#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 1487511#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1487512#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1489004#L1521 assume !(0 != activate_threads_~tmp___3~0); 1489071#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1489072#L685 assume !(1 == ~t5_pc~0); 1488545#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 1488546#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1488153#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1487503#L1529 assume !(0 != activate_threads_~tmp___4~0); 1487504#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1487798#L704 assume !(1 == ~t6_pc~0); 1487799#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 1488279#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1488280#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1488723#L1537 assume !(0 != activate_threads_~tmp___5~0); 1487880#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1487881#L723 assume !(1 == ~t7_pc~0); 1488265#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 1488458#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1488622#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1488948#L1545 assume !(0 != activate_threads_~tmp___6~0); 1488389#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1487553#L742 assume !(1 == ~t8_pc~0); 1487554#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 1487708#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1487709#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1488412#L1553 assume !(0 != activate_threads_~tmp___7~0); 1488618#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1487634#L761 assume !(1 == ~t9_pc~0); 1487635#L761-2 is_transmit9_triggered_~__retres1~9 := 0; 1487509#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1487510#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1488754#L1561 assume !(0 != activate_threads_~tmp___8~0); 1487762#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1487317#L780 assume !(1 == ~t10_pc~0); 1487318#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 1487535#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1487536#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1488422#L1569 assume !(0 != activate_threads_~tmp___9~0); 1488534#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1488875#L799 assume !(1 == ~t11_pc~0); 1487775#L799-2 is_transmit11_triggered_~__retres1~11 := 0; 1487320#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1487321#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1488349#L1577 assume !(0 != activate_threads_~tmp___10~0); 1487463#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1487464#L818 assume !(1 == ~t12_pc~0); 1487107#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 1487108#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1488419#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1489070#L1585 assume !(0 != activate_threads_~tmp___11~0); 1489148#L1585-2 assume !(1 == ~M_E~0); 1487066#L1336-1 assume !(1 == ~T1_E~0); 1487067#L1341-1 assume !(1 == ~T2_E~0); 1487127#L1346-1 assume !(1 == ~T3_E~0); 1487128#L1351-1 assume !(1 == ~T4_E~0); 1487428#L1356-1 assume !(1 == ~T5_E~0); 1487429#L1361-1 assume !(1 == ~T6_E~0); 1489016#L1366-1 assume !(1 == ~T7_E~0); 1487473#L1371-1 assume !(1 == ~T8_E~0); 1487474#L1376-1 assume !(1 == ~T9_E~0); 1488293#L1381-1 assume !(1 == ~T10_E~0); 1488294#L1386-1 assume !(1 == ~T11_E~0); 1489069#L1391-1 assume !(1 == ~T12_E~0); 1489092#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 1488183#L1401-1 assume !(1 == ~E_1~0); 1488184#L1406-1 assume !(1 == ~E_2~0); 1488452#L1411-1 assume !(1 == ~E_3~0); 1488453#L1416-1 assume !(1 == ~E_4~0); 1488122#L1421-1 assume !(1 == ~E_5~0); 1487604#L1426-1 assume !(1 == ~E_6~0); 1487605#L1431-1 assume !(1 == ~E_7~0); 1487179#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1487180#L1441-1 assume !(1 == ~E_9~0); 1487947#L1446-1 assume !(1 == ~E_10~0); 1487948#L1451-1 assume !(1 == ~E_11~0); 1488690#L1456-1 assume !(1 == ~E_12~0); 1488691#L1807-1 [2021-11-02 23:17:40,596 INFO L793 eck$LassoCheckResult]: Loop: 1488691#L1807-1 assume !false; 1533110#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 1533107#L1173 assume !false; 1533106#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1533101#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1533090#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1533088#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1533085#L1000 assume !(0 != eval_~tmp~0); 1533086#L1188 start_simulation_~kernel_st~0 := 2; 1564383#L838-1 start_simulation_~kernel_st~0 := 3; 1564367#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1564366#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1564365#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1564364#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1564363#L1213-3 assume !(0 == ~T4_E~0); 1564362#L1218-3 assume !(0 == ~T5_E~0); 1564361#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1564359#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1564358#L1233-3 assume !(0 == ~T8_E~0); 1564357#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1564356#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1564354#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1564352#L1253-3 assume !(0 == ~T12_E~0); 1564350#L1258-3 assume !(0 == ~E_M~0); 1564348#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1564346#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1564344#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1564342#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1564340#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1564338#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1564336#L1293-3 assume !(0 == ~E_7~0); 1564334#L1298-3 assume !(0 == ~E_8~0); 1564332#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1564330#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1564328#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1564326#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1564324#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1564322#L590-42 assume !(1 == ~m_pc~0); 1564320#L590-44 is_master_triggered_~__retres1~0 := 0; 1564318#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1564316#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1564314#L1489-42 assume !(0 != activate_threads_~tmp~1); 1564312#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1564310#L609-42 assume !(1 == ~t1_pc~0); 1564308#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 1564305#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1564303#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1564301#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1564299#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1564297#L628-42 assume !(1 == ~t2_pc~0); 1564295#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 1564293#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1564291#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1564194#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1564100#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1564099#L647-42 assume !(1 == ~t3_pc~0); 1564098#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 1564096#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1564095#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1564094#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1564092#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1564090#L666-42 assume !(1 == ~t4_pc~0); 1564088#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 1564086#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1564084#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1564082#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1564080#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1561810#L685-42 assume !(1 == ~t5_pc~0); 1561809#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 1561808#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1561807#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1561805#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1561804#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1561801#L704-42 assume 1 == ~t6_pc~0; 1561802#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1561803#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1561806#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1561792#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1561790#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1561788#L723-42 assume !(1 == ~t7_pc~0); 1561785#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 1561783#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1561780#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1561778#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1561776#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1561774#L742-42 assume 1 == ~t8_pc~0; 1561772#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1561769#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1561768#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1561766#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1561764#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1561762#L761-42 assume !(1 == ~t9_pc~0); 1540471#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 1561759#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1561756#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1561754#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 1561752#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1561750#L780-42 assume !(1 == ~t10_pc~0); 1561748#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 1561745#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1561742#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1561740#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1561738#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1533499#L799-42 assume !(1 == ~t11_pc~0); 1533497#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 1533496#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1533492#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1533490#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1533488#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1533486#L818-42 assume !(1 == ~t12_pc~0); 1533483#L818-44 is_transmit12_triggered_~__retres1~12 := 0; 1533480#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1533477#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1533475#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1533473#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 1533471#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1533469#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1533467#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1533465#L1351-3 assume !(1 == ~T4_E~0); 1533462#L1356-3 assume !(1 == ~T5_E~0); 1533460#L1361-3 assume !(1 == ~T6_E~0); 1533458#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1533456#L1371-3 assume !(1 == ~T8_E~0); 1533454#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1533452#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1533451#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1533449#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1533447#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1533445#L1401-3 assume !(1 == ~E_1~0); 1533443#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1533441#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1533438#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1533436#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1533434#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1533432#L1431-3 assume !(1 == ~E_7~0); 1533430#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1533427#L1441-3 assume !(1 == ~E_9~0); 1533424#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1533422#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1533420#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1533418#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1533411#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1533398#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1533396#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 1533393#L1826 assume !(0 == start_simulation_~tmp~3); 1533390#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1533377#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1533368#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1533366#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 1533364#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1533362#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 1533360#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1533358#L1839 assume !(0 != start_simulation_~tmp___0~1); 1488691#L1807-1 [2021-11-02 23:17:40,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:40,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1100206592, now seen corresponding path program 1 times [2021-11-02 23:17:40,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:40,597 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273390558] [2021-11-02 23:17:40,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:40,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:40,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:40,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:40,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:40,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273390558] [2021-11-02 23:17:40,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273390558] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:40,647 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:40,648 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:40,648 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707729090] [2021-11-02 23:17:40,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:40,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:40,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1340832177, now seen corresponding path program 1 times [2021-11-02 23:17:40,649 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:40,649 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916200236] [2021-11-02 23:17:40,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:40,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:40,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:40,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:40,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:40,689 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916200236] [2021-11-02 23:17:40,689 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916200236] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:40,689 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:40,689 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:40,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710130599] [2021-11-02 23:17:40,690 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:40,690 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:40,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:40,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:40,691 INFO L87 Difference]: Start difference. First operand 84380 states and 119363 transitions. cyclomatic complexity: 34987 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:41,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:41,292 INFO L93 Difference]: Finished difference Result 173258 states and 244619 transitions. [2021-11-02 23:17:41,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:41,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173258 states and 244619 transitions. [2021-11-02 23:17:42,655 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 172720 [2021-11-02 23:17:43,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 173258 states to 173258 states and 244619 transitions. [2021-11-02 23:17:43,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173258 [2021-11-02 23:17:43,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173258 [2021-11-02 23:17:43,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173258 states and 244619 transitions. [2021-11-02 23:17:43,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:43,323 INFO L681 BuchiCegarLoop]: Abstraction has 173258 states and 244619 transitions. [2021-11-02 23:17:43,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173258 states and 244619 transitions. [2021-11-02 23:17:45,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173258 to 91982. [2021-11-02 23:17:45,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91982 states, 91982 states have (on average 1.4130155900067405) internal successors, (129972), 91981 states have internal predecessors, (129972), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:45,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91982 states to 91982 states and 129972 transitions. [2021-11-02 23:17:45,409 INFO L704 BuchiCegarLoop]: Abstraction has 91982 states and 129972 transitions. [2021-11-02 23:17:45,409 INFO L587 BuchiCegarLoop]: Abstraction has 91982 states and 129972 transitions. [2021-11-02 23:17:45,409 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-02 23:17:45,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91982 states and 129972 transitions. [2021-11-02 23:17:45,664 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 91616 [2021-11-02 23:17:45,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:17:45,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:17:45,669 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:45,669 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:17:45,670 INFO L791 eck$LassoCheckResult]: Stem: 1745532#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1745533#L-1 havoc main_#res;havoc main_~__retres1~14;havoc main_~__retres1~14;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1746630#L1770 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1746631#L838 assume 1 == ~m_i~0;~m_st~0 := 0; 1746555#L845-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1746354#L850-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1746355#L855-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1744887#L860-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1744888#L865-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1746095#L870-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1746096#L875-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1746285#L880-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1745547#L885-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1745478#L890-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1745102#L895-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1745103#L900-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1745237#L905-1 assume !(0 == ~M_E~0); 1745238#L1198-1 assume !(0 == ~T1_E~0); 1745830#L1203-1 assume !(0 == ~T2_E~0); 1745831#L1208-1 assume !(0 == ~T3_E~0); 1746502#L1213-1 assume !(0 == ~T4_E~0); 1746658#L1218-1 assume !(0 == ~T5_E~0); 1744749#L1223-1 assume !(0 == ~T6_E~0); 1744750#L1228-1 assume !(0 == ~T7_E~0); 1746473#L1233-1 assume !(0 == ~T8_E~0); 1746187#L1238-1 assume !(0 == ~T9_E~0); 1746188#L1243-1 assume !(0 == ~T10_E~0); 1746618#L1248-1 assume !(0 == ~T11_E~0); 1746629#L1253-1 assume !(0 == ~T12_E~0); 1745890#L1258-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1745891#L1263-1 assume !(0 == ~E_1~0); 1745935#L1268-1 assume !(0 == ~E_2~0); 1745936#L1273-1 assume !(0 == ~E_3~0); 1746771#L1278-1 assume !(0 == ~E_4~0); 1746772#L1283-1 assume !(0 == ~E_5~0); 1746783#L1288-1 assume !(0 == ~E_6~0); 1746784#L1293-1 assume !(0 == ~E_7~0); 1746670#L1298-1 assume !(0 == ~E_8~0); 1746671#L1303-1 assume !(0 == ~E_9~0); 1745107#L1308-1 assume !(0 == ~E_10~0); 1745108#L1313-1 assume !(0 == ~E_11~0); 1746805#L1318-1 assume !(0 == ~E_12~0); 1746806#L1323-1 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1746864#L590 assume !(1 == ~m_pc~0); 1745324#L590-2 is_master_triggered_~__retres1~0 := 0; 1745325#L601 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1745564#L602 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1745565#L1489 assume !(0 != activate_threads_~tmp~1); 1746863#L1489-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1746503#L609 assume !(1 == ~t1_pc~0); 1746216#L609-2 is_transmit1_triggered_~__retres1~1 := 0; 1746217#L620 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1744799#L621 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1744800#L1497 assume !(0 != activate_threads_~tmp___0~0); 1746781#L1497-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1746782#L628 assume !(1 == ~t2_pc~0); 1746542#L628-2 is_transmit2_triggered_~__retres1~2 := 0; 1746543#L639 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1745943#L640 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1745944#L1505 assume !(0 != activate_threads_~tmp___1~0); 1745967#L1505-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1745968#L647 assume !(1 == ~t3_pc~0); 1745146#L647-2 is_transmit3_triggered_~__retres1~3 := 0; 1745145#L658 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1745404#L659 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1745405#L1513 assume !(0 != activate_threads_~tmp___2~0); 1746005#L1513-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1746006#L666 assume !(1 == ~t4_pc~0); 1746651#L666-2 is_transmit4_triggered_~__retres1~4 := 0; 1745155#L677 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1745156#L678 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1746859#L1521 assume !(0 != activate_threads_~tmp___3~0); 1746858#L1521-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1746770#L685 assume !(1 == ~t5_pc~0); 1746213#L685-2 is_transmit5_triggered_~__retres1~5 := 0; 1746214#L696 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1745792#L697 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1745147#L1529 assume !(0 != activate_threads_~tmp___4~0); 1745148#L1529-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1745609#L704 assume !(1 == ~t6_pc~0); 1746428#L704-2 is_transmit6_triggered_~__retres1~6 := 0; 1746755#L715 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1746853#L716 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1746850#L1537 assume !(0 != activate_threads_~tmp___5~0); 1746849#L1537-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1745906#L723 assume !(1 == ~t7_pc~0); 1745908#L723-2 is_transmit7_triggered_~__retres1~7 := 0; 1746847#L734 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1746607#L735 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1746608#L1545 assume !(0 != activate_threads_~tmp___6~0); 1746041#L1545-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1745199#L742 assume !(1 == ~t8_pc~0); 1745200#L742-2 is_transmit8_triggered_~__retres1~8 := 0; 1745354#L753 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1745355#L754 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1746399#L1553 assume !(0 != activate_threads_~tmp___7~0); 1746286#L1553-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1746287#L761 assume !(1 == ~t9_pc~0); 1745287#L761-2 is_transmit9_triggered_~__retres1~9 := 0; 1745153#L772 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1745154#L773 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1746807#L1561 assume !(0 != activate_threads_~tmp___8~0); 1745406#L1561-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1744965#L780 assume !(1 == ~t10_pc~0); 1744966#L780-2 is_transmit10_triggered_~__retres1~10 := 0; 1746841#L791 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1746078#L792 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1746079#L1569 assume !(0 != activate_threads_~tmp___9~0); 1746201#L1569-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1746839#L799 assume !(1 == ~t11_pc~0); 1745415#L799-2 is_transmit11_triggered_~__retres1~11 := 0; 1744963#L810 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1744964#L811 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1746451#L1577 assume !(0 != activate_threads_~tmp___10~0); 1745112#L1577-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1745113#L818 assume !(1 == ~t12_pc~0); 1746835#L818-2 is_transmit12_triggered_~__retres1~12 := 0; 1746834#L829 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1746833#L830 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1746832#L1585 assume !(0 != activate_threads_~tmp___11~0); 1746831#L1585-2 assume !(1 == ~M_E~0); 1746830#L1336-1 assume !(1 == ~T1_E~0); 1746829#L1341-1 assume !(1 == ~T2_E~0); 1746828#L1346-1 assume !(1 == ~T3_E~0); 1746827#L1351-1 assume !(1 == ~T4_E~0); 1746826#L1356-1 assume !(1 == ~T5_E~0); 1746825#L1361-1 assume !(1 == ~T6_E~0); 1746824#L1366-1 assume !(1 == ~T7_E~0); 1746823#L1371-1 assume !(1 == ~T8_E~0); 1746822#L1376-1 assume !(1 == ~T9_E~0); 1746821#L1381-1 assume !(1 == ~T10_E~0); 1746820#L1386-1 assume !(1 == ~T11_E~0); 1746819#L1391-1 assume !(1 == ~T12_E~0); 1746818#L1396-1 assume 1 == ~E_M~0;~E_M~0 := 2; 1745825#L1401-1 assume !(1 == ~E_1~0); 1745826#L1406-1 assume !(1 == ~E_2~0); 1746109#L1411-1 assume !(1 == ~E_3~0); 1746110#L1416-1 assume !(1 == ~E_4~0); 1745758#L1421-1 assume !(1 == ~E_5~0); 1745249#L1426-1 assume !(1 == ~E_6~0); 1745250#L1431-1 assume !(1 == ~E_7~0); 1744829#L1436-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1744830#L1441-1 assume !(1 == ~E_9~0); 1745583#L1446-1 assume !(1 == ~E_10~0); 1745584#L1451-1 assume !(1 == ~E_11~0); 1746356#L1456-1 assume !(1 == ~E_12~0); 1746357#L1807-1 [2021-11-02 23:17:45,671 INFO L793 eck$LassoCheckResult]: Loop: 1746357#L1807-1 assume !false; 1782072#L1808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_~tmp~0;havoc eval_~tmp~0; 1782069#L1173 assume !false; 1782068#L996 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1782064#L918 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1782051#L985 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1782049#L986 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1782047#L1000 assume !(0 != eval_~tmp~0); 1782048#L1188 start_simulation_~kernel_st~0 := 2; 1795567#L838-1 start_simulation_~kernel_st~0 := 3; 1795565#L1198-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1795563#L1198-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1795561#L1203-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1795559#L1208-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1795537#L1213-3 assume !(0 == ~T4_E~0); 1795529#L1218-3 assume !(0 == ~T5_E~0); 1795520#L1223-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1795512#L1228-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1795504#L1233-3 assume !(0 == ~T8_E~0); 1795496#L1238-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1795476#L1243-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1795471#L1248-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1795464#L1253-3 assume !(0 == ~T12_E~0); 1786021#L1258-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1786023#L1263-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1786015#L1268-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1786016#L1273-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1786009#L1278-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1786010#L1283-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1786002#L1288-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1786003#L1293-3 assume !(0 == ~E_7~0); 1785996#L1298-3 assume !(0 == ~E_8~0); 1785997#L1303-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1785990#L1308-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1785991#L1313-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1785984#L1318-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1785985#L1323-3 havoc activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1785978#L590-42 assume !(1 == ~m_pc~0); 1785979#L590-44 is_master_triggered_~__retres1~0 := 0; 1785972#L601-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1785973#L602-14 activate_threads_#t~ret23 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1785967#L1489-42 assume !(0 != activate_threads_~tmp~1); 1785968#L1489-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1785959#L609-42 assume !(1 == ~t1_pc~0); 1785961#L609-44 is_transmit1_triggered_~__retres1~1 := 0; 1785952#L620-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1785953#L621-14 activate_threads_#t~ret24 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1785946#L1497-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1785947#L1497-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1785940#L628-42 assume !(1 == ~t2_pc~0); 1781507#L628-44 is_transmit2_triggered_~__retres1~2 := 0; 1785936#L639-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1785937#L640-14 activate_threads_#t~ret25 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1785929#L1505-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1785930#L1505-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1785888#L647-42 assume !(1 == ~t3_pc~0); 1785890#L647-44 is_transmit3_triggered_~__retres1~3 := 0; 1785792#L658-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1785793#L659-14 activate_threads_#t~ret26 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1785788#L1513-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1785789#L1513-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1785782#L666-42 assume !(1 == ~t4_pc~0); 1785783#L666-44 is_transmit4_triggered_~__retres1~4 := 0; 1785776#L677-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1785777#L678-14 activate_threads_#t~ret27 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1785770#L1521-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1785771#L1521-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1785004#L685-42 assume !(1 == ~t5_pc~0); 1785005#L685-44 is_transmit5_triggered_~__retres1~5 := 0; 1784999#L696-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1785000#L697-14 activate_threads_#t~ret28 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1784993#L1529-42 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1784994#L1529-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1784982#L704-42 assume 1 == ~t6_pc~0; 1784984#L705-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1785163#L715-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1785164#L716-14 activate_threads_#t~ret29 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1784968#L1537-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1784969#L1537-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1784961#L723-42 assume !(1 == ~t7_pc~0); 1784960#L723-44 is_transmit7_triggered_~__retres1~7 := 0; 1784955#L734-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1784956#L735-14 activate_threads_#t~ret30 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1784951#L1545-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1784952#L1545-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1784946#L742-42 assume 1 == ~t8_pc~0; 1784947#L743-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1784926#L753-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1784927#L754-14 activate_threads_#t~ret31 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1784918#L1553-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1784919#L1553-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1782655#L761-42 assume !(1 == ~t9_pc~0); 1782656#L761-44 is_transmit9_triggered_~__retres1~9 := 0; 1782650#L772-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1782651#L773-14 activate_threads_#t~ret32 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1782644#L1561-42 assume !(0 != activate_threads_~tmp___8~0); 1782645#L1561-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1782637#L780-42 assume !(1 == ~t10_pc~0); 1782639#L780-44 is_transmit10_triggered_~__retres1~10 := 0; 1782630#L791-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1782631#L792-14 activate_threads_#t~ret33 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1782624#L1569-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1782625#L1569-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1782619#L799-42 assume !(1 == ~t11_pc~0); 1782618#L799-44 is_transmit11_triggered_~__retres1~11 := 0; 1782617#L810-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1782616#L811-14 activate_threads_#t~ret34 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1782615#L1577-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1782614#L1577-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1782613#L818-42 assume 1 == ~t12_pc~0; 1782611#L819-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1782610#L829-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1782609#L830-14 activate_threads_#t~ret35 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1782608#L1585-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1782607#L1585-44 assume 1 == ~M_E~0;~M_E~0 := 2; 1782606#L1336-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1782605#L1341-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1782604#L1346-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1782603#L1351-3 assume !(1 == ~T4_E~0); 1782602#L1356-3 assume !(1 == ~T5_E~0); 1782601#L1361-3 assume !(1 == ~T6_E~0); 1782600#L1366-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1782599#L1371-3 assume !(1 == ~T8_E~0); 1782598#L1376-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1782597#L1381-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1782596#L1386-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1782595#L1391-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1782593#L1396-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1782591#L1401-3 assume !(1 == ~E_1~0); 1782589#L1406-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1782587#L1411-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1782585#L1416-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1782583#L1421-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1782581#L1426-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1782579#L1431-3 assume !(1 == ~E_7~0); 1782577#L1436-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1782575#L1441-3 assume !(1 == ~E_9~0); 1782573#L1446-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1782571#L1451-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1782569#L1456-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1782567#L1461-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1782562#L918-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1782549#L985-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1782547#L986-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 1782545#L1826 assume !(0 == start_simulation_~tmp~3); 1782543#L1826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~13;havoc exists_runnable_thread_~__retres1~13; 1782535#L918-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13 := 1; 1782526#L985-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~13; 1782524#L986-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 1782522#L1781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1782520#L1788 stop_simulation_#res := stop_simulation_~__retres2~0; 1782518#L1789 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1782515#L1839 assume !(0 != start_simulation_~tmp___0~1); 1746357#L1807-1 [2021-11-02 23:17:45,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:45,671 INFO L85 PathProgramCache]: Analyzing trace with hash 621796094, now seen corresponding path program 1 times [2021-11-02 23:17:45,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:45,671 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629801747] [2021-11-02 23:17:45,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:45,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:45,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:45,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:45,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:45,711 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629801747] [2021-11-02 23:17:45,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629801747] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:45,711 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:45,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:45,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339543368] [2021-11-02 23:17:45,712 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:17:45,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:17:45,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1940774740, now seen corresponding path program 1 times [2021-11-02 23:17:45,713 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:17:45,713 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098234479] [2021-11-02 23:17:45,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:17:45,714 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:17:45,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:17:45,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:17:45,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:17:45,752 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098234479] [2021-11-02 23:17:45,752 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098234479] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:17:45,752 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:17:45,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:17:45,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100617735] [2021-11-02 23:17:45,753 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:17:45,753 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:17:45,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:17:45,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:17:45,754 INFO L87 Difference]: Start difference. First operand 91982 states and 129972 transitions. cyclomatic complexity: 37994 Second operand has 4 states, 4 states have (on average 36.5) internal successors, (146), 3 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:17:46,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:17:46,349 INFO L93 Difference]: Finished difference Result 162780 states and 229505 transitions. [2021-11-02 23:17:46,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:17:46,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162780 states and 229505 transitions. [2021-11-02 23:17:47,975 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 162368 [2021-11-02 23:17:48,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162780 states to 162780 states and 229505 transitions. [2021-11-02 23:17:48,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162780 [2021-11-02 23:17:48,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162780 [2021-11-02 23:17:48,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162780 states and 229505 transitions. [2021-11-02 23:17:48,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:17:48,551 INFO L681 BuchiCegarLoop]: Abstraction has 162780 states and 229505 transitions. [2021-11-02 23:17:48,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162780 states and 229505 transitions.