./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9ad7fb26 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 168328a62fef61b02ba6f144616119c681e0fd23340d79049fea75fcecfad304 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-9ad7fb2 [2021-11-02 23:08:37,897 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-02 23:08:37,900 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-02 23:08:37,960 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-02 23:08:37,961 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-02 23:08:37,963 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-02 23:08:37,965 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-02 23:08:37,969 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-02 23:08:37,975 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-02 23:08:37,982 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-02 23:08:37,984 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-02 23:08:37,986 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-02 23:08:37,990 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-02 23:08:37,993 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-02 23:08:37,998 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-02 23:08:38,001 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-02 23:08:38,004 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-02 23:08:38,013 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-02 23:08:38,016 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-02 23:08:38,028 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-02 23:08:38,030 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-02 23:08:38,034 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-02 23:08:38,036 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-02 23:08:38,038 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-02 23:08:38,044 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-02 23:08:38,051 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-02 23:08:38,052 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-02 23:08:38,053 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-02 23:08:38,055 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-02 23:08:38,057 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-02 23:08:38,059 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-02 23:08:38,060 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-02 23:08:38,063 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-02 23:08:38,065 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-02 23:08:38,067 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-02 23:08:38,067 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-02 23:08:38,068 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-02 23:08:38,069 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-02 23:08:38,069 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-02 23:08:38,070 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-02 23:08:38,071 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-02 23:08:38,073 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-02 23:08:38,146 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-02 23:08:38,146 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-02 23:08:38,147 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-02 23:08:38,147 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-02 23:08:38,148 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-02 23:08:38,149 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-02 23:08:38,149 INFO L138 SettingsManager]: * Use SBE=true [2021-11-02 23:08:38,149 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-02 23:08:38,150 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-02 23:08:38,150 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-02 23:08:38,150 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-02 23:08:38,151 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-02 23:08:38,151 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-02 23:08:38,151 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-02 23:08:38,152 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-02 23:08:38,152 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-02 23:08:38,152 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-02 23:08:38,153 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-02 23:08:38,153 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-02 23:08:38,153 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-02 23:08:38,154 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-02 23:08:38,154 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-02 23:08:38,154 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-02 23:08:38,154 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-02 23:08:38,155 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-02 23:08:38,155 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-02 23:08:38,155 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-02 23:08:38,156 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-02 23:08:38,156 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-02 23:08:38,157 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-02 23:08:38,157 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-02 23:08:38,157 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-02 23:08:38,158 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-02 23:08:38,159 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 168328a62fef61b02ba6f144616119c681e0fd23340d79049fea75fcecfad304 [2021-11-02 23:08:38,509 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-02 23:08:38,544 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-02 23:08:38,547 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-02 23:08:38,549 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-02 23:08:38,550 INFO L275 PluginConnector]: CDTParser initialized [2021-11-02 23:08:38,552 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/../../sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-02 23:08:38,657 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/data/711e7b0f1/1ca94556ef5a476f915f2af337322ced/FLAG24280e1db [2021-11-02 23:08:39,382 INFO L306 CDTParser]: Found 1 translation units. [2021-11-02 23:08:39,383 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-02 23:08:39,419 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/data/711e7b0f1/1ca94556ef5a476f915f2af337322ced/FLAG24280e1db [2021-11-02 23:08:39,599 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/data/711e7b0f1/1ca94556ef5a476f915f2af337322ced [2021-11-02 23:08:39,602 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-02 23:08:39,604 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-02 23:08:39,608 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-02 23:08:39,608 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-02 23:08:39,615 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-02 23:08:39,616 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:08:39" (1/1) ... [2021-11-02 23:08:39,619 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1df8a732 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:39, skipping insertion in model container [2021-11-02 23:08:39,619 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.11 11:08:39" (1/1) ... [2021-11-02 23:08:39,628 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-02 23:08:39,689 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-02 23:08:39,912 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/sv-benchmarks/c/systemc/token_ring.15.cil.c[364,377] [2021-11-02 23:08:40,092 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:08:40,112 INFO L203 MainTranslator]: Completed pre-run [2021-11-02 23:08:40,138 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/sv-benchmarks/c/systemc/token_ring.15.cil.c[364,377] [2021-11-02 23:08:40,242 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-02 23:08:40,275 INFO L208 MainTranslator]: Completed translation [2021-11-02 23:08:40,276 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40 WrapperNode [2021-11-02 23:08:40,276 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-02 23:08:40,277 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-02 23:08:40,278 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-02 23:08:40,278 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-02 23:08:40,287 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,306 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,479 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-02 23:08:40,480 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-02 23:08:40,480 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-02 23:08:40,480 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-02 23:08:40,500 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,500 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,516 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,518 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,644 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,750 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,766 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,792 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-02 23:08:40,794 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-02 23:08:40,796 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-02 23:08:40,796 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-02 23:08:40,798 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (1/1) ... [2021-11-02 23:08:40,809 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-02 23:08:40,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/z3 [2021-11-02 23:08:40,851 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-02 23:08:40,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f171fe5-780e-42aa-8954-7baa31930dcf/bin/uautomizer-tBqnrhUYjU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-02 23:08:40,915 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-02 23:08:40,916 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-02 23:08:40,916 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-02 23:08:40,916 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-02 23:08:44,299 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-02 23:08:44,299 INFO L299 CfgBuilder]: Removed 622 assume(true) statements. [2021-11-02 23:08:44,305 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:08:44 BoogieIcfgContainer [2021-11-02 23:08:44,305 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-02 23:08:44,307 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-02 23:08:44,307 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-02 23:08:44,311 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-02 23:08:44,312 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:08:44,312 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.11 11:08:39" (1/3) ... [2021-11-02 23:08:44,314 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8ef5413 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:08:44, skipping insertion in model container [2021-11-02 23:08:44,314 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:08:44,314 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.11 11:08:40" (2/3) ... [2021-11-02 23:08:44,315 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8ef5413 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.11 11:08:44, skipping insertion in model container [2021-11-02 23:08:44,315 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-02 23:08:44,315 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.11 11:08:44" (3/3) ... [2021-11-02 23:08:44,317 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2021-11-02 23:08:44,375 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-02 23:08:44,376 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-02 23:08:44,376 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-02 23:08:44,376 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-02 23:08:44,376 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-02 23:08:44,376 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-02 23:08:44,377 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-02 23:08:44,377 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-02 23:08:44,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:44,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2021-11-02 23:08:44,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:44,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:44,612 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:44,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:44,613 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-02 23:08:44,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:44,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2021-11-02 23:08:44,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:44,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:44,667 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:44,667 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:44,681 INFO L791 eck$LassoCheckResult]: Stem: 478#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1910#L-1true havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1918#L1890true havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1543#L894true assume !(1 == ~m_i~0);~m_st~0 := 2; 575#L901-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 455#L906-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 835#L911-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 321#L916-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 577#L921-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 714#L926-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 848#L931-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 871#L936-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 943#L941-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 327#L946-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1783#L951-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 175#L956-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1943#L961-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 427#L966-1true assume !(0 == ~M_E~0); 1831#L1278-1true assume !(0 == ~T1_E~0); 1211#L1283-1true assume !(0 == ~T2_E~0); 1864#L1288-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1651#L1293-1true assume !(0 == ~T4_E~0); 1614#L1298-1true assume !(0 == ~T5_E~0); 1440#L1303-1true assume !(0 == ~T6_E~0); 223#L1308-1true assume !(0 == ~T7_E~0); 186#L1313-1true assume !(0 == ~T8_E~0); 1915#L1318-1true assume !(0 == ~T9_E~0); 188#L1323-1true assume !(0 == ~T10_E~0); 288#L1328-1true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1871#L1333-1true assume !(0 == ~T12_E~0); 993#L1338-1true assume !(0 == ~T13_E~0); 1160#L1343-1true assume !(0 == ~E_M~0); 1743#L1348-1true assume !(0 == ~E_1~0); 1753#L1353-1true assume !(0 == ~E_2~0); 745#L1358-1true assume !(0 == ~E_3~0); 1027#L1363-1true assume !(0 == ~E_4~0); 1098#L1368-1true assume 0 == ~E_5~0;~E_5~0 := 1; 104#L1373-1true assume !(0 == ~E_6~0); 504#L1378-1true assume !(0 == ~E_7~0); 261#L1383-1true assume !(0 == ~E_8~0); 1148#L1388-1true assume !(0 == ~E_9~0); 1078#L1393-1true assume !(0 == ~E_10~0); 1086#L1398-1true assume !(0 == ~E_11~0); 1895#L1403-1true assume !(0 == ~E_12~0); 1437#L1408-1true assume 0 == ~E_13~0;~E_13~0 := 1; 244#L1413-1true havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1811#L627true assume 1 == ~m_pc~0; 1919#L628true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 457#L638true is_master_triggered_#res := is_master_triggered_~__retres1~0; 893#L639true activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1524#L1590true assume !(0 != activate_threads_~tmp~1); 1744#L1590-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 208#L646true assume !(1 == ~t1_pc~0); 1410#L646-2true is_transmit1_triggered_~__retres1~1 := 0; 612#L657true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 646#L658true activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1302#L1598true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 146#L1598-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1725#L665true assume 1 == ~t2_pc~0; 1882#L666true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1179#L676true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 255#L677true activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 592#L1606true assume !(0 != activate_threads_~tmp___1~0); 815#L1606-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 861#L684true assume !(1 == ~t3_pc~0); 788#L684-2true is_transmit3_triggered_~__retres1~3 := 0; 852#L695true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1678#L696true activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1850#L1614true assume !(0 != activate_threads_~tmp___2~0); 1937#L1614-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1766#L703true assume 1 == ~t4_pc~0; 420#L704true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1386#L714true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 738#L715true activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 392#L1622true assume !(0 != activate_threads_~tmp___3~0); 1702#L1622-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1311#L722true assume !(1 == ~t5_pc~0); 368#L722-2true is_transmit5_triggered_~__retres1~5 := 0; 583#L733true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1069#L734true activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20#L1630true assume !(0 != activate_threads_~tmp___4~0); 1815#L1630-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 123#L741true assume 1 == ~t6_pc~0; 278#L742true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 784#L752true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 367#L753true activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 178#L1638true assume !(0 != activate_threads_~tmp___5~0); 351#L1638-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 419#L760true assume 1 == ~t7_pc~0; 338#L761true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 949#L771true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 252#L772true activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1453#L1646true assume !(0 != activate_threads_~tmp___6~0); 471#L1646-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1385#L779true assume !(1 == ~t8_pc~0); 1549#L779-2true is_transmit8_triggered_~__retres1~8 := 0; 69#L790true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 273#L791true activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1361#L1654true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 778#L1654-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1676#L798true assume 1 == ~t9_pc~0; 1374#L799true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 1249#L809true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 143#L810true activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1866#L1662true assume !(0 != activate_threads_~tmp___8~0); 38#L1662-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 61#L817true assume !(1 == ~t10_pc~0); 1878#L817-2true is_transmit10_triggered_~__retres1~10 := 0; 482#L828true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 869#L829true activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 179#L1670true assume !(0 != activate_threads_~tmp___9~0); 1591#L1670-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 739#L836true assume 1 == ~t11_pc~0; 842#L837true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 228#L847true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1553#L848true activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 209#L1678true assume !(0 != activate_threads_~tmp___10~0); 1978#L1678-2true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1265#L855true assume !(1 == ~t12_pc~0); 942#L855-2true is_transmit12_triggered_~__retres1~12 := 0; 1121#L866true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1231#L867true activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1155#L1686true assume !(0 != activate_threads_~tmp___11~0); 1084#L1686-2true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 204#L874true assume 1 == ~t13_pc~0; 1529#L875true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 293#L885true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 369#L886true activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1232#L1694true assume !(0 != activate_threads_~tmp___12~0); 1611#L1694-2true assume !(1 == ~M_E~0); 320#L1426-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1049#L1431-1true assume !(1 == ~T2_E~0); 70#L1436-1true assume !(1 == ~T3_E~0); 772#L1441-1true assume !(1 == ~T4_E~0); 500#L1446-1true assume !(1 == ~T5_E~0); 1853#L1451-1true assume !(1 == ~T6_E~0); 1157#L1456-1true assume !(1 == ~T7_E~0); 771#L1461-1true assume !(1 == ~T8_E~0); 451#L1466-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1843#L1471-1true assume !(1 == ~T10_E~0); 1122#L1476-1true assume !(1 == ~T11_E~0); 1365#L1481-1true assume !(1 == ~T12_E~0); 1673#L1486-1true assume !(1 == ~T13_E~0); 230#L1491-1true assume !(1 == ~E_M~0); 43#L1496-1true assume !(1 == ~E_1~0); 783#L1501-1true assume !(1 == ~E_2~0); 498#L1506-1true assume 1 == ~E_3~0;~E_3~0 := 2; 1072#L1511-1true assume !(1 == ~E_4~0); 470#L1516-1true assume !(1 == ~E_5~0); 22#L1521-1true assume !(1 == ~E_6~0); 42#L1526-1true assume !(1 == ~E_7~0); 334#L1531-1true assume !(1 == ~E_8~0); 679#L1536-1true assume !(1 == ~E_9~0); 176#L1541-1true assume !(1 == ~E_10~0); 1721#L1546-1true assume 1 == ~E_11~0;~E_11~0 := 2; 1464#L1551-1true assume !(1 == ~E_12~0); 264#L1556-1true assume !(1 == ~E_13~0); 280#L1927-1true [2021-11-02 23:08:44,686 INFO L793 eck$LassoCheckResult]: Loop: 280#L1927-1true assume !false; 1660#L1928true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 298#L1253true assume false; 1471#L1268true start_simulation_~kernel_st~0 := 2; 185#L894-1true start_simulation_~kernel_st~0 := 3; 826#L1278-2true assume 0 == ~M_E~0;~M_E~0 := 1; 506#L1278-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1701#L1283-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 275#L1288-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1869#L1293-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1222#L1298-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1778#L1303-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1490#L1308-3true assume !(0 == ~T7_E~0); 1218#L1313-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 680#L1318-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 163#L1323-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1345#L1328-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1759#L1333-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 235#L1338-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 1093#L1343-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1615#L1348-3true assume !(0 == ~E_1~0); 1364#L1353-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1393#L1358-3true assume 0 == ~E_3~0;~E_3~0 := 1; 653#L1363-3true assume 0 == ~E_4~0;~E_4~0 := 1; 345#L1368-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1956#L1373-3true assume 0 == ~E_6~0;~E_6~0 := 1; 917#L1378-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1525#L1383-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1146#L1388-3true assume !(0 == ~E_9~0); 1128#L1393-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1491#L1398-3true assume 0 == ~E_11~0;~E_11~0 := 1; 538#L1403-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1375#L1408-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1510#L1413-3true havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 447#L627-45true assume 1 == ~m_pc~0; 1156#L628-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1352#L638-15true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1729#L639-15true activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 666#L1590-45true assume !(0 != activate_threads_~tmp~1); 1273#L1590-47true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1927#L646-45true assume 1 == ~t1_pc~0; 1407#L647-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1825#L657-15true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 703#L658-15true activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1083#L1598-45true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 220#L1598-47true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1163#L665-45true assume 1 == ~t2_pc~0; 62#L666-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 510#L676-15true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1684#L677-15true activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 74#L1606-45true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1451#L1606-47true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 830#L684-45true assume 1 == ~t3_pc~0; 1561#L685-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 983#L695-15true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1508#L696-15true activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1502#L1614-45true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1158#L1614-47true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 923#L703-45true assume 1 == ~t4_pc~0; 781#L704-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1990#L714-15true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 485#L715-15true activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 312#L1622-45true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 503#L1622-47true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1056#L722-45true assume !(1 == ~t5_pc~0); 1413#L722-47true is_transmit5_triggered_~__retres1~5 := 0; 1521#L733-15true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1692#L734-15true activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1683#L1630-45true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 763#L1630-47true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1546#L741-45true assume 1 == ~t6_pc~0; 362#L742-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 582#L752-15true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 849#L753-15true activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 879#L1638-45true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 971#L1638-47true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1741#L760-45true assume !(1 == ~t7_pc~0); 1108#L760-47true is_transmit7_triggered_~__retres1~7 := 0; 1341#L771-15true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 522#L772-15true activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1412#L1646-45true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 994#L1646-47true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1229#L779-45true assume !(1 == ~t8_pc~0); 201#L779-47true is_transmit8_triggered_~__retres1~8 := 0; 441#L790-15true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 211#L791-15true activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1824#L1654-45true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 972#L1654-47true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1877#L798-45true assume 1 == ~t9_pc~0; 1663#L799-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 894#L809-15true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1981#L810-15true activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 662#L1662-45true assume !(0 != activate_threads_~tmp___8~0); 878#L1662-47true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 589#L817-45true assume 1 == ~t10_pc~0; 1125#L818-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1573#L828-15true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 892#L829-15true activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 425#L1670-45true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 364#L1670-47true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1046#L836-45true assume 1 == ~t11_pc~0; 789#L837-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 1496#L847-15true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 523#L848-15true activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 914#L1678-45true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 996#L1678-47true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1704#L855-45true assume !(1 == ~t12_pc~0); 931#L855-47true is_transmit12_triggered_~__retres1~12 := 0; 181#L866-15true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1256#L867-15true activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 760#L1686-45true assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1325#L1686-47true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 556#L874-45true assume 1 == ~t13_pc~0; 1422#L875-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 497#L885-15true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 720#L886-15true activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 259#L1694-45true assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 765#L1694-47true assume 1 == ~M_E~0;~M_E~0 := 2; 1088#L1426-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 231#L1431-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 306#L1436-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 24#L1441-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1202#L1446-3true assume !(1 == ~T5_E~0); 1189#L1451-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 549#L1456-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 324#L1461-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1693#L1466-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1888#L1471-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 292#L1476-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1772#L1481-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 530#L1486-3true assume !(1 == ~T13_E~0); 305#L1491-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1542#L1496-3true assume 1 == ~E_1~0;~E_1~0 := 2; 572#L1501-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1677#L1506-3true assume 1 == ~E_3~0;~E_3~0 := 2; 916#L1511-3true assume 1 == ~E_4~0;~E_4~0 := 2; 910#L1516-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1809#L1521-3true assume 1 == ~E_6~0;~E_6~0 := 2; 659#L1526-3true assume !(1 == ~E_7~0); 990#L1531-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1608#L1536-3true assume 1 == ~E_9~0;~E_9~0 := 2; 316#L1541-3true assume 1 == ~E_10~0;~E_10~0 := 2; 339#L1546-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1735#L1551-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1552#L1556-3true assume 1 == ~E_13~0;~E_13~0 := 2; 94#L1561-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 597#L979-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1130#L1051-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1388#L1052-1true start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 960#L1946true assume !(0 == start_simulation_~tmp~3); 706#L1946-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1054#L979-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1603#L1051-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1619#L1052-2true stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1050#L1901true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15#L1908true stop_simulation_#res := stop_simulation_~__retres2~0; 1135#L1909true start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 134#L1959true assume !(0 != start_simulation_~tmp___0~1); 280#L1927-1true [2021-11-02 23:08:44,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:44,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1425010847, now seen corresponding path program 1 times [2021-11-02 23:08:44,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:44,717 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563000256] [2021-11-02 23:08:44,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:44,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:44,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:45,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:45,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:45,151 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563000256] [2021-11-02 23:08:45,152 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563000256] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:45,153 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:45,154 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:45,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884984481] [2021-11-02 23:08:45,163 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:45,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:45,167 INFO L85 PathProgramCache]: Analyzing trace with hash -879078067, now seen corresponding path program 1 times [2021-11-02 23:08:45,168 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:45,168 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661218834] [2021-11-02 23:08:45,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:45,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:45,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:45,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:45,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:45,287 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661218834] [2021-11-02 23:08:45,288 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661218834] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:45,288 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:45,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:45,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677974343] [2021-11-02 23:08:45,290 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:45,291 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:45,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:45,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:45,317 INFO L87 Difference]: Start difference. First operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:45,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:45,447 INFO L93 Difference]: Finished difference Result 1992 states and 2962 transitions. [2021-11-02 23:08:45,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:45,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1992 states and 2962 transitions. [2021-11-02 23:08:45,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:45,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1992 states to 1986 states and 2956 transitions. [2021-11-02 23:08:45,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:45,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:45,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2956 transitions. [2021-11-02 23:08:45,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:45,520 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-02 23:08:45,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2956 transitions. [2021-11-02 23:08:45,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:45,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4884189325276937) internal successors, (2956), 1985 states have internal predecessors, (2956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:45,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2956 transitions. [2021-11-02 23:08:45,657 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-02 23:08:45,657 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-02 23:08:45,657 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-02 23:08:45,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2956 transitions. [2021-11-02 23:08:45,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:45,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:45,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:45,682 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:45,683 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:45,684 INFO L791 eck$LassoCheckResult]: Stem: 4896#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4897#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5976#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5890#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 5043#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4853#L906-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4854#L911-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4621#L916-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4622#L921-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5045#L926-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5231#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5391#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5412#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4629#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4630#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4357#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4358#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4805#L966-1 assume !(0 == ~M_E~0); 4806#L1278-1 assume !(0 == ~T1_E~0); 5718#L1283-1 assume !(0 == ~T2_E~0); 5719#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5924#L1293-1 assume !(0 == ~T4_E~0); 5912#L1298-1 assume !(0 == ~T5_E~0); 5856#L1303-1 assume !(0 == ~T6_E~0); 4456#L1308-1 assume !(0 == ~T7_E~0); 4380#L1313-1 assume !(0 == ~T8_E~0); 4381#L1318-1 assume !(0 == ~T9_E~0); 4383#L1323-1 assume !(0 == ~T10_E~0); 4384#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4567#L1333-1 assume !(0 == ~T12_E~0); 5529#L1338-1 assume !(0 == ~T13_E~0); 5530#L1343-1 assume !(0 == ~E_M~0); 5672#L1348-1 assume !(0 == ~E_1~0); 5952#L1353-1 assume !(0 == ~E_2~0); 5274#L1358-1 assume !(0 == ~E_3~0); 5275#L1363-1 assume !(0 == ~E_4~0); 5566#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4209#L1373-1 assume !(0 == ~E_6~0); 4210#L1378-1 assume !(0 == ~E_7~0); 4524#L1383-1 assume !(0 == ~E_8~0); 4525#L1388-1 assume !(0 == ~E_9~0); 5603#L1393-1 assume !(0 == ~E_10~0); 5604#L1398-1 assume !(0 == ~E_11~0); 5610#L1403-1 assume !(0 == ~E_12~0); 5854#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 4495#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4496#L627 assume 1 == ~m_pc~0; 5964#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4857#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4858#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5436#L1590 assume !(0 != activate_threads_~tmp~1); 5884#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4425#L646 assume !(1 == ~t1_pc~0); 4426#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 5085#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5093#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5143#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4298#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4299#L665 assume 1 == ~t2_pc~0; 5946#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4966#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4512#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4513#L1606 assume !(0 != activate_threads_~tmp___1~0); 5068#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5356#L684 assume !(1 == ~t3_pc~0); 5322#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 5323#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5393#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5931#L1614 assume !(0 != activate_threads_~tmp___2~0); 5970#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5955#L703 assume 1 == ~t4_pc~0; 4792#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4653#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5264#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4747#L1622 assume !(0 != activate_threads_~tmp___3~0); 4748#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5788#L722 assume !(1 == ~t5_pc~0); 4704#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 4705#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5053#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4033#L1630 assume !(0 != activate_threads_~tmp___4~0); 4034#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4245#L741 assume 1 == ~t6_pc~0; 4246#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4550#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4703#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4363#L1638 assume !(0 != activate_threads_~tmp___5~0); 4364#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4677#L760 assume 1 == ~t7_pc~0; 4648#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4649#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4507#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 4508#L1646 assume !(0 != activate_threads_~tmp___6~0); 4884#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4885#L779 assume !(1 == ~t8_pc~0); 4290#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 4139#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4140#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 4542#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5312#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5313#L798 assume 1 == ~t9_pc~0; 5815#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 5753#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4291#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4292#L1662 assume !(0 != activate_threads_~tmp___8~0); 4074#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4075#L817 assume !(1 == ~t10_pc~0); 4121#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 4903#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 4904#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4365#L1670 assume !(0 != activate_threads_~tmp___9~0); 4366#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5265#L836 assume 1 == ~t11_pc~0; 5266#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 4464#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4465#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 4428#L1678 assume !(0 != activate_threads_~tmp___10~0); 4429#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5763#L855 assume !(1 == ~t12_pc~0); 5090#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 5091#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 5644#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 5669#L1686 assume !(0 != activate_threads_~tmp___11~0); 5609#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 4414#L874 assume 1 == ~t13_pc~0; 4415#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 4576#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4577#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 4706#L1694 assume !(0 != activate_threads_~tmp___12~0); 5736#L1694-2 assume !(1 == ~M_E~0); 4619#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4620#L1431-1 assume !(1 == ~T2_E~0); 4141#L1436-1 assume !(1 == ~T3_E~0); 4142#L1441-1 assume !(1 == ~T4_E~0); 4934#L1446-1 assume !(1 == ~T5_E~0); 4935#L1451-1 assume !(1 == ~T6_E~0); 5670#L1456-1 assume !(1 == ~T7_E~0); 5306#L1461-1 assume !(1 == ~T8_E~0); 4849#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4850#L1471-1 assume !(1 == ~T10_E~0); 5645#L1476-1 assume !(1 == ~T11_E~0); 5646#L1481-1 assume !(1 == ~T12_E~0); 5811#L1486-1 assume !(1 == ~T13_E~0); 4468#L1491-1 assume !(1 == ~E_M~0); 4083#L1496-1 assume !(1 == ~E_1~0); 4084#L1501-1 assume !(1 == ~E_2~0); 4929#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4930#L1511-1 assume !(1 == ~E_4~0); 4883#L1516-1 assume !(1 == ~E_5~0); 4037#L1521-1 assume !(1 == ~E_6~0); 4038#L1526-1 assume !(1 == ~E_7~0); 4082#L1531-1 assume !(1 == ~E_8~0); 4640#L1536-1 assume !(1 == ~E_9~0); 4359#L1541-1 assume !(1 == ~E_10~0); 4360#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 5865#L1551-1 assume !(1 == ~E_12~0); 4529#L1556-1 assume !(1 == ~E_13~0); 4272#L1927-1 [2021-11-02 23:08:45,685 INFO L793 eck$LassoCheckResult]: Loop: 4272#L1927-1 assume !false; 4553#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 4564#L1253 assume !false; 4025#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4026#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4712#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4635#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4636#L1066 assume !(0 != eval_~tmp~0); 5869#L1268 start_simulation_~kernel_st~0 := 2; 4378#L894-1 start_simulation_~kernel_st~0 := 3; 4379#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4944#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4945#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4544#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4545#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5730#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5731#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5873#L1308-3 assume !(0 == ~T7_E~0); 5725#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5187#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4331#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4332#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5805#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4478#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4479#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5617#L1348-3 assume !(0 == ~E_1~0); 5809#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5810#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5149#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4664#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4665#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5465#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5466#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5663#L1388-3 assume !(0 == ~E_9~0); 5650#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5651#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4995#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4996#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5817#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4842#L627-45 assume !(1 == ~m_pc~0); 4843#L627-47 is_master_triggered_~__retres1~0 := 0; 5339#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5807#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5170#L1590-45 assume !(0 != activate_threads_~tmp~1); 5171#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5767#L646-45 assume !(1 == ~t1_pc~0); 5032#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 5033#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5217#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5218#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4449#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4450#L665-45 assume 1 == ~t2_pc~0; 4123#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4124#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4950#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4150#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4151#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5371#L684-45 assume 1 == ~t3_pc~0; 5372#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4447#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5523#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5874#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5671#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5476#L703-45 assume 1 == ~t4_pc~0; 5315#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5317#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4910#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4604#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4605#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4941#L722-45 assume 1 == ~t5_pc~0; 4931#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4932#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5882#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 5932#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5297#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5298#L741-45 assume 1 == ~t6_pc~0; 4694#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4695#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5052#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5392#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5423#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5511#L760-45 assume 1 == ~t7_pc~0; 5399#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5400#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4971#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 4972#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5531#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5532#L779-45 assume !(1 == ~t8_pc~0); 4407#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 4408#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4432#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 4433#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5512#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5513#L798-45 assume 1 == ~t9_pc~0; 5927#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 5049#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5437#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 5160#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 5161#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5063#L817-45 assume 1 == ~t10_pc~0; 5064#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 5648#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5435#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4802#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 4699#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4700#L836-45 assume !(1 == ~t11_pc~0); 4204#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 4205#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4973#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 4974#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5461#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5534#L855-45 assume 1 == ~t12_pc~0; 4922#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 4369#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4370#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 5294#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 5295#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5018#L874-45 assume !(1 == ~t13_pc~0); 5019#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 4927#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4928#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 4520#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 4521#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 5300#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4469#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4470#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4041#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4042#L1446-3 assume !(1 == ~T5_E~0); 5700#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5009#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4624#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4625#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5936#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4574#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4575#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4983#L1486-3 assume !(1 == ~T13_E~0); 4593#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4594#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5038#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5039#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5464#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5455#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5456#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5158#L1526-3 assume !(1 == ~E_7~0); 5159#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5528#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4611#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4612#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4651#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5894#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4188#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4189#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4296#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5653#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 5496#L1946 assume !(0 == start_simulation_~tmp~3); 5221#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5222#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4535#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5910#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 5586#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4023#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 4024#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 4271#L1959 assume !(0 != start_simulation_~tmp___0~1); 4272#L1927-1 [2021-11-02 23:08:45,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:45,687 INFO L85 PathProgramCache]: Analyzing trace with hash -813741789, now seen corresponding path program 1 times [2021-11-02 23:08:45,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:45,687 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136204184] [2021-11-02 23:08:45,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:45,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:45,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:45,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:45,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:45,836 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136204184] [2021-11-02 23:08:45,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136204184] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:45,837 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:45,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:45,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469938439] [2021-11-02 23:08:45,838 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:45,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:45,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1679024933, now seen corresponding path program 1 times [2021-11-02 23:08:45,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:45,840 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123222853] [2021-11-02 23:08:45,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:45,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:45,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:46,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:46,003 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:46,003 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123222853] [2021-11-02 23:08:46,004 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123222853] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:46,004 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:46,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:46,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129126471] [2021-11-02 23:08:46,005 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:46,005 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:46,006 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:46,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:46,007 INFO L87 Difference]: Start difference. First operand 1986 states and 2956 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:46,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:46,096 INFO L93 Difference]: Finished difference Result 1986 states and 2955 transitions. [2021-11-02 23:08:46,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:46,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2955 transitions. [2021-11-02 23:08:46,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:46,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2955 transitions. [2021-11-02 23:08:46,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:46,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:46,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2955 transitions. [2021-11-02 23:08:46,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:46,151 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-02 23:08:46,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2955 transitions. [2021-11-02 23:08:46,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:46,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.487915407854985) internal successors, (2955), 1985 states have internal predecessors, (2955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:46,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2955 transitions. [2021-11-02 23:08:46,207 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-02 23:08:46,207 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-02 23:08:46,208 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-02 23:08:46,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2955 transitions. [2021-11-02 23:08:46,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:46,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:46,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:46,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:46,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:46,236 INFO L791 eck$LassoCheckResult]: Stem: 8875#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8876#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9955#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9869#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 9022#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8832#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8833#L911-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8600#L916-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8601#L921-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9024#L926-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9210#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9370#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9391#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8608#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8609#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8336#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8337#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8784#L966-1 assume !(0 == ~M_E~0); 8785#L1278-1 assume !(0 == ~T1_E~0); 9697#L1283-1 assume !(0 == ~T2_E~0); 9698#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9903#L1293-1 assume !(0 == ~T4_E~0); 9891#L1298-1 assume !(0 == ~T5_E~0); 9835#L1303-1 assume !(0 == ~T6_E~0); 8435#L1308-1 assume !(0 == ~T7_E~0); 8359#L1313-1 assume !(0 == ~T8_E~0); 8360#L1318-1 assume !(0 == ~T9_E~0); 8362#L1323-1 assume !(0 == ~T10_E~0); 8363#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8546#L1333-1 assume !(0 == ~T12_E~0); 9508#L1338-1 assume !(0 == ~T13_E~0); 9509#L1343-1 assume !(0 == ~E_M~0); 9651#L1348-1 assume !(0 == ~E_1~0); 9931#L1353-1 assume !(0 == ~E_2~0); 9253#L1358-1 assume !(0 == ~E_3~0); 9254#L1363-1 assume !(0 == ~E_4~0); 9545#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8188#L1373-1 assume !(0 == ~E_6~0); 8189#L1378-1 assume !(0 == ~E_7~0); 8503#L1383-1 assume !(0 == ~E_8~0); 8504#L1388-1 assume !(0 == ~E_9~0); 9582#L1393-1 assume !(0 == ~E_10~0); 9583#L1398-1 assume !(0 == ~E_11~0); 9589#L1403-1 assume !(0 == ~E_12~0); 9833#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 8474#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8475#L627 assume 1 == ~m_pc~0; 9943#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8836#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8837#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9415#L1590 assume !(0 != activate_threads_~tmp~1); 9863#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8404#L646 assume !(1 == ~t1_pc~0); 8405#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 9064#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9072#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9122#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8277#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8278#L665 assume 1 == ~t2_pc~0; 9925#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8945#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8491#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8492#L1606 assume !(0 != activate_threads_~tmp___1~0); 9047#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9335#L684 assume !(1 == ~t3_pc~0); 9301#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 9302#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9372#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9910#L1614 assume !(0 != activate_threads_~tmp___2~0); 9949#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9934#L703 assume 1 == ~t4_pc~0; 8771#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8632#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9243#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8726#L1622 assume !(0 != activate_threads_~tmp___3~0); 8727#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9767#L722 assume !(1 == ~t5_pc~0); 8683#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 8684#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9032#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8012#L1630 assume !(0 != activate_threads_~tmp___4~0); 8013#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8224#L741 assume 1 == ~t6_pc~0; 8225#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8529#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8682#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8342#L1638 assume !(0 != activate_threads_~tmp___5~0); 8343#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8656#L760 assume 1 == ~t7_pc~0; 8627#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8628#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8486#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8487#L1646 assume !(0 != activate_threads_~tmp___6~0); 8863#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8864#L779 assume !(1 == ~t8_pc~0); 8269#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 8118#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8119#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 8521#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9291#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9292#L798 assume 1 == ~t9_pc~0; 9794#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 9732#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8270#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8271#L1662 assume !(0 != activate_threads_~tmp___8~0); 8053#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8054#L817 assume !(1 == ~t10_pc~0); 8100#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 8882#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8883#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 8344#L1670 assume !(0 != activate_threads_~tmp___9~0); 8345#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 9244#L836 assume 1 == ~t11_pc~0; 9245#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 8443#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8444#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 8407#L1678 assume !(0 != activate_threads_~tmp___10~0); 8408#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 9742#L855 assume !(1 == ~t12_pc~0); 9069#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 9070#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 9623#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 9648#L1686 assume !(0 != activate_threads_~tmp___11~0); 9588#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 8393#L874 assume 1 == ~t13_pc~0; 8394#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 8555#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 8556#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 8685#L1694 assume !(0 != activate_threads_~tmp___12~0); 9715#L1694-2 assume !(1 == ~M_E~0); 8598#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8599#L1431-1 assume !(1 == ~T2_E~0); 8120#L1436-1 assume !(1 == ~T3_E~0); 8121#L1441-1 assume !(1 == ~T4_E~0); 8913#L1446-1 assume !(1 == ~T5_E~0); 8914#L1451-1 assume !(1 == ~T6_E~0); 9649#L1456-1 assume !(1 == ~T7_E~0); 9285#L1461-1 assume !(1 == ~T8_E~0); 8828#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8829#L1471-1 assume !(1 == ~T10_E~0); 9624#L1476-1 assume !(1 == ~T11_E~0); 9625#L1481-1 assume !(1 == ~T12_E~0); 9790#L1486-1 assume !(1 == ~T13_E~0); 8447#L1491-1 assume !(1 == ~E_M~0); 8062#L1496-1 assume !(1 == ~E_1~0); 8063#L1501-1 assume !(1 == ~E_2~0); 8908#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 8909#L1511-1 assume !(1 == ~E_4~0); 8862#L1516-1 assume !(1 == ~E_5~0); 8016#L1521-1 assume !(1 == ~E_6~0); 8017#L1526-1 assume !(1 == ~E_7~0); 8061#L1531-1 assume !(1 == ~E_8~0); 8619#L1536-1 assume !(1 == ~E_9~0); 8338#L1541-1 assume !(1 == ~E_10~0); 8339#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 9844#L1551-1 assume !(1 == ~E_12~0); 8508#L1556-1 assume !(1 == ~E_13~0); 8251#L1927-1 [2021-11-02 23:08:46,237 INFO L793 eck$LassoCheckResult]: Loop: 8251#L1927-1 assume !false; 8532#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 8543#L1253 assume !false; 8004#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8005#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8691#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8614#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 8615#L1066 assume !(0 != eval_~tmp~0); 9848#L1268 start_simulation_~kernel_st~0 := 2; 8357#L894-1 start_simulation_~kernel_st~0 := 3; 8358#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8923#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8924#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8523#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8524#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9709#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9710#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9852#L1308-3 assume !(0 == ~T7_E~0); 9704#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9166#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8310#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8311#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9784#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8457#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8458#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9596#L1348-3 assume !(0 == ~E_1~0); 9788#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9789#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9128#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8643#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8644#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9444#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9445#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9642#L1388-3 assume !(0 == ~E_9~0); 9629#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9630#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8974#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8975#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9796#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8821#L627-45 assume !(1 == ~m_pc~0); 8822#L627-47 is_master_triggered_~__retres1~0 := 0; 9318#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9786#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9149#L1590-45 assume !(0 != activate_threads_~tmp~1); 9150#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9746#L646-45 assume !(1 == ~t1_pc~0); 9011#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 9012#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9196#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9197#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8428#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8429#L665-45 assume 1 == ~t2_pc~0; 8102#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8103#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8929#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8129#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8130#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9350#L684-45 assume 1 == ~t3_pc~0; 9351#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8426#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9502#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9853#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9650#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9455#L703-45 assume 1 == ~t4_pc~0; 9294#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9296#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8889#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8583#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8584#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8920#L722-45 assume !(1 == ~t5_pc~0); 8912#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 8911#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9861#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 9911#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9276#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9277#L741-45 assume 1 == ~t6_pc~0; 8673#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8674#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9031#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 9371#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9402#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9490#L760-45 assume 1 == ~t7_pc~0; 9378#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9379#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8950#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8951#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9510#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9511#L779-45 assume !(1 == ~t8_pc~0); 8386#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 8387#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8411#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 8412#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9491#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9492#L798-45 assume 1 == ~t9_pc~0; 9906#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 9028#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 9416#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 9139#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 9140#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 9042#L817-45 assume 1 == ~t10_pc~0; 9043#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 9627#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 9414#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 8781#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 8678#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8679#L836-45 assume !(1 == ~t11_pc~0); 8183#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 8184#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8952#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 8953#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 9440#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 9513#L855-45 assume 1 == ~t12_pc~0; 8901#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 8348#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8349#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 9273#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 9274#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 8997#L874-45 assume !(1 == ~t13_pc~0); 8998#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 8906#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 8907#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 8499#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 8500#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 9279#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8448#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8449#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8020#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8021#L1446-3 assume !(1 == ~T5_E~0); 9679#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8988#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8603#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8604#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9915#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8553#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8554#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8962#L1486-3 assume !(1 == ~T13_E~0); 8572#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8573#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9017#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9018#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9443#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9434#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9435#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9137#L1526-3 assume !(1 == ~E_7~0); 9138#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9507#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8590#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8591#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8630#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9873#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8167#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8168#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8275#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9632#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 9475#L1946 assume !(0 == start_simulation_~tmp~3); 9200#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9201#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8514#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9889#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 9565#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8002#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 8003#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 8250#L1959 assume !(0 != start_simulation_~tmp___0~1); 8251#L1927-1 [2021-11-02 23:08:46,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:46,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1586891621, now seen corresponding path program 1 times [2021-11-02 23:08:46,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:46,239 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546275405] [2021-11-02 23:08:46,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:46,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:46,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:46,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:46,360 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:46,361 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546275405] [2021-11-02 23:08:46,361 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546275405] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:46,362 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:46,362 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:46,362 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191288810] [2021-11-02 23:08:46,363 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:46,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:46,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1406029510, now seen corresponding path program 1 times [2021-11-02 23:08:46,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:46,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783094916] [2021-11-02 23:08:46,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:46,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:46,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:46,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:46,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:46,514 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783094916] [2021-11-02 23:08:46,514 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783094916] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:46,514 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:46,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:46,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589443673] [2021-11-02 23:08:46,519 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:46,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:46,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:46,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:46,521 INFO L87 Difference]: Start difference. First operand 1986 states and 2955 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:46,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:46,573 INFO L93 Difference]: Finished difference Result 1986 states and 2954 transitions. [2021-11-02 23:08:46,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:46,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2954 transitions. [2021-11-02 23:08:46,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:46,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2954 transitions. [2021-11-02 23:08:46,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:46,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:46,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2954 transitions. [2021-11-02 23:08:46,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:46,629 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-02 23:08:46,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2954 transitions. [2021-11-02 23:08:46,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:46,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.487411883182276) internal successors, (2954), 1985 states have internal predecessors, (2954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:46,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2954 transitions. [2021-11-02 23:08:46,735 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-02 23:08:46,735 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-02 23:08:46,735 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-02 23:08:46,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2954 transitions. [2021-11-02 23:08:46,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:46,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:46,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:46,755 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:46,756 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:46,756 INFO L791 eck$LassoCheckResult]: Stem: 12854#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12855#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13934#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13848#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 13001#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12811#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12812#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12579#L916-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12580#L921-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13003#L926-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13189#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13349#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13370#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12587#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12588#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12315#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12316#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12763#L966-1 assume !(0 == ~M_E~0); 12764#L1278-1 assume !(0 == ~T1_E~0); 13676#L1283-1 assume !(0 == ~T2_E~0); 13677#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13882#L1293-1 assume !(0 == ~T4_E~0); 13870#L1298-1 assume !(0 == ~T5_E~0); 13814#L1303-1 assume !(0 == ~T6_E~0); 12414#L1308-1 assume !(0 == ~T7_E~0); 12338#L1313-1 assume !(0 == ~T8_E~0); 12339#L1318-1 assume !(0 == ~T9_E~0); 12341#L1323-1 assume !(0 == ~T10_E~0); 12342#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12525#L1333-1 assume !(0 == ~T12_E~0); 13487#L1338-1 assume !(0 == ~T13_E~0); 13488#L1343-1 assume !(0 == ~E_M~0); 13630#L1348-1 assume !(0 == ~E_1~0); 13910#L1353-1 assume !(0 == ~E_2~0); 13232#L1358-1 assume !(0 == ~E_3~0); 13233#L1363-1 assume !(0 == ~E_4~0); 13524#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12167#L1373-1 assume !(0 == ~E_6~0); 12168#L1378-1 assume !(0 == ~E_7~0); 12482#L1383-1 assume !(0 == ~E_8~0); 12483#L1388-1 assume !(0 == ~E_9~0); 13561#L1393-1 assume !(0 == ~E_10~0); 13562#L1398-1 assume !(0 == ~E_11~0); 13568#L1403-1 assume !(0 == ~E_12~0); 13812#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 12453#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12454#L627 assume 1 == ~m_pc~0; 13922#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12815#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12816#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13394#L1590 assume !(0 != activate_threads_~tmp~1); 13842#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12383#L646 assume !(1 == ~t1_pc~0); 12384#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 13043#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13051#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 13101#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12256#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12257#L665 assume 1 == ~t2_pc~0; 13904#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12924#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12470#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12471#L1606 assume !(0 != activate_threads_~tmp___1~0); 13026#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13314#L684 assume !(1 == ~t3_pc~0); 13280#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 13281#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13351#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13889#L1614 assume !(0 != activate_threads_~tmp___2~0); 13928#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13913#L703 assume 1 == ~t4_pc~0; 12750#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12611#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13222#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12705#L1622 assume !(0 != activate_threads_~tmp___3~0); 12706#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13746#L722 assume !(1 == ~t5_pc~0); 12662#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 12663#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13011#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 11991#L1630 assume !(0 != activate_threads_~tmp___4~0); 11992#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12203#L741 assume 1 == ~t6_pc~0; 12204#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12508#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12661#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12321#L1638 assume !(0 != activate_threads_~tmp___5~0); 12322#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12635#L760 assume 1 == ~t7_pc~0; 12606#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12607#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12465#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 12466#L1646 assume !(0 != activate_threads_~tmp___6~0); 12842#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12843#L779 assume !(1 == ~t8_pc~0); 12248#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 12097#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12098#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 12500#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13270#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13271#L798 assume 1 == ~t9_pc~0; 13773#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 13711#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12249#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 12250#L1662 assume !(0 != activate_threads_~tmp___8~0); 12032#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12033#L817 assume !(1 == ~t10_pc~0); 12079#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 12861#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12862#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 12323#L1670 assume !(0 != activate_threads_~tmp___9~0); 12324#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 13223#L836 assume 1 == ~t11_pc~0; 13224#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 12422#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12423#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 12386#L1678 assume !(0 != activate_threads_~tmp___10~0); 12387#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 13721#L855 assume !(1 == ~t12_pc~0); 13048#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 13049#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 13602#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 13627#L1686 assume !(0 != activate_threads_~tmp___11~0); 13567#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 12372#L874 assume 1 == ~t13_pc~0; 12373#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 12534#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 12535#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 12664#L1694 assume !(0 != activate_threads_~tmp___12~0); 13694#L1694-2 assume !(1 == ~M_E~0); 12577#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12578#L1431-1 assume !(1 == ~T2_E~0); 12099#L1436-1 assume !(1 == ~T3_E~0); 12100#L1441-1 assume !(1 == ~T4_E~0); 12892#L1446-1 assume !(1 == ~T5_E~0); 12893#L1451-1 assume !(1 == ~T6_E~0); 13628#L1456-1 assume !(1 == ~T7_E~0); 13264#L1461-1 assume !(1 == ~T8_E~0); 12807#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12808#L1471-1 assume !(1 == ~T10_E~0); 13603#L1476-1 assume !(1 == ~T11_E~0); 13604#L1481-1 assume !(1 == ~T12_E~0); 13769#L1486-1 assume !(1 == ~T13_E~0); 12426#L1491-1 assume !(1 == ~E_M~0); 12041#L1496-1 assume !(1 == ~E_1~0); 12042#L1501-1 assume !(1 == ~E_2~0); 12887#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 12888#L1511-1 assume !(1 == ~E_4~0); 12841#L1516-1 assume !(1 == ~E_5~0); 11995#L1521-1 assume !(1 == ~E_6~0); 11996#L1526-1 assume !(1 == ~E_7~0); 12040#L1531-1 assume !(1 == ~E_8~0); 12598#L1536-1 assume !(1 == ~E_9~0); 12317#L1541-1 assume !(1 == ~E_10~0); 12318#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 13823#L1551-1 assume !(1 == ~E_12~0); 12487#L1556-1 assume !(1 == ~E_13~0); 12230#L1927-1 [2021-11-02 23:08:46,757 INFO L793 eck$LassoCheckResult]: Loop: 12230#L1927-1 assume !false; 12511#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 12522#L1253 assume !false; 11983#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 11984#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12670#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12593#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12594#L1066 assume !(0 != eval_~tmp~0); 13827#L1268 start_simulation_~kernel_st~0 := 2; 12336#L894-1 start_simulation_~kernel_st~0 := 3; 12337#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12902#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12903#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12502#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12503#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13688#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13689#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L1308-3 assume !(0 == ~T7_E~0); 13683#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13145#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12289#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12290#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13763#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12436#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12437#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13575#L1348-3 assume !(0 == ~E_1~0); 13767#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13768#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13107#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12622#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12623#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13423#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13424#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13621#L1388-3 assume !(0 == ~E_9~0); 13608#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13609#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12953#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12954#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13775#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12800#L627-45 assume !(1 == ~m_pc~0); 12801#L627-47 is_master_triggered_~__retres1~0 := 0; 13297#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13765#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13128#L1590-45 assume !(0 != activate_threads_~tmp~1); 13129#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13725#L646-45 assume 1 == ~t1_pc~0; 13796#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12991#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13175#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 13176#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12407#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12408#L665-45 assume 1 == ~t2_pc~0; 12081#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12082#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12908#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12108#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12109#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13329#L684-45 assume 1 == ~t3_pc~0; 13330#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12405#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13481#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13832#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13629#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13434#L703-45 assume 1 == ~t4_pc~0; 13273#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13275#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12868#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12562#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12563#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12899#L722-45 assume 1 == ~t5_pc~0; 12889#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12890#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13840#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 13890#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13255#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13256#L741-45 assume 1 == ~t6_pc~0; 12652#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12653#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13010#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 13350#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13381#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13469#L760-45 assume 1 == ~t7_pc~0; 13357#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13358#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12929#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 12930#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13489#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13490#L779-45 assume 1 == ~t8_pc~0; 13441#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12366#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12390#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 12391#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13470#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13471#L798-45 assume 1 == ~t9_pc~0; 13885#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 13007#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 13395#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 13118#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 13119#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 13021#L817-45 assume 1 == ~t10_pc~0; 13022#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 13606#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 13393#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 12760#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 12657#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12658#L836-45 assume !(1 == ~t11_pc~0); 12162#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 12163#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12931#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 12932#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 13419#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 13492#L855-45 assume 1 == ~t12_pc~0; 12880#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 12327#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 12328#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 13252#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 13253#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 12976#L874-45 assume !(1 == ~t13_pc~0); 12977#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 12885#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 12886#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 12478#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 12479#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 13258#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12427#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12428#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11999#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12000#L1446-3 assume !(1 == ~T5_E~0); 13658#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12967#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12582#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12583#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13894#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12532#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12533#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12941#L1486-3 assume !(1 == ~T13_E~0); 12551#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12552#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12996#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12997#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13422#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13413#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13414#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13116#L1526-3 assume !(1 == ~E_7~0); 13117#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13486#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12569#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12570#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12609#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13852#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12146#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 12147#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12254#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13611#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 13454#L1946 assume !(0 == start_simulation_~tmp~3); 13179#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13180#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12493#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13868#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 13544#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11981#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 11982#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 12229#L1959 assume !(0 != start_simulation_~tmp___0~1); 12230#L1927-1 [2021-11-02 23:08:46,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:46,759 INFO L85 PathProgramCache]: Analyzing trace with hash 140310755, now seen corresponding path program 1 times [2021-11-02 23:08:46,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:46,759 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551769656] [2021-11-02 23:08:46,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:46,761 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:46,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:46,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:46,842 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:46,842 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551769656] [2021-11-02 23:08:46,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551769656] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:46,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:46,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:46,845 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388125034] [2021-11-02 23:08:46,845 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:46,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:46,846 INFO L85 PathProgramCache]: Analyzing trace with hash -880887971, now seen corresponding path program 1 times [2021-11-02 23:08:46,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:46,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392123680] [2021-11-02 23:08:46,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:46,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:46,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:46,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:46,931 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:46,932 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392123680] [2021-11-02 23:08:46,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392123680] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:46,933 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:46,934 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:46,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586229618] [2021-11-02 23:08:46,936 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:46,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:46,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:46,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:46,943 INFO L87 Difference]: Start difference. First operand 1986 states and 2954 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:46,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:46,985 INFO L93 Difference]: Finished difference Result 1986 states and 2953 transitions. [2021-11-02 23:08:46,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:46,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2953 transitions. [2021-11-02 23:08:47,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2953 transitions. [2021-11-02 23:08:47,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:47,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:47,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2953 transitions. [2021-11-02 23:08:47,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:47,036 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-02 23:08:47,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2953 transitions. [2021-11-02 23:08:47,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:47,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.486908358509567) internal successors, (2953), 1985 states have internal predecessors, (2953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:47,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2953 transitions. [2021-11-02 23:08:47,092 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-02 23:08:47,092 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-02 23:08:47,092 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-02 23:08:47,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2953 transitions. [2021-11-02 23:08:47,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,108 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:47,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:47,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,114 INFO L791 eck$LassoCheckResult]: Stem: 16833#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16834#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17913#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17827#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 16980#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16790#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16791#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16558#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16559#L921-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16982#L926-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17168#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17328#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17349#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16566#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16567#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16294#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16295#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16742#L966-1 assume !(0 == ~M_E~0); 16743#L1278-1 assume !(0 == ~T1_E~0); 17655#L1283-1 assume !(0 == ~T2_E~0); 17656#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17861#L1293-1 assume !(0 == ~T4_E~0); 17849#L1298-1 assume !(0 == ~T5_E~0); 17793#L1303-1 assume !(0 == ~T6_E~0); 16393#L1308-1 assume !(0 == ~T7_E~0); 16317#L1313-1 assume !(0 == ~T8_E~0); 16318#L1318-1 assume !(0 == ~T9_E~0); 16320#L1323-1 assume !(0 == ~T10_E~0); 16321#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16504#L1333-1 assume !(0 == ~T12_E~0); 17466#L1338-1 assume !(0 == ~T13_E~0); 17467#L1343-1 assume !(0 == ~E_M~0); 17609#L1348-1 assume !(0 == ~E_1~0); 17889#L1353-1 assume !(0 == ~E_2~0); 17211#L1358-1 assume !(0 == ~E_3~0); 17212#L1363-1 assume !(0 == ~E_4~0); 17503#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 16146#L1373-1 assume !(0 == ~E_6~0); 16147#L1378-1 assume !(0 == ~E_7~0); 16461#L1383-1 assume !(0 == ~E_8~0); 16462#L1388-1 assume !(0 == ~E_9~0); 17540#L1393-1 assume !(0 == ~E_10~0); 17541#L1398-1 assume !(0 == ~E_11~0); 17547#L1403-1 assume !(0 == ~E_12~0); 17791#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 16432#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16433#L627 assume 1 == ~m_pc~0; 17901#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16794#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16795#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 17373#L1590 assume !(0 != activate_threads_~tmp~1); 17821#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16362#L646 assume !(1 == ~t1_pc~0); 16363#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 17022#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17030#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 17080#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16235#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16236#L665 assume 1 == ~t2_pc~0; 17883#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16903#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16449#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16450#L1606 assume !(0 != activate_threads_~tmp___1~0); 17005#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17293#L684 assume !(1 == ~t3_pc~0); 17259#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 17260#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17330#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 17868#L1614 assume !(0 != activate_threads_~tmp___2~0); 17907#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17892#L703 assume 1 == ~t4_pc~0; 16729#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16590#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17201#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16684#L1622 assume !(0 != activate_threads_~tmp___3~0); 16685#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17725#L722 assume !(1 == ~t5_pc~0); 16641#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 16642#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16990#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 15970#L1630 assume !(0 != activate_threads_~tmp___4~0); 15971#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16182#L741 assume 1 == ~t6_pc~0; 16183#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16487#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16640#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16300#L1638 assume !(0 != activate_threads_~tmp___5~0); 16301#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16614#L760 assume 1 == ~t7_pc~0; 16585#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16586#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16444#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 16445#L1646 assume !(0 != activate_threads_~tmp___6~0); 16821#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16822#L779 assume !(1 == ~t8_pc~0); 16227#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 16076#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16077#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 16479#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17249#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17250#L798 assume 1 == ~t9_pc~0; 17752#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 17690#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16228#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 16229#L1662 assume !(0 != activate_threads_~tmp___8~0); 16011#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 16012#L817 assume !(1 == ~t10_pc~0); 16058#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 16840#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 16841#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 16302#L1670 assume !(0 != activate_threads_~tmp___9~0); 16303#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 17202#L836 assume 1 == ~t11_pc~0; 17203#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 16401#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 16402#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 16365#L1678 assume !(0 != activate_threads_~tmp___10~0); 16366#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 17700#L855 assume !(1 == ~t12_pc~0); 17027#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 17028#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 17581#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 17606#L1686 assume !(0 != activate_threads_~tmp___11~0); 17546#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 16351#L874 assume 1 == ~t13_pc~0; 16352#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 16513#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 16514#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 16643#L1694 assume !(0 != activate_threads_~tmp___12~0); 17673#L1694-2 assume !(1 == ~M_E~0); 16556#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16557#L1431-1 assume !(1 == ~T2_E~0); 16078#L1436-1 assume !(1 == ~T3_E~0); 16079#L1441-1 assume !(1 == ~T4_E~0); 16871#L1446-1 assume !(1 == ~T5_E~0); 16872#L1451-1 assume !(1 == ~T6_E~0); 17607#L1456-1 assume !(1 == ~T7_E~0); 17243#L1461-1 assume !(1 == ~T8_E~0); 16786#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16787#L1471-1 assume !(1 == ~T10_E~0); 17582#L1476-1 assume !(1 == ~T11_E~0); 17583#L1481-1 assume !(1 == ~T12_E~0); 17748#L1486-1 assume !(1 == ~T13_E~0); 16405#L1491-1 assume !(1 == ~E_M~0); 16020#L1496-1 assume !(1 == ~E_1~0); 16021#L1501-1 assume !(1 == ~E_2~0); 16866#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 16867#L1511-1 assume !(1 == ~E_4~0); 16820#L1516-1 assume !(1 == ~E_5~0); 15974#L1521-1 assume !(1 == ~E_6~0); 15975#L1526-1 assume !(1 == ~E_7~0); 16019#L1531-1 assume !(1 == ~E_8~0); 16577#L1536-1 assume !(1 == ~E_9~0); 16296#L1541-1 assume !(1 == ~E_10~0); 16297#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 17802#L1551-1 assume !(1 == ~E_12~0); 16466#L1556-1 assume !(1 == ~E_13~0); 16209#L1927-1 [2021-11-02 23:08:47,114 INFO L793 eck$LassoCheckResult]: Loop: 16209#L1927-1 assume !false; 16490#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 16501#L1253 assume !false; 15962#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 15963#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16649#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16572#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16573#L1066 assume !(0 != eval_~tmp~0); 17806#L1268 start_simulation_~kernel_st~0 := 2; 16315#L894-1 start_simulation_~kernel_st~0 := 3; 16316#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16881#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16882#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16481#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16482#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17667#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17668#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17810#L1308-3 assume !(0 == ~T7_E~0); 17662#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17124#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16268#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16269#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17742#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16415#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16416#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17554#L1348-3 assume !(0 == ~E_1~0); 17746#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17747#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17086#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16601#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16602#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17402#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17403#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17600#L1388-3 assume !(0 == ~E_9~0); 17587#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17588#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16932#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16933#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17754#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16779#L627-45 assume !(1 == ~m_pc~0); 16780#L627-47 is_master_triggered_~__retres1~0 := 0; 17276#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17744#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 17107#L1590-45 assume !(0 != activate_threads_~tmp~1); 17108#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17704#L646-45 assume !(1 == ~t1_pc~0); 16969#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 16970#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17154#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 17155#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16386#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16387#L665-45 assume 1 == ~t2_pc~0; 16060#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16061#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16887#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16087#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16088#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17308#L684-45 assume 1 == ~t3_pc~0; 17309#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16384#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17460#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 17811#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17608#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17413#L703-45 assume 1 == ~t4_pc~0; 17252#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17254#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16847#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16541#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16542#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16878#L722-45 assume 1 == ~t5_pc~0; 16868#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16869#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17819#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 17869#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17234#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17235#L741-45 assume 1 == ~t6_pc~0; 16631#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16632#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16989#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 17329#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17360#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17448#L760-45 assume 1 == ~t7_pc~0; 17336#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17337#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16908#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 16909#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17468#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17469#L779-45 assume !(1 == ~t8_pc~0); 16344#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 16345#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16369#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 16370#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17449#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17450#L798-45 assume 1 == ~t9_pc~0; 17864#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 16986#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 17374#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 17097#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 17098#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 17000#L817-45 assume 1 == ~t10_pc~0; 17001#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 17585#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 17372#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 16739#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 16636#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 16637#L836-45 assume !(1 == ~t11_pc~0); 16141#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 16142#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 16910#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 16911#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 17398#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 17471#L855-45 assume 1 == ~t12_pc~0; 16859#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 16306#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 16307#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 17231#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 17232#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 16955#L874-45 assume !(1 == ~t13_pc~0); 16956#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 16864#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 16865#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 16457#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 16458#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 17237#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16406#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16407#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15978#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15979#L1446-3 assume !(1 == ~T5_E~0); 17637#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16946#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16561#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16562#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17873#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16511#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16512#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16920#L1486-3 assume !(1 == ~T13_E~0); 16530#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16531#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16975#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16976#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17401#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17392#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17393#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17095#L1526-3 assume !(1 == ~E_7~0); 17096#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17465#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16548#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16549#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16588#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17831#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16125#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 16126#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16233#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17590#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 17433#L1946 assume !(0 == start_simulation_~tmp~3); 17158#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17159#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16472#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17847#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 17523#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15960#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 15961#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 16208#L1959 assume !(0 != start_simulation_~tmp___0~1); 16209#L1927-1 [2021-11-02 23:08:47,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1063478181, now seen corresponding path program 1 times [2021-11-02 23:08:47,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,117 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490604109] [2021-11-02 23:08:47,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:47,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:47,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:47,171 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:47,171 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490604109] [2021-11-02 23:08:47,171 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [490604109] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:47,172 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:47,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:47,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322578539] [2021-11-02 23:08:47,173 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:47,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1679024933, now seen corresponding path program 2 times [2021-11-02 23:08:47,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,174 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486204052] [2021-11-02 23:08:47,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,175 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:47,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:47,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:47,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:47,308 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486204052] [2021-11-02 23:08:47,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486204052] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:47,309 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:47,309 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:47,310 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037056011] [2021-11-02 23:08:47,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:47,311 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:47,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:47,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:47,312 INFO L87 Difference]: Start difference. First operand 1986 states and 2953 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:47,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:47,365 INFO L93 Difference]: Finished difference Result 1986 states and 2952 transitions. [2021-11-02 23:08:47,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:47,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2952 transitions. [2021-11-02 23:08:47,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2952 transitions. [2021-11-02 23:08:47,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:47,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:47,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2952 transitions. [2021-11-02 23:08:47,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:47,410 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-02 23:08:47,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2952 transitions. [2021-11-02 23:08:47,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:47,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.486404833836858) internal successors, (2952), 1985 states have internal predecessors, (2952), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:47,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2952 transitions. [2021-11-02 23:08:47,466 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-02 23:08:47,466 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-02 23:08:47,466 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-02 23:08:47,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2952 transitions. [2021-11-02 23:08:47,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:47,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:47,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,485 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,486 INFO L791 eck$LassoCheckResult]: Stem: 20812#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20813#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21892#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21806#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 20959#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20769#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20770#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20537#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20538#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20961#L926-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21147#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21307#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21328#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20545#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20546#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20273#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20274#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20721#L966-1 assume !(0 == ~M_E~0); 20722#L1278-1 assume !(0 == ~T1_E~0); 21634#L1283-1 assume !(0 == ~T2_E~0); 21635#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21840#L1293-1 assume !(0 == ~T4_E~0); 21828#L1298-1 assume !(0 == ~T5_E~0); 21772#L1303-1 assume !(0 == ~T6_E~0); 20372#L1308-1 assume !(0 == ~T7_E~0); 20296#L1313-1 assume !(0 == ~T8_E~0); 20297#L1318-1 assume !(0 == ~T9_E~0); 20299#L1323-1 assume !(0 == ~T10_E~0); 20300#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20483#L1333-1 assume !(0 == ~T12_E~0); 21445#L1338-1 assume !(0 == ~T13_E~0); 21446#L1343-1 assume !(0 == ~E_M~0); 21588#L1348-1 assume !(0 == ~E_1~0); 21868#L1353-1 assume !(0 == ~E_2~0); 21190#L1358-1 assume !(0 == ~E_3~0); 21191#L1363-1 assume !(0 == ~E_4~0); 21482#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20125#L1373-1 assume !(0 == ~E_6~0); 20126#L1378-1 assume !(0 == ~E_7~0); 20440#L1383-1 assume !(0 == ~E_8~0); 20441#L1388-1 assume !(0 == ~E_9~0); 21519#L1393-1 assume !(0 == ~E_10~0); 21520#L1398-1 assume !(0 == ~E_11~0); 21526#L1403-1 assume !(0 == ~E_12~0); 21770#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 20411#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20412#L627 assume 1 == ~m_pc~0; 21880#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 20773#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20774#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21352#L1590 assume !(0 != activate_threads_~tmp~1); 21800#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20341#L646 assume !(1 == ~t1_pc~0); 20342#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 21001#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21009#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21059#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20214#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20215#L665 assume 1 == ~t2_pc~0; 21862#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20882#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20428#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20429#L1606 assume !(0 != activate_threads_~tmp___1~0); 20984#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21272#L684 assume !(1 == ~t3_pc~0); 21238#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 21239#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21309#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21847#L1614 assume !(0 != activate_threads_~tmp___2~0); 21886#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21871#L703 assume 1 == ~t4_pc~0; 20708#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20569#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21180#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20663#L1622 assume !(0 != activate_threads_~tmp___3~0); 20664#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21704#L722 assume !(1 == ~t5_pc~0); 20620#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 20621#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20969#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 19949#L1630 assume !(0 != activate_threads_~tmp___4~0); 19950#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20161#L741 assume 1 == ~t6_pc~0; 20162#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20466#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20619#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20279#L1638 assume !(0 != activate_threads_~tmp___5~0); 20280#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20593#L760 assume 1 == ~t7_pc~0; 20564#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20565#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20423#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20424#L1646 assume !(0 != activate_threads_~tmp___6~0); 20800#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20801#L779 assume !(1 == ~t8_pc~0); 20206#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 20055#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20056#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 20458#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21228#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21229#L798 assume 1 == ~t9_pc~0; 21731#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 21669#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20207#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 20208#L1662 assume !(0 != activate_threads_~tmp___8~0); 19990#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 19991#L817 assume !(1 == ~t10_pc~0); 20037#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 20819#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20820#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 20281#L1670 assume !(0 != activate_threads_~tmp___9~0); 20282#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 21181#L836 assume 1 == ~t11_pc~0; 21182#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 20380#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 20381#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 20344#L1678 assume !(0 != activate_threads_~tmp___10~0); 20345#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 21679#L855 assume !(1 == ~t12_pc~0); 21006#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 21007#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 21560#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 21585#L1686 assume !(0 != activate_threads_~tmp___11~0); 21525#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 20330#L874 assume 1 == ~t13_pc~0; 20331#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 20492#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 20493#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 20622#L1694 assume !(0 != activate_threads_~tmp___12~0); 21652#L1694-2 assume !(1 == ~M_E~0); 20535#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20536#L1431-1 assume !(1 == ~T2_E~0); 20057#L1436-1 assume !(1 == ~T3_E~0); 20058#L1441-1 assume !(1 == ~T4_E~0); 20850#L1446-1 assume !(1 == ~T5_E~0); 20851#L1451-1 assume !(1 == ~T6_E~0); 21586#L1456-1 assume !(1 == ~T7_E~0); 21222#L1461-1 assume !(1 == ~T8_E~0); 20765#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20766#L1471-1 assume !(1 == ~T10_E~0); 21561#L1476-1 assume !(1 == ~T11_E~0); 21562#L1481-1 assume !(1 == ~T12_E~0); 21727#L1486-1 assume !(1 == ~T13_E~0); 20384#L1491-1 assume !(1 == ~E_M~0); 19999#L1496-1 assume !(1 == ~E_1~0); 20000#L1501-1 assume !(1 == ~E_2~0); 20845#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 20846#L1511-1 assume !(1 == ~E_4~0); 20799#L1516-1 assume !(1 == ~E_5~0); 19953#L1521-1 assume !(1 == ~E_6~0); 19954#L1526-1 assume !(1 == ~E_7~0); 19998#L1531-1 assume !(1 == ~E_8~0); 20556#L1536-1 assume !(1 == ~E_9~0); 20275#L1541-1 assume !(1 == ~E_10~0); 20276#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 21781#L1551-1 assume !(1 == ~E_12~0); 20445#L1556-1 assume !(1 == ~E_13~0); 20188#L1927-1 [2021-11-02 23:08:47,486 INFO L793 eck$LassoCheckResult]: Loop: 20188#L1927-1 assume !false; 20469#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 20480#L1253 assume !false; 19941#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 19942#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20628#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20551#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 20552#L1066 assume !(0 != eval_~tmp~0); 21785#L1268 start_simulation_~kernel_st~0 := 2; 20294#L894-1 start_simulation_~kernel_st~0 := 3; 20295#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20860#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20861#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20460#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20461#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21646#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21647#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21789#L1308-3 assume !(0 == ~T7_E~0); 21641#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21103#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20247#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20248#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21721#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20394#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20395#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21533#L1348-3 assume !(0 == ~E_1~0); 21725#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21726#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21065#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20580#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20581#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21381#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21382#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21579#L1388-3 assume !(0 == ~E_9~0); 21566#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21567#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20911#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20912#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21733#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20758#L627-45 assume !(1 == ~m_pc~0); 20759#L627-47 is_master_triggered_~__retres1~0 := 0; 21255#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21723#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21086#L1590-45 assume !(0 != activate_threads_~tmp~1); 21087#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21683#L646-45 assume !(1 == ~t1_pc~0); 20948#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 20949#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21133#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21134#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20365#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20366#L665-45 assume 1 == ~t2_pc~0; 20039#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20040#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20866#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20066#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20067#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21287#L684-45 assume 1 == ~t3_pc~0; 21288#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20363#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21439#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21790#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21587#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21392#L703-45 assume !(1 == ~t4_pc~0); 21232#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 21233#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20826#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20520#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20521#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20857#L722-45 assume !(1 == ~t5_pc~0); 20849#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 20848#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21798#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 21848#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21213#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21214#L741-45 assume 1 == ~t6_pc~0; 20610#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20611#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20968#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 21308#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21339#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21427#L760-45 assume 1 == ~t7_pc~0; 21315#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21316#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20887#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20888#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21447#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21448#L779-45 assume !(1 == ~t8_pc~0); 20323#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 20324#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20348#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 20349#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21428#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21429#L798-45 assume 1 == ~t9_pc~0; 21843#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 20965#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21353#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 21076#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 21077#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 20979#L817-45 assume 1 == ~t10_pc~0; 20980#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 21564#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21351#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 20718#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 20615#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20616#L836-45 assume !(1 == ~t11_pc~0); 20120#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 20121#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 20889#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 20890#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 21377#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 21450#L855-45 assume 1 == ~t12_pc~0; 20838#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 20285#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 20286#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 21210#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 21211#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 20934#L874-45 assume !(1 == ~t13_pc~0); 20935#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 20843#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 20844#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 20436#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 20437#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 21216#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20385#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20386#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19957#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19958#L1446-3 assume !(1 == ~T5_E~0); 21616#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20925#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20540#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20541#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21852#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20490#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20491#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20899#L1486-3 assume !(1 == ~T13_E~0); 20509#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20510#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20954#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20955#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21380#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21371#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21372#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21074#L1526-3 assume !(1 == ~E_7~0); 21075#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21444#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20527#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20528#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20567#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21810#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20104#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 20105#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20212#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21569#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 21412#L1946 assume !(0 == start_simulation_~tmp~3); 21137#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21138#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20451#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21826#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 21502#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19939#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 19940#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 20187#L1959 assume !(0 != start_simulation_~tmp___0~1); 20188#L1927-1 [2021-11-02 23:08:47,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,487 INFO L85 PathProgramCache]: Analyzing trace with hash 677615779, now seen corresponding path program 1 times [2021-11-02 23:08:47,488 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,488 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373971365] [2021-11-02 23:08:47,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:47,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:47,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:47,540 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:47,540 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373971365] [2021-11-02 23:08:47,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373971365] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:47,541 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:47,541 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:47,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980645350] [2021-11-02 23:08:47,543 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:47,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1885880921, now seen corresponding path program 1 times [2021-11-02 23:08:47,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,545 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900734937] [2021-11-02 23:08:47,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:47,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:47,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:47,645 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:47,646 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900734937] [2021-11-02 23:08:47,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900734937] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:47,646 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:47,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:47,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146329691] [2021-11-02 23:08:47,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:47,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:47,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:47,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:47,657 INFO L87 Difference]: Start difference. First operand 1986 states and 2952 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:47,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:47,714 INFO L93 Difference]: Finished difference Result 1986 states and 2951 transitions. [2021-11-02 23:08:47,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:47,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2951 transitions. [2021-11-02 23:08:47,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2951 transitions. [2021-11-02 23:08:47,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:47,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:47,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2951 transitions. [2021-11-02 23:08:47,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:47,777 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-02 23:08:47,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2951 transitions. [2021-11-02 23:08:47,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:47,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.485901309164149) internal successors, (2951), 1985 states have internal predecessors, (2951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:47,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2951 transitions. [2021-11-02 23:08:47,855 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-02 23:08:47,855 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-02 23:08:47,856 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-02 23:08:47,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2951 transitions. [2021-11-02 23:08:47,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:47,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:47,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:47,875 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,875 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:47,876 INFO L791 eck$LassoCheckResult]: Stem: 24791#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24792#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25871#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25785#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 24938#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24748#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24749#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24516#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24517#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24940#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25126#L931-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25286#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25307#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24524#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24525#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24252#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24253#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 24700#L966-1 assume !(0 == ~M_E~0); 24701#L1278-1 assume !(0 == ~T1_E~0); 25613#L1283-1 assume !(0 == ~T2_E~0); 25614#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25819#L1293-1 assume !(0 == ~T4_E~0); 25807#L1298-1 assume !(0 == ~T5_E~0); 25751#L1303-1 assume !(0 == ~T6_E~0); 24351#L1308-1 assume !(0 == ~T7_E~0); 24275#L1313-1 assume !(0 == ~T8_E~0); 24276#L1318-1 assume !(0 == ~T9_E~0); 24278#L1323-1 assume !(0 == ~T10_E~0); 24279#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24462#L1333-1 assume !(0 == ~T12_E~0); 25424#L1338-1 assume !(0 == ~T13_E~0); 25425#L1343-1 assume !(0 == ~E_M~0); 25567#L1348-1 assume !(0 == ~E_1~0); 25847#L1353-1 assume !(0 == ~E_2~0); 25169#L1358-1 assume !(0 == ~E_3~0); 25170#L1363-1 assume !(0 == ~E_4~0); 25461#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 24104#L1373-1 assume !(0 == ~E_6~0); 24105#L1378-1 assume !(0 == ~E_7~0); 24419#L1383-1 assume !(0 == ~E_8~0); 24420#L1388-1 assume !(0 == ~E_9~0); 25498#L1393-1 assume !(0 == ~E_10~0); 25499#L1398-1 assume !(0 == ~E_11~0); 25505#L1403-1 assume !(0 == ~E_12~0); 25749#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 24390#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24391#L627 assume 1 == ~m_pc~0; 25859#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 24752#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24753#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 25331#L1590 assume !(0 != activate_threads_~tmp~1); 25779#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24320#L646 assume !(1 == ~t1_pc~0); 24321#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 24980#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24988#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 25038#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24193#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24194#L665 assume 1 == ~t2_pc~0; 25841#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 24861#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24407#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24408#L1606 assume !(0 != activate_threads_~tmp___1~0); 24963#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25251#L684 assume !(1 == ~t3_pc~0); 25217#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 25218#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25288#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25826#L1614 assume !(0 != activate_threads_~tmp___2~0); 25865#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25850#L703 assume 1 == ~t4_pc~0; 24687#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 24548#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25159#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 24642#L1622 assume !(0 != activate_threads_~tmp___3~0); 24643#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25683#L722 assume !(1 == ~t5_pc~0); 24599#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 24600#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24948#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 23928#L1630 assume !(0 != activate_threads_~tmp___4~0); 23929#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 24140#L741 assume 1 == ~t6_pc~0; 24141#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 24445#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 24598#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24258#L1638 assume !(0 != activate_threads_~tmp___5~0); 24259#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24572#L760 assume 1 == ~t7_pc~0; 24543#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 24544#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24402#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 24403#L1646 assume !(0 != activate_threads_~tmp___6~0); 24779#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24780#L779 assume !(1 == ~t8_pc~0); 24185#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 24034#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24035#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 24437#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25207#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 25208#L798 assume 1 == ~t9_pc~0; 25710#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 25648#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 24186#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 24187#L1662 assume !(0 != activate_threads_~tmp___8~0); 23969#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 23970#L817 assume !(1 == ~t10_pc~0); 24016#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 24798#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24799#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 24260#L1670 assume !(0 != activate_threads_~tmp___9~0); 24261#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 25160#L836 assume 1 == ~t11_pc~0; 25161#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 24359#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24360#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 24323#L1678 assume !(0 != activate_threads_~tmp___10~0); 24324#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 25658#L855 assume !(1 == ~t12_pc~0); 24985#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 24986#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 25539#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 25564#L1686 assume !(0 != activate_threads_~tmp___11~0); 25504#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 24309#L874 assume 1 == ~t13_pc~0; 24310#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 24471#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 24472#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 24601#L1694 assume !(0 != activate_threads_~tmp___12~0); 25631#L1694-2 assume !(1 == ~M_E~0); 24514#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24515#L1431-1 assume !(1 == ~T2_E~0); 24036#L1436-1 assume !(1 == ~T3_E~0); 24037#L1441-1 assume !(1 == ~T4_E~0); 24829#L1446-1 assume !(1 == ~T5_E~0); 24830#L1451-1 assume !(1 == ~T6_E~0); 25565#L1456-1 assume !(1 == ~T7_E~0); 25201#L1461-1 assume !(1 == ~T8_E~0); 24744#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24745#L1471-1 assume !(1 == ~T10_E~0); 25540#L1476-1 assume !(1 == ~T11_E~0); 25541#L1481-1 assume !(1 == ~T12_E~0); 25706#L1486-1 assume !(1 == ~T13_E~0); 24363#L1491-1 assume !(1 == ~E_M~0); 23978#L1496-1 assume !(1 == ~E_1~0); 23979#L1501-1 assume !(1 == ~E_2~0); 24824#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 24825#L1511-1 assume !(1 == ~E_4~0); 24778#L1516-1 assume !(1 == ~E_5~0); 23932#L1521-1 assume !(1 == ~E_6~0); 23933#L1526-1 assume !(1 == ~E_7~0); 23977#L1531-1 assume !(1 == ~E_8~0); 24535#L1536-1 assume !(1 == ~E_9~0); 24254#L1541-1 assume !(1 == ~E_10~0); 24255#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 25760#L1551-1 assume !(1 == ~E_12~0); 24424#L1556-1 assume !(1 == ~E_13~0); 24167#L1927-1 [2021-11-02 23:08:47,877 INFO L793 eck$LassoCheckResult]: Loop: 24167#L1927-1 assume !false; 24448#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 24459#L1253 assume !false; 23920#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 23921#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24607#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 24530#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 24531#L1066 assume !(0 != eval_~tmp~0); 25764#L1268 start_simulation_~kernel_st~0 := 2; 24273#L894-1 start_simulation_~kernel_st~0 := 3; 24274#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 24839#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24840#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24439#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24440#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25625#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25626#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25768#L1308-3 assume !(0 == ~T7_E~0); 25620#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25082#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24226#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24227#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25700#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24373#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 24374#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25512#L1348-3 assume !(0 == ~E_1~0); 25704#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25705#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25044#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24559#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24560#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25360#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25361#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25558#L1388-3 assume !(0 == ~E_9~0); 25545#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25546#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24890#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24891#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25712#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24737#L627-45 assume !(1 == ~m_pc~0); 24738#L627-47 is_master_triggered_~__retres1~0 := 0; 25234#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25702#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 25065#L1590-45 assume !(0 != activate_threads_~tmp~1); 25066#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25662#L646-45 assume 1 == ~t1_pc~0; 25733#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24928#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25112#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 25113#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24344#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24345#L665-45 assume 1 == ~t2_pc~0; 24018#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 24019#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24845#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24045#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 24046#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25266#L684-45 assume 1 == ~t3_pc~0; 25267#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 24342#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25418#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 25769#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25566#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25371#L703-45 assume 1 == ~t4_pc~0; 25210#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25212#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24805#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 24499#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 24500#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24836#L722-45 assume 1 == ~t5_pc~0; 24826#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 24827#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25777#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 25827#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25192#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25193#L741-45 assume 1 == ~t6_pc~0; 24589#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 24590#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 24947#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 25287#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25318#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25406#L760-45 assume !(1 == ~t7_pc~0); 25296#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 25295#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24866#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 24867#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25426#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25427#L779-45 assume 1 == ~t8_pc~0; 25378#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 24303#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24327#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 24328#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25407#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 25408#L798-45 assume 1 == ~t9_pc~0; 25822#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 24944#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 25332#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 25055#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 25056#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24958#L817-45 assume !(1 == ~t10_pc~0); 24960#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 25543#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 25330#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 24697#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 24594#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 24595#L836-45 assume !(1 == ~t11_pc~0); 24099#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 24100#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24868#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 24869#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 25356#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 25429#L855-45 assume 1 == ~t12_pc~0; 24817#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 24264#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 24265#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 25189#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 25190#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 24913#L874-45 assume !(1 == ~t13_pc~0); 24914#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 24822#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 24823#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 24415#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 24416#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 25195#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24364#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24365#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23936#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23937#L1446-3 assume !(1 == ~T5_E~0); 25595#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24904#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24519#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24520#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25831#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24469#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24470#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24878#L1486-3 assume !(1 == ~T13_E~0); 24488#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24489#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24933#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24934#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25359#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25350#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25351#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25053#L1526-3 assume !(1 == ~E_7~0); 25054#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25423#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24506#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24507#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24546#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25789#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24083#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 24084#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24191#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25548#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 25391#L1946 assume !(0 == start_simulation_~tmp~3); 25116#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25117#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24430#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25805#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 25481#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23918#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 23919#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 24166#L1959 assume !(0 != start_simulation_~tmp___0~1); 24167#L1927-1 [2021-11-02 23:08:47,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,878 INFO L85 PathProgramCache]: Analyzing trace with hash 942263269, now seen corresponding path program 1 times [2021-11-02 23:08:47,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,879 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368484539] [2021-11-02 23:08:47,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:47,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:47,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:47,940 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:47,941 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368484539] [2021-11-02 23:08:47,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368484539] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:47,941 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:47,942 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:47,942 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302951182] [2021-11-02 23:08:47,943 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:47,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:47,944 INFO L85 PathProgramCache]: Analyzing trace with hash 2134169307, now seen corresponding path program 1 times [2021-11-02 23:08:47,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:47,944 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996630966] [2021-11-02 23:08:47,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:47,945 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,062 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996630966] [2021-11-02 23:08:48,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996630966] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,062 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363330394] [2021-11-02 23:08:48,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:48,064 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:48,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:48,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:48,065 INFO L87 Difference]: Start difference. First operand 1986 states and 2951 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:48,107 INFO L93 Difference]: Finished difference Result 1986 states and 2950 transitions. [2021-11-02 23:08:48,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:48,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2950 transitions. [2021-11-02 23:08:48,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2950 transitions. [2021-11-02 23:08:48,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:48,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:48,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2950 transitions. [2021-11-02 23:08:48,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:48,154 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-02 23:08:48,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2950 transitions. [2021-11-02 23:08:48,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:48,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.48539778449144) internal successors, (2950), 1985 states have internal predecessors, (2950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2950 transitions. [2021-11-02 23:08:48,210 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-02 23:08:48,210 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-02 23:08:48,210 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-02 23:08:48,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2950 transitions. [2021-11-02 23:08:48,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:48,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:48,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,227 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,227 INFO L791 eck$LassoCheckResult]: Stem: 28770#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28771#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29850#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 29764#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 28917#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28727#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28728#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28495#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28496#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28919#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29105#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29265#L936-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29286#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28503#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28504#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28231#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28232#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 28679#L966-1 assume !(0 == ~M_E~0); 28680#L1278-1 assume !(0 == ~T1_E~0); 29592#L1283-1 assume !(0 == ~T2_E~0); 29593#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29798#L1293-1 assume !(0 == ~T4_E~0); 29786#L1298-1 assume !(0 == ~T5_E~0); 29730#L1303-1 assume !(0 == ~T6_E~0); 28330#L1308-1 assume !(0 == ~T7_E~0); 28254#L1313-1 assume !(0 == ~T8_E~0); 28255#L1318-1 assume !(0 == ~T9_E~0); 28257#L1323-1 assume !(0 == ~T10_E~0); 28258#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28441#L1333-1 assume !(0 == ~T12_E~0); 29403#L1338-1 assume !(0 == ~T13_E~0); 29404#L1343-1 assume !(0 == ~E_M~0); 29546#L1348-1 assume !(0 == ~E_1~0); 29826#L1353-1 assume !(0 == ~E_2~0); 29148#L1358-1 assume !(0 == ~E_3~0); 29149#L1363-1 assume !(0 == ~E_4~0); 29440#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 28083#L1373-1 assume !(0 == ~E_6~0); 28084#L1378-1 assume !(0 == ~E_7~0); 28398#L1383-1 assume !(0 == ~E_8~0); 28399#L1388-1 assume !(0 == ~E_9~0); 29477#L1393-1 assume !(0 == ~E_10~0); 29478#L1398-1 assume !(0 == ~E_11~0); 29484#L1403-1 assume !(0 == ~E_12~0); 29728#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 28369#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28370#L627 assume 1 == ~m_pc~0; 29838#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28731#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28732#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 29310#L1590 assume !(0 != activate_threads_~tmp~1); 29758#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28299#L646 assume !(1 == ~t1_pc~0); 28300#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 28959#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28967#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29017#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28172#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28173#L665 assume 1 == ~t2_pc~0; 29820#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28840#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28386#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28387#L1606 assume !(0 != activate_threads_~tmp___1~0); 28942#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29230#L684 assume !(1 == ~t3_pc~0); 29196#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 29197#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29267#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29805#L1614 assume !(0 != activate_threads_~tmp___2~0); 29844#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29829#L703 assume 1 == ~t4_pc~0; 28666#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28527#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29138#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28621#L1622 assume !(0 != activate_threads_~tmp___3~0); 28622#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29662#L722 assume !(1 == ~t5_pc~0); 28578#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 28579#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28927#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 27907#L1630 assume !(0 != activate_threads_~tmp___4~0); 27908#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28119#L741 assume 1 == ~t6_pc~0; 28120#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 28424#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28577#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 28237#L1638 assume !(0 != activate_threads_~tmp___5~0); 28238#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28551#L760 assume 1 == ~t7_pc~0; 28522#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 28523#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28381#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 28382#L1646 assume !(0 != activate_threads_~tmp___6~0); 28758#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28759#L779 assume !(1 == ~t8_pc~0); 28164#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 28013#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28014#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 28416#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 29186#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 29187#L798 assume 1 == ~t9_pc~0; 29689#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 29627#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28165#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 28166#L1662 assume !(0 != activate_threads_~tmp___8~0); 27948#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 27949#L817 assume !(1 == ~t10_pc~0); 27995#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 28777#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28778#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 28239#L1670 assume !(0 != activate_threads_~tmp___9~0); 28240#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29139#L836 assume 1 == ~t11_pc~0; 29140#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 28338#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28339#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 28302#L1678 assume !(0 != activate_threads_~tmp___10~0); 28303#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 29637#L855 assume !(1 == ~t12_pc~0); 28964#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 28965#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 29518#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 29543#L1686 assume !(0 != activate_threads_~tmp___11~0); 29483#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 28288#L874 assume 1 == ~t13_pc~0; 28289#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 28450#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 28451#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 28580#L1694 assume !(0 != activate_threads_~tmp___12~0); 29610#L1694-2 assume !(1 == ~M_E~0); 28493#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28494#L1431-1 assume !(1 == ~T2_E~0); 28015#L1436-1 assume !(1 == ~T3_E~0); 28016#L1441-1 assume !(1 == ~T4_E~0); 28808#L1446-1 assume !(1 == ~T5_E~0); 28809#L1451-1 assume !(1 == ~T6_E~0); 29544#L1456-1 assume !(1 == ~T7_E~0); 29180#L1461-1 assume !(1 == ~T8_E~0); 28723#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28724#L1471-1 assume !(1 == ~T10_E~0); 29519#L1476-1 assume !(1 == ~T11_E~0); 29520#L1481-1 assume !(1 == ~T12_E~0); 29685#L1486-1 assume !(1 == ~T13_E~0); 28342#L1491-1 assume !(1 == ~E_M~0); 27957#L1496-1 assume !(1 == ~E_1~0); 27958#L1501-1 assume !(1 == ~E_2~0); 28803#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28804#L1511-1 assume !(1 == ~E_4~0); 28757#L1516-1 assume !(1 == ~E_5~0); 27911#L1521-1 assume !(1 == ~E_6~0); 27912#L1526-1 assume !(1 == ~E_7~0); 27956#L1531-1 assume !(1 == ~E_8~0); 28514#L1536-1 assume !(1 == ~E_9~0); 28233#L1541-1 assume !(1 == ~E_10~0); 28234#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 29739#L1551-1 assume !(1 == ~E_12~0); 28403#L1556-1 assume !(1 == ~E_13~0); 28146#L1927-1 [2021-11-02 23:08:48,228 INFO L793 eck$LassoCheckResult]: Loop: 28146#L1927-1 assume !false; 28427#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 28438#L1253 assume !false; 27899#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 27900#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28586#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 28509#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 28510#L1066 assume !(0 != eval_~tmp~0); 29743#L1268 start_simulation_~kernel_st~0 := 2; 28252#L894-1 start_simulation_~kernel_st~0 := 3; 28253#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28818#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28819#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28418#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28419#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29604#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29605#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29747#L1308-3 assume !(0 == ~T7_E~0); 29599#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29061#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28205#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28206#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29679#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28352#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 28353#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29491#L1348-3 assume !(0 == ~E_1~0); 29683#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29684#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29023#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28538#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28539#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29339#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29340#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29537#L1388-3 assume !(0 == ~E_9~0); 29524#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29525#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28869#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28870#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29691#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28716#L627-45 assume !(1 == ~m_pc~0); 28717#L627-47 is_master_triggered_~__retres1~0 := 0; 29213#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29681#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 29044#L1590-45 assume !(0 != activate_threads_~tmp~1); 29045#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29641#L646-45 assume 1 == ~t1_pc~0; 29712#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 28907#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29091#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29092#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28323#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28324#L665-45 assume 1 == ~t2_pc~0; 27997#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 27998#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28824#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28024#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28025#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29245#L684-45 assume !(1 == ~t3_pc~0); 28320#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 28321#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29397#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29748#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29545#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29350#L703-45 assume 1 == ~t4_pc~0; 29189#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 29191#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28784#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28478#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28479#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28815#L722-45 assume 1 == ~t5_pc~0; 28805#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 28806#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29756#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 29806#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29171#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29172#L741-45 assume 1 == ~t6_pc~0; 28568#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 28569#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28926#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 29266#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 29297#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29385#L760-45 assume 1 == ~t7_pc~0; 29273#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 29274#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28845#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 28846#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 29405#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 29406#L779-45 assume !(1 == ~t8_pc~0); 28281#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 28282#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28306#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 28307#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 29386#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 29387#L798-45 assume 1 == ~t9_pc~0; 29801#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 28923#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 29311#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 29034#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 29035#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 28937#L817-45 assume 1 == ~t10_pc~0; 28938#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 29522#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 29309#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 28676#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 28573#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 28574#L836-45 assume !(1 == ~t11_pc~0); 28078#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 28079#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28847#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 28848#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 29335#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 29408#L855-45 assume 1 == ~t12_pc~0; 28796#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 28243#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 28244#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 29168#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 29169#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 28892#L874-45 assume !(1 == ~t13_pc~0); 28893#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 28801#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 28802#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 28394#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 28395#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 29174#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28343#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28344#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27915#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27916#L1446-3 assume !(1 == ~T5_E~0); 29574#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28883#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28498#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28499#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29810#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28448#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28449#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28857#L1486-3 assume !(1 == ~T13_E~0); 28467#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28468#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28912#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28913#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29338#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29329#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29330#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29032#L1526-3 assume !(1 == ~E_7~0); 29033#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29402#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28485#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28486#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28525#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29768#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28062#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 28063#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28170#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29527#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 29370#L1946 assume !(0 == start_simulation_~tmp~3); 29095#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29096#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28409#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29784#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 29460#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27897#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 27898#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 28145#L1959 assume !(0 != start_simulation_~tmp___0~1); 28146#L1927-1 [2021-11-02 23:08:48,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,229 INFO L85 PathProgramCache]: Analyzing trace with hash -988862365, now seen corresponding path program 1 times [2021-11-02 23:08:48,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,229 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581237558] [2021-11-02 23:08:48,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,286 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581237558] [2021-11-02 23:08:48,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581237558] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,286 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971662242] [2021-11-02 23:08:48,287 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:48,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,288 INFO L85 PathProgramCache]: Analyzing trace with hash -480447653, now seen corresponding path program 1 times [2021-11-02 23:08:48,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,289 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346000319] [2021-11-02 23:08:48,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,352 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,354 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346000319] [2021-11-02 23:08:48,362 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346000319] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,362 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,362 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317443910] [2021-11-02 23:08:48,363 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:48,363 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:48,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:48,364 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:48,365 INFO L87 Difference]: Start difference. First operand 1986 states and 2950 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:48,418 INFO L93 Difference]: Finished difference Result 1986 states and 2949 transitions. [2021-11-02 23:08:48,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:48,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2949 transitions. [2021-11-02 23:08:48,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2949 transitions. [2021-11-02 23:08:48,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:48,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:48,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2949 transitions. [2021-11-02 23:08:48,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:48,462 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-02 23:08:48,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2949 transitions. [2021-11-02 23:08:48,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:48,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4848942598187311) internal successors, (2949), 1985 states have internal predecessors, (2949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2949 transitions. [2021-11-02 23:08:48,519 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-02 23:08:48,519 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-02 23:08:48,519 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-02 23:08:48,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2949 transitions. [2021-11-02 23:08:48,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:48,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:48,537 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,537 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,538 INFO L791 eck$LassoCheckResult]: Stem: 32749#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32750#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33829#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33743#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 32896#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32706#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32707#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32474#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32475#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32898#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33084#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33244#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33265#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32482#L946-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32483#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32210#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32211#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 32658#L966-1 assume !(0 == ~M_E~0); 32659#L1278-1 assume !(0 == ~T1_E~0); 33571#L1283-1 assume !(0 == ~T2_E~0); 33572#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33777#L1293-1 assume !(0 == ~T4_E~0); 33765#L1298-1 assume !(0 == ~T5_E~0); 33709#L1303-1 assume !(0 == ~T6_E~0); 32309#L1308-1 assume !(0 == ~T7_E~0); 32233#L1313-1 assume !(0 == ~T8_E~0); 32234#L1318-1 assume !(0 == ~T9_E~0); 32236#L1323-1 assume !(0 == ~T10_E~0); 32237#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32420#L1333-1 assume !(0 == ~T12_E~0); 33382#L1338-1 assume !(0 == ~T13_E~0); 33383#L1343-1 assume !(0 == ~E_M~0); 33525#L1348-1 assume !(0 == ~E_1~0); 33805#L1353-1 assume !(0 == ~E_2~0); 33127#L1358-1 assume !(0 == ~E_3~0); 33128#L1363-1 assume !(0 == ~E_4~0); 33419#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 32062#L1373-1 assume !(0 == ~E_6~0); 32063#L1378-1 assume !(0 == ~E_7~0); 32377#L1383-1 assume !(0 == ~E_8~0); 32378#L1388-1 assume !(0 == ~E_9~0); 33456#L1393-1 assume !(0 == ~E_10~0); 33457#L1398-1 assume !(0 == ~E_11~0); 33463#L1403-1 assume !(0 == ~E_12~0); 33707#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 32348#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32349#L627 assume 1 == ~m_pc~0; 33817#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 32710#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32711#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 33289#L1590 assume !(0 != activate_threads_~tmp~1); 33737#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32278#L646 assume !(1 == ~t1_pc~0); 32279#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 32938#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32946#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32996#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32151#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32152#L665 assume 1 == ~t2_pc~0; 33799#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32819#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32365#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32366#L1606 assume !(0 != activate_threads_~tmp___1~0); 32921#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33209#L684 assume !(1 == ~t3_pc~0); 33175#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 33176#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33246#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 33784#L1614 assume !(0 != activate_threads_~tmp___2~0); 33823#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33808#L703 assume 1 == ~t4_pc~0; 32645#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32506#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33117#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32600#L1622 assume !(0 != activate_threads_~tmp___3~0); 32601#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33641#L722 assume !(1 == ~t5_pc~0); 32557#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 32558#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32906#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 31886#L1630 assume !(0 != activate_threads_~tmp___4~0); 31887#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32098#L741 assume 1 == ~t6_pc~0; 32099#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32403#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32556#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32216#L1638 assume !(0 != activate_threads_~tmp___5~0); 32217#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32530#L760 assume 1 == ~t7_pc~0; 32501#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32502#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32360#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 32361#L1646 assume !(0 != activate_threads_~tmp___6~0); 32737#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32738#L779 assume !(1 == ~t8_pc~0); 32143#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 31992#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31993#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 32395#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 33165#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 33166#L798 assume 1 == ~t9_pc~0; 33668#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 33606#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32144#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 32145#L1662 assume !(0 != activate_threads_~tmp___8~0); 31927#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 31928#L817 assume !(1 == ~t10_pc~0); 31974#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 32756#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32757#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 32218#L1670 assume !(0 != activate_threads_~tmp___9~0); 32219#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 33118#L836 assume 1 == ~t11_pc~0; 33119#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 32317#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32318#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 32281#L1678 assume !(0 != activate_threads_~tmp___10~0); 32282#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 33616#L855 assume !(1 == ~t12_pc~0); 32943#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 32944#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 33497#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 33522#L1686 assume !(0 != activate_threads_~tmp___11~0); 33462#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 32267#L874 assume 1 == ~t13_pc~0; 32268#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 32429#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 32430#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 32559#L1694 assume !(0 != activate_threads_~tmp___12~0); 33589#L1694-2 assume !(1 == ~M_E~0); 32472#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32473#L1431-1 assume !(1 == ~T2_E~0); 31994#L1436-1 assume !(1 == ~T3_E~0); 31995#L1441-1 assume !(1 == ~T4_E~0); 32787#L1446-1 assume !(1 == ~T5_E~0); 32788#L1451-1 assume !(1 == ~T6_E~0); 33523#L1456-1 assume !(1 == ~T7_E~0); 33159#L1461-1 assume !(1 == ~T8_E~0); 32702#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32703#L1471-1 assume !(1 == ~T10_E~0); 33498#L1476-1 assume !(1 == ~T11_E~0); 33499#L1481-1 assume !(1 == ~T12_E~0); 33664#L1486-1 assume !(1 == ~T13_E~0); 32321#L1491-1 assume !(1 == ~E_M~0); 31936#L1496-1 assume !(1 == ~E_1~0); 31937#L1501-1 assume !(1 == ~E_2~0); 32782#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 32783#L1511-1 assume !(1 == ~E_4~0); 32736#L1516-1 assume !(1 == ~E_5~0); 31890#L1521-1 assume !(1 == ~E_6~0); 31891#L1526-1 assume !(1 == ~E_7~0); 31935#L1531-1 assume !(1 == ~E_8~0); 32493#L1536-1 assume !(1 == ~E_9~0); 32212#L1541-1 assume !(1 == ~E_10~0); 32213#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 33718#L1551-1 assume !(1 == ~E_12~0); 32382#L1556-1 assume !(1 == ~E_13~0); 32125#L1927-1 [2021-11-02 23:08:48,539 INFO L793 eck$LassoCheckResult]: Loop: 32125#L1927-1 assume !false; 32406#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 32417#L1253 assume !false; 31878#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 31879#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32565#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 32488#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 32489#L1066 assume !(0 != eval_~tmp~0); 33722#L1268 start_simulation_~kernel_st~0 := 2; 32231#L894-1 start_simulation_~kernel_st~0 := 3; 32232#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32797#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32798#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32397#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32398#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33583#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33584#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33726#L1308-3 assume !(0 == ~T7_E~0); 33578#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33040#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32184#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32185#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33658#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32331#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 32332#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33470#L1348-3 assume !(0 == ~E_1~0); 33662#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33663#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33002#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32517#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32518#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33318#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33319#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33516#L1388-3 assume !(0 == ~E_9~0); 33503#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33504#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32848#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32849#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33670#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32695#L627-45 assume !(1 == ~m_pc~0); 32696#L627-47 is_master_triggered_~__retres1~0 := 0; 33192#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33660#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 33023#L1590-45 assume !(0 != activate_threads_~tmp~1); 33024#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33620#L646-45 assume !(1 == ~t1_pc~0); 32885#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 32886#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33070#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 33071#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32302#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32303#L665-45 assume 1 == ~t2_pc~0; 31976#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 31977#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32803#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32003#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32004#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33224#L684-45 assume 1 == ~t3_pc~0; 33225#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32300#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33376#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 33727#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33524#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33329#L703-45 assume 1 == ~t4_pc~0; 33168#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 33170#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32763#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32457#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32458#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32794#L722-45 assume 1 == ~t5_pc~0; 32784#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32785#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33735#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 33785#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 33150#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33151#L741-45 assume 1 == ~t6_pc~0; 32547#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32548#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32905#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 33245#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 33276#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 33364#L760-45 assume 1 == ~t7_pc~0; 33252#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 33253#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32824#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 32825#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 33384#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 33385#L779-45 assume !(1 == ~t8_pc~0); 32260#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 32261#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32285#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 32286#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 33365#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 33366#L798-45 assume 1 == ~t9_pc~0; 33780#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 32902#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 33290#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 33013#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 33014#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 32916#L817-45 assume 1 == ~t10_pc~0; 32917#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 33501#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 33288#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 32655#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 32552#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32553#L836-45 assume !(1 == ~t11_pc~0); 32057#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 32058#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32826#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 32827#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 33314#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 33387#L855-45 assume 1 == ~t12_pc~0; 32775#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 32222#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32223#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 33147#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 33148#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 32871#L874-45 assume !(1 == ~t13_pc~0); 32872#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 32780#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 32781#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 32373#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 32374#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 33153#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32322#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32323#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31894#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31895#L1446-3 assume !(1 == ~T5_E~0); 33553#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32862#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32477#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32478#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33789#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32427#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32428#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32836#L1486-3 assume !(1 == ~T13_E~0); 32446#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32447#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32891#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32892#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33317#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33308#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33309#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33011#L1526-3 assume !(1 == ~E_7~0); 33012#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33381#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32464#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32465#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32504#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33747#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32041#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 32042#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32149#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33506#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 33349#L1946 assume !(0 == start_simulation_~tmp~3); 33074#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33075#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32388#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33763#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 33439#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 31876#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 31877#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 32124#L1959 assume !(0 != start_simulation_~tmp___0~1); 32125#L1927-1 [2021-11-02 23:08:48,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,540 INFO L85 PathProgramCache]: Analyzing trace with hash 334316581, now seen corresponding path program 1 times [2021-11-02 23:08:48,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,540 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354965725] [2021-11-02 23:08:48,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,594 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354965725] [2021-11-02 23:08:48,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354965725] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,594 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137714453] [2021-11-02 23:08:48,596 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:48,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1679024933, now seen corresponding path program 3 times [2021-11-02 23:08:48,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,597 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619562706] [2021-11-02 23:08:48,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,659 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,659 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619562706] [2021-11-02 23:08:48,659 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619562706] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,659 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,660 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981937566] [2021-11-02 23:08:48,661 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:48,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:48,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:48,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:48,662 INFO L87 Difference]: Start difference. First operand 1986 states and 2949 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:48,703 INFO L93 Difference]: Finished difference Result 1986 states and 2948 transitions. [2021-11-02 23:08:48,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:48,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2948 transitions. [2021-11-02 23:08:48,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2948 transitions. [2021-11-02 23:08:48,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:48,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:48,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2948 transitions. [2021-11-02 23:08:48,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:48,759 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-02 23:08:48,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2948 transitions. [2021-11-02 23:08:48,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:48,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4843907351460222) internal successors, (2948), 1985 states have internal predecessors, (2948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:48,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2948 transitions. [2021-11-02 23:08:48,843 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-02 23:08:48,843 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-02 23:08:48,843 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-02 23:08:48,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2948 transitions. [2021-11-02 23:08:48,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:48,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:48,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:48,860 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:48,861 INFO L791 eck$LassoCheckResult]: Stem: 36728#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36729#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37808#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37722#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 36875#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36685#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36686#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36453#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36454#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36877#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37063#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37223#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37244#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36461#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36462#L951-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36189#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36190#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 36637#L966-1 assume !(0 == ~M_E~0); 36638#L1278-1 assume !(0 == ~T1_E~0); 37550#L1283-1 assume !(0 == ~T2_E~0); 37551#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37756#L1293-1 assume !(0 == ~T4_E~0); 37744#L1298-1 assume !(0 == ~T5_E~0); 37688#L1303-1 assume !(0 == ~T6_E~0); 36288#L1308-1 assume !(0 == ~T7_E~0); 36212#L1313-1 assume !(0 == ~T8_E~0); 36213#L1318-1 assume !(0 == ~T9_E~0); 36215#L1323-1 assume !(0 == ~T10_E~0); 36216#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36399#L1333-1 assume !(0 == ~T12_E~0); 37361#L1338-1 assume !(0 == ~T13_E~0); 37362#L1343-1 assume !(0 == ~E_M~0); 37504#L1348-1 assume !(0 == ~E_1~0); 37784#L1353-1 assume !(0 == ~E_2~0); 37106#L1358-1 assume !(0 == ~E_3~0); 37107#L1363-1 assume !(0 == ~E_4~0); 37398#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 36041#L1373-1 assume !(0 == ~E_6~0); 36042#L1378-1 assume !(0 == ~E_7~0); 36356#L1383-1 assume !(0 == ~E_8~0); 36357#L1388-1 assume !(0 == ~E_9~0); 37435#L1393-1 assume !(0 == ~E_10~0); 37436#L1398-1 assume !(0 == ~E_11~0); 37442#L1403-1 assume !(0 == ~E_12~0); 37686#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 36327#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36328#L627 assume 1 == ~m_pc~0; 37796#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 36689#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36690#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 37268#L1590 assume !(0 != activate_threads_~tmp~1); 37716#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36257#L646 assume !(1 == ~t1_pc~0); 36258#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 36917#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36925#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36975#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36130#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36131#L665 assume 1 == ~t2_pc~0; 37778#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 36798#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36344#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 36345#L1606 assume !(0 != activate_threads_~tmp___1~0); 36900#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37188#L684 assume !(1 == ~t3_pc~0); 37154#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 37155#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37225#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 37763#L1614 assume !(0 != activate_threads_~tmp___2~0); 37802#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37787#L703 assume 1 == ~t4_pc~0; 36624#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36485#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37096#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 36579#L1622 assume !(0 != activate_threads_~tmp___3~0); 36580#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 37620#L722 assume !(1 == ~t5_pc~0); 36536#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 36537#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36885#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 35865#L1630 assume !(0 != activate_threads_~tmp___4~0); 35866#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36077#L741 assume 1 == ~t6_pc~0; 36078#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 36382#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 36535#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 36195#L1638 assume !(0 != activate_threads_~tmp___5~0); 36196#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 36509#L760 assume 1 == ~t7_pc~0; 36480#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 36481#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36339#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 36340#L1646 assume !(0 != activate_threads_~tmp___6~0); 36716#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 36717#L779 assume !(1 == ~t8_pc~0); 36122#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 35971#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35972#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 36374#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 37144#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 37145#L798 assume 1 == ~t9_pc~0; 37647#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 37585#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 36123#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36124#L1662 assume !(0 != activate_threads_~tmp___8~0); 35906#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 35907#L817 assume !(1 == ~t10_pc~0); 35953#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 36735#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 36736#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 36197#L1670 assume !(0 != activate_threads_~tmp___9~0); 36198#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 37097#L836 assume 1 == ~t11_pc~0; 37098#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 36296#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 36297#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 36260#L1678 assume !(0 != activate_threads_~tmp___10~0); 36261#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 37595#L855 assume !(1 == ~t12_pc~0); 36922#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 36923#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 37476#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 37501#L1686 assume !(0 != activate_threads_~tmp___11~0); 37441#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 36246#L874 assume 1 == ~t13_pc~0; 36247#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 36408#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 36409#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 36538#L1694 assume !(0 != activate_threads_~tmp___12~0); 37568#L1694-2 assume !(1 == ~M_E~0); 36451#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36452#L1431-1 assume !(1 == ~T2_E~0); 35973#L1436-1 assume !(1 == ~T3_E~0); 35974#L1441-1 assume !(1 == ~T4_E~0); 36766#L1446-1 assume !(1 == ~T5_E~0); 36767#L1451-1 assume !(1 == ~T6_E~0); 37502#L1456-1 assume !(1 == ~T7_E~0); 37138#L1461-1 assume !(1 == ~T8_E~0); 36681#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36682#L1471-1 assume !(1 == ~T10_E~0); 37477#L1476-1 assume !(1 == ~T11_E~0); 37478#L1481-1 assume !(1 == ~T12_E~0); 37643#L1486-1 assume !(1 == ~T13_E~0); 36300#L1491-1 assume !(1 == ~E_M~0); 35915#L1496-1 assume !(1 == ~E_1~0); 35916#L1501-1 assume !(1 == ~E_2~0); 36761#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 36762#L1511-1 assume !(1 == ~E_4~0); 36715#L1516-1 assume !(1 == ~E_5~0); 35869#L1521-1 assume !(1 == ~E_6~0); 35870#L1526-1 assume !(1 == ~E_7~0); 35914#L1531-1 assume !(1 == ~E_8~0); 36472#L1536-1 assume !(1 == ~E_9~0); 36191#L1541-1 assume !(1 == ~E_10~0); 36192#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 37697#L1551-1 assume !(1 == ~E_12~0); 36361#L1556-1 assume !(1 == ~E_13~0); 36104#L1927-1 [2021-11-02 23:08:48,862 INFO L793 eck$LassoCheckResult]: Loop: 36104#L1927-1 assume !false; 36385#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 36396#L1253 assume !false; 35857#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 35858#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36544#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 36467#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 36468#L1066 assume !(0 != eval_~tmp~0); 37701#L1268 start_simulation_~kernel_st~0 := 2; 36210#L894-1 start_simulation_~kernel_st~0 := 3; 36211#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36776#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36777#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36376#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36377#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37562#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37563#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37705#L1308-3 assume !(0 == ~T7_E~0); 37557#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37019#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36163#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36164#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37637#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36310#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 36311#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37449#L1348-3 assume !(0 == ~E_1~0); 37641#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37642#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36981#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36496#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36497#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37297#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37298#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37495#L1388-3 assume !(0 == ~E_9~0); 37482#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37483#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36827#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36828#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37649#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36674#L627-45 assume !(1 == ~m_pc~0); 36675#L627-47 is_master_triggered_~__retres1~0 := 0; 37171#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37639#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 37002#L1590-45 assume !(0 != activate_threads_~tmp~1); 37003#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37599#L646-45 assume !(1 == ~t1_pc~0); 36864#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 36865#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37049#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 37050#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36281#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36282#L665-45 assume 1 == ~t2_pc~0; 35955#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 35956#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36782#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35982#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35983#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37203#L684-45 assume 1 == ~t3_pc~0; 37204#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 36279#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37355#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 37706#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 37503#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37308#L703-45 assume 1 == ~t4_pc~0; 37147#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 37149#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36742#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 36436#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36437#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36773#L722-45 assume 1 == ~t5_pc~0; 36763#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36764#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 37714#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 37764#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 37129#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37130#L741-45 assume !(1 == ~t6_pc~0); 36528#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 36527#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 36884#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 37224#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 37255#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 37343#L760-45 assume !(1 == ~t7_pc~0); 37233#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 37232#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36803#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 36804#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 37363#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 37364#L779-45 assume 1 == ~t8_pc~0; 37315#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 36240#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36264#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 36265#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 37344#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 37345#L798-45 assume !(1 == ~t9_pc~0); 36880#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 36881#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 37269#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36992#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 36993#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 36895#L817-45 assume 1 == ~t10_pc~0; 36896#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 37480#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 37267#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 36634#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 36531#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 36532#L836-45 assume !(1 == ~t11_pc~0); 36036#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 36037#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 36805#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 36806#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 37293#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 37366#L855-45 assume 1 == ~t12_pc~0; 36754#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 36201#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 36202#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 37126#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 37127#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 36850#L874-45 assume !(1 == ~t13_pc~0); 36851#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 36759#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 36760#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 36352#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 36353#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 37132#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36301#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36302#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35873#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35874#L1446-3 assume !(1 == ~T5_E~0); 37532#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36841#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36456#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36457#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37768#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36406#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36407#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36815#L1486-3 assume !(1 == ~T13_E~0); 36425#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36426#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36870#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36871#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37296#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37287#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37288#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36990#L1526-3 assume !(1 == ~E_7~0); 36991#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37360#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36443#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36444#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36483#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37726#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 36020#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 36021#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36128#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37485#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 37328#L1946 assume !(0 == start_simulation_~tmp~3); 37053#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37054#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36367#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37742#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 37418#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35855#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 35856#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 36103#L1959 assume !(0 != start_simulation_~tmp___0~1); 36104#L1927-1 [2021-11-02 23:08:48,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,863 INFO L85 PathProgramCache]: Analyzing trace with hash -3970969, now seen corresponding path program 1 times [2021-11-02 23:08:48,863 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,864 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351957739] [2021-11-02 23:08:48,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,864 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:48,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:48,912 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:48,912 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351957739] [2021-11-02 23:08:48,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351957739] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:48,912 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:48,913 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:48,913 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344706068] [2021-11-02 23:08:48,914 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:48,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:48,915 INFO L85 PathProgramCache]: Analyzing trace with hash -1634020711, now seen corresponding path program 1 times [2021-11-02 23:08:48,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:48,916 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433292858] [2021-11-02 23:08:48,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:48,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:48,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,032 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,032 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433292858] [2021-11-02 23:08:49,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433292858] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,039 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178989742] [2021-11-02 23:08:49,040 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:49,041 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:49,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:49,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:49,045 INFO L87 Difference]: Start difference. First operand 1986 states and 2948 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:49,084 INFO L93 Difference]: Finished difference Result 1986 states and 2947 transitions. [2021-11-02 23:08:49,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:49,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2947 transitions. [2021-11-02 23:08:49,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2947 transitions. [2021-11-02 23:08:49,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:49,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:49,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2947 transitions. [2021-11-02 23:08:49,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:49,121 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-02 23:08:49,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2947 transitions. [2021-11-02 23:08:49,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:49,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4838872104733132) internal successors, (2947), 1985 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2947 transitions. [2021-11-02 23:08:49,172 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-02 23:08:49,172 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-02 23:08:49,172 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-02 23:08:49,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2947 transitions. [2021-11-02 23:08:49,184 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:49,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:49,188 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,189 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,189 INFO L791 eck$LassoCheckResult]: Stem: 40707#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 40708#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41787#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41701#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 40854#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40664#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40665#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40432#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40433#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40856#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41042#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41202#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41223#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40440#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40441#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40168#L956-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40169#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 40616#L966-1 assume !(0 == ~M_E~0); 40617#L1278-1 assume !(0 == ~T1_E~0); 41529#L1283-1 assume !(0 == ~T2_E~0); 41530#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41735#L1293-1 assume !(0 == ~T4_E~0); 41723#L1298-1 assume !(0 == ~T5_E~0); 41667#L1303-1 assume !(0 == ~T6_E~0); 40267#L1308-1 assume !(0 == ~T7_E~0); 40191#L1313-1 assume !(0 == ~T8_E~0); 40192#L1318-1 assume !(0 == ~T9_E~0); 40194#L1323-1 assume !(0 == ~T10_E~0); 40195#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40378#L1333-1 assume !(0 == ~T12_E~0); 41340#L1338-1 assume !(0 == ~T13_E~0); 41341#L1343-1 assume !(0 == ~E_M~0); 41483#L1348-1 assume !(0 == ~E_1~0); 41763#L1353-1 assume !(0 == ~E_2~0); 41085#L1358-1 assume !(0 == ~E_3~0); 41086#L1363-1 assume !(0 == ~E_4~0); 41377#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40020#L1373-1 assume !(0 == ~E_6~0); 40021#L1378-1 assume !(0 == ~E_7~0); 40335#L1383-1 assume !(0 == ~E_8~0); 40336#L1388-1 assume !(0 == ~E_9~0); 41414#L1393-1 assume !(0 == ~E_10~0); 41415#L1398-1 assume !(0 == ~E_11~0); 41421#L1403-1 assume !(0 == ~E_12~0); 41665#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 40306#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40307#L627 assume 1 == ~m_pc~0; 41775#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 40668#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40669#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 41247#L1590 assume !(0 != activate_threads_~tmp~1); 41695#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40236#L646 assume !(1 == ~t1_pc~0); 40237#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 40896#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40904#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 40954#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40109#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40110#L665 assume 1 == ~t2_pc~0; 41757#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40777#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40323#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 40324#L1606 assume !(0 != activate_threads_~tmp___1~0); 40879#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41167#L684 assume !(1 == ~t3_pc~0); 41133#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 41134#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41204#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 41742#L1614 assume !(0 != activate_threads_~tmp___2~0); 41781#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41766#L703 assume 1 == ~t4_pc~0; 40603#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40464#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41075#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 40558#L1622 assume !(0 != activate_threads_~tmp___3~0); 40559#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41599#L722 assume !(1 == ~t5_pc~0); 40515#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 40516#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40864#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 39844#L1630 assume !(0 != activate_threads_~tmp___4~0); 39845#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40056#L741 assume 1 == ~t6_pc~0; 40057#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 40361#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40514#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 40174#L1638 assume !(0 != activate_threads_~tmp___5~0); 40175#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40488#L760 assume 1 == ~t7_pc~0; 40459#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 40460#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40318#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 40319#L1646 assume !(0 != activate_threads_~tmp___6~0); 40695#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40696#L779 assume !(1 == ~t8_pc~0); 40101#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 39950#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 39951#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 40353#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 41123#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 41124#L798 assume 1 == ~t9_pc~0; 41626#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 41564#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 40102#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40103#L1662 assume !(0 != activate_threads_~tmp___8~0); 39885#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 39886#L817 assume !(1 == ~t10_pc~0); 39932#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 40714#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 40715#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 40176#L1670 assume !(0 != activate_threads_~tmp___9~0); 40177#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 41076#L836 assume 1 == ~t11_pc~0; 41077#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 40275#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 40276#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 40239#L1678 assume !(0 != activate_threads_~tmp___10~0); 40240#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 41574#L855 assume !(1 == ~t12_pc~0); 40901#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 40902#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 41455#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 41480#L1686 assume !(0 != activate_threads_~tmp___11~0); 41420#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 40225#L874 assume 1 == ~t13_pc~0; 40226#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 40387#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 40388#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 40517#L1694 assume !(0 != activate_threads_~tmp___12~0); 41547#L1694-2 assume !(1 == ~M_E~0); 40430#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40431#L1431-1 assume !(1 == ~T2_E~0); 39952#L1436-1 assume !(1 == ~T3_E~0); 39953#L1441-1 assume !(1 == ~T4_E~0); 40745#L1446-1 assume !(1 == ~T5_E~0); 40746#L1451-1 assume !(1 == ~T6_E~0); 41481#L1456-1 assume !(1 == ~T7_E~0); 41117#L1461-1 assume !(1 == ~T8_E~0); 40660#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40661#L1471-1 assume !(1 == ~T10_E~0); 41456#L1476-1 assume !(1 == ~T11_E~0); 41457#L1481-1 assume !(1 == ~T12_E~0); 41622#L1486-1 assume !(1 == ~T13_E~0); 40279#L1491-1 assume !(1 == ~E_M~0); 39894#L1496-1 assume !(1 == ~E_1~0); 39895#L1501-1 assume !(1 == ~E_2~0); 40740#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 40741#L1511-1 assume !(1 == ~E_4~0); 40694#L1516-1 assume !(1 == ~E_5~0); 39848#L1521-1 assume !(1 == ~E_6~0); 39849#L1526-1 assume !(1 == ~E_7~0); 39893#L1531-1 assume !(1 == ~E_8~0); 40451#L1536-1 assume !(1 == ~E_9~0); 40170#L1541-1 assume !(1 == ~E_10~0); 40171#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 41676#L1551-1 assume !(1 == ~E_12~0); 40340#L1556-1 assume !(1 == ~E_13~0); 40083#L1927-1 [2021-11-02 23:08:49,190 INFO L793 eck$LassoCheckResult]: Loop: 40083#L1927-1 assume !false; 40364#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 40375#L1253 assume !false; 39836#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 39837#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40523#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 40446#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 40447#L1066 assume !(0 != eval_~tmp~0); 41680#L1268 start_simulation_~kernel_st~0 := 2; 40189#L894-1 start_simulation_~kernel_st~0 := 3; 40190#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 40755#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40756#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40355#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40356#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41541#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41542#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41684#L1308-3 assume !(0 == ~T7_E~0); 41536#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40998#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40142#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40143#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41616#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40289#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 40290#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41428#L1348-3 assume !(0 == ~E_1~0); 41620#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41621#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40960#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40475#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40476#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41276#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41277#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41474#L1388-3 assume !(0 == ~E_9~0); 41461#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41462#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40806#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40807#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41628#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40653#L627-45 assume !(1 == ~m_pc~0); 40654#L627-47 is_master_triggered_~__retres1~0 := 0; 41150#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41618#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 40981#L1590-45 assume !(0 != activate_threads_~tmp~1); 40982#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41578#L646-45 assume 1 == ~t1_pc~0; 41649#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 40844#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41028#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 41029#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40260#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40261#L665-45 assume !(1 == ~t2_pc~0); 39936#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 39935#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40761#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39961#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39962#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41182#L684-45 assume !(1 == ~t3_pc~0); 40257#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 40258#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41334#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 41685#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 41482#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41287#L703-45 assume 1 == ~t4_pc~0; 41126#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 41128#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40721#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 40415#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40416#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40752#L722-45 assume 1 == ~t5_pc~0; 40742#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 40743#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 41693#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 41743#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 41108#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41109#L741-45 assume 1 == ~t6_pc~0; 40505#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 40506#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40863#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 41203#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 41234#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 41322#L760-45 assume 1 == ~t7_pc~0; 41210#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 41211#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40782#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 40783#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 41342#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 41343#L779-45 assume !(1 == ~t8_pc~0); 40218#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 40219#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40243#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 40244#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 41323#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 41324#L798-45 assume 1 == ~t9_pc~0; 41738#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 40860#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 41248#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40971#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 40972#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 40874#L817-45 assume 1 == ~t10_pc~0; 40875#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 41459#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 41246#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 40613#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 40510#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 40511#L836-45 assume !(1 == ~t11_pc~0); 40015#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 40016#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 40784#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 40785#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 41272#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 41345#L855-45 assume 1 == ~t12_pc~0; 40733#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 40180#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 40181#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 41105#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 41106#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 40829#L874-45 assume !(1 == ~t13_pc~0); 40830#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 40738#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 40739#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 40331#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 40332#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 41111#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40280#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40281#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39852#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39853#L1446-3 assume !(1 == ~T5_E~0); 41511#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40820#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40435#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40436#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41747#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40385#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40386#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40794#L1486-3 assume !(1 == ~T13_E~0); 40404#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40405#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40849#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40850#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41275#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41266#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41267#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40969#L1526-3 assume !(1 == ~E_7~0); 40970#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41339#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40422#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40423#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40462#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41705#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39999#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 40000#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40107#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41464#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 41307#L1946 assume !(0 == start_simulation_~tmp~3); 41032#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41033#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40346#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41721#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 41397#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39834#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 39835#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 40082#L1959 assume !(0 != start_simulation_~tmp___0~1); 40083#L1927-1 [2021-11-02 23:08:49,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,191 INFO L85 PathProgramCache]: Analyzing trace with hash -430525467, now seen corresponding path program 1 times [2021-11-02 23:08:49,191 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,192 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462775269] [2021-11-02 23:08:49,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,247 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,248 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462775269] [2021-11-02 23:08:49,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462775269] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,248 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,248 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245252141] [2021-11-02 23:08:49,249 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:49,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,250 INFO L85 PathProgramCache]: Analyzing trace with hash 522178042, now seen corresponding path program 1 times [2021-11-02 23:08:49,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,251 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489685200] [2021-11-02 23:08:49,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,316 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489685200] [2021-11-02 23:08:49,316 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489685200] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,316 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162188847] [2021-11-02 23:08:49,317 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:49,317 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:49,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:49,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:49,319 INFO L87 Difference]: Start difference. First operand 1986 states and 2947 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:49,358 INFO L93 Difference]: Finished difference Result 1986 states and 2946 transitions. [2021-11-02 23:08:49,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:49,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2946 transitions. [2021-11-02 23:08:49,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2946 transitions. [2021-11-02 23:08:49,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:49,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:49,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2946 transitions. [2021-11-02 23:08:49,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:49,394 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-02 23:08:49,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2946 transitions. [2021-11-02 23:08:49,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:49,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4833836858006042) internal successors, (2946), 1985 states have internal predecessors, (2946), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2946 transitions. [2021-11-02 23:08:49,444 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-02 23:08:49,444 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-02 23:08:49,445 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-02 23:08:49,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2946 transitions. [2021-11-02 23:08:49,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:49,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:49,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,461 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,461 INFO L791 eck$LassoCheckResult]: Stem: 44686#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 44687#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45766#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 45680#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 44833#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44643#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44644#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44411#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44412#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44835#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45021#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45181#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45202#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44419#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44420#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44147#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44148#L961-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 44595#L966-1 assume !(0 == ~M_E~0); 44596#L1278-1 assume !(0 == ~T1_E~0); 45508#L1283-1 assume !(0 == ~T2_E~0); 45509#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45714#L1293-1 assume !(0 == ~T4_E~0); 45702#L1298-1 assume !(0 == ~T5_E~0); 45646#L1303-1 assume !(0 == ~T6_E~0); 44246#L1308-1 assume !(0 == ~T7_E~0); 44170#L1313-1 assume !(0 == ~T8_E~0); 44171#L1318-1 assume !(0 == ~T9_E~0); 44173#L1323-1 assume !(0 == ~T10_E~0); 44174#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44357#L1333-1 assume !(0 == ~T12_E~0); 45319#L1338-1 assume !(0 == ~T13_E~0); 45320#L1343-1 assume !(0 == ~E_M~0); 45462#L1348-1 assume !(0 == ~E_1~0); 45742#L1353-1 assume !(0 == ~E_2~0); 45064#L1358-1 assume !(0 == ~E_3~0); 45065#L1363-1 assume !(0 == ~E_4~0); 45356#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 43999#L1373-1 assume !(0 == ~E_6~0); 44000#L1378-1 assume !(0 == ~E_7~0); 44314#L1383-1 assume !(0 == ~E_8~0); 44315#L1388-1 assume !(0 == ~E_9~0); 45393#L1393-1 assume !(0 == ~E_10~0); 45394#L1398-1 assume !(0 == ~E_11~0); 45400#L1403-1 assume !(0 == ~E_12~0); 45644#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 44285#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44286#L627 assume 1 == ~m_pc~0; 45754#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 44647#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44648#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 45226#L1590 assume !(0 != activate_threads_~tmp~1); 45674#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44215#L646 assume !(1 == ~t1_pc~0); 44216#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 44875#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44883#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 44933#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44088#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44089#L665 assume 1 == ~t2_pc~0; 45736#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 44756#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44302#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44303#L1606 assume !(0 != activate_threads_~tmp___1~0); 44858#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45146#L684 assume !(1 == ~t3_pc~0); 45112#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 45113#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45183#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 45721#L1614 assume !(0 != activate_threads_~tmp___2~0); 45760#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45745#L703 assume 1 == ~t4_pc~0; 44582#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 44443#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45054#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 44537#L1622 assume !(0 != activate_threads_~tmp___3~0); 44538#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 45578#L722 assume !(1 == ~t5_pc~0); 44494#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 44495#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44843#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 43823#L1630 assume !(0 != activate_threads_~tmp___4~0); 43824#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44035#L741 assume 1 == ~t6_pc~0; 44036#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 44340#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44493#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 44153#L1638 assume !(0 != activate_threads_~tmp___5~0); 44154#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 44467#L760 assume 1 == ~t7_pc~0; 44438#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 44439#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44297#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 44298#L1646 assume !(0 != activate_threads_~tmp___6~0); 44674#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44675#L779 assume !(1 == ~t8_pc~0); 44080#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 43929#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 43930#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 44332#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 45102#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 45103#L798 assume 1 == ~t9_pc~0; 45605#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 45543#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 44081#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 44082#L1662 assume !(0 != activate_threads_~tmp___8~0); 43864#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 43865#L817 assume !(1 == ~t10_pc~0); 43911#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 44693#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 44694#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 44155#L1670 assume !(0 != activate_threads_~tmp___9~0); 44156#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 45055#L836 assume 1 == ~t11_pc~0; 45056#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 44254#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 44255#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 44218#L1678 assume !(0 != activate_threads_~tmp___10~0); 44219#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 45553#L855 assume !(1 == ~t12_pc~0); 44880#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 44881#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 45434#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 45459#L1686 assume !(0 != activate_threads_~tmp___11~0); 45399#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 44204#L874 assume 1 == ~t13_pc~0; 44205#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 44366#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 44367#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 44496#L1694 assume !(0 != activate_threads_~tmp___12~0); 45526#L1694-2 assume !(1 == ~M_E~0); 44409#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44410#L1431-1 assume !(1 == ~T2_E~0); 43931#L1436-1 assume !(1 == ~T3_E~0); 43932#L1441-1 assume !(1 == ~T4_E~0); 44724#L1446-1 assume !(1 == ~T5_E~0); 44725#L1451-1 assume !(1 == ~T6_E~0); 45460#L1456-1 assume !(1 == ~T7_E~0); 45096#L1461-1 assume !(1 == ~T8_E~0); 44639#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44640#L1471-1 assume !(1 == ~T10_E~0); 45435#L1476-1 assume !(1 == ~T11_E~0); 45436#L1481-1 assume !(1 == ~T12_E~0); 45601#L1486-1 assume !(1 == ~T13_E~0); 44258#L1491-1 assume !(1 == ~E_M~0); 43873#L1496-1 assume !(1 == ~E_1~0); 43874#L1501-1 assume !(1 == ~E_2~0); 44719#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 44720#L1511-1 assume !(1 == ~E_4~0); 44673#L1516-1 assume !(1 == ~E_5~0); 43827#L1521-1 assume !(1 == ~E_6~0); 43828#L1526-1 assume !(1 == ~E_7~0); 43872#L1531-1 assume !(1 == ~E_8~0); 44430#L1536-1 assume !(1 == ~E_9~0); 44149#L1541-1 assume !(1 == ~E_10~0); 44150#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 45655#L1551-1 assume !(1 == ~E_12~0); 44319#L1556-1 assume !(1 == ~E_13~0); 44062#L1927-1 [2021-11-02 23:08:49,462 INFO L793 eck$LassoCheckResult]: Loop: 44062#L1927-1 assume !false; 44343#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 44354#L1253 assume !false; 43815#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 43816#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44502#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 44425#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 44426#L1066 assume !(0 != eval_~tmp~0); 45659#L1268 start_simulation_~kernel_st~0 := 2; 44168#L894-1 start_simulation_~kernel_st~0 := 3; 44169#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 44734#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44735#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44334#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44335#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45520#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45521#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45663#L1308-3 assume !(0 == ~T7_E~0); 45515#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44977#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44121#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44122#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45595#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44268#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 44269#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45407#L1348-3 assume !(0 == ~E_1~0); 45599#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45600#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44939#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44454#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44455#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45255#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45256#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45453#L1388-3 assume !(0 == ~E_9~0); 45440#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45441#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44785#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44786#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45607#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44632#L627-45 assume !(1 == ~m_pc~0); 44633#L627-47 is_master_triggered_~__retres1~0 := 0; 45129#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45597#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 44960#L1590-45 assume !(0 != activate_threads_~tmp~1); 44961#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45557#L646-45 assume !(1 == ~t1_pc~0); 44822#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 44823#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45007#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 45008#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44239#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44240#L665-45 assume 1 == ~t2_pc~0; 43913#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 43914#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44740#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 43940#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43941#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45161#L684-45 assume 1 == ~t3_pc~0; 45162#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 44237#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45313#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 45664#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 45461#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45266#L703-45 assume 1 == ~t4_pc~0; 45105#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 45107#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44700#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 44394#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 44395#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44731#L722-45 assume 1 == ~t5_pc~0; 44721#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 44722#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 45672#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 45722#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45087#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45088#L741-45 assume 1 == ~t6_pc~0; 44484#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 44485#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44842#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 45182#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 45213#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45301#L760-45 assume 1 == ~t7_pc~0; 45189#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 45190#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44761#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 44762#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 45321#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 45322#L779-45 assume !(1 == ~t8_pc~0); 44197#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 44198#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 44222#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 44223#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 45302#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 45303#L798-45 assume 1 == ~t9_pc~0; 45717#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 44839#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 45227#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 44950#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 44951#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44853#L817-45 assume 1 == ~t10_pc~0; 44854#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 45438#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 45225#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 44592#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 44489#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 44490#L836-45 assume !(1 == ~t11_pc~0); 43994#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 43995#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 44763#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 44764#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 45251#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 45324#L855-45 assume 1 == ~t12_pc~0; 44712#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 44159#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 44160#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 45084#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 45085#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 44808#L874-45 assume !(1 == ~t13_pc~0); 44809#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 44717#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 44718#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 44310#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 44311#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 45090#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44259#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44260#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43831#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43832#L1446-3 assume !(1 == ~T5_E~0); 45490#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44799#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44414#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44415#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45726#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44364#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44365#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44773#L1486-3 assume !(1 == ~T13_E~0); 44383#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44384#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44828#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44829#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45254#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45245#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45246#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44948#L1526-3 assume !(1 == ~E_7~0); 44949#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45318#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44401#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44402#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44441#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45684#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43978#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 43979#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44086#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45443#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 45286#L1946 assume !(0 == start_simulation_~tmp~3); 45011#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45012#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44325#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45700#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 45376#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43813#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 43814#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 44061#L1959 assume !(0 != start_simulation_~tmp___0~1); 44062#L1927-1 [2021-11-02 23:08:49,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,463 INFO L85 PathProgramCache]: Analyzing trace with hash 109904039, now seen corresponding path program 1 times [2021-11-02 23:08:49,463 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,463 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696635523] [2021-11-02 23:08:49,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,464 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696635523] [2021-11-02 23:08:49,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696635523] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,510 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452232136] [2021-11-02 23:08:49,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:49,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1679024933, now seen corresponding path program 4 times [2021-11-02 23:08:49,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,514 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40929073] [2021-11-02 23:08:49,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,571 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,572 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40929073] [2021-11-02 23:08:49,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40929073] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414088269] [2021-11-02 23:08:49,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:49,574 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:49,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:49,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:49,575 INFO L87 Difference]: Start difference. First operand 1986 states and 2946 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:49,614 INFO L93 Difference]: Finished difference Result 1986 states and 2945 transitions. [2021-11-02 23:08:49,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:49,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2945 transitions. [2021-11-02 23:08:49,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2945 transitions. [2021-11-02 23:08:49,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:49,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:49,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2945 transitions. [2021-11-02 23:08:49,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:49,650 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-02 23:08:49,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2945 transitions. [2021-11-02 23:08:49,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:49,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4828801611278952) internal successors, (2945), 1985 states have internal predecessors, (2945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2945 transitions. [2021-11-02 23:08:49,702 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-02 23:08:49,702 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-02 23:08:49,702 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-02 23:08:49,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2945 transitions. [2021-11-02 23:08:49,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:49,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:49,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:49,718 INFO L791 eck$LassoCheckResult]: Stem: 48665#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 48666#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49745#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49659#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 48812#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48622#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48623#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48390#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48391#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48814#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49000#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49160#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49181#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48398#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48399#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48126#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48127#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 48574#L966-1 assume !(0 == ~M_E~0); 48575#L1278-1 assume !(0 == ~T1_E~0); 49487#L1283-1 assume !(0 == ~T2_E~0); 49488#L1288-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49693#L1293-1 assume !(0 == ~T4_E~0); 49681#L1298-1 assume !(0 == ~T5_E~0); 49625#L1303-1 assume !(0 == ~T6_E~0); 48225#L1308-1 assume !(0 == ~T7_E~0); 48149#L1313-1 assume !(0 == ~T8_E~0); 48150#L1318-1 assume !(0 == ~T9_E~0); 48152#L1323-1 assume !(0 == ~T10_E~0); 48153#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48336#L1333-1 assume !(0 == ~T12_E~0); 49298#L1338-1 assume !(0 == ~T13_E~0); 49299#L1343-1 assume !(0 == ~E_M~0); 49441#L1348-1 assume !(0 == ~E_1~0); 49721#L1353-1 assume !(0 == ~E_2~0); 49043#L1358-1 assume !(0 == ~E_3~0); 49044#L1363-1 assume !(0 == ~E_4~0); 49335#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 47978#L1373-1 assume !(0 == ~E_6~0); 47979#L1378-1 assume !(0 == ~E_7~0); 48293#L1383-1 assume !(0 == ~E_8~0); 48294#L1388-1 assume !(0 == ~E_9~0); 49372#L1393-1 assume !(0 == ~E_10~0); 49373#L1398-1 assume !(0 == ~E_11~0); 49379#L1403-1 assume !(0 == ~E_12~0); 49623#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 48264#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48265#L627 assume 1 == ~m_pc~0; 49733#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 48626#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48627#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 49205#L1590 assume !(0 != activate_threads_~tmp~1); 49653#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48194#L646 assume !(1 == ~t1_pc~0); 48195#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 48854#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48862#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 48912#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48067#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48068#L665 assume 1 == ~t2_pc~0; 49715#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 48735#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48281#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 48282#L1606 assume !(0 != activate_threads_~tmp___1~0); 48837#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49125#L684 assume !(1 == ~t3_pc~0); 49091#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 49092#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49162#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49700#L1614 assume !(0 != activate_threads_~tmp___2~0); 49739#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49724#L703 assume 1 == ~t4_pc~0; 48561#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 48422#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49033#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 48516#L1622 assume !(0 != activate_threads_~tmp___3~0); 48517#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49557#L722 assume !(1 == ~t5_pc~0); 48473#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 48474#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48822#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 47802#L1630 assume !(0 != activate_threads_~tmp___4~0); 47803#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48014#L741 assume 1 == ~t6_pc~0; 48015#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 48319#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 48472#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 48132#L1638 assume !(0 != activate_threads_~tmp___5~0); 48133#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48446#L760 assume 1 == ~t7_pc~0; 48417#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 48418#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48276#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 48277#L1646 assume !(0 != activate_threads_~tmp___6~0); 48653#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 48654#L779 assume !(1 == ~t8_pc~0); 48059#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 47908#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 47909#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 48311#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 49081#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 49082#L798 assume 1 == ~t9_pc~0; 49584#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 49522#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 48060#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 48061#L1662 assume !(0 != activate_threads_~tmp___8~0); 47843#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 47844#L817 assume !(1 == ~t10_pc~0); 47890#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 48672#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 48673#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 48134#L1670 assume !(0 != activate_threads_~tmp___9~0); 48135#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 49034#L836 assume 1 == ~t11_pc~0; 49035#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 48233#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 48234#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 48197#L1678 assume !(0 != activate_threads_~tmp___10~0); 48198#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 49532#L855 assume !(1 == ~t12_pc~0); 48859#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 48860#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 49413#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 49438#L1686 assume !(0 != activate_threads_~tmp___11~0); 49378#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 48183#L874 assume 1 == ~t13_pc~0; 48184#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 48345#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 48346#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 48475#L1694 assume !(0 != activate_threads_~tmp___12~0); 49505#L1694-2 assume !(1 == ~M_E~0); 48388#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48389#L1431-1 assume !(1 == ~T2_E~0); 47910#L1436-1 assume !(1 == ~T3_E~0); 47911#L1441-1 assume !(1 == ~T4_E~0); 48703#L1446-1 assume !(1 == ~T5_E~0); 48704#L1451-1 assume !(1 == ~T6_E~0); 49439#L1456-1 assume !(1 == ~T7_E~0); 49075#L1461-1 assume !(1 == ~T8_E~0); 48618#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48619#L1471-1 assume !(1 == ~T10_E~0); 49414#L1476-1 assume !(1 == ~T11_E~0); 49415#L1481-1 assume !(1 == ~T12_E~0); 49580#L1486-1 assume !(1 == ~T13_E~0); 48237#L1491-1 assume !(1 == ~E_M~0); 47852#L1496-1 assume !(1 == ~E_1~0); 47853#L1501-1 assume !(1 == ~E_2~0); 48698#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 48699#L1511-1 assume !(1 == ~E_4~0); 48652#L1516-1 assume !(1 == ~E_5~0); 47806#L1521-1 assume !(1 == ~E_6~0); 47807#L1526-1 assume !(1 == ~E_7~0); 47851#L1531-1 assume !(1 == ~E_8~0); 48409#L1536-1 assume !(1 == ~E_9~0); 48128#L1541-1 assume !(1 == ~E_10~0); 48129#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 49634#L1551-1 assume !(1 == ~E_12~0); 48298#L1556-1 assume !(1 == ~E_13~0); 48041#L1927-1 [2021-11-02 23:08:49,718 INFO L793 eck$LassoCheckResult]: Loop: 48041#L1927-1 assume !false; 48322#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 48333#L1253 assume !false; 47794#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 47795#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48481#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 48404#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 48405#L1066 assume !(0 != eval_~tmp~0); 49638#L1268 start_simulation_~kernel_st~0 := 2; 48147#L894-1 start_simulation_~kernel_st~0 := 3; 48148#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48713#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48714#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48313#L1288-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48314#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49499#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49500#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49642#L1308-3 assume !(0 == ~T7_E~0); 49494#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48956#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48100#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48101#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49574#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48247#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 48248#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49386#L1348-3 assume !(0 == ~E_1~0); 49578#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49579#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48918#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48433#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48434#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49234#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49235#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49432#L1388-3 assume !(0 == ~E_9~0); 49419#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49420#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48764#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48765#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49586#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48611#L627-45 assume !(1 == ~m_pc~0); 48612#L627-47 is_master_triggered_~__retres1~0 := 0; 49108#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49576#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 48939#L1590-45 assume !(0 != activate_threads_~tmp~1); 48940#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49536#L646-45 assume !(1 == ~t1_pc~0); 48801#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 48802#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48986#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 48987#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48218#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48219#L665-45 assume 1 == ~t2_pc~0; 47892#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 47893#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48719#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 47919#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 47920#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49140#L684-45 assume 1 == ~t3_pc~0; 49141#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 48216#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49292#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 49643#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 49440#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49245#L703-45 assume 1 == ~t4_pc~0; 49084#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 49086#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48679#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 48373#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 48374#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48710#L722-45 assume 1 == ~t5_pc~0; 48700#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 48701#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49651#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 49701#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49066#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49067#L741-45 assume !(1 == ~t6_pc~0); 48465#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 48464#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 48821#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 49161#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 49192#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 49280#L760-45 assume 1 == ~t7_pc~0; 49168#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 49169#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48740#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 48741#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49300#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49301#L779-45 assume !(1 == ~t8_pc~0); 48176#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 48177#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 48201#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 48202#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 49281#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 49282#L798-45 assume 1 == ~t9_pc~0; 49696#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 48818#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 49206#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 48929#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 48930#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 48832#L817-45 assume 1 == ~t10_pc~0; 48833#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 49417#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 49204#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 48571#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 48468#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 48469#L836-45 assume !(1 == ~t11_pc~0); 47973#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 47974#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 48742#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 48743#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49230#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 49303#L855-45 assume 1 == ~t12_pc~0; 48691#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 48138#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48139#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 49063#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 49064#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 48787#L874-45 assume !(1 == ~t13_pc~0); 48788#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 48696#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 48697#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 48289#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 48290#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 49069#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48238#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48239#L1436-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47810#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47811#L1446-3 assume !(1 == ~T5_E~0); 49469#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48778#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48393#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48394#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49705#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48343#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48344#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48752#L1486-3 assume !(1 == ~T13_E~0); 48362#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48363#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48807#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48808#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49233#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49224#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49225#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48927#L1526-3 assume !(1 == ~E_7~0); 48928#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49297#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 48380#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48381#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48420#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49663#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47957#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 47958#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48065#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49422#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 49265#L1946 assume !(0 == start_simulation_~tmp~3); 48990#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 48991#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48304#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49679#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 49355#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47792#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 47793#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 48040#L1959 assume !(0 != start_simulation_~tmp___0~1); 48041#L1927-1 [2021-11-02 23:08:49,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,719 INFO L85 PathProgramCache]: Analyzing trace with hash 265884581, now seen corresponding path program 1 times [2021-11-02 23:08:49,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142712705] [2021-11-02 23:08:49,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,777 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,778 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142712705] [2021-11-02 23:08:49,778 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142712705] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,778 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,778 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:49,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109405404] [2021-11-02 23:08:49,780 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:49,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:49,781 INFO L85 PathProgramCache]: Analyzing trace with hash -476830598, now seen corresponding path program 1 times [2021-11-02 23:08:49,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:49,781 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215636713] [2021-11-02 23:08:49,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:49,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:49,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:49,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:49,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:49,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215636713] [2021-11-02 23:08:49,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215636713] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:49,837 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:49,838 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:49,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046858585] [2021-11-02 23:08:49,839 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:49,839 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:49,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:49,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:49,840 INFO L87 Difference]: Start difference. First operand 1986 states and 2945 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:49,915 INFO L93 Difference]: Finished difference Result 1986 states and 2940 transitions. [2021-11-02 23:08:49,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:49,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2940 transitions. [2021-11-02 23:08:49,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:49,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2940 transitions. [2021-11-02 23:08:49,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:49,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:49,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2940 transitions. [2021-11-02 23:08:49,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:49,948 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-02 23:08:49,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2940 transitions. [2021-11-02 23:08:49,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:49,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4803625377643506) internal successors, (2940), 1985 states have internal predecessors, (2940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:49,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2940 transitions. [2021-11-02 23:08:49,992 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-02 23:08:49,993 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-02 23:08:49,993 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-02 23:08:49,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2940 transitions. [2021-11-02 23:08:50,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:50,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:50,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,006 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,006 INFO L791 eck$LassoCheckResult]: Stem: 52644#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 52645#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53724#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53638#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 52791#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52601#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52602#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52369#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52370#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52793#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52979#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53139#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53160#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52377#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52378#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52105#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52106#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 52553#L966-1 assume !(0 == ~M_E~0); 52554#L1278-1 assume !(0 == ~T1_E~0); 53466#L1283-1 assume !(0 == ~T2_E~0); 53467#L1288-1 assume !(0 == ~T3_E~0); 53672#L1293-1 assume !(0 == ~T4_E~0); 53660#L1298-1 assume !(0 == ~T5_E~0); 53604#L1303-1 assume !(0 == ~T6_E~0); 52204#L1308-1 assume !(0 == ~T7_E~0); 52128#L1313-1 assume !(0 == ~T8_E~0); 52129#L1318-1 assume !(0 == ~T9_E~0); 52131#L1323-1 assume !(0 == ~T10_E~0); 52132#L1328-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52315#L1333-1 assume !(0 == ~T12_E~0); 53277#L1338-1 assume !(0 == ~T13_E~0); 53278#L1343-1 assume !(0 == ~E_M~0); 53420#L1348-1 assume !(0 == ~E_1~0); 53700#L1353-1 assume !(0 == ~E_2~0); 53022#L1358-1 assume !(0 == ~E_3~0); 53023#L1363-1 assume !(0 == ~E_4~0); 53314#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 51957#L1373-1 assume !(0 == ~E_6~0); 51958#L1378-1 assume !(0 == ~E_7~0); 52272#L1383-1 assume !(0 == ~E_8~0); 52273#L1388-1 assume !(0 == ~E_9~0); 53351#L1393-1 assume !(0 == ~E_10~0); 53352#L1398-1 assume !(0 == ~E_11~0); 53358#L1403-1 assume !(0 == ~E_12~0); 53602#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 52243#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52244#L627 assume 1 == ~m_pc~0; 53712#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 52605#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52606#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 53184#L1590 assume !(0 != activate_threads_~tmp~1); 53632#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52173#L646 assume !(1 == ~t1_pc~0); 52174#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 52833#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52841#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 52891#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52046#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52047#L665 assume 1 == ~t2_pc~0; 53694#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 52714#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52260#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 52261#L1606 assume !(0 != activate_threads_~tmp___1~0); 52816#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53104#L684 assume !(1 == ~t3_pc~0); 53070#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 53071#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53141#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 53679#L1614 assume !(0 != activate_threads_~tmp___2~0); 53718#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53703#L703 assume 1 == ~t4_pc~0; 52540#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 52401#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53012#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 52495#L1622 assume !(0 != activate_threads_~tmp___3~0); 52496#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53536#L722 assume !(1 == ~t5_pc~0); 52452#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 52453#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52801#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 51781#L1630 assume !(0 != activate_threads_~tmp___4~0); 51782#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 51993#L741 assume 1 == ~t6_pc~0; 51994#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 52298#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 52451#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 52111#L1638 assume !(0 != activate_threads_~tmp___5~0); 52112#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 52425#L760 assume 1 == ~t7_pc~0; 52396#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 52397#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 52255#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 52256#L1646 assume !(0 != activate_threads_~tmp___6~0); 52632#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 52633#L779 assume !(1 == ~t8_pc~0); 52038#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 51887#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 51888#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 52290#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 53060#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 53061#L798 assume 1 == ~t9_pc~0; 53563#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 53501#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 52039#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 52040#L1662 assume !(0 != activate_threads_~tmp___8~0); 51822#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 51823#L817 assume !(1 == ~t10_pc~0); 51869#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 52651#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 52652#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 52113#L1670 assume !(0 != activate_threads_~tmp___9~0); 52114#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 53013#L836 assume 1 == ~t11_pc~0; 53014#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 52212#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 52213#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 52176#L1678 assume !(0 != activate_threads_~tmp___10~0); 52177#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 53511#L855 assume !(1 == ~t12_pc~0); 52838#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 52839#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 53392#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 53417#L1686 assume !(0 != activate_threads_~tmp___11~0); 53357#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 52162#L874 assume 1 == ~t13_pc~0; 52163#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 52324#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 52325#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 52454#L1694 assume !(0 != activate_threads_~tmp___12~0); 53484#L1694-2 assume !(1 == ~M_E~0); 52367#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52368#L1431-1 assume !(1 == ~T2_E~0); 51889#L1436-1 assume !(1 == ~T3_E~0); 51890#L1441-1 assume !(1 == ~T4_E~0); 52682#L1446-1 assume !(1 == ~T5_E~0); 52683#L1451-1 assume !(1 == ~T6_E~0); 53418#L1456-1 assume !(1 == ~T7_E~0); 53054#L1461-1 assume !(1 == ~T8_E~0); 52597#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52598#L1471-1 assume !(1 == ~T10_E~0); 53393#L1476-1 assume !(1 == ~T11_E~0); 53394#L1481-1 assume !(1 == ~T12_E~0); 53559#L1486-1 assume !(1 == ~T13_E~0); 52216#L1491-1 assume !(1 == ~E_M~0); 51831#L1496-1 assume !(1 == ~E_1~0); 51832#L1501-1 assume !(1 == ~E_2~0); 52677#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 52678#L1511-1 assume !(1 == ~E_4~0); 52631#L1516-1 assume !(1 == ~E_5~0); 51785#L1521-1 assume !(1 == ~E_6~0); 51786#L1526-1 assume !(1 == ~E_7~0); 51830#L1531-1 assume !(1 == ~E_8~0); 52388#L1536-1 assume !(1 == ~E_9~0); 52107#L1541-1 assume !(1 == ~E_10~0); 52108#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 53613#L1551-1 assume !(1 == ~E_12~0); 52277#L1556-1 assume !(1 == ~E_13~0); 52020#L1927-1 [2021-11-02 23:08:50,007 INFO L793 eck$LassoCheckResult]: Loop: 52020#L1927-1 assume !false; 52301#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 52312#L1253 assume !false; 51773#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 51774#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52460#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 52383#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 52384#L1066 assume !(0 != eval_~tmp~0); 53617#L1268 start_simulation_~kernel_st~0 := 2; 52126#L894-1 start_simulation_~kernel_st~0 := 3; 52127#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52692#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52693#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52292#L1288-3 assume !(0 == ~T3_E~0); 52293#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53478#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53479#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53621#L1308-3 assume !(0 == ~T7_E~0); 53473#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52935#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52079#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52080#L1328-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53553#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52226#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 52227#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53365#L1348-3 assume !(0 == ~E_1~0); 53557#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53558#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52897#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52412#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52413#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53213#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53214#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53411#L1388-3 assume !(0 == ~E_9~0); 53398#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53399#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52743#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52744#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53565#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52590#L627-45 assume 1 == ~m_pc~0; 52592#L628-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 53087#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53555#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 52918#L1590-45 assume !(0 != activate_threads_~tmp~1); 52919#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53515#L646-45 assume 1 == ~t1_pc~0; 53586#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 52781#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52965#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 52966#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52197#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52198#L665-45 assume !(1 == ~t2_pc~0); 51873#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 51872#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52698#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 51898#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 51899#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53119#L684-45 assume 1 == ~t3_pc~0; 53120#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 52195#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53271#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 53622#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 53419#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53224#L703-45 assume 1 == ~t4_pc~0; 53063#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 53065#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52658#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 52352#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 52353#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52689#L722-45 assume 1 == ~t5_pc~0; 52679#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 52680#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53630#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 53680#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 53045#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 53046#L741-45 assume 1 == ~t6_pc~0; 52442#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 52443#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 52800#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 53140#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 53171#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53259#L760-45 assume 1 == ~t7_pc~0; 53147#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 53148#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 52719#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 52720#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 53279#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 53280#L779-45 assume !(1 == ~t8_pc~0); 52155#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 52156#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 52180#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 52181#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 53260#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 53261#L798-45 assume 1 == ~t9_pc~0; 53675#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 52797#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 53185#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 52908#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 52909#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 52811#L817-45 assume 1 == ~t10_pc~0; 52812#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 53396#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 53183#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 52550#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 52447#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 52448#L836-45 assume !(1 == ~t11_pc~0); 51952#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 51953#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 52721#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 52722#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 53209#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 53282#L855-45 assume 1 == ~t12_pc~0; 52670#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 52117#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 52118#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 53042#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 53043#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 52766#L874-45 assume 1 == ~t13_pc~0; 52768#L875-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 52675#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 52676#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 52268#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 52269#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 53048#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52217#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52218#L1436-3 assume !(1 == ~T3_E~0); 51789#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51790#L1446-3 assume !(1 == ~T5_E~0); 53448#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52757#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52372#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52373#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53684#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52322#L1476-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52323#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52731#L1486-3 assume !(1 == ~T13_E~0); 52341#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52342#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52786#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52787#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53212#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53203#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53204#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52906#L1526-3 assume !(1 == ~E_7~0); 52907#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53276#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52359#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52360#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 52399#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53642#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 51936#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 51937#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52044#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53401#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 53244#L1946 assume !(0 == start_simulation_~tmp~3); 52969#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 52970#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52283#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53658#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 53334#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 51771#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 51772#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 52019#L1959 assume !(0 != start_simulation_~tmp___0~1); 52020#L1927-1 [2021-11-02 23:08:50,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,007 INFO L85 PathProgramCache]: Analyzing trace with hash 335532455, now seen corresponding path program 1 times [2021-11-02 23:08:50,008 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,008 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951418399] [2021-11-02 23:08:50,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951418399] [2021-11-02 23:08:50,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951418399] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,053 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:50,054 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275862607] [2021-11-02 23:08:50,054 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:50,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,055 INFO L85 PathProgramCache]: Analyzing trace with hash -2048832487, now seen corresponding path program 1 times [2021-11-02 23:08:50,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,055 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089621733] [2021-11-02 23:08:50,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,103 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,103 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089621733] [2021-11-02 23:08:50,103 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089621733] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,104 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,104 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:50,104 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [359114930] [2021-11-02 23:08:50,105 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:50,105 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:50,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:50,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:50,106 INFO L87 Difference]: Start difference. First operand 1986 states and 2940 transitions. cyclomatic complexity: 955 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:50,144 INFO L93 Difference]: Finished difference Result 1986 states and 2935 transitions. [2021-11-02 23:08:50,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:50,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2935 transitions. [2021-11-02 23:08:50,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2935 transitions. [2021-11-02 23:08:50,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:50,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:50,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2935 transitions. [2021-11-02 23:08:50,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:50,176 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-02 23:08:50,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2935 transitions. [2021-11-02 23:08:50,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:50,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4778449144008057) internal successors, (2935), 1985 states have internal predecessors, (2935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2935 transitions. [2021-11-02 23:08:50,226 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-02 23:08:50,227 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-02 23:08:50,227 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-02 23:08:50,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2935 transitions. [2021-11-02 23:08:50,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:50,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:50,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,242 INFO L791 eck$LassoCheckResult]: Stem: 56623#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 56624#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 57703#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 57617#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 56770#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56580#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56581#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56348#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56349#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56772#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56958#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57118#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 57139#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56356#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56357#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56084#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56085#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 56532#L966-1 assume !(0 == ~M_E~0); 56533#L1278-1 assume !(0 == ~T1_E~0); 57445#L1283-1 assume !(0 == ~T2_E~0); 57446#L1288-1 assume !(0 == ~T3_E~0); 57651#L1293-1 assume !(0 == ~T4_E~0); 57639#L1298-1 assume !(0 == ~T5_E~0); 57583#L1303-1 assume !(0 == ~T6_E~0); 56183#L1308-1 assume !(0 == ~T7_E~0); 56107#L1313-1 assume !(0 == ~T8_E~0); 56108#L1318-1 assume !(0 == ~T9_E~0); 56110#L1323-1 assume !(0 == ~T10_E~0); 56111#L1328-1 assume !(0 == ~T11_E~0); 56294#L1333-1 assume !(0 == ~T12_E~0); 57256#L1338-1 assume !(0 == ~T13_E~0); 57257#L1343-1 assume !(0 == ~E_M~0); 57399#L1348-1 assume !(0 == ~E_1~0); 57679#L1353-1 assume !(0 == ~E_2~0); 57001#L1358-1 assume !(0 == ~E_3~0); 57002#L1363-1 assume !(0 == ~E_4~0); 57293#L1368-1 assume 0 == ~E_5~0;~E_5~0 := 1; 55936#L1373-1 assume !(0 == ~E_6~0); 55937#L1378-1 assume !(0 == ~E_7~0); 56251#L1383-1 assume !(0 == ~E_8~0); 56252#L1388-1 assume !(0 == ~E_9~0); 57330#L1393-1 assume !(0 == ~E_10~0); 57331#L1398-1 assume !(0 == ~E_11~0); 57337#L1403-1 assume !(0 == ~E_12~0); 57581#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 56222#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56223#L627 assume 1 == ~m_pc~0; 57691#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 56584#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56585#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 57163#L1590 assume !(0 != activate_threads_~tmp~1); 57611#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56152#L646 assume !(1 == ~t1_pc~0); 56153#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 56812#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56820#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 56870#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56025#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56026#L665 assume 1 == ~t2_pc~0; 57673#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 56693#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56239#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 56240#L1606 assume !(0 != activate_threads_~tmp___1~0); 56795#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57083#L684 assume !(1 == ~t3_pc~0); 57049#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 57050#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57120#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 57658#L1614 assume !(0 != activate_threads_~tmp___2~0); 57697#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57682#L703 assume 1 == ~t4_pc~0; 56519#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 56380#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56991#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 56474#L1622 assume !(0 != activate_threads_~tmp___3~0); 56475#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57515#L722 assume !(1 == ~t5_pc~0); 56431#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 56432#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56780#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 55760#L1630 assume !(0 != activate_threads_~tmp___4~0); 55761#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 55972#L741 assume 1 == ~t6_pc~0; 55973#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 56277#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 56430#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 56090#L1638 assume !(0 != activate_threads_~tmp___5~0); 56091#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 56404#L760 assume 1 == ~t7_pc~0; 56375#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 56376#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 56234#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 56235#L1646 assume !(0 != activate_threads_~tmp___6~0); 56611#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 56612#L779 assume !(1 == ~t8_pc~0); 56017#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 55866#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 55867#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 56269#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 57039#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 57040#L798 assume 1 == ~t9_pc~0; 57542#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 57480#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 56018#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 56019#L1662 assume !(0 != activate_threads_~tmp___8~0); 55801#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 55802#L817 assume !(1 == ~t10_pc~0); 55848#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 56630#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 56631#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 56092#L1670 assume !(0 != activate_threads_~tmp___9~0); 56093#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 56992#L836 assume 1 == ~t11_pc~0; 56993#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 56191#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 56192#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56155#L1678 assume !(0 != activate_threads_~tmp___10~0); 56156#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 57490#L855 assume !(1 == ~t12_pc~0); 56817#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 56818#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 57371#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 57396#L1686 assume !(0 != activate_threads_~tmp___11~0); 57336#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 56141#L874 assume 1 == ~t13_pc~0; 56142#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 56303#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 56304#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 56433#L1694 assume !(0 != activate_threads_~tmp___12~0); 57463#L1694-2 assume !(1 == ~M_E~0); 56346#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56347#L1431-1 assume !(1 == ~T2_E~0); 55868#L1436-1 assume !(1 == ~T3_E~0); 55869#L1441-1 assume !(1 == ~T4_E~0); 56661#L1446-1 assume !(1 == ~T5_E~0); 56662#L1451-1 assume !(1 == ~T6_E~0); 57397#L1456-1 assume !(1 == ~T7_E~0); 57033#L1461-1 assume !(1 == ~T8_E~0); 56576#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56577#L1471-1 assume !(1 == ~T10_E~0); 57372#L1476-1 assume !(1 == ~T11_E~0); 57373#L1481-1 assume !(1 == ~T12_E~0); 57538#L1486-1 assume !(1 == ~T13_E~0); 56195#L1491-1 assume !(1 == ~E_M~0); 55810#L1496-1 assume !(1 == ~E_1~0); 55811#L1501-1 assume !(1 == ~E_2~0); 56656#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 56657#L1511-1 assume !(1 == ~E_4~0); 56610#L1516-1 assume !(1 == ~E_5~0); 55764#L1521-1 assume !(1 == ~E_6~0); 55765#L1526-1 assume !(1 == ~E_7~0); 55809#L1531-1 assume !(1 == ~E_8~0); 56367#L1536-1 assume !(1 == ~E_9~0); 56086#L1541-1 assume !(1 == ~E_10~0); 56087#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 57592#L1551-1 assume !(1 == ~E_12~0); 56256#L1556-1 assume !(1 == ~E_13~0); 55999#L1927-1 [2021-11-02 23:08:50,243 INFO L793 eck$LassoCheckResult]: Loop: 55999#L1927-1 assume !false; 56280#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 56291#L1253 assume !false; 55752#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 55753#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56439#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 56362#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 56363#L1066 assume !(0 != eval_~tmp~0); 57596#L1268 start_simulation_~kernel_st~0 := 2; 56105#L894-1 start_simulation_~kernel_st~0 := 3; 56106#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56671#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56672#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56271#L1288-3 assume !(0 == ~T3_E~0); 56272#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57457#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57458#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57600#L1308-3 assume !(0 == ~T7_E~0); 57452#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56914#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 56058#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 56059#L1328-3 assume !(0 == ~T11_E~0); 57532#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56205#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 56206#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57344#L1348-3 assume !(0 == ~E_1~0); 57536#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57537#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56876#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56391#L1368-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56392#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57192#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57193#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57390#L1388-3 assume !(0 == ~E_9~0); 57377#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 57378#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56722#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 56723#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 57544#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56569#L627-45 assume !(1 == ~m_pc~0); 56570#L627-47 is_master_triggered_~__retres1~0 := 0; 57066#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57534#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 56897#L1590-45 assume !(0 != activate_threads_~tmp~1); 56898#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57494#L646-45 assume !(1 == ~t1_pc~0); 56759#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 56760#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56944#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 56945#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56176#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56177#L665-45 assume 1 == ~t2_pc~0; 55850#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 55851#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56677#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 55877#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 55878#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57098#L684-45 assume 1 == ~t3_pc~0; 57099#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56174#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57250#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 57601#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 57398#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57203#L703-45 assume 1 == ~t4_pc~0; 57042#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 57044#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56637#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 56331#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 56332#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56668#L722-45 assume 1 == ~t5_pc~0; 56658#L723-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56659#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57609#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 57659#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 57024#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 57025#L741-45 assume 1 == ~t6_pc~0; 56421#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 56422#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 56779#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 57119#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 57150#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57238#L760-45 assume 1 == ~t7_pc~0; 57126#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 57127#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 56698#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 56699#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 57258#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57259#L779-45 assume !(1 == ~t8_pc~0); 56134#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 56135#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 56159#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 56160#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 57239#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 57240#L798-45 assume 1 == ~t9_pc~0; 57654#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 56776#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 57164#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 56887#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 56888#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 56790#L817-45 assume 1 == ~t10_pc~0; 56791#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 57375#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 57162#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 56529#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 56426#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 56427#L836-45 assume !(1 == ~t11_pc~0); 55931#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 55932#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 56700#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56701#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 57188#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 57261#L855-45 assume 1 == ~t12_pc~0; 56649#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 56096#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 56097#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 57021#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 57022#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 56745#L874-45 assume !(1 == ~t13_pc~0); 56746#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 56654#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 56655#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 56247#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 56248#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 57027#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56196#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56197#L1436-3 assume !(1 == ~T3_E~0); 55768#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55769#L1446-3 assume !(1 == ~T5_E~0); 57427#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56736#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56351#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56352#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57663#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56301#L1476-3 assume !(1 == ~T11_E~0); 56302#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56710#L1486-3 assume !(1 == ~T13_E~0); 56320#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56321#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56765#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56766#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57191#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57182#L1516-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57183#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56885#L1526-3 assume !(1 == ~E_7~0); 56886#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57255#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56338#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56339#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56378#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57621#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 55915#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 55916#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56023#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57380#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 57223#L1946 assume !(0 == start_simulation_~tmp~3); 56948#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 56949#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56262#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57637#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 57313#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 55750#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 55751#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 55998#L1959 assume !(0 != start_simulation_~tmp___0~1); 55999#L1927-1 [2021-11-02 23:08:50,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,244 INFO L85 PathProgramCache]: Analyzing trace with hash -612519511, now seen corresponding path program 1 times [2021-11-02 23:08:50,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,245 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511185980] [2021-11-02 23:08:50,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,295 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511185980] [2021-11-02 23:08:50,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511185980] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,295 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,295 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:50,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266165634] [2021-11-02 23:08:50,296 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:50,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,297 INFO L85 PathProgramCache]: Analyzing trace with hash 145618387, now seen corresponding path program 1 times [2021-11-02 23:08:50,297 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,297 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483825816] [2021-11-02 23:08:50,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,354 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483825816] [2021-11-02 23:08:50,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483825816] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,354 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:50,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117724815] [2021-11-02 23:08:50,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:50,356 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:50,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:50,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:50,357 INFO L87 Difference]: Start difference. First operand 1986 states and 2935 transitions. cyclomatic complexity: 950 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:50,454 INFO L93 Difference]: Finished difference Result 1986 states and 2914 transitions. [2021-11-02 23:08:50,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:50,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2914 transitions. [2021-11-02 23:08:50,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2914 transitions. [2021-11-02 23:08:50,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:50,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:50,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2914 transitions. [2021-11-02 23:08:50,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:50,497 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-02 23:08:50,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2914 transitions. [2021-11-02 23:08:50,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:50,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4672708962739174) internal successors, (2914), 1985 states have internal predecessors, (2914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2914 transitions. [2021-11-02 23:08:50,547 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-02 23:08:50,548 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-02 23:08:50,548 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-02 23:08:50,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2914 transitions. [2021-11-02 23:08:50,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:50,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:50,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,561 INFO L791 eck$LassoCheckResult]: Stem: 60601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 60602#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 61682#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 61596#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 60747#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60558#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60559#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60326#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60327#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60749#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60935#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61095#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 61116#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60334#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60335#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60062#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60063#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60510#L966-1 assume !(0 == ~M_E~0); 60511#L1278-1 assume !(0 == ~T1_E~0); 61422#L1283-1 assume !(0 == ~T2_E~0); 61423#L1288-1 assume !(0 == ~T3_E~0); 61630#L1293-1 assume !(0 == ~T4_E~0); 61618#L1298-1 assume !(0 == ~T5_E~0); 61561#L1303-1 assume !(0 == ~T6_E~0); 60161#L1308-1 assume !(0 == ~T7_E~0); 60085#L1313-1 assume !(0 == ~T8_E~0); 60086#L1318-1 assume !(0 == ~T9_E~0); 60088#L1323-1 assume !(0 == ~T10_E~0); 60089#L1328-1 assume !(0 == ~T11_E~0); 60272#L1333-1 assume !(0 == ~T12_E~0); 61233#L1338-1 assume !(0 == ~T13_E~0); 61234#L1343-1 assume !(0 == ~E_M~0); 61375#L1348-1 assume !(0 == ~E_1~0); 61658#L1353-1 assume !(0 == ~E_2~0); 60978#L1358-1 assume !(0 == ~E_3~0); 60979#L1363-1 assume !(0 == ~E_4~0); 61270#L1368-1 assume !(0 == ~E_5~0); 59915#L1373-1 assume !(0 == ~E_6~0); 59916#L1378-1 assume !(0 == ~E_7~0); 60229#L1383-1 assume !(0 == ~E_8~0); 60230#L1388-1 assume !(0 == ~E_9~0); 61306#L1393-1 assume !(0 == ~E_10~0); 61307#L1398-1 assume !(0 == ~E_11~0); 61313#L1403-1 assume !(0 == ~E_12~0); 61559#L1408-1 assume 0 == ~E_13~0;~E_13~0 := 1; 60200#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60201#L627 assume 1 == ~m_pc~0; 61670#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 60562#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60563#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 61140#L1590 assume !(0 != activate_threads_~tmp~1); 61590#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60130#L646 assume !(1 == ~t1_pc~0); 60131#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 60789#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60797#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 60847#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60003#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60004#L665 assume 1 == ~t2_pc~0; 61652#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 60670#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60217#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 60218#L1606 assume !(0 != activate_threads_~tmp___1~0); 60772#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61060#L684 assume !(1 == ~t3_pc~0); 61026#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 61027#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61097#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 61637#L1614 assume !(0 != activate_threads_~tmp___2~0); 61676#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61661#L703 assume 1 == ~t4_pc~0; 60497#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 60358#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60968#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 60452#L1622 assume !(0 != activate_threads_~tmp___3~0); 60453#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 61492#L722 assume !(1 == ~t5_pc~0); 60409#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 60410#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60757#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 59739#L1630 assume !(0 != activate_threads_~tmp___4~0); 59740#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 59951#L741 assume 1 == ~t6_pc~0; 59952#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 60255#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60408#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 60068#L1638 assume !(0 != activate_threads_~tmp___5~0); 60069#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 60382#L760 assume 1 == ~t7_pc~0; 60353#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 60354#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 60212#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 60213#L1646 assume !(0 != activate_threads_~tmp___6~0); 60589#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 60590#L779 assume !(1 == ~t8_pc~0); 59995#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 59845#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 59846#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 60247#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 61016#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 61017#L798 assume 1 == ~t9_pc~0; 61519#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 61457#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 59996#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 59997#L1662 assume !(0 != activate_threads_~tmp___8~0); 59780#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 59781#L817 assume !(1 == ~t10_pc~0); 59827#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 60608#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 60609#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 60070#L1670 assume !(0 != activate_threads_~tmp___9~0); 60071#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 60969#L836 assume 1 == ~t11_pc~0; 60970#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 60169#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 60170#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 60133#L1678 assume !(0 != activate_threads_~tmp___10~0); 60134#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 61467#L855 assume !(1 == ~t12_pc~0); 60794#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 60795#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 61347#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 61372#L1686 assume !(0 != activate_threads_~tmp___11~0); 61312#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 60119#L874 assume 1 == ~t13_pc~0; 60120#L875 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 60281#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 60282#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 60411#L1694 assume !(0 != activate_threads_~tmp___12~0); 61440#L1694-2 assume !(1 == ~M_E~0); 60324#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60325#L1431-1 assume !(1 == ~T2_E~0); 59847#L1436-1 assume !(1 == ~T3_E~0); 59848#L1441-1 assume !(1 == ~T4_E~0); 60638#L1446-1 assume !(1 == ~T5_E~0); 60639#L1451-1 assume !(1 == ~T6_E~0); 61373#L1456-1 assume !(1 == ~T7_E~0); 61010#L1461-1 assume !(1 == ~T8_E~0); 60554#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60555#L1471-1 assume !(1 == ~T10_E~0); 61348#L1476-1 assume !(1 == ~T11_E~0); 61349#L1481-1 assume !(1 == ~T12_E~0); 61515#L1486-1 assume !(1 == ~T13_E~0); 60173#L1491-1 assume !(1 == ~E_M~0); 59789#L1496-1 assume !(1 == ~E_1~0); 59790#L1501-1 assume !(1 == ~E_2~0); 60634#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 60635#L1511-1 assume !(1 == ~E_4~0); 60588#L1516-1 assume !(1 == ~E_5~0); 59743#L1521-1 assume !(1 == ~E_6~0); 59744#L1526-1 assume !(1 == ~E_7~0); 59788#L1531-1 assume !(1 == ~E_8~0); 60345#L1536-1 assume !(1 == ~E_9~0); 60064#L1541-1 assume !(1 == ~E_10~0); 60065#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 61570#L1551-1 assume !(1 == ~E_12~0); 60234#L1556-1 assume !(1 == ~E_13~0); 59978#L1927-1 [2021-11-02 23:08:50,562 INFO L793 eck$LassoCheckResult]: Loop: 59978#L1927-1 assume !false; 60258#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 60269#L1253 assume !false; 59731#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 59732#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60417#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 60340#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 60341#L1066 assume !(0 != eval_~tmp~0); 61574#L1268 start_simulation_~kernel_st~0 := 2; 60083#L894-1 start_simulation_~kernel_st~0 := 3; 60084#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 60648#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60649#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60249#L1288-3 assume !(0 == ~T3_E~0); 60250#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61434#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61435#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61578#L1308-3 assume !(0 == ~T7_E~0); 61429#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60890#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60036#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 60037#L1328-3 assume !(0 == ~T11_E~0); 61509#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60183#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 60184#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61320#L1348-3 assume !(0 == ~E_1~0); 61513#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61514#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60853#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60369#L1368-3 assume !(0 == ~E_5~0); 60370#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61169#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61170#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61366#L1388-3 assume !(0 == ~E_9~0); 61353#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61354#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60699#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 60700#L1408-3 assume 0 == ~E_13~0;~E_13~0 := 1; 61521#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60547#L627-45 assume !(1 == ~m_pc~0); 60548#L627-47 is_master_triggered_~__retres1~0 := 0; 61043#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61511#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 60874#L1590-45 assume !(0 != activate_threads_~tmp~1); 60875#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61471#L646-45 assume !(1 == ~t1_pc~0); 60736#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 60737#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60921#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 60922#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60154#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60155#L665-45 assume 1 == ~t2_pc~0; 59829#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 59830#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60654#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 59856#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 59857#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61075#L684-45 assume 1 == ~t3_pc~0; 61076#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 60152#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61227#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 61580#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 61374#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61180#L703-45 assume 1 == ~t4_pc~0; 61019#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 61021#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60615#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 60309#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 60310#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60645#L722-45 assume !(1 == ~t5_pc~0); 60637#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 61547#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 61588#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 61638#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 61001#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 61002#L741-45 assume !(1 == ~t6_pc~0); 60401#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 60400#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60756#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 61096#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 61127#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 61215#L760-45 assume !(1 == ~t7_pc~0); 61105#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 61104#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 60675#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 60676#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 61235#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 61236#L779-45 assume !(1 == ~t8_pc~0); 60112#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 60113#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 60137#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 60138#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 61216#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 61217#L798-45 assume !(1 == ~t9_pc~0); 60752#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 60753#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 61141#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 60864#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 60865#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 60767#L817-45 assume 1 == ~t10_pc~0; 60768#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 61351#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 61139#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 60507#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 60404#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 60405#L836-45 assume 1 == ~t11_pc~0; 61028#L837-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 59911#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 60677#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 60678#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 61165#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 61238#L855-45 assume 1 == ~t12_pc~0; 60627#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 60074#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 60075#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 60998#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 60999#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 60722#L874-45 assume !(1 == ~t13_pc~0); 60723#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 60632#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 60633#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 60225#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 60226#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 61004#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60174#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60175#L1436-3 assume !(1 == ~T3_E~0); 59747#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59748#L1446-3 assume !(1 == ~T5_E~0); 61403#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60713#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60329#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60330#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61642#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60279#L1476-3 assume !(1 == ~T11_E~0); 60280#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60687#L1486-3 assume !(1 == ~T13_E~0); 60298#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 60299#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60742#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60743#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61168#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61159#L1516-3 assume !(1 == ~E_5~0); 61160#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60862#L1526-3 assume !(1 == ~E_7~0); 60863#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61232#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60316#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60317#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60356#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61600#L1556-3 assume 1 == ~E_13~0;~E_13~0 := 2; 59894#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 59895#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60001#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61356#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 61200#L1946 assume !(0 == start_simulation_~tmp~3); 60925#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 60926#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60240#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61616#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 61290#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 59729#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 59730#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 59977#L1959 assume !(0 != start_simulation_~tmp___0~1); 59978#L1927-1 [2021-11-02 23:08:50,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,563 INFO L85 PathProgramCache]: Analyzing trace with hash -124472405, now seen corresponding path program 1 times [2021-11-02 23:08:50,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,563 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397777632] [2021-11-02 23:08:50,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,622 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,622 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397777632] [2021-11-02 23:08:50,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397777632] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,623 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,623 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:50,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936893787] [2021-11-02 23:08:50,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:50,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,624 INFO L85 PathProgramCache]: Analyzing trace with hash 285797548, now seen corresponding path program 1 times [2021-11-02 23:08:50,625 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,625 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894760453] [2021-11-02 23:08:50,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:50,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:50,682 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:50,683 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894760453] [2021-11-02 23:08:50,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894760453] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:50,683 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:50,683 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:50,684 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005993044] [2021-11-02 23:08:50,684 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:50,684 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:50,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:50,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:50,686 INFO L87 Difference]: Start difference. First operand 1986 states and 2914 transitions. cyclomatic complexity: 929 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:50,830 INFO L93 Difference]: Finished difference Result 1986 states and 2893 transitions. [2021-11-02 23:08:50,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:50,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2893 transitions. [2021-11-02 23:08:50,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2893 transitions. [2021-11-02 23:08:50,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-02 23:08:50,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-02 23:08:50,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2893 transitions. [2021-11-02 23:08:50,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:50,863 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-02 23:08:50,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2893 transitions. [2021-11-02 23:08:50,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-02 23:08:50,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4566968781470293) internal successors, (2893), 1985 states have internal predecessors, (2893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:50,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2893 transitions. [2021-11-02 23:08:50,934 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-02 23:08:50,935 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-02 23:08:50,935 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-02 23:08:50,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2893 transitions. [2021-11-02 23:08:50,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-02 23:08:50,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:50,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:50,949 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,950 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:50,950 INFO L791 eck$LassoCheckResult]: Stem: 64578#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 64579#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 65661#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65574#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 64724#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64535#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64536#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64303#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64304#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64726#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64913#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65073#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65094#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64311#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64312#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64040#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64041#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64487#L966-1 assume !(0 == ~M_E~0); 64488#L1278-1 assume !(0 == ~T1_E~0); 65400#L1283-1 assume !(0 == ~T2_E~0); 65401#L1288-1 assume !(0 == ~T3_E~0); 65608#L1293-1 assume !(0 == ~T4_E~0); 65596#L1298-1 assume !(0 == ~T5_E~0); 65539#L1303-1 assume !(0 == ~T6_E~0); 64139#L1308-1 assume !(0 == ~T7_E~0); 64063#L1313-1 assume !(0 == ~T8_E~0); 64064#L1318-1 assume !(0 == ~T9_E~0); 64066#L1323-1 assume !(0 == ~T10_E~0); 64067#L1328-1 assume !(0 == ~T11_E~0); 64250#L1333-1 assume !(0 == ~T12_E~0); 65211#L1338-1 assume !(0 == ~T13_E~0); 65212#L1343-1 assume !(0 == ~E_M~0); 65353#L1348-1 assume !(0 == ~E_1~0); 65636#L1353-1 assume !(0 == ~E_2~0); 64956#L1358-1 assume !(0 == ~E_3~0); 64957#L1363-1 assume !(0 == ~E_4~0); 65248#L1368-1 assume !(0 == ~E_5~0); 63894#L1373-1 assume !(0 == ~E_6~0); 63895#L1378-1 assume !(0 == ~E_7~0); 64207#L1383-1 assume !(0 == ~E_8~0); 64208#L1388-1 assume !(0 == ~E_9~0); 65284#L1393-1 assume !(0 == ~E_10~0); 65285#L1398-1 assume !(0 == ~E_11~0); 65291#L1403-1 assume !(0 == ~E_12~0); 65537#L1408-1 assume !(0 == ~E_13~0); 64178#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64179#L627 assume 1 == ~m_pc~0; 65649#L628 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 64539#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64540#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 65118#L1590 assume !(0 != activate_threads_~tmp~1); 65568#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64108#L646 assume !(1 == ~t1_pc~0); 64109#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 64767#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64775#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 64825#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 63982#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 63983#L665 assume 1 == ~t2_pc~0; 65630#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 64647#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64195#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 64196#L1606 assume !(0 != activate_threads_~tmp___1~0); 64749#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65038#L684 assume !(1 == ~t3_pc~0); 65004#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 65005#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65075#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 65615#L1614 assume !(0 != activate_threads_~tmp___2~0); 65655#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65639#L703 assume 1 == ~t4_pc~0; 64474#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64335#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64946#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 64429#L1622 assume !(0 != activate_threads_~tmp___3~0); 64430#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65470#L722 assume !(1 == ~t5_pc~0); 64386#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 64387#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64734#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 63718#L1630 assume !(0 != activate_threads_~tmp___4~0); 63719#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 63930#L741 assume 1 == ~t6_pc~0; 63931#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 64233#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 64385#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 64046#L1638 assume !(0 != activate_threads_~tmp___5~0); 64047#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 64359#L760 assume 1 == ~t7_pc~0; 64330#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 64331#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 64190#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 64191#L1646 assume !(0 != activate_threads_~tmp___6~0); 64566#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 64567#L779 assume !(1 == ~t8_pc~0); 63974#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 63824#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 63825#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 64225#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 64994#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 64995#L798 assume 1 == ~t9_pc~0; 65497#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 65435#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 63975#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 63976#L1662 assume !(0 != activate_threads_~tmp___8~0); 63759#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 63760#L817 assume !(1 == ~t10_pc~0); 63806#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 64585#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 64586#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 64048#L1670 assume !(0 != activate_threads_~tmp___9~0); 64049#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 64947#L836 assume 1 == ~t11_pc~0; 64948#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 64147#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 64148#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 64111#L1678 assume !(0 != activate_threads_~tmp___10~0); 64112#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 65445#L855 assume !(1 == ~t12_pc~0); 64772#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 64773#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 65325#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 65350#L1686 assume !(0 != activate_threads_~tmp___11~0); 65290#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 64097#L874 assume !(1 == ~t13_pc~0); 64099#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 64259#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 64260#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 64388#L1694 assume !(0 != activate_threads_~tmp___12~0); 65418#L1694-2 assume !(1 == ~M_E~0); 64301#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64302#L1431-1 assume !(1 == ~T2_E~0); 63826#L1436-1 assume !(1 == ~T3_E~0); 63827#L1441-1 assume !(1 == ~T4_E~0); 64615#L1446-1 assume !(1 == ~T5_E~0); 64616#L1451-1 assume !(1 == ~T6_E~0); 65351#L1456-1 assume !(1 == ~T7_E~0); 64988#L1461-1 assume !(1 == ~T8_E~0); 64531#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64532#L1471-1 assume !(1 == ~T10_E~0); 65326#L1476-1 assume !(1 == ~T11_E~0); 65327#L1481-1 assume !(1 == ~T12_E~0); 65493#L1486-1 assume !(1 == ~T13_E~0); 64151#L1491-1 assume !(1 == ~E_M~0); 63768#L1496-1 assume !(1 == ~E_1~0); 63769#L1501-1 assume !(1 == ~E_2~0); 64611#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 64612#L1511-1 assume !(1 == ~E_4~0); 64565#L1516-1 assume !(1 == ~E_5~0); 63722#L1521-1 assume !(1 == ~E_6~0); 63723#L1526-1 assume !(1 == ~E_7~0); 63767#L1531-1 assume !(1 == ~E_8~0); 64322#L1536-1 assume !(1 == ~E_9~0); 64042#L1541-1 assume !(1 == ~E_10~0); 64043#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 65548#L1551-1 assume !(1 == ~E_12~0); 64212#L1556-1 assume !(1 == ~E_13~0); 63957#L1927-1 [2021-11-02 23:08:50,951 INFO L793 eck$LassoCheckResult]: Loop: 63957#L1927-1 assume !false; 64236#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 64247#L1253 assume !false; 63710#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 63711#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64394#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 64317#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 64318#L1066 assume !(0 != eval_~tmp~0); 65552#L1268 start_simulation_~kernel_st~0 := 2; 64061#L894-1 start_simulation_~kernel_st~0 := 3; 64062#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 64625#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64626#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64227#L1288-3 assume !(0 == ~T3_E~0); 64228#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65412#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65413#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65556#L1308-3 assume !(0 == ~T7_E~0); 65407#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64868#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64015#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64016#L1328-3 assume !(0 == ~T11_E~0); 65487#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64161#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64162#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65298#L1348-3 assume !(0 == ~E_1~0); 65491#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65492#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64831#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 64346#L1368-3 assume !(0 == ~E_5~0); 64347#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65147#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65148#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65344#L1388-3 assume !(0 == ~E_9~0); 65331#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65332#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64676#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64677#L1408-3 assume !(0 == ~E_13~0); 65499#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64524#L627-45 assume !(1 == ~m_pc~0); 64525#L627-47 is_master_triggered_~__retres1~0 := 0; 65021#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65489#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 64852#L1590-45 assume !(0 != activate_threads_~tmp~1); 64853#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65449#L646-45 assume 1 == ~t1_pc~0; 65520#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 64714#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64899#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 64900#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 64132#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64133#L665-45 assume 1 == ~t2_pc~0; 63808#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 63809#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64631#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 63835#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 63836#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65053#L684-45 assume !(1 == ~t3_pc~0); 64129#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 64130#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65205#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 65558#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65352#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65158#L703-45 assume 1 == ~t4_pc~0; 64997#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64999#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64592#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 64286#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 64287#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64622#L722-45 assume !(1 == ~t5_pc~0); 64614#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 65525#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65566#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 65616#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 64979#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64980#L741-45 assume 1 == ~t6_pc~0; 64376#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 64377#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 64733#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 65074#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 65105#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 65193#L760-45 assume 1 == ~t7_pc~0; 65081#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 65082#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 64652#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 64653#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 65213#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 65214#L779-45 assume !(1 == ~t8_pc~0); 64090#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 64091#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 64115#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 64116#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 65194#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 65195#L798-45 assume !(1 == ~t9_pc~0); 64729#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 64730#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 65119#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 64842#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 64843#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 64744#L817-45 assume 1 == ~t10_pc~0; 64745#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 65329#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 65117#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 64484#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 64381#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 64382#L836-45 assume !(1 == ~t11_pc~0); 63889#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 63890#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 64654#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 64655#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 65143#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 65216#L855-45 assume 1 == ~t12_pc~0; 64604#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 64052#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 64053#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 64976#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 64977#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 64698#L874-45 assume !(1 == ~t13_pc~0); 64699#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 64609#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 64610#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 64203#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 64204#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 64982#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64152#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64153#L1436-3 assume !(1 == ~T3_E~0); 63726#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63727#L1446-3 assume !(1 == ~T5_E~0); 65381#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64690#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64306#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64307#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65620#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64257#L1476-3 assume !(1 == ~T11_E~0); 64258#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64664#L1486-3 assume !(1 == ~T13_E~0); 64275#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64276#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64719#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64720#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65146#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65137#L1516-3 assume !(1 == ~E_5~0); 65138#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64840#L1526-3 assume !(1 == ~E_7~0); 64841#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65210#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64293#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64294#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64333#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65578#L1556-3 assume !(1 == ~E_13~0); 63873#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 63874#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 63980#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65334#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 65178#L1946 assume !(0 == start_simulation_~tmp~3); 64903#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 64904#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64218#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65594#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 65268#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 63708#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 63709#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 63956#L1959 assume !(0 != start_simulation_~tmp___0~1); 63957#L1927-1 [2021-11-02 23:08:50,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:50,953 INFO L85 PathProgramCache]: Analyzing trace with hash 26114798, now seen corresponding path program 1 times [2021-11-02 23:08:50,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:50,953 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203193563] [2021-11-02 23:08:50,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:50,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:50,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:51,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:51,004 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:51,005 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203193563] [2021-11-02 23:08:51,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203193563] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:51,005 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:51,005 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:51,006 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153999074] [2021-11-02 23:08:51,006 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:51,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:51,007 INFO L85 PathProgramCache]: Analyzing trace with hash -315413751, now seen corresponding path program 1 times [2021-11-02 23:08:51,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:51,008 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505390272] [2021-11-02 23:08:51,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:51,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:51,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:51,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:51,068 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:51,068 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505390272] [2021-11-02 23:08:51,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505390272] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:51,068 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:51,069 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:51,069 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967573968] [2021-11-02 23:08:51,070 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:51,070 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:51,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:51,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:51,071 INFO L87 Difference]: Start difference. First operand 1986 states and 2893 transitions. cyclomatic complexity: 908 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:51,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:51,244 INFO L93 Difference]: Finished difference Result 3779 states and 5465 transitions. [2021-11-02 23:08:51,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:51,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3779 states and 5465 transitions. [2021-11-02 23:08:51,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3608 [2021-11-02 23:08:51,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3779 states to 3779 states and 5465 transitions. [2021-11-02 23:08:51,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3779 [2021-11-02 23:08:51,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3779 [2021-11-02 23:08:51,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3779 states and 5465 transitions. [2021-11-02 23:08:51,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:51,301 INFO L681 BuchiCegarLoop]: Abstraction has 3779 states and 5465 transitions. [2021-11-02 23:08:51,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3779 states and 5465 transitions. [2021-11-02 23:08:51,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3779 to 3683. [2021-11-02 23:08:51,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3683 states, 3683 states have (on average 1.4474613087157209) internal successors, (5331), 3682 states have internal predecessors, (5331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:51,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3683 states to 3683 states and 5331 transitions. [2021-11-02 23:08:51,393 INFO L704 BuchiCegarLoop]: Abstraction has 3683 states and 5331 transitions. [2021-11-02 23:08:51,394 INFO L587 BuchiCegarLoop]: Abstraction has 3683 states and 5331 transitions. [2021-11-02 23:08:51,394 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-02 23:08:51,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3683 states and 5331 transitions. [2021-11-02 23:08:51,411 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3512 [2021-11-02 23:08:51,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:51,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:51,417 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:51,417 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:51,418 INFO L791 eck$LassoCheckResult]: Stem: 70355#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 70356#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 71481#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 71381#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 70507#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70311#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70312#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70078#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70079#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70509#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70700#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 70861#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70885#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70086#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 70087#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69813#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69814#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 70262#L966-1 assume !(0 == ~M_E~0); 70263#L1278-1 assume !(0 == ~T1_E~0); 71200#L1283-1 assume !(0 == ~T2_E~0); 71201#L1288-1 assume !(0 == ~T3_E~0); 71420#L1293-1 assume !(0 == ~T4_E~0); 71404#L1298-1 assume !(0 == ~T5_E~0); 71343#L1303-1 assume !(0 == ~T6_E~0); 69911#L1308-1 assume !(0 == ~T7_E~0); 69836#L1313-1 assume !(0 == ~T8_E~0); 69837#L1318-1 assume !(0 == ~T9_E~0); 69839#L1323-1 assume !(0 == ~T10_E~0); 69840#L1328-1 assume !(0 == ~T11_E~0); 70024#L1333-1 assume !(0 == ~T12_E~0); 71007#L1338-1 assume !(0 == ~T13_E~0); 71008#L1343-1 assume !(0 == ~E_M~0); 71153#L1348-1 assume !(0 == ~E_1~0); 71451#L1353-1 assume !(0 == ~E_2~0); 70741#L1358-1 assume !(0 == ~E_3~0); 70742#L1363-1 assume !(0 == ~E_4~0); 71043#L1368-1 assume !(0 == ~E_5~0); 69666#L1373-1 assume !(0 == ~E_6~0); 69667#L1378-1 assume !(0 == ~E_7~0); 69979#L1383-1 assume !(0 == ~E_8~0); 69980#L1388-1 assume !(0 == ~E_9~0); 71080#L1393-1 assume !(0 == ~E_10~0); 71081#L1398-1 assume !(0 == ~E_11~0); 71087#L1403-1 assume !(0 == ~E_12~0); 71341#L1408-1 assume !(0 == ~E_13~0); 69950#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69951#L627 assume !(1 == ~m_pc~0); 71049#L627-2 is_master_triggered_~__retres1~0 := 0; 70315#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70316#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 70909#L1590 assume !(0 != activate_threads_~tmp~1); 71375#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69881#L646 assume !(1 == ~t1_pc~0); 69882#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 70551#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70559#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 70609#L1598 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69755#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69756#L665 assume 1 == ~t2_pc~0; 71445#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 70427#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69967#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 69968#L1606 assume !(0 != activate_threads_~tmp___1~0); 70533#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70826#L684 assume !(1 == ~t3_pc~0); 70790#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 70791#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70864#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 71428#L1614 assume !(0 != activate_threads_~tmp___2~0); 71472#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 71456#L703 assume 1 == ~t4_pc~0; 70249#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 70110#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70731#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 70203#L1622 assume !(0 != activate_threads_~tmp___3~0); 70204#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 71271#L722 assume !(1 == ~t5_pc~0); 70160#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 70161#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70518#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 69490#L1630 assume !(0 != activate_threads_~tmp___4~0); 69491#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69703#L741 assume 1 == ~t6_pc~0; 69704#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 70007#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70159#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 69819#L1638 assume !(0 != activate_threads_~tmp___5~0); 69820#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 70133#L760 assume 1 == ~t7_pc~0; 70105#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 70106#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 69962#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 69963#L1646 assume !(0 != activate_threads_~tmp___6~0); 70343#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 70344#L779 assume !(1 == ~t8_pc~0); 69747#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 69596#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 69597#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 69999#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 70780#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 70781#L798 assume 1 == ~t9_pc~0; 71298#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 71236#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 69748#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 69749#L1662 assume !(0 != activate_threads_~tmp___8~0); 69531#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 69532#L817 assume !(1 == ~t10_pc~0); 69578#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 70362#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70363#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 69821#L1670 assume !(0 != activate_threads_~tmp___9~0); 69822#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 70732#L836 assume 1 == ~t11_pc~0; 70733#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 69919#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 69920#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 69884#L1678 assume !(0 != activate_threads_~tmp___10~0); 69885#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 71246#L855 assume !(1 == ~t12_pc~0); 70556#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 70557#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 71121#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 71147#L1686 assume !(0 != activate_threads_~tmp___11~0); 71086#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 69870#L874 assume !(1 == ~t13_pc~0); 69872#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 70033#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 70034#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 70162#L1694 assume !(0 != activate_threads_~tmp___12~0); 71219#L1694-2 assume !(1 == ~M_E~0); 70076#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70077#L1431-1 assume !(1 == ~T2_E~0); 69598#L1436-1 assume !(1 == ~T3_E~0); 69599#L1441-1 assume !(1 == ~T4_E~0); 70392#L1446-1 assume !(1 == ~T5_E~0); 70393#L1451-1 assume !(1 == ~T6_E~0); 71151#L1456-1 assume !(1 == ~T7_E~0); 70774#L1461-1 assume !(1 == ~T8_E~0); 70307#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70308#L1471-1 assume !(1 == ~T10_E~0); 71122#L1476-1 assume !(1 == ~T11_E~0); 71123#L1481-1 assume !(1 == ~T12_E~0); 71294#L1486-1 assume !(1 == ~T13_E~0); 69923#L1491-1 assume !(1 == ~E_M~0); 69540#L1496-1 assume !(1 == ~E_1~0); 69541#L1501-1 assume !(1 == ~E_2~0); 70388#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 70389#L1511-1 assume !(1 == ~E_4~0); 70342#L1516-1 assume !(1 == ~E_5~0); 69494#L1521-1 assume !(1 == ~E_6~0); 69495#L1526-1 assume !(1 == ~E_7~0); 69539#L1531-1 assume !(1 == ~E_8~0); 70097#L1536-1 assume !(1 == ~E_9~0); 69815#L1541-1 assume !(1 == ~E_10~0); 69816#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 71352#L1551-1 assume !(1 == ~E_12~0); 69984#L1556-1 assume !(1 == ~E_13~0); 69985#L1927-1 [2021-11-02 23:08:51,419 INFO L793 eck$LassoCheckResult]: Loop: 69985#L1927-1 assume !false; 71624#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 70021#L1253 assume !false; 71606#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 71549#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 71534#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 71525#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 71519#L1066 assume !(0 != eval_~tmp~0); 71356#L1268 start_simulation_~kernel_st~0 := 2; 69834#L894-1 start_simulation_~kernel_st~0 := 3; 69835#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70403#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70404#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70001#L1288-3 assume !(0 == ~T3_E~0); 70002#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71475#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71460#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 71362#L1308-3 assume !(0 == ~T7_E~0); 71207#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70655#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69788#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69789#L1328-3 assume !(0 == ~T11_E~0); 71288#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69933#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69934#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71094#L1348-3 assume !(0 == ~E_1~0); 71292#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71293#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70615#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70120#L1368-3 assume !(0 == ~E_5~0); 70121#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70938#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70939#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71140#L1388-3 assume !(0 == ~E_9~0); 71127#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 71128#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70456#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 70457#L1408-3 assume !(0 == ~E_13~0); 71300#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70298#L627-45 assume !(1 == ~m_pc~0); 70299#L627-47 is_master_triggered_~__retres1~0 := 0; 70807#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71290#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 70636#L1590-45 assume !(0 != activate_threads_~tmp~1); 70637#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71250#L646-45 assume !(1 == ~t1_pc~0); 70496#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 70497#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70686#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 70687#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69904#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69905#L665-45 assume 1 == ~t2_pc~0; 69580#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 69581#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70411#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 69607#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69608#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70841#L684-45 assume 1 == ~t3_pc~0; 70842#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 69902#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 71000#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 73079#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 73077#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 73075#L703-45 assume 1 == ~t4_pc~0; 73073#L704-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 73071#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 73070#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 73069#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 70399#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70400#L722-45 assume !(1 == ~t5_pc~0); 70391#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 71328#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 71373#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 71430#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 70765#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 70766#L741-45 assume 1 == ~t6_pc~0; 70150#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 70151#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70517#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 70862#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 70896#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 70988#L760-45 assume 1 == ~t7_pc~0; 70870#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 70871#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 70432#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 70433#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 71009#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 71010#L779-45 assume !(1 == ~t8_pc~0); 69863#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 69864#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 69888#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 69889#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 70989#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 70990#L798-45 assume !(1 == ~t9_pc~0); 70512#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 70513#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 70910#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 70626#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 70627#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 70528#L817-45 assume 1 == ~t10_pc~0; 70529#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 71125#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70908#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 70259#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 70155#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 70156#L836-45 assume 1 == ~t11_pc~0; 70792#L837-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 69662#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 70434#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 70435#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 70934#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 71012#L855-45 assume 1 == ~t12_pc~0; 70381#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 69825#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 69826#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 70762#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 70763#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 70481#L874-45 assume !(1 == ~t13_pc~0); 70482#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 70386#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 70387#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 69975#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 69976#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 70768#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69924#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69925#L1436-3 assume !(1 == ~T3_E~0); 69498#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69499#L1446-3 assume !(1 == ~T5_E~0); 71181#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70473#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70081#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70082#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 71435#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70031#L1476-3 assume !(1 == ~T11_E~0); 70032#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70444#L1486-3 assume !(1 == ~T13_E~0); 70050#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70051#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70502#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70503#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70937#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70928#L1516-3 assume !(1 == ~E_5~0); 70929#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70624#L1526-3 assume !(1 == ~E_7~0); 70625#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 71005#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70068#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70069#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 70108#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 71385#L1556-3 assume !(1 == ~E_13~0); 69645#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 69646#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69753#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 71130#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 70972#L1946 assume !(0 == start_simulation_~tmp~3); 70973#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 71681#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 71667#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 71661#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 71655#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 71649#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 71641#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 71635#L1959 assume !(0 != start_simulation_~tmp___0~1); 69985#L1927-1 [2021-11-02 23:08:51,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:51,420 INFO L85 PathProgramCache]: Analyzing trace with hash 751194223, now seen corresponding path program 1 times [2021-11-02 23:08:51,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:51,420 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881794947] [2021-11-02 23:08:51,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:51,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:51,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:51,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:51,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:51,488 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881794947] [2021-11-02 23:08:51,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881794947] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:51,489 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:51,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:08:51,489 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829506382] [2021-11-02 23:08:51,490 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:51,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:51,491 INFO L85 PathProgramCache]: Analyzing trace with hash -372343638, now seen corresponding path program 1 times [2021-11-02 23:08:51,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:51,491 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256511517] [2021-11-02 23:08:51,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:51,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:51,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:51,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:51,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:51,552 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256511517] [2021-11-02 23:08:51,552 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256511517] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:51,552 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:51,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:51,553 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488432380] [2021-11-02 23:08:51,554 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:51,554 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:51,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:08:51,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:08:51,556 INFO L87 Difference]: Start difference. First operand 3683 states and 5331 transitions. cyclomatic complexity: 1650 Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:52,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:52,156 INFO L93 Difference]: Finished difference Result 10454 states and 15089 transitions. [2021-11-02 23:08:52,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 23:08:52,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10454 states and 15089 transitions. [2021-11-02 23:08:52,215 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10054 [2021-11-02 23:08:52,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10454 states to 10454 states and 15089 transitions. [2021-11-02 23:08:52,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10454 [2021-11-02 23:08:52,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10454 [2021-11-02 23:08:52,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10454 states and 15089 transitions. [2021-11-02 23:08:52,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:52,292 INFO L681 BuchiCegarLoop]: Abstraction has 10454 states and 15089 transitions. [2021-11-02 23:08:52,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10454 states and 15089 transitions. [2021-11-02 23:08:52,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10454 to 3779. [2021-11-02 23:08:52,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3779 states, 3779 states have (on average 1.436094204816089) internal successors, (5427), 3778 states have internal predecessors, (5427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:52,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3779 states to 3779 states and 5427 transitions. [2021-11-02 23:08:52,519 INFO L704 BuchiCegarLoop]: Abstraction has 3779 states and 5427 transitions. [2021-11-02 23:08:52,519 INFO L587 BuchiCegarLoop]: Abstraction has 3779 states and 5427 transitions. [2021-11-02 23:08:52,519 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-02 23:08:52,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3779 states and 5427 transitions. [2021-11-02 23:08:52,532 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3605 [2021-11-02 23:08:52,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:52,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:52,536 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:52,536 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:52,536 INFO L791 eck$LassoCheckResult]: Stem: 84502#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 84503#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85715#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 85596#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 84655#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84459#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84460#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84227#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84228#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84663#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84856#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85035#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85057#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 84237#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 84238#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 83963#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 83964#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 84410#L966-1 assume !(0 == ~M_E~0); 84411#L1278-1 assume !(0 == ~T1_E~0); 85386#L1283-1 assume !(0 == ~T2_E~0); 85387#L1288-1 assume !(0 == ~T3_E~0); 85639#L1293-1 assume !(0 == ~T4_E~0); 85621#L1298-1 assume !(0 == ~T5_E~0); 85547#L1303-1 assume !(0 == ~T6_E~0); 84062#L1308-1 assume !(0 == ~T7_E~0); 83986#L1313-1 assume !(0 == ~T8_E~0); 83987#L1318-1 assume !(0 == ~T9_E~0); 83989#L1323-1 assume !(0 == ~T10_E~0); 83990#L1328-1 assume !(0 == ~T11_E~0); 84174#L1333-1 assume !(0 == ~T12_E~0); 85182#L1338-1 assume !(0 == ~T13_E~0); 85183#L1343-1 assume !(0 == ~E_M~0); 85338#L1348-1 assume !(0 == ~E_1~0); 85678#L1353-1 assume !(0 == ~E_2~0); 84900#L1358-1 assume !(0 == ~E_3~0); 84901#L1363-1 assume !(0 == ~E_4~0); 85220#L1368-1 assume !(0 == ~E_5~0); 83816#L1373-1 assume !(0 == ~E_6~0); 83817#L1378-1 assume !(0 == ~E_7~0); 84130#L1383-1 assume !(0 == ~E_8~0); 84131#L1388-1 assume !(0 == ~E_9~0); 85259#L1393-1 assume !(0 == ~E_10~0); 85260#L1398-1 assume !(0 == ~E_11~0); 85268#L1403-1 assume !(0 == ~E_12~0); 85545#L1408-1 assume !(0 == ~E_13~0); 84101#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84102#L627 assume !(1 == ~m_pc~0); 85225#L627-2 is_master_triggered_~__retres1~0 := 0; 84465#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84466#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 85082#L1590 assume !(0 != activate_threads_~tmp~1); 85588#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84036#L646 assume !(1 == ~t1_pc~0); 84037#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 84711#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84712#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 85458#L1598 assume !(0 != activate_threads_~tmp___0~0); 83905#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83906#L665 assume 1 == ~t2_pc~0; 85670#L666 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 84573#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84118#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 84119#L1606 assume !(0 != activate_threads_~tmp___1~0); 84680#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84990#L684 assume !(1 == ~t3_pc~0); 84953#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 84954#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85036#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 85652#L1614 assume !(0 != activate_threads_~tmp___2~0); 85705#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85686#L703 assume 1 == ~t4_pc~0; 84397#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 84259#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84889#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 84352#L1622 assume !(0 != activate_threads_~tmp___3~0); 84353#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 85463#L722 assume !(1 == ~t5_pc~0); 84309#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 84310#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 84665#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 83640#L1630 assume !(0 != activate_threads_~tmp___4~0); 83641#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83853#L741 assume 1 == ~t6_pc~0; 83854#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 84156#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 84308#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 83969#L1638 assume !(0 != activate_threads_~tmp___5~0); 83970#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 84282#L760 assume 1 == ~t7_pc~0; 84254#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 84255#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 84113#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 84114#L1646 assume !(0 != activate_threads_~tmp___6~0); 84490#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 84491#L779 assume !(1 == ~t8_pc~0); 83897#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 83746#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 83747#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 84148#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 84943#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 84944#L798 assume 1 == ~t9_pc~0; 85495#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 85421#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 83898#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 83899#L1662 assume !(0 != activate_threads_~tmp___8~0); 83681#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 83682#L817 assume !(1 == ~t10_pc~0); 83728#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 84509#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 84510#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 83971#L1670 assume !(0 != activate_threads_~tmp___9~0); 83972#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 84890#L836 assume 1 == ~t11_pc~0; 84891#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 84070#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 84071#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 84039#L1678 assume !(0 != activate_threads_~tmp___10~0); 84040#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 85433#L855 assume !(1 == ~t12_pc~0); 84707#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 84708#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 85304#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 85332#L1686 assume !(0 != activate_threads_~tmp___11~0); 85267#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 84021#L874 assume !(1 == ~t13_pc~0); 84023#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 84183#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 84184#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 84311#L1694 assume !(0 != activate_threads_~tmp___12~0); 85404#L1694-2 assume !(1 == ~M_E~0); 84225#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84226#L1431-1 assume !(1 == ~T2_E~0); 83750#L1436-1 assume !(1 == ~T3_E~0); 83751#L1441-1 assume !(1 == ~T4_E~0); 84540#L1446-1 assume !(1 == ~T5_E~0); 84541#L1451-1 assume !(1 == ~T6_E~0); 85336#L1456-1 assume !(1 == ~T7_E~0); 84936#L1461-1 assume !(1 == ~T8_E~0); 84455#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84456#L1471-1 assume !(1 == ~T10_E~0); 85305#L1476-1 assume !(1 == ~T11_E~0); 85306#L1481-1 assume !(1 == ~T12_E~0); 85491#L1486-1 assume !(1 == ~T13_E~0); 84074#L1491-1 assume !(1 == ~E_M~0); 83690#L1496-1 assume !(1 == ~E_1~0); 83691#L1501-1 assume !(1 == ~E_2~0); 84536#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 84537#L1511-1 assume !(1 == ~E_4~0); 84489#L1516-1 assume !(1 == ~E_5~0); 83644#L1521-1 assume !(1 == ~E_6~0); 83645#L1526-1 assume !(1 == ~E_7~0); 83689#L1531-1 assume !(1 == ~E_8~0); 84246#L1536-1 assume !(1 == ~E_9~0); 83965#L1541-1 assume !(1 == ~E_10~0); 83966#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 85556#L1551-1 assume !(1 == ~E_12~0); 84135#L1556-1 assume !(1 == ~E_13~0); 83880#L1927-1 [2021-11-02 23:08:52,537 INFO L793 eck$LassoCheckResult]: Loop: 83880#L1927-1 assume !false; 84159#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 84173#L1253 assume !false; 83632#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 83633#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 84317#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 84241#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 84242#L1066 assume !(0 != eval_~tmp~0); 85561#L1268 start_simulation_~kernel_st~0 := 2; 83984#L894-1 start_simulation_~kernel_st~0 := 3; 83985#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 84551#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 84552#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 84150#L1288-3 assume !(0 == ~T3_E~0); 84151#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85398#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85399#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85569#L1308-3 assume !(0 == ~T7_E~0); 85395#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 84811#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 83938#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83939#L1328-3 assume !(0 == ~T11_E~0); 85482#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85684#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 87264#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87239#L1348-3 assume !(0 == ~E_1~0); 87238#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87237#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84772#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 84773#L1368-3 assume !(0 == ~E_5~0); 85727#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85728#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87152#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85324#L1388-3 assume !(0 == ~E_9~0); 85325#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85570#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 84603#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 84604#L1408-3 assume !(0 == ~E_13~0); 85579#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84446#L627-45 assume !(1 == ~m_pc~0); 84447#L627-47 is_master_triggered_~__retres1~0 := 0; 84974#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 85484#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 84794#L1590-45 assume !(0 != activate_threads_~tmp~1); 84795#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 85436#L646-45 assume !(1 == ~t1_pc~0); 84645#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 84646#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87213#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 85266#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 84055#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 84056#L665-45 assume 1 == ~t2_pc~0; 83730#L666-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 83731#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84557#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 83757#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 83758#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 85011#L684-45 assume !(1 == ~t3_pc~0); 84053#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 84054#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85175#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 85572#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 85337#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85125#L703-45 assume !(1 == ~t4_pc~0); 84947#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 84948#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84516#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 84210#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 84211#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 84548#L722-45 assume !(1 == ~t5_pc~0); 84539#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 85530#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 85586#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 85653#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 84924#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 84925#L741-45 assume 1 == ~t6_pc~0; 84299#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 84300#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 84664#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 87067#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 87066#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 87065#L760-45 assume 1 == ~t7_pc~0; 87063#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 87062#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 87061#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 87060#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 87059#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 87058#L779-45 assume 1 == ~t8_pc~0; 87057#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 87055#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 87054#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 87053#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 87052#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 87051#L798-45 assume 1 == ~t9_pc~0; 87049#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 87048#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 87047#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 87046#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 87045#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 87044#L817-45 assume !(1 == ~t10_pc~0); 87043#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 87041#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 87040#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 87039#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 87038#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 85235#L836-45 assume !(1 == ~t11_pc~0); 83808#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 83809#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 84580#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 84581#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 85110#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 85186#L855-45 assume !(1 == ~t12_pc~0); 84527#L855-47 is_transmit12_triggered_~__retres1~12 := 0; 83975#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 83976#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 84921#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 84922#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 84627#L874-45 assume !(1 == ~t13_pc~0); 84628#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 84534#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 84535#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 84122#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 84123#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 84927#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84075#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84076#L1436-3 assume !(1 == ~T3_E~0); 83648#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83649#L1446-3 assume !(1 == ~T5_E~0); 85364#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84620#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84230#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 84231#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85658#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84181#L1476-3 assume !(1 == ~T11_E~0); 84182#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84591#L1486-3 assume !(1 == ~T13_E~0); 84199#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84200#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84650#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84651#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85113#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85103#L1516-3 assume !(1 == ~E_5~0); 85104#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 84778#L1526-3 assume !(1 == ~E_7~0); 84779#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85180#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 84217#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 84218#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 84257#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85600#L1556-3 assume !(1 == ~E_13~0); 83795#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 83796#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 83903#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 85313#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 85145#L1946 assume !(0 == start_simulation_~tmp~3); 84846#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 84847#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 84141#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 85619#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 85241#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 83627#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 83628#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 83879#L1959 assume !(0 != start_simulation_~tmp___0~1); 83880#L1927-1 [2021-11-02 23:08:52,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:52,538 INFO L85 PathProgramCache]: Analyzing trace with hash -555948175, now seen corresponding path program 1 times [2021-11-02 23:08:52,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:52,538 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122864455] [2021-11-02 23:08:52,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:52,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:52,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:52,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:52,586 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:52,586 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122864455] [2021-11-02 23:08:52,587 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122864455] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:52,587 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:52,587 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:52,587 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895496288] [2021-11-02 23:08:52,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:52,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:52,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1176363003, now seen corresponding path program 1 times [2021-11-02 23:08:52,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:52,590 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365003471] [2021-11-02 23:08:52,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:52,590 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:52,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:52,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:52,639 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:52,639 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365003471] [2021-11-02 23:08:52,640 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365003471] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:52,640 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:52,640 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:52,640 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115463639] [2021-11-02 23:08:52,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:52,642 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:52,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:08:52,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:08:52,643 INFO L87 Difference]: Start difference. First operand 3779 states and 5427 transitions. cyclomatic complexity: 1650 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:53,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:53,171 INFO L93 Difference]: Finished difference Result 9042 states and 12886 transitions. [2021-11-02 23:08:53,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:08:53,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9042 states and 12886 transitions. [2021-11-02 23:08:53,222 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8762 [2021-11-02 23:08:53,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9042 states to 9042 states and 12886 transitions. [2021-11-02 23:08:53,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9042 [2021-11-02 23:08:53,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9042 [2021-11-02 23:08:53,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9042 states and 12886 transitions. [2021-11-02 23:08:53,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:53,286 INFO L681 BuchiCegarLoop]: Abstraction has 9042 states and 12886 transitions. [2021-11-02 23:08:53,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9042 states and 12886 transitions. [2021-11-02 23:08:53,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9042 to 7148. [2021-11-02 23:08:53,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7148 states, 7148 states have (on average 1.4292109681029659) internal successors, (10216), 7147 states have internal predecessors, (10216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:53,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7148 states to 7148 states and 10216 transitions. [2021-11-02 23:08:53,435 INFO L704 BuchiCegarLoop]: Abstraction has 7148 states and 10216 transitions. [2021-11-02 23:08:53,435 INFO L587 BuchiCegarLoop]: Abstraction has 7148 states and 10216 transitions. [2021-11-02 23:08:53,435 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-02 23:08:53,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7148 states and 10216 transitions. [2021-11-02 23:08:53,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6974 [2021-11-02 23:08:53,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:53,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:53,468 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:53,469 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:53,469 INFO L791 eck$LassoCheckResult]: Stem: 97328#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 97329#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 98543#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98416#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 97484#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97285#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97286#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97055#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97056#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97486#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97684#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97852#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97873#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97063#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97064#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96791#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96792#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97238#L966-1 assume !(0 == ~M_E~0); 97239#L1278-1 assume !(0 == ~T1_E~0); 98212#L1283-1 assume !(0 == ~T2_E~0); 98213#L1288-1 assume !(0 == ~T3_E~0); 98466#L1293-1 assume !(0 == ~T4_E~0); 98451#L1298-1 assume !(0 == ~T5_E~0); 98365#L1303-1 assume !(0 == ~T6_E~0); 96890#L1308-1 assume !(0 == ~T7_E~0); 96814#L1313-1 assume !(0 == ~T8_E~0); 96815#L1318-1 assume !(0 == ~T9_E~0); 96817#L1323-1 assume !(0 == ~T10_E~0); 96818#L1328-1 assume !(0 == ~T11_E~0); 97002#L1333-1 assume !(0 == ~T12_E~0); 97999#L1338-1 assume !(0 == ~T13_E~0); 98000#L1343-1 assume !(0 == ~E_M~0); 98160#L1348-1 assume !(0 == ~E_1~0); 98506#L1353-1 assume !(0 == ~E_2~0); 97727#L1358-1 assume !(0 == ~E_3~0); 97728#L1363-1 assume !(0 == ~E_4~0); 98037#L1368-1 assume !(0 == ~E_5~0); 96646#L1373-1 assume !(0 == ~E_6~0); 96647#L1378-1 assume !(0 == ~E_7~0); 96957#L1383-1 assume !(0 == ~E_8~0); 96958#L1388-1 assume !(0 == ~E_9~0); 98078#L1393-1 assume !(0 == ~E_10~0); 98079#L1398-1 assume !(0 == ~E_11~0); 98088#L1403-1 assume !(0 == ~E_12~0); 98363#L1408-1 assume !(0 == ~E_13~0); 96928#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96929#L627 assume !(1 == ~m_pc~0); 98043#L627-2 is_master_triggered_~__retres1~0 := 0; 97289#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97290#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 97898#L1590 assume !(0 != activate_threads_~tmp~1); 98404#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96860#L646 assume !(1 == ~t1_pc~0); 96861#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 97537#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 97538#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 97590#L1598 assume !(0 != activate_threads_~tmp___0~0); 96733#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96734#L665 assume !(1 == ~t2_pc~0); 97403#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 97404#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96945#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 96946#L1606 assume !(0 != activate_threads_~tmp___1~0); 97510#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97816#L684 assume !(1 == ~t3_pc~0); 97780#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 97781#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97854#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 98482#L1614 assume !(0 != activate_threads_~tmp___2~0); 98535#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98511#L703 assume 1 == ~t4_pc~0; 97225#L704 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 97087#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97717#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 97180#L1622 assume !(0 != activate_threads_~tmp___3~0); 97181#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98282#L722 assume !(1 == ~t5_pc~0); 97137#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 97138#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97495#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 96471#L1630 assume !(0 != activate_threads_~tmp___4~0); 96472#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 96681#L741 assume 1 == ~t6_pc~0; 96682#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 96985#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97136#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 96797#L1638 assume !(0 != activate_threads_~tmp___5~0); 96798#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97110#L760 assume 1 == ~t7_pc~0; 97082#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 97083#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 96940#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 96941#L1646 assume !(0 != activate_threads_~tmp___6~0); 97316#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 97317#L779 assume !(1 == ~t8_pc~0); 96725#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 96577#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 96578#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 96977#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 97769#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 97770#L798 assume 1 == ~t9_pc~0; 98314#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 98247#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 96726#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 96727#L1662 assume !(0 != activate_threads_~tmp___8~0); 96512#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 96513#L817 assume !(1 == ~t10_pc~0); 96559#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 97335#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 97336#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 96799#L1670 assume !(0 != activate_threads_~tmp___9~0); 96800#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 97718#L836 assume 1 == ~t11_pc~0; 97719#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 96898#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 96899#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 96863#L1678 assume !(0 != activate_threads_~tmp___10~0); 96864#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 98257#L855 assume !(1 == ~t12_pc~0); 97534#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 97535#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 98125#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 98154#L1686 assume !(0 != activate_threads_~tmp___11~0); 98087#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 96849#L874 assume !(1 == ~t13_pc~0); 96851#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 97011#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 97012#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 97139#L1694 assume !(0 != activate_threads_~tmp___12~0); 98230#L1694-2 assume !(1 == ~M_E~0); 97053#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97054#L1431-1 assume !(1 == ~T2_E~0); 96579#L1436-1 assume !(1 == ~T3_E~0); 96580#L1441-1 assume !(1 == ~T4_E~0); 97366#L1446-1 assume !(1 == ~T5_E~0); 97367#L1451-1 assume !(1 == ~T6_E~0); 98158#L1456-1 assume !(1 == ~T7_E~0); 97763#L1461-1 assume !(1 == ~T8_E~0); 97281#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 97282#L1471-1 assume !(1 == ~T10_E~0); 98126#L1476-1 assume !(1 == ~T11_E~0); 98127#L1481-1 assume !(1 == ~T12_E~0); 98310#L1486-1 assume !(1 == ~T13_E~0); 96902#L1491-1 assume !(1 == ~E_M~0); 96521#L1496-1 assume !(1 == ~E_1~0); 96522#L1501-1 assume !(1 == ~E_2~0); 97362#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 97363#L1511-1 assume !(1 == ~E_4~0); 97315#L1516-1 assume !(1 == ~E_5~0); 96475#L1521-1 assume !(1 == ~E_6~0); 96476#L1526-1 assume !(1 == ~E_7~0); 96520#L1531-1 assume !(1 == ~E_8~0); 97074#L1536-1 assume !(1 == ~E_9~0); 96793#L1541-1 assume !(1 == ~E_10~0); 96794#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 98377#L1551-1 assume !(1 == ~E_12~0); 96963#L1556-1 assume !(1 == ~E_13~0); 96708#L1927-1 [2021-11-02 23:08:53,470 INFO L793 eck$LassoCheckResult]: Loop: 96708#L1927-1 assume !false; 96988#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 96999#L1253 assume !false; 96463#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 96464#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 97145#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 97069#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 97070#L1066 assume !(0 != eval_~tmp~0); 98381#L1268 start_simulation_~kernel_st~0 := 2; 96812#L894-1 start_simulation_~kernel_st~0 := 3; 96813#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 97377#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 97378#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96979#L1288-3 assume !(0 == ~T3_E~0); 96980#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98224#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98225#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 98386#L1308-3 assume !(0 == ~T7_E~0); 98219#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 97638#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 96766#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 96767#L1328-3 assume !(0 == ~T11_E~0); 98303#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96911#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96912#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98095#L1348-3 assume !(0 == ~E_1~0); 98308#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98309#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103100#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103099#L1368-3 assume !(0 == ~E_5~0); 103098#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103097#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103096#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103095#L1388-3 assume !(0 == ~E_9~0); 103094#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 103093#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103092#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 103091#L1408-3 assume !(0 == ~E_13~0); 98394#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97274#L627-45 assume !(1 == ~m_pc~0); 97275#L627-47 is_master_triggered_~__retres1~0 := 0; 97797#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98305#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 103112#L1590-45 assume !(0 != activate_threads_~tmp~1); 103111#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 103110#L646-45 assume 1 == ~t1_pc~0; 103109#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 103107#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 103105#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 103102#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 103101#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98167#L665-45 assume !(1 == ~t2_pc~0); 97737#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 97387#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97388#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 96587#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 96588#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97832#L684-45 assume !(1 == ~t3_pc~0); 96880#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 96881#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97993#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 98390#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 98159#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97942#L703-45 assume !(1 == ~t4_pc~0); 97773#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 97774#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97342#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 97038#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 97039#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97374#L722-45 assume !(1 == ~t5_pc~0); 97365#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 98351#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98402#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 98484#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 97753#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 97754#L741-45 assume 1 == ~t6_pc~0; 97127#L742-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 97128#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97494#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 97853#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 97883#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97978#L760-45 assume 1 == ~t7_pc~0; 97860#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 97861#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 97409#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 97410#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 98001#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 98002#L779-45 assume !(1 == ~t8_pc~0); 96842#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 96843#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 96867#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 96868#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 97979#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 97980#L798-45 assume !(1 == ~t9_pc~0); 97489#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 97490#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 97899#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 97609#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 97610#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 97505#L817-45 assume !(1 == ~t10_pc~0); 97507#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 98129#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 97897#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 97235#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 97132#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 97133#L836-45 assume !(1 == ~t11_pc~0); 96641#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 96642#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 97411#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 97412#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 97924#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 98004#L855-45 assume 1 == ~t12_pc~0; 97355#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 96803#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 96804#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 97750#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 97751#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 97458#L874-45 assume !(1 == ~t13_pc~0); 97459#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 97360#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 97361#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 96953#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 96954#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 97756#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96903#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96904#L1436-3 assume !(1 == ~T3_E~0); 96479#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96480#L1446-3 assume !(1 == ~T5_E~0); 98191#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97450#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 97058#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 97059#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98488#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 97009#L1476-3 assume !(1 == ~T11_E~0); 97010#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97421#L1486-3 assume !(1 == ~T13_E~0); 97027#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97028#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97479#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97480#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97927#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97918#L1516-3 assume !(1 == ~E_5~0); 97919#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97607#L1526-3 assume !(1 == ~E_7~0); 97608#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97998#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97045#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97046#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 97085#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 98420#L1556-3 assume !(1 == ~E_13~0); 96625#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 96626#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 96731#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 98134#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 97964#L1946 assume !(0 == start_simulation_~tmp~3); 97674#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 97675#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 96969#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 98449#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 98060#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 96461#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 96462#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 96707#L1959 assume !(0 != start_simulation_~tmp___0~1); 96708#L1927-1 [2021-11-02 23:08:53,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:53,471 INFO L85 PathProgramCache]: Analyzing trace with hash 1628452466, now seen corresponding path program 1 times [2021-11-02 23:08:53,472 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:53,472 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677575087] [2021-11-02 23:08:53,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:53,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:53,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:53,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:53,548 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:53,548 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677575087] [2021-11-02 23:08:53,548 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677575087] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:53,548 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:53,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:08:53,549 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501062623] [2021-11-02 23:08:53,549 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:53,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:53,550 INFO L85 PathProgramCache]: Analyzing trace with hash 389073766, now seen corresponding path program 1 times [2021-11-02 23:08:53,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:53,551 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668011704] [2021-11-02 23:08:53,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:53,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:53,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:53,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:53,601 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:53,601 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668011704] [2021-11-02 23:08:53,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668011704] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:53,602 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:53,602 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:53,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726559922] [2021-11-02 23:08:53,603 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:53,603 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:53,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:08:53,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:08:53,604 INFO L87 Difference]: Start difference. First operand 7148 states and 10216 transitions. cyclomatic complexity: 3070 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:53,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:53,802 INFO L93 Difference]: Finished difference Result 13663 states and 19439 transitions. [2021-11-02 23:08:53,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:08:53,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13663 states and 19439 transitions. [2021-11-02 23:08:53,961 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13480 [2021-11-02 23:08:54,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13663 states to 13663 states and 19439 transitions. [2021-11-02 23:08:54,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13663 [2021-11-02 23:08:54,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13663 [2021-11-02 23:08:54,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13663 states and 19439 transitions. [2021-11-02 23:08:54,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:54,059 INFO L681 BuchiCegarLoop]: Abstraction has 13663 states and 19439 transitions. [2021-11-02 23:08:54,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13663 states and 19439 transitions. [2021-11-02 23:08:54,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13663 to 13655. [2021-11-02 23:08:54,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13655 states, 13655 states have (on average 1.4229952398388868) internal successors, (19431), 13654 states have internal predecessors, (19431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:54,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13655 states to 13655 states and 19431 transitions. [2021-11-02 23:08:54,444 INFO L704 BuchiCegarLoop]: Abstraction has 13655 states and 19431 transitions. [2021-11-02 23:08:54,444 INFO L587 BuchiCegarLoop]: Abstraction has 13655 states and 19431 transitions. [2021-11-02 23:08:54,444 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-02 23:08:54,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13655 states and 19431 transitions. [2021-11-02 23:08:54,507 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13472 [2021-11-02 23:08:54,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:54,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:54,511 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:54,511 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:54,512 INFO L791 eck$LassoCheckResult]: Stem: 118152#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 118153#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 119427#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 119275#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 118307#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118109#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118110#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117874#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117875#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118309#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 118504#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 118678#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 118701#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 117882#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 117883#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 117608#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 117609#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 118059#L966-1 assume !(0 == ~M_E~0); 118060#L1278-1 assume !(0 == ~T1_E~0); 119051#L1283-1 assume !(0 == ~T2_E~0); 119052#L1288-1 assume !(0 == ~T3_E~0); 119331#L1293-1 assume !(0 == ~T4_E~0); 119308#L1298-1 assume !(0 == ~T5_E~0); 119226#L1303-1 assume !(0 == ~T6_E~0); 117707#L1308-1 assume !(0 == ~T7_E~0); 117631#L1313-1 assume !(0 == ~T8_E~0); 117632#L1318-1 assume !(0 == ~T9_E~0); 117634#L1323-1 assume !(0 == ~T10_E~0); 117635#L1328-1 assume !(0 == ~T11_E~0); 117820#L1333-1 assume !(0 == ~T12_E~0); 118835#L1338-1 assume !(0 == ~T13_E~0); 118836#L1343-1 assume !(0 == ~E_M~0); 119000#L1348-1 assume !(0 == ~E_1~0); 119382#L1353-1 assume !(0 == ~E_2~0); 118548#L1358-1 assume !(0 == ~E_3~0); 118549#L1363-1 assume !(0 == ~E_4~0); 118876#L1368-1 assume !(0 == ~E_5~0); 117463#L1373-1 assume !(0 == ~E_6~0); 117464#L1378-1 assume !(0 == ~E_7~0); 117775#L1383-1 assume !(0 == ~E_8~0); 117776#L1388-1 assume !(0 == ~E_9~0); 118916#L1393-1 assume !(0 == ~E_10~0); 118917#L1398-1 assume !(0 == ~E_11~0); 118924#L1403-1 assume !(0 == ~E_12~0); 119224#L1408-1 assume !(0 == ~E_13~0); 117746#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117747#L627 assume !(1 == ~m_pc~0); 118882#L627-2 is_master_triggered_~__retres1~0 := 0; 118113#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118114#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 118727#L1590 assume !(0 != activate_threads_~tmp~1); 119266#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117677#L646 assume !(1 == ~t1_pc~0); 117678#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 118361#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 118362#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 119127#L1598 assume !(0 != activate_threads_~tmp___0~0); 117550#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117551#L665 assume !(1 == ~t2_pc~0); 118223#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 118224#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117763#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 117764#L1606 assume !(0 != activate_threads_~tmp___1~0); 118334#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118640#L684 assume !(1 == ~t3_pc~0); 118603#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 118604#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118680#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 119345#L1614 assume !(0 != activate_threads_~tmp___2~0); 119418#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119387#L703 assume !(1 == ~t4_pc~0); 117905#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 117906#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 118538#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 118001#L1622 assume !(0 != activate_threads_~tmp___3~0); 118002#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 119134#L722 assume !(1 == ~t5_pc~0); 117958#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 117959#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 118319#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 117288#L1630 assume !(0 != activate_threads_~tmp___4~0); 117289#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117498#L741 assume 1 == ~t6_pc~0; 117499#L742 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 117803#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117957#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 117614#L1638 assume !(0 != activate_threads_~tmp___5~0); 117615#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 117929#L760 assume 1 == ~t7_pc~0; 117901#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 117902#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 117758#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 117759#L1646 assume !(0 != activate_threads_~tmp___6~0); 118140#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 118141#L779 assume !(1 == ~t8_pc~0); 117542#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 117394#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 117395#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 117795#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 118591#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 118592#L798 assume 1 == ~t9_pc~0; 119174#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 119091#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 117543#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 117544#L1662 assume !(0 != activate_threads_~tmp___8~0); 117329#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 117330#L817 assume !(1 == ~t10_pc~0); 117376#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 118159#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 118160#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 117616#L1670 assume !(0 != activate_threads_~tmp___9~0); 117617#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 118539#L836 assume 1 == ~t11_pc~0; 118540#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 117716#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 117717#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 117680#L1678 assume !(0 != activate_threads_~tmp___10~0); 117681#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 119102#L855 assume !(1 == ~t12_pc~0); 118358#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 118359#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 118964#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 118997#L1686 assume !(0 != activate_threads_~tmp___11~0); 118923#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 117666#L874 assume !(1 == ~t13_pc~0); 117668#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 117829#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 117830#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 117960#L1694 assume !(0 != activate_threads_~tmp___12~0); 119070#L1694-2 assume !(1 == ~M_E~0); 117872#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117873#L1431-1 assume !(1 == ~T2_E~0); 117396#L1436-1 assume !(1 == ~T3_E~0); 117397#L1441-1 assume !(1 == ~T4_E~0); 118189#L1446-1 assume !(1 == ~T5_E~0); 118190#L1451-1 assume !(1 == ~T6_E~0); 118998#L1456-1 assume !(1 == ~T7_E~0); 118585#L1461-1 assume !(1 == ~T8_E~0); 118105#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 118106#L1471-1 assume !(1 == ~T10_E~0); 118965#L1476-1 assume !(1 == ~T11_E~0); 118966#L1481-1 assume !(1 == ~T12_E~0); 119168#L1486-1 assume !(1 == ~T13_E~0); 117720#L1491-1 assume !(1 == ~E_M~0); 117338#L1496-1 assume !(1 == ~E_1~0); 117339#L1501-1 assume !(1 == ~E_2~0); 118185#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 118186#L1511-1 assume !(1 == ~E_4~0); 118139#L1516-1 assume !(1 == ~E_5~0); 117292#L1521-1 assume !(1 == ~E_6~0); 117293#L1526-1 assume !(1 == ~E_7~0); 117337#L1531-1 assume !(1 == ~E_8~0); 117893#L1536-1 assume !(1 == ~E_9~0); 117610#L1541-1 assume !(1 == ~E_10~0); 117611#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 119236#L1551-1 assume !(1 == ~E_12~0); 117780#L1556-1 assume !(1 == ~E_13~0); 117781#L1927-1 [2021-11-02 23:08:54,513 INFO L793 eck$LassoCheckResult]: Loop: 117781#L1927-1 assume !false; 126430#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 126426#L1253 assume !false; 126423#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 126393#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 126386#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 126384#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 126382#L1066 assume !(0 != eval_~tmp~0); 119240#L1268 start_simulation_~kernel_st~0 := 2; 117629#L894-1 start_simulation_~kernel_st~0 := 3; 117630#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 118200#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118201#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117797#L1288-3 assume !(0 == ~T3_E~0); 117798#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119064#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119065#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 119246#L1308-3 assume !(0 == ~T7_E~0); 119058#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 118458#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117583#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117584#L1328-3 assume !(0 == ~T11_E~0); 119157#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117729#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117730#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 118931#L1348-3 assume !(0 == ~E_1~0); 119166#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119167#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118420#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117916#L1368-3 assume !(0 == ~E_5~0); 117917#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 118759#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 118760#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 118989#L1388-3 assume !(0 == ~E_9~0); 118990#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 129533#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 129532#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 129531#L1408-3 assume !(0 == ~E_13~0); 129530#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129529#L627-45 assume !(1 == ~m_pc~0); 129528#L627-47 is_master_triggered_~__retres1~0 := 0; 129527#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129526#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 129525#L1590-45 assume !(0 != activate_threads_~tmp~1); 129524#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129523#L646-45 assume 1 == ~t1_pc~0; 129522#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 129521#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129519#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 129520#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 117700#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117701#L665-45 assume !(1 == ~t2_pc~0); 119007#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 129601#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129599#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 129597#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 129595#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 129592#L684-45 assume 1 == ~t3_pc~0; 129589#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 129587#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129585#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 129583#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 129581#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 129578#L703-45 assume !(1 == ~t4_pc~0); 129576#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 129574#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129572#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 129570#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 129568#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 129565#L722-45 assume !(1 == ~t5_pc~0); 129562#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 129561#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 129560#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 129559#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 129558#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 129557#L741-45 assume !(1 == ~t6_pc~0); 129555#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 129554#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 129553#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 129552#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 129551#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 129550#L760-45 assume !(1 == ~t7_pc~0); 129549#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 129547#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 129546#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 129545#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 118837#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 118838#L779-45 assume 1 == ~t8_pc~0; 118784#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 117660#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 117684#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 117685#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 118815#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 118816#L798-45 assume !(1 == ~t9_pc~0); 118312#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 118313#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 118728#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 118432#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 118433#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 118329#L817-45 assume !(1 == ~t10_pc~0); 118331#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 118968#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 118726#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 118056#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 117952#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 117953#L836-45 assume !(1 == ~t11_pc~0); 117458#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 117459#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 118231#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 118232#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 118754#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 118840#L855-45 assume !(1 == ~t12_pc~0); 118179#L855-47 is_transmit12_triggered_~__retres1~12 := 0; 117620#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 117621#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 118572#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 118573#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 118280#L874-45 assume !(1 == ~t13_pc~0); 118281#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 118183#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 118184#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 117771#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 117772#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 118578#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117721#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117722#L1436-3 assume !(1 == ~T3_E~0); 129233#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 129231#L1446-3 assume !(1 == ~T5_E~0); 129228#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 129226#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 129224#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 129222#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 129220#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 129217#L1476-3 assume !(1 == ~T11_E~0); 129215#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 129213#L1486-3 assume !(1 == ~T13_E~0); 129211#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 129209#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 129207#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129205#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129202#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 129200#L1516-3 assume !(1 == ~E_5~0); 129199#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 129198#L1526-3 assume !(1 == ~E_7~0); 129155#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 129154#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 129151#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 129147#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 129141#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 129138#L1556-3 assume !(1 == ~E_13~0); 117442#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 117443#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 117548#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 118973#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 118799#L1946 assume !(0 == start_simulation_~tmp~3); 118494#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 118495#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 117787#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 119305#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 118898#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 118899#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 127101#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 127099#L1959 assume !(0 != start_simulation_~tmp___0~1); 117781#L1927-1 [2021-11-02 23:08:54,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:54,514 INFO L85 PathProgramCache]: Analyzing trace with hash 143212275, now seen corresponding path program 1 times [2021-11-02 23:08:54,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:54,514 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907416341] [2021-11-02 23:08:54,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:54,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:54,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:54,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:54,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:54,587 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907416341] [2021-11-02 23:08:54,587 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907416341] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:54,588 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:54,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:54,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866624445] [2021-11-02 23:08:54,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:54,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:54,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1495569147, now seen corresponding path program 1 times [2021-11-02 23:08:54,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:54,590 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911786544] [2021-11-02 23:08:54,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:54,590 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:54,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:54,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:54,666 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:54,666 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911786544] [2021-11-02 23:08:54,666 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911786544] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:54,667 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:54,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:54,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891264184] [2021-11-02 23:08:54,668 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:54,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:54,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:08:54,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:08:54,670 INFO L87 Difference]: Start difference. First operand 13655 states and 19431 transitions. cyclomatic complexity: 5780 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:55,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:55,359 INFO L93 Difference]: Finished difference Result 33100 states and 46804 transitions. [2021-11-02 23:08:55,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:08:55,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33100 states and 46804 transitions. [2021-11-02 23:08:55,670 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 32482 [2021-11-02 23:08:55,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33100 states to 33100 states and 46804 transitions. [2021-11-02 23:08:55,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33100 [2021-11-02 23:08:55,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33100 [2021-11-02 23:08:55,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33100 states and 46804 transitions. [2021-11-02 23:08:55,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:55,852 INFO L681 BuchiCegarLoop]: Abstraction has 33100 states and 46804 transitions. [2021-11-02 23:08:55,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33100 states and 46804 transitions. [2021-11-02 23:08:56,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33100 to 26210. [2021-11-02 23:08:56,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26210 states, 26210 states have (on average 1.417626859977108) internal successors, (37156), 26209 states have internal predecessors, (37156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:56,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26210 states to 26210 states and 37156 transitions. [2021-11-02 23:08:56,435 INFO L704 BuchiCegarLoop]: Abstraction has 26210 states and 37156 transitions. [2021-11-02 23:08:56,435 INFO L587 BuchiCegarLoop]: Abstraction has 26210 states and 37156 transitions. [2021-11-02 23:08:56,435 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-02 23:08:56,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26210 states and 37156 transitions. [2021-11-02 23:08:56,710 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26016 [2021-11-02 23:08:56,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:08:56,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:08:56,715 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:56,715 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:08:56,716 INFO L791 eck$LassoCheckResult]: Stem: 164908#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 164909#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 166180#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 166031#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 165064#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164865#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164866#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164632#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164633#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 165071#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 165262#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 165440#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 165462#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164642#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164643#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164371#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 164372#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 164816#L966-1 assume !(0 == ~M_E~0); 164817#L1278-1 assume !(0 == ~T1_E~0); 165810#L1283-1 assume !(0 == ~T2_E~0); 165811#L1288-1 assume !(0 == ~T3_E~0); 166090#L1293-1 assume !(0 == ~T4_E~0); 166068#L1298-1 assume !(0 == ~T5_E~0); 165980#L1303-1 assume !(0 == ~T6_E~0); 164470#L1308-1 assume !(0 == ~T7_E~0); 164394#L1313-1 assume !(0 == ~T8_E~0); 164395#L1318-1 assume !(0 == ~T9_E~0); 164399#L1323-1 assume !(0 == ~T10_E~0); 164400#L1328-1 assume !(0 == ~T11_E~0); 164578#L1333-1 assume !(0 == ~T12_E~0); 165595#L1338-1 assume !(0 == ~T13_E~0); 165596#L1343-1 assume !(0 == ~E_M~0); 165755#L1348-1 assume !(0 == ~E_1~0); 166137#L1353-1 assume !(0 == ~E_2~0); 165306#L1358-1 assume !(0 == ~E_3~0); 165307#L1363-1 assume !(0 == ~E_4~0); 165634#L1368-1 assume !(0 == ~E_5~0); 164227#L1373-1 assume !(0 == ~E_6~0); 164228#L1378-1 assume !(0 == ~E_7~0); 164536#L1383-1 assume !(0 == ~E_8~0); 164537#L1388-1 assume !(0 == ~E_9~0); 165673#L1393-1 assume !(0 == ~E_10~0); 165674#L1398-1 assume !(0 == ~E_11~0); 165681#L1403-1 assume !(0 == ~E_12~0); 165977#L1408-1 assume !(0 == ~E_13~0); 164506#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 164507#L627 assume !(1 == ~m_pc~0); 165638#L627-2 is_master_triggered_~__retres1~0 := 0; 164873#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 164874#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 165487#L1590 assume !(0 != activate_threads_~tmp~1); 166022#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 164444#L646 assume !(1 == ~t1_pc~0); 164445#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 165121#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 165122#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 165888#L1598 assume !(0 != activate_threads_~tmp___0~0); 164313#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164314#L665 assume !(1 == ~t2_pc~0); 164981#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 164982#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 164523#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 164524#L1606 assume !(0 != activate_threads_~tmp___1~0); 165090#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 165402#L684 assume !(1 == ~t3_pc~0); 165363#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 165364#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 165441#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 166105#L1614 assume !(0 != activate_threads_~tmp___2~0); 166172#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 166142#L703 assume !(1 == ~t4_pc~0); 164664#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 164665#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 165295#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 164759#L1622 assume !(0 != activate_threads_~tmp___3~0); 164760#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 165894#L722 assume !(1 == ~t5_pc~0); 164716#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 164717#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 165075#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 164055#L1630 assume !(0 != activate_threads_~tmp___4~0); 164056#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 164262#L741 assume !(1 == ~t6_pc~0); 164263#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 165358#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 164715#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 164377#L1638 assume !(0 != activate_threads_~tmp___5~0); 164378#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 164688#L760 assume 1 == ~t7_pc~0; 164660#L761 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 164661#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 164521#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 164522#L1646 assume !(0 != activate_threads_~tmp___6~0); 164896#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 164897#L779 assume !(1 == ~t8_pc~0); 164305#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 164159#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 164160#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 164554#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 165347#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 165348#L798 assume 1 == ~t9_pc~0; 165927#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 165849#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 164306#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 164307#L1662 assume !(0 != activate_threads_~tmp___8~0); 164094#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 164095#L817 assume !(1 == ~t10_pc~0); 164141#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 164915#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 164916#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 164379#L1670 assume !(0 != activate_threads_~tmp___9~0); 164380#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 165296#L836 assume 1 == ~t11_pc~0; 165297#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 164476#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 164477#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 164447#L1678 assume !(0 != activate_threads_~tmp___10~0); 164448#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 165862#L855 assume !(1 == ~t12_pc~0); 165116#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 165117#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 165721#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 165752#L1686 assume !(0 != activate_threads_~tmp___11~0); 165680#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 164429#L874 assume !(1 == ~t13_pc~0); 164431#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 164587#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 164588#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 164718#L1694 assume !(0 != activate_threads_~tmp___12~0); 165830#L1694-2 assume !(1 == ~M_E~0); 164630#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164631#L1431-1 assume !(1 == ~T2_E~0); 164165#L1436-1 assume !(1 == ~T3_E~0); 164166#L1441-1 assume !(1 == ~T4_E~0); 164945#L1446-1 assume !(1 == ~T5_E~0); 164946#L1451-1 assume !(1 == ~T6_E~0); 165753#L1456-1 assume !(1 == ~T7_E~0); 165341#L1461-1 assume !(1 == ~T8_E~0); 164861#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 164862#L1471-1 assume !(1 == ~T10_E~0); 165722#L1476-1 assume !(1 == ~T11_E~0); 165723#L1481-1 assume !(1 == ~T12_E~0); 165922#L1486-1 assume !(1 == ~T13_E~0); 164480#L1491-1 assume !(1 == ~E_M~0); 164103#L1496-1 assume !(1 == ~E_1~0); 164104#L1501-1 assume !(1 == ~E_2~0); 164941#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 164942#L1511-1 assume !(1 == ~E_4~0); 164895#L1516-1 assume !(1 == ~E_5~0); 164057#L1521-1 assume !(1 == ~E_6~0); 164058#L1526-1 assume !(1 == ~E_7~0); 164102#L1531-1 assume !(1 == ~E_8~0); 164652#L1536-1 assume !(1 == ~E_9~0); 164373#L1541-1 assume !(1 == ~E_10~0); 164374#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 165992#L1551-1 assume !(1 == ~E_12~0); 164541#L1556-1 assume !(1 == ~E_13~0); 164288#L1927-1 [2021-11-02 23:08:56,717 INFO L793 eck$LassoCheckResult]: Loop: 164288#L1927-1 assume !false; 164564#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 164575#L1253 assume !false; 164045#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 164046#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 164724#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 164647#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 164648#L1066 assume !(0 != eval_~tmp~0); 165996#L1268 start_simulation_~kernel_st~0 := 2; 164392#L894-1 start_simulation_~kernel_st~0 := 3; 164393#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 164956#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 164957#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 164556#L1288-3 assume !(0 == ~T3_E~0); 164557#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 165824#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 165825#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 166004#L1308-3 assume !(0 == ~T7_E~0); 165817#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 165217#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 164346#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 164347#L1328-3 assume !(0 == ~T11_E~0); 165915#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 164489#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 164490#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 165689#L1348-3 assume !(0 == ~E_1~0); 165920#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 165921#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 165941#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189319#L1368-3 assume !(0 == ~E_5~0); 189318#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189317#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 189316#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189307#L1388-3 assume !(0 == ~E_9~0); 165727#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 165728#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 165011#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 165012#L1408-3 assume !(0 == ~E_13~0); 165926#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 164852#L627-45 assume !(1 == ~m_pc~0); 164853#L627-47 is_master_triggered_~__retres1~0 := 0; 165381#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 165917#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 165198#L1590-45 assume !(0 != activate_threads_~tmp~1); 165199#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 165868#L646-45 assume 1 == ~t1_pc~0; 165956#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 165957#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 190219#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 190218#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 164461#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164462#L665-45 assume !(1 == ~t2_pc~0); 165315#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 164966#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 164967#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 164169#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 164170#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 165418#L684-45 assume !(1 == ~t3_pc~0); 164458#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 164459#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 165588#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 166009#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 165754#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 165531#L703-45 assume !(1 == ~t4_pc~0); 165532#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 165818#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 164922#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 164614#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 164615#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 164953#L722-45 assume !(1 == ~t5_pc~0); 164944#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 165962#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 166020#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 166107#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 165332#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 165333#L741-45 assume !(1 == ~t6_pc~0); 165766#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 165073#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 165074#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 165439#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 165472#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 165573#L760-45 assume 1 == ~t7_pc~0; 165447#L761-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 165448#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 164987#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 164988#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 165597#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 165598#L779-45 assume !(1 == ~t8_pc~0); 164420#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 164421#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 164440#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 164441#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 165574#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 165575#L798-45 assume 1 == ~t9_pc~0; 166096#L799-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 165068#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 165488#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 165188#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 165189#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 165085#L817-45 assume 1 == ~t10_pc~0; 165086#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 165725#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 165486#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 164813#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 164711#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 164712#L836-45 assume 1 == ~t11_pc~0; 165365#L837-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 164223#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 164989#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 164990#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 165512#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 165600#L855-45 assume 1 == ~t12_pc~0; 164934#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 164383#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 164384#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 165329#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 165330#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 165036#L874-45 assume !(1 == ~t13_pc~0); 165037#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 164939#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 164940#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 164532#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 164533#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 165335#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164481#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 164482#L1436-3 assume !(1 == ~T3_E~0); 164061#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164062#L1446-3 assume !(1 == ~T5_E~0); 165789#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 165028#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 164635#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 164636#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 166113#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 164585#L1476-3 assume !(1 == ~T11_E~0); 164586#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 164999#L1486-3 assume !(1 == ~T13_E~0); 164603#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 164604#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 165058#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 165059#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 165516#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 165507#L1516-3 assume !(1 == ~E_5~0); 165508#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 165186#L1526-3 assume !(1 == ~E_7~0); 165187#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 165593#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 164622#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 164623#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 164663#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 166037#L1556-3 assume !(1 == ~E_13~0); 164206#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 164207#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 164311#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 165730#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 165558#L1946 assume !(0 == start_simulation_~tmp~3); 165559#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 189024#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 189017#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 166071#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 165657#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 164043#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 164044#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 164287#L1959 assume !(0 != start_simulation_~tmp___0~1); 164288#L1927-1 [2021-11-02 23:08:56,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:56,718 INFO L85 PathProgramCache]: Analyzing trace with hash 284311796, now seen corresponding path program 1 times [2021-11-02 23:08:56,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:56,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340680131] [2021-11-02 23:08:56,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:56,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:56,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:56,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:56,780 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:56,780 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340680131] [2021-11-02 23:08:56,780 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340680131] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:56,781 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:56,781 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:56,781 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475989108] [2021-11-02 23:08:56,782 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:08:56,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:08:56,782 INFO L85 PathProgramCache]: Analyzing trace with hash 1121240360, now seen corresponding path program 1 times [2021-11-02 23:08:56,783 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:08:56,783 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428926748] [2021-11-02 23:08:56,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:08:56,784 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:08:56,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:08:56,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:08:56,838 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:08:56,838 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428926748] [2021-11-02 23:08:56,838 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428926748] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:08:56,838 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:08:56,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:08:56,839 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221779637] [2021-11-02 23:08:56,839 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:08:56,840 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:08:56,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:08:56,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:08:56,841 INFO L87 Difference]: Start difference. First operand 26210 states and 37156 transitions. cyclomatic complexity: 10950 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:08:57,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:08:57,647 INFO L93 Difference]: Finished difference Result 63621 states and 89645 transitions. [2021-11-02 23:08:57,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:08:57,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63621 states and 89645 transitions. [2021-11-02 23:08:58,255 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 62560 [2021-11-02 23:08:58,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63621 states to 63621 states and 89645 transitions. [2021-11-02 23:08:58,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63621 [2021-11-02 23:08:58,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63621 [2021-11-02 23:08:58,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63621 states and 89645 transitions. [2021-11-02 23:08:58,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:08:58,617 INFO L681 BuchiCegarLoop]: Abstraction has 63621 states and 89645 transitions. [2021-11-02 23:08:58,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63621 states and 89645 transitions. [2021-11-02 23:08:59,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63621 to 50409. [2021-11-02 23:08:59,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50409 states, 50409 states have (on average 1.4126247297109644) internal successors, (71209), 50408 states have internal predecessors, (71209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:00,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50409 states to 50409 states and 71209 transitions. [2021-11-02 23:09:00,071 INFO L704 BuchiCegarLoop]: Abstraction has 50409 states and 71209 transitions. [2021-11-02 23:09:00,071 INFO L587 BuchiCegarLoop]: Abstraction has 50409 states and 71209 transitions. [2021-11-02 23:09:00,071 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-02 23:09:00,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50409 states and 71209 transitions. [2021-11-02 23:09:00,252 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 50192 [2021-11-02 23:09:00,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:00,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:00,257 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:00,257 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:00,258 INFO L791 eck$LassoCheckResult]: Stem: 254750#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 254751#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 256081#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 255903#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 254905#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 254707#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 254708#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 254474#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 254475#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 254907#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 255106#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 255278#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 255303#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 254482#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 254483#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 254212#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 254213#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 254657#L966-1 assume !(0 == ~M_E~0); 254658#L1278-1 assume !(0 == ~T1_E~0); 255674#L1283-1 assume !(0 == ~T2_E~0); 255675#L1288-1 assume !(0 == ~T3_E~0); 255969#L1293-1 assume !(0 == ~T4_E~0); 255945#L1298-1 assume !(0 == ~T5_E~0); 255848#L1303-1 assume !(0 == ~T6_E~0); 254310#L1308-1 assume !(0 == ~T7_E~0); 254235#L1313-1 assume !(0 == ~T8_E~0); 254236#L1318-1 assume !(0 == ~T9_E~0); 254238#L1323-1 assume !(0 == ~T10_E~0); 254239#L1328-1 assume !(0 == ~T11_E~0); 254421#L1333-1 assume !(0 == ~T12_E~0); 255439#L1338-1 assume !(0 == ~T13_E~0); 255440#L1343-1 assume !(0 == ~E_M~0); 255619#L1348-1 assume !(0 == ~E_1~0); 256021#L1353-1 assume !(0 == ~E_2~0); 255149#L1358-1 assume !(0 == ~E_3~0); 255150#L1363-1 assume !(0 == ~E_4~0); 255478#L1368-1 assume !(0 == ~E_5~0); 254068#L1373-1 assume !(0 == ~E_6~0); 254069#L1378-1 assume !(0 == ~E_7~0); 254377#L1383-1 assume !(0 == ~E_8~0); 254378#L1388-1 assume !(0 == ~E_9~0); 255529#L1393-1 assume !(0 == ~E_10~0); 255530#L1398-1 assume !(0 == ~E_11~0); 255537#L1403-1 assume !(0 == ~E_12~0); 255846#L1408-1 assume !(0 == ~E_13~0); 254348#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 254349#L627 assume !(1 == ~m_pc~0); 255484#L627-2 is_master_triggered_~__retres1~0 := 0; 254711#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 254712#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 255329#L1590 assume !(0 != activate_threads_~tmp~1); 255894#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 254280#L646 assume !(1 == ~t1_pc~0); 254281#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 255829#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 256102#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 255755#L1598 assume !(0 != activate_threads_~tmp___0~0); 254154#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 254155#L665 assume !(1 == ~t2_pc~0); 254820#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 254821#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 254365#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 254366#L1606 assume !(0 != activate_threads_~tmp___1~0); 254931#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 255238#L684 assume !(1 == ~t3_pc~0); 255202#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 255203#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 255280#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 255981#L1614 assume !(0 != activate_threads_~tmp___2~0); 256063#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 256030#L703 assume !(1 == ~t4_pc~0); 254503#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 254504#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 255139#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 254598#L1622 assume !(0 != activate_threads_~tmp___3~0); 254599#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 255761#L722 assume !(1 == ~t5_pc~0); 254555#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 254556#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 254916#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 253894#L1630 assume !(0 != activate_threads_~tmp___4~0); 253895#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 254103#L741 assume !(1 == ~t6_pc~0); 254104#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 255198#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 254554#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 254218#L1638 assume !(0 != activate_threads_~tmp___5~0); 254219#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 254526#L760 assume !(1 == ~t7_pc~0); 254644#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 255103#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 254360#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 254361#L1646 assume !(0 != activate_threads_~tmp___6~0); 254738#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 254739#L779 assume !(1 == ~t8_pc~0); 254146#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 254000#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 254001#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 254397#L1654 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 255191#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 255192#L798 assume 1 == ~t9_pc~0; 255796#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 255711#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 254147#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 254148#L1662 assume !(0 != activate_threads_~tmp___8~0); 253935#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 253936#L817 assume !(1 == ~t10_pc~0); 253982#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 254757#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 254758#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 254220#L1670 assume !(0 != activate_threads_~tmp___9~0); 254221#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 255140#L836 assume 1 == ~t11_pc~0; 255141#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 254318#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 254319#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 254283#L1678 assume !(0 != activate_threads_~tmp___10~0); 254284#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 255723#L855 assume !(1 == ~t12_pc~0); 254955#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 254956#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 255581#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 255613#L1686 assume !(0 != activate_threads_~tmp___11~0); 255536#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 254269#L874 assume !(1 == ~t13_pc~0); 254271#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 254430#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 254431#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 254557#L1694 assume !(0 != activate_threads_~tmp___12~0); 255694#L1694-2 assume !(1 == ~M_E~0); 254472#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 254473#L1431-1 assume !(1 == ~T2_E~0); 254002#L1436-1 assume !(1 == ~T3_E~0); 254003#L1441-1 assume !(1 == ~T4_E~0); 254786#L1446-1 assume !(1 == ~T5_E~0); 254787#L1451-1 assume !(1 == ~T6_E~0); 255617#L1456-1 assume !(1 == ~T7_E~0); 255185#L1461-1 assume !(1 == ~T8_E~0); 254703#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 254704#L1471-1 assume !(1 == ~T10_E~0); 255582#L1476-1 assume !(1 == ~T11_E~0); 255583#L1481-1 assume !(1 == ~T12_E~0); 255792#L1486-1 assume !(1 == ~T13_E~0); 254322#L1491-1 assume !(1 == ~E_M~0); 253944#L1496-1 assume !(1 == ~E_1~0); 253945#L1501-1 assume !(1 == ~E_2~0); 254782#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 254783#L1511-1 assume !(1 == ~E_4~0); 254737#L1516-1 assume !(1 == ~E_5~0); 253898#L1521-1 assume !(1 == ~E_6~0); 253899#L1526-1 assume !(1 == ~E_7~0); 253943#L1531-1 assume !(1 == ~E_8~0); 254494#L1536-1 assume !(1 == ~E_9~0); 254214#L1541-1 assume !(1 == ~E_10~0); 254215#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 255865#L1551-1 assume !(1 == ~E_12~0); 254382#L1556-1 assume !(1 == ~E_13~0); 254383#L1927-1 [2021-11-02 23:09:00,258 INFO L793 eck$LassoCheckResult]: Loop: 254383#L1927-1 assume !false; 301238#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 301233#L1253 assume !false; 301231#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 301162#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 301152#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 301148#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 301142#L1066 assume !(0 != eval_~tmp~0); 255869#L1268 start_simulation_~kernel_st~0 := 2; 254233#L894-1 start_simulation_~kernel_st~0 := 3; 254234#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 254797#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 254798#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 254399#L1288-3 assume !(0 == ~T3_E~0); 254400#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 255688#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 255689#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 255877#L1308-3 assume !(0 == ~T7_E~0); 255681#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 255060#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 254187#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 254188#L1328-3 assume !(0 == ~T11_E~0); 255786#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 254331#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 254332#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 255544#L1348-3 assume !(0 == ~E_1~0); 255790#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 255791#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 255020#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 254514#L1368-3 assume !(0 == ~E_5~0); 254515#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 255358#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 255359#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 255602#L1388-3 assume !(0 == ~E_9~0); 255587#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 255588#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 254850#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 254851#L1408-3 assume !(0 == ~E_13~0); 255798#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 254693#L627-45 assume !(1 == ~m_pc~0); 254694#L627-47 is_master_triggered_~__retres1~0 := 0; 255219#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 255788#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 255041#L1590-45 assume !(0 != activate_threads_~tmp~1); 255042#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 255729#L646-45 assume !(1 == ~t1_pc~0); 254892#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 254893#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 255093#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 255094#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 254303#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 254304#L665-45 assume !(1 == ~t2_pc~0); 255158#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 254805#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 254806#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 254010#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 254011#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 255254#L684-45 assume 1 == ~t3_pc~0; 255255#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 254301#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 255430#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 255879#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 255618#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 255369#L703-45 assume !(1 == ~t4_pc~0); 255370#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 255682#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 254764#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 254457#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 254458#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 254794#L722-45 assume !(1 == ~t5_pc~0); 254785#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 255832#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 255892#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 304241#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 304240#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 304239#L741-45 assume !(1 == ~t6_pc~0); 303271#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 304237#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 304236#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 304235#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 304234#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 304203#L760-45 assume !(1 == ~t7_pc~0); 255562#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 255563#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 255783#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 302446#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 302445#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 302076#L779-45 assume !(1 == ~t8_pc~0); 302074#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 302073#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 302072#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 302071#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 302070#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 302069#L798-45 assume !(1 == ~t9_pc~0); 302068#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 302066#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 302065#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 302064#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 302063#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 302062#L817-45 assume 1 == ~t10_pc~0; 302060#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 302058#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 302056#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 302054#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 302052#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 302050#L836-45 assume !(1 == ~t11_pc~0); 302046#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 302044#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 302042#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 302040#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 301859#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 301855#L855-45 assume 1 == ~t12_pc~0; 301849#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 301842#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 301836#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 301830#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 301824#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 301817#L874-45 assume !(1 == ~t13_pc~0); 301811#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 301804#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 301800#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 301793#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 301784#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 301779#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 301752#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 301683#L1436-3 assume !(1 == ~T3_E~0); 301677#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 301671#L1446-3 assume !(1 == ~T5_E~0); 301665#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 301657#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 301650#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 301643#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 301637#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 301629#L1476-3 assume !(1 == ~T11_E~0); 301621#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 301617#L1486-3 assume !(1 == ~T13_E~0); 301616#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 301615#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 301614#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 301613#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 301611#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 301609#L1516-3 assume !(1 == ~E_5~0); 301607#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 301605#L1526-3 assume !(1 == ~E_7~0); 301603#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 301601#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 301597#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 301595#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 301593#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 301587#L1556-3 assume !(1 == ~E_13~0); 301586#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 301572#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 301562#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 301557#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 301552#L1946 assume !(0 == start_simulation_~tmp~3); 301548#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 301403#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 301388#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 301378#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 301370#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 301355#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 301344#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 301335#L1959 assume !(0 != start_simulation_~tmp___0~1); 254383#L1927-1 [2021-11-02 23:09:00,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:00,259 INFO L85 PathProgramCache]: Analyzing trace with hash 1421940661, now seen corresponding path program 1 times [2021-11-02 23:09:00,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:00,260 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938600701] [2021-11-02 23:09:00,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:00,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:00,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:00,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:00,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:00,312 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938600701] [2021-11-02 23:09:00,312 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938600701] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:00,312 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:00,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-02 23:09:00,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144968283] [2021-11-02 23:09:00,313 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:00,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:00,314 INFO L85 PathProgramCache]: Analyzing trace with hash -295170301, now seen corresponding path program 1 times [2021-11-02 23:09:00,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:00,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423036674] [2021-11-02 23:09:00,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:00,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:00,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:00,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:00,358 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:00,359 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423036674] [2021-11-02 23:09:00,359 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423036674] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:00,359 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:00,359 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:00,359 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765529052] [2021-11-02 23:09:00,360 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:00,360 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:00,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-02 23:09:00,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-02 23:09:00,361 INFO L87 Difference]: Start difference. First operand 50409 states and 71209 transitions. cyclomatic complexity: 20804 Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:01,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:01,511 INFO L93 Difference]: Finished difference Result 122666 states and 174518 transitions. [2021-11-02 23:09:01,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-02 23:09:01,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122666 states and 174518 transitions. [2021-11-02 23:09:02,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 122224 [2021-11-02 23:09:03,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122666 states to 122666 states and 174518 transitions. [2021-11-02 23:09:03,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122666 [2021-11-02 23:09:03,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122666 [2021-11-02 23:09:03,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122666 states and 174518 transitions. [2021-11-02 23:09:03,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:09:03,267 INFO L681 BuchiCegarLoop]: Abstraction has 122666 states and 174518 transitions. [2021-11-02 23:09:03,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122666 states and 174518 transitions. [2021-11-02 23:09:04,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122666 to 51708. [2021-11-02 23:09:04,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51708 states, 51708 states have (on average 1.4022588380908176) internal successors, (72508), 51707 states have internal predecessors, (72508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:04,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51708 states to 51708 states and 72508 transitions. [2021-11-02 23:09:04,734 INFO L704 BuchiCegarLoop]: Abstraction has 51708 states and 72508 transitions. [2021-11-02 23:09:04,734 INFO L587 BuchiCegarLoop]: Abstraction has 51708 states and 72508 transitions. [2021-11-02 23:09:04,734 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-02 23:09:04,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51708 states and 72508 transitions. [2021-11-02 23:09:05,444 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 51488 [2021-11-02 23:09:05,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:05,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:05,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:05,451 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:05,451 INFO L791 eck$LassoCheckResult]: Stem: 427850#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 427851#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 429241#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 429056#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 428005#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 427805#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 427806#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 427567#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 427568#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 428007#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 428210#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 428394#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 428417#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 427576#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 427577#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 427301#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 427302#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 427756#L966-1 assume !(0 == ~M_E~0); 427757#L1278-1 assume !(0 == ~T1_E~0); 428801#L1283-1 assume !(0 == ~T2_E~0); 428802#L1288-1 assume !(0 == ~T3_E~0); 429121#L1293-1 assume !(0 == ~T4_E~0); 429098#L1298-1 assume !(0 == ~T5_E~0); 428990#L1303-1 assume !(0 == ~T6_E~0); 427400#L1308-1 assume !(0 == ~T7_E~0); 427324#L1313-1 assume !(0 == ~T8_E~0); 427325#L1318-1 assume !(0 == ~T9_E~0); 427327#L1323-1 assume !(0 == ~T10_E~0); 427328#L1328-1 assume !(0 == ~T11_E~0); 427513#L1333-1 assume !(0 == ~T12_E~0); 428555#L1338-1 assume !(0 == ~T13_E~0); 428556#L1343-1 assume !(0 == ~E_M~0); 428739#L1348-1 assume !(0 == ~E_1~0); 429175#L1353-1 assume !(0 == ~E_2~0); 428254#L1358-1 assume !(0 == ~E_3~0); 428255#L1363-1 assume !(0 == ~E_4~0); 428596#L1368-1 assume !(0 == ~E_5~0); 427156#L1373-1 assume !(0 == ~E_6~0); 427157#L1378-1 assume !(0 == ~E_7~0); 427467#L1383-1 assume !(0 == ~E_8~0); 427468#L1388-1 assume !(0 == ~E_9~0); 428652#L1393-1 assume !(0 == ~E_10~0); 428653#L1398-1 assume !(0 == ~E_11~0); 428660#L1403-1 assume !(0 == ~E_12~0); 428988#L1408-1 assume !(0 == ~E_13~0); 427438#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 427439#L627 assume !(1 == ~m_pc~0); 428601#L627-2 is_master_triggered_~__retres1~0 := 0; 427809#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 427810#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 428444#L1590 assume !(0 != activate_threads_~tmp~1); 429047#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 427369#L646 assume !(1 == ~t1_pc~0); 427370#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 428971#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 429264#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 428892#L1598 assume !(0 != activate_threads_~tmp___0~0); 427243#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 427244#L665 assume !(1 == ~t2_pc~0); 427919#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 427920#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 427455#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 427456#L1606 assume !(0 != activate_threads_~tmp___1~0); 428032#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 428350#L684 assume !(1 == ~t3_pc~0); 428312#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 428313#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 428398#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 429134#L1614 assume !(0 != activate_threads_~tmp___2~0); 429218#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 429185#L703 assume !(1 == ~t4_pc~0); 427597#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 427598#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 428244#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 427696#L1622 assume !(0 != activate_threads_~tmp___3~0); 427697#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 428898#L722 assume !(1 == ~t5_pc~0); 427651#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 427652#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 428016#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 426982#L1630 assume !(0 != activate_threads_~tmp___4~0); 426983#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 427191#L741 assume !(1 == ~t6_pc~0); 427192#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 428307#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 427650#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 427307#L1638 assume !(0 != activate_threads_~tmp___5~0); 427308#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 427621#L760 assume !(1 == ~t7_pc~0); 427743#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 428206#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 427450#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 427451#L1646 assume !(0 != activate_threads_~tmp___6~0); 427836#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 427837#L779 assume !(1 == ~t8_pc~0); 427235#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 427088#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 427089#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 428933#L1654 assume !(0 != activate_threads_~tmp___7~0); 428299#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 428300#L798 assume 1 == ~t9_pc~0; 428942#L799 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 428846#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 427236#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 427237#L1662 assume !(0 != activate_threads_~tmp___8~0); 427023#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 427024#L817 assume !(1 == ~t10_pc~0); 427070#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 427857#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 427858#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 427309#L1670 assume !(0 != activate_threads_~tmp___9~0); 427310#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 428245#L836 assume 1 == ~t11_pc~0; 428246#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 427408#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 427409#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 427372#L1678 assume !(0 != activate_threads_~tmp___10~0); 427373#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 428861#L855 assume !(1 == ~t12_pc~0); 428057#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 428058#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 428699#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 428736#L1686 assume !(0 != activate_threads_~tmp___11~0); 428659#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 427358#L874 assume !(1 == ~t13_pc~0); 427360#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 427522#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 427523#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 427653#L1694 assume !(0 != activate_threads_~tmp___12~0); 428827#L1694-2 assume !(1 == ~M_E~0); 427565#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 427566#L1431-1 assume !(1 == ~T2_E~0); 427090#L1436-1 assume !(1 == ~T3_E~0); 427091#L1441-1 assume !(1 == ~T4_E~0); 427887#L1446-1 assume !(1 == ~T5_E~0); 427888#L1451-1 assume !(1 == ~T6_E~0); 428737#L1456-1 assume !(1 == ~T7_E~0); 428292#L1461-1 assume !(1 == ~T8_E~0); 427801#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 427802#L1471-1 assume !(1 == ~T10_E~0); 428700#L1476-1 assume !(1 == ~T11_E~0); 428701#L1481-1 assume !(1 == ~T12_E~0); 428936#L1486-1 assume !(1 == ~T13_E~0); 427412#L1491-1 assume !(1 == ~E_M~0); 427032#L1496-1 assume !(1 == ~E_1~0); 427033#L1501-1 assume !(1 == ~E_2~0); 427883#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 427884#L1511-1 assume !(1 == ~E_4~0); 427835#L1516-1 assume !(1 == ~E_5~0); 426986#L1521-1 assume !(1 == ~E_6~0); 426987#L1526-1 assume !(1 == ~E_7~0); 427031#L1531-1 assume !(1 == ~E_8~0); 427588#L1536-1 assume !(1 == ~E_9~0); 427303#L1541-1 assume !(1 == ~E_10~0); 427304#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 429009#L1551-1 assume !(1 == ~E_12~0); 427473#L1556-1 assume !(1 == ~E_13~0); 427474#L1927-1 [2021-11-02 23:09:05,452 INFO L793 eck$LassoCheckResult]: Loop: 427474#L1927-1 assume !false; 441919#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 441909#L1253 assume !false; 441903#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 441434#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 441419#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 441411#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 441401#L1066 assume !(0 != eval_~tmp~0); 441402#L1268 start_simulation_~kernel_st~0 := 2; 467855#L894-1 start_simulation_~kernel_st~0 := 3; 467849#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 467842#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 467835#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 467814#L1288-3 assume !(0 == ~T3_E~0); 467806#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 467798#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 467790#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 467782#L1308-3 assume !(0 == ~T7_E~0); 467774#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 467766#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 467758#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 467750#L1328-3 assume !(0 == ~T11_E~0); 467743#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 467735#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 467658#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 467651#L1348-3 assume !(0 == ~E_1~0); 467645#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 467572#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 467563#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 467554#L1368-3 assume !(0 == ~E_5~0); 467546#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 467538#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 467532#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 467526#L1388-3 assume !(0 == ~E_9~0); 467519#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 467513#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 467441#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 467435#L1408-3 assume !(0 == ~E_13~0); 467429#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 467428#L627-45 assume !(1 == ~m_pc~0); 467427#L627-47 is_master_triggered_~__retres1~0 := 0; 467426#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 467425#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 467424#L1590-45 assume !(0 != activate_threads_~tmp~1); 467423#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 467422#L646-45 assume !(1 == ~t1_pc~0); 467421#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 467419#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 467417#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 467415#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 467413#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 467412#L665-45 assume !(1 == ~t2_pc~0); 447187#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 467411#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 467410#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 467409#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 467408#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 467407#L684-45 assume !(1 == ~t3_pc~0); 467406#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 467404#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 467403#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 467402#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 467401#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 467400#L703-45 assume !(1 == ~t4_pc~0); 467398#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 467396#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 467394#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 467392#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 467390#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 467388#L722-45 assume !(1 == ~t5_pc~0); 467385#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 467382#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 467379#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 467376#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 467373#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 467371#L741-45 assume !(1 == ~t6_pc~0); 441559#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 467369#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 467367#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 467365#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 467363#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 443448#L760-45 assume !(1 == ~t7_pc~0); 443447#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 443446#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 443445#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 443444#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 443443#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 443442#L779-45 assume 1 == ~t8_pc~0; 443440#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 443438#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 443436#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 443434#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 443432#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 443430#L798-45 assume !(1 == ~t9_pc~0); 443428#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 443425#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 443423#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 443420#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 443418#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 443416#L817-45 assume 1 == ~t10_pc~0; 443396#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 443394#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 443392#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 443390#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 443388#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 443386#L836-45 assume !(1 == ~t11_pc~0); 443383#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 443381#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 443379#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 443377#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 443375#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 443373#L855-45 assume 1 == ~t12_pc~0; 443370#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 443368#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 443366#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 443364#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 443362#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 443357#L874-45 assume !(1 == ~t13_pc~0); 443355#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 443353#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 443350#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 443348#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 443345#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 443343#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 443341#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 443339#L1436-3 assume !(1 == ~T3_E~0); 443337#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 443335#L1446-3 assume !(1 == ~T5_E~0); 443332#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 443330#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 443316#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 443315#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 443302#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 443292#L1476-3 assume !(1 == ~T11_E~0); 443284#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 443279#L1486-3 assume !(1 == ~T13_E~0); 443275#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 443272#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 443269#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 443231#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 443227#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 443207#L1516-3 assume !(1 == ~E_5~0); 443200#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 443100#L1526-3 assume !(1 == ~E_7~0); 443094#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 443089#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 443018#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 443016#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 443015#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 443014#L1556-3 assume !(1 == ~E_13~0); 442882#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 442265#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 442249#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 442243#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 442234#L1946 assume !(0 == start_simulation_~tmp~3); 442227#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 442028#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 442019#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 442017#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 442015#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 442013#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 442011#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 441937#L1959 assume !(0 != start_simulation_~tmp___0~1); 427474#L1927-1 [2021-11-02 23:09:05,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:05,453 INFO L85 PathProgramCache]: Analyzing trace with hash 1982640439, now seen corresponding path program 1 times [2021-11-02 23:09:05,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:05,453 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923636420] [2021-11-02 23:09:05,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:05,454 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:05,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:05,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:05,511 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:05,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923636420] [2021-11-02 23:09:05,511 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923636420] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:05,511 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:05,512 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:05,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367657449] [2021-11-02 23:09:05,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:05,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:05,513 INFO L85 PathProgramCache]: Analyzing trace with hash -52965693, now seen corresponding path program 1 times [2021-11-02 23:09:05,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:05,514 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261550001] [2021-11-02 23:09:05,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:05,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:05,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:05,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:05,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:05,574 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261550001] [2021-11-02 23:09:05,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261550001] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:05,574 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:05,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:05,575 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [359038032] [2021-11-02 23:09:05,577 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:05,577 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:05,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:09:05,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:09:05,578 INFO L87 Difference]: Start difference. First operand 51708 states and 72508 transitions. cyclomatic complexity: 20804 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:06,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:06,353 INFO L93 Difference]: Finished difference Result 125195 states and 174545 transitions. [2021-11-02 23:09:06,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:09:06,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125195 states and 174545 transitions. [2021-11-02 23:09:07,399 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 123200 [2021-11-02 23:09:07,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125195 states to 125195 states and 174545 transitions. [2021-11-02 23:09:07,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125195 [2021-11-02 23:09:07,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125195 [2021-11-02 23:09:07,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125195 states and 174545 transitions. [2021-11-02 23:09:07,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:09:07,917 INFO L681 BuchiCegarLoop]: Abstraction has 125195 states and 174545 transitions. [2021-11-02 23:09:07,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125195 states and 174545 transitions. [2021-11-02 23:09:09,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125195 to 99499. [2021-11-02 23:09:09,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99499 states, 99499 states have (on average 1.3976522377109317) internal successors, (139065), 99498 states have internal predecessors, (139065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:09,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99499 states to 99499 states and 139065 transitions. [2021-11-02 23:09:09,686 INFO L704 BuchiCegarLoop]: Abstraction has 99499 states and 139065 transitions. [2021-11-02 23:09:09,686 INFO L587 BuchiCegarLoop]: Abstraction has 99499 states and 139065 transitions. [2021-11-02 23:09:09,686 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-02 23:09:09,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99499 states and 139065 transitions. [2021-11-02 23:09:10,510 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 99232 [2021-11-02 23:09:10,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:10,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:10,517 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:10,518 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:10,530 INFO L791 eck$LassoCheckResult]: Stem: 604764#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 604765#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 606171#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 605965#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 604927#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 604720#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 604721#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 604485#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 604486#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 604935#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 605137#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 605320#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 605345#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 604496#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 604497#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 604219#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 604220#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 604670#L966-1 assume !(0 == ~M_E~0); 604671#L1278-1 assume !(0 == ~T1_E~0); 605730#L1283-1 assume !(0 == ~T2_E~0); 605731#L1288-1 assume !(0 == ~T3_E~0); 606039#L1293-1 assume !(0 == ~T4_E~0); 606014#L1298-1 assume !(0 == ~T5_E~0); 605907#L1303-1 assume !(0 == ~T6_E~0); 604319#L1308-1 assume !(0 == ~T7_E~0); 604242#L1313-1 assume !(0 == ~T8_E~0); 604243#L1318-1 assume !(0 == ~T9_E~0); 604247#L1323-1 assume !(0 == ~T10_E~0); 604248#L1328-1 assume !(0 == ~T11_E~0); 604431#L1333-1 assume !(0 == ~T12_E~0); 605489#L1338-1 assume !(0 == ~T13_E~0); 605490#L1343-1 assume !(0 == ~E_M~0); 605673#L1348-1 assume !(0 == ~E_1~0); 606100#L1353-1 assume !(0 == ~E_2~0); 605182#L1358-1 assume !(0 == ~E_3~0); 605183#L1363-1 assume !(0 == ~E_4~0); 605532#L1368-1 assume !(0 == ~E_5~0); 604072#L1373-1 assume !(0 == ~E_6~0); 604073#L1378-1 assume !(0 == ~E_7~0); 604385#L1383-1 assume !(0 == ~E_8~0); 604386#L1388-1 assume !(0 == ~E_9~0); 605585#L1393-1 assume !(0 == ~E_10~0); 605586#L1398-1 assume !(0 == ~E_11~0); 605595#L1403-1 assume !(0 == ~E_12~0); 605903#L1408-1 assume !(0 == ~E_13~0); 604355#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 604356#L627 assume !(1 == ~m_pc~0); 605535#L627-2 is_master_triggered_~__retres1~0 := 0; 604728#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 604729#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 605373#L1590 assume !(0 != activate_threads_~tmp~1); 605953#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 604293#L646 assume !(1 == ~t1_pc~0); 604294#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 605880#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 606204#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 605809#L1598 assume !(0 != activate_threads_~tmp___0~0); 604159#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 604160#L665 assume !(1 == ~t2_pc~0); 604839#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 604840#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 604373#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 604374#L1606 assume !(0 != activate_threads_~tmp___1~0); 604952#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 605279#L684 assume !(1 == ~t3_pc~0); 605237#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 605238#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 605322#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 606057#L1614 assume !(0 != activate_threads_~tmp___2~0); 606142#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 606110#L703 assume !(1 == ~t4_pc~0); 604515#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 604516#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 605171#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 604611#L1622 assume !(0 != activate_threads_~tmp___3~0); 604612#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 605815#L722 assume !(1 == ~t5_pc~0); 604568#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 604569#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 604937#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 603898#L1630 assume !(0 != activate_threads_~tmp___4~0); 603899#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 604109#L741 assume !(1 == ~t6_pc~0); 604110#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 605232#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 604567#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 604225#L1638 assume !(0 != activate_threads_~tmp___5~0); 604226#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 604538#L760 assume !(1 == ~t7_pc~0); 604657#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 605136#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 604371#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 604372#L1646 assume !(0 != activate_threads_~tmp___6~0); 604752#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 604753#L779 assume !(1 == ~t8_pc~0); 604151#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 605971#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 604405#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 604406#L1654 assume !(0 != activate_threads_~tmp___7~0); 605223#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 605224#L798 assume !(1 == ~t9_pc~0); 606056#L798-2 is_transmit9_triggered_~__retres1~9 := 0; 605774#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 604152#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 604153#L1662 assume !(0 != activate_threads_~tmp___8~0); 603937#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 603938#L817 assume !(1 == ~t10_pc~0); 603984#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 604771#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 604772#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 604227#L1670 assume !(0 != activate_threads_~tmp___9~0); 604228#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 605172#L836 assume 1 == ~t11_pc~0; 605173#L837 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 604325#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 604326#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 604296#L1678 assume !(0 != activate_threads_~tmp___10~0); 604297#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 605787#L855 assume !(1 == ~t12_pc~0); 604978#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 604979#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 605636#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 605670#L1686 assume !(0 != activate_threads_~tmp___11~0); 605594#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 604278#L874 assume !(1 == ~t13_pc~0); 604280#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 604441#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 604442#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 604570#L1694 assume !(0 != activate_threads_~tmp___12~0); 605754#L1694-2 assume !(1 == ~M_E~0); 604483#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 604484#L1431-1 assume !(1 == ~T2_E~0); 604008#L1436-1 assume !(1 == ~T3_E~0); 604009#L1441-1 assume !(1 == ~T4_E~0); 604802#L1446-1 assume !(1 == ~T5_E~0); 604803#L1451-1 assume !(1 == ~T6_E~0); 605671#L1456-1 assume !(1 == ~T7_E~0); 605217#L1461-1 assume !(1 == ~T8_E~0); 604716#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 604717#L1471-1 assume !(1 == ~T10_E~0); 605637#L1476-1 assume !(1 == ~T11_E~0); 605638#L1481-1 assume !(1 == ~T12_E~0); 605848#L1486-1 assume !(1 == ~T13_E~0); 604329#L1491-1 assume !(1 == ~E_M~0); 603946#L1496-1 assume !(1 == ~E_1~0); 603947#L1501-1 assume !(1 == ~E_2~0); 604798#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 604799#L1511-1 assume !(1 == ~E_4~0); 604751#L1516-1 assume !(1 == ~E_5~0); 603902#L1521-1 assume !(1 == ~E_6~0); 603903#L1526-1 assume !(1 == ~E_7~0); 603945#L1531-1 assume !(1 == ~E_8~0); 604506#L1536-1 assume !(1 == ~E_9~0); 604221#L1541-1 assume !(1 == ~E_10~0); 604222#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 605921#L1551-1 assume !(1 == ~E_12~0); 604390#L1556-1 assume !(1 == ~E_13~0); 604391#L1927-1 [2021-11-02 23:09:10,531 INFO L793 eck$LassoCheckResult]: Loop: 604391#L1927-1 assume !false; 670743#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 670735#L1253 assume !false; 670734#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 670657#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 670644#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 670635#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 670626#L1066 assume !(0 != eval_~tmp~0); 670627#L1268 start_simulation_~kernel_st~0 := 2; 689676#L894-1 start_simulation_~kernel_st~0 := 3; 689674#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 689673#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 689671#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 689669#L1288-3 assume !(0 == ~T3_E~0); 689667#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 689665#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 689661#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 689659#L1308-3 assume !(0 == ~T7_E~0); 689657#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 689655#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 689652#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 689650#L1328-3 assume !(0 == ~T11_E~0); 689648#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 689645#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 689643#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 689641#L1348-3 assume !(0 == ~E_1~0); 689639#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 689637#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 689635#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 689632#L1368-3 assume !(0 == ~E_5~0); 689630#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 689628#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 689626#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 689624#L1388-3 assume !(0 == ~E_9~0); 689622#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 689619#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 689617#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 689615#L1408-3 assume !(0 == ~E_13~0); 689613#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 689611#L627-45 assume !(1 == ~m_pc~0); 689609#L627-47 is_master_triggered_~__retres1~0 := 0; 689606#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 689604#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 689602#L1590-45 assume !(0 != activate_threads_~tmp~1); 689600#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 689598#L646-45 assume !(1 == ~t1_pc~0); 689593#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 689591#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 689589#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 689587#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 689584#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 689580#L665-45 assume !(1 == ~t2_pc~0); 687727#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 689577#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 689575#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 689569#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 689566#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 689563#L684-45 assume 1 == ~t3_pc~0; 689435#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 689432#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 689430#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 688278#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 688121#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 671895#L703-45 assume !(1 == ~t4_pc~0); 671894#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 671893#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 671888#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 671883#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 671877#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 671871#L722-45 assume !(1 == ~t5_pc~0); 671864#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 671857#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 671851#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 671845#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 671839#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 671832#L741-45 assume !(1 == ~t6_pc~0); 662217#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 671820#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 671812#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 671805#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 671797#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 671787#L760-45 assume !(1 == ~t7_pc~0); 669183#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 671771#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 671763#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 671756#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 671749#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 671739#L779-45 assume 1 == ~t8_pc~0; 671730#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 671720#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 671709#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 671699#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 671691#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 671682#L798-45 assume !(1 == ~t9_pc~0); 625679#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 671669#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 671662#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 671655#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 671647#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 671640#L817-45 assume 1 == ~t10_pc~0; 671631#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 671622#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 671615#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 671608#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 671599#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 671593#L836-45 assume !(1 == ~t11_pc~0); 671584#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 671577#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 671571#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 671564#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 671557#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 671551#L855-45 assume 1 == ~t12_pc~0; 671542#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 671535#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 671529#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 671522#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 671517#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 671510#L874-45 assume !(1 == ~t13_pc~0); 671503#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 671497#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 671488#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 671479#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 671470#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 671461#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 671455#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 671449#L1436-3 assume !(1 == ~T3_E~0); 671443#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 671434#L1446-3 assume !(1 == ~T5_E~0); 671425#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 671417#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 671409#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 671403#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 671395#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 671386#L1476-3 assume !(1 == ~T11_E~0); 671378#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 671370#L1486-3 assume !(1 == ~T13_E~0); 671362#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 671353#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 671345#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 671337#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 671331#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 671324#L1516-3 assume !(1 == ~E_5~0); 671318#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 671313#L1526-3 assume !(1 == ~E_7~0); 671307#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 671301#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 671295#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 671290#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 671287#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 671286#L1556-3 assume !(1 == ~E_13~0); 671285#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 671275#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 671267#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 671265#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 671262#L1946 assume !(0 == start_simulation_~tmp~3); 671258#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 671053#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 671039#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 671029#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 671021#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 671012#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 670805#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 670764#L1959 assume !(0 != start_simulation_~tmp___0~1); 604391#L1927-1 [2021-11-02 23:09:10,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:10,547 INFO L85 PathProgramCache]: Analyzing trace with hash -2072059528, now seen corresponding path program 1 times [2021-11-02 23:09:10,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:10,547 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609729191] [2021-11-02 23:09:10,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:10,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:10,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:10,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:10,639 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:10,639 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609729191] [2021-11-02 23:09:10,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609729191] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:10,640 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:10,640 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:10,640 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213440072] [2021-11-02 23:09:10,641 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:10,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:10,642 INFO L85 PathProgramCache]: Analyzing trace with hash -374288156, now seen corresponding path program 1 times [2021-11-02 23:09:10,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:10,642 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773572054] [2021-11-02 23:09:10,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:10,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:10,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:10,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:10,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:10,691 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773572054] [2021-11-02 23:09:10,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773572054] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:10,691 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:10,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:10,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140645244] [2021-11-02 23:09:10,692 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:10,693 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:10,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-02 23:09:10,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-02 23:09:10,694 INFO L87 Difference]: Start difference. First operand 99499 states and 139065 transitions. cyclomatic complexity: 39570 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:11,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:11,985 INFO L93 Difference]: Finished difference Result 240058 states and 333606 transitions. [2021-11-02 23:09:11,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-02 23:09:11,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240058 states and 333606 transitions. [2021-11-02 23:09:13,958 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 236256 [2021-11-02 23:09:14,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240058 states to 240058 states and 333606 transitions. [2021-11-02 23:09:14,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 240058 [2021-11-02 23:09:14,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 240058 [2021-11-02 23:09:14,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 240058 states and 333606 transitions. [2021-11-02 23:09:14,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:09:14,894 INFO L681 BuchiCegarLoop]: Abstraction has 240058 states and 333606 transitions. [2021-11-02 23:09:15,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240058 states and 333606 transitions. [2021-11-02 23:09:17,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240058 to 191402. [2021-11-02 23:09:17,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3932874264636732) internal successors, (266678), 191401 states have internal predecessors, (266678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:17,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 266678 transitions. [2021-11-02 23:09:17,823 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 266678 transitions. [2021-11-02 23:09:17,823 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 266678 transitions. [2021-11-02 23:09:17,823 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-02 23:09:17,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 266678 transitions. [2021-11-02 23:09:19,321 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-02 23:09:19,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:19,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:19,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:19,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:19,339 INFO L791 eck$LassoCheckResult]: Stem: 944322#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 944323#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 945697#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 945506#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 944486#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 944278#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 944279#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 944049#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 944050#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 944488#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 944695#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 944874#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 944897#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 944057#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 944058#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 943783#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 943784#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 944228#L966-1 assume !(0 == ~M_E~0); 944229#L1278-1 assume !(0 == ~T1_E~0); 945271#L1283-1 assume !(0 == ~T2_E~0); 945272#L1288-1 assume !(0 == ~T3_E~0); 945571#L1293-1 assume !(0 == ~T4_E~0); 945548#L1298-1 assume !(0 == ~T5_E~0); 945448#L1303-1 assume !(0 == ~T6_E~0); 943881#L1308-1 assume !(0 == ~T7_E~0); 943806#L1313-1 assume !(0 == ~T8_E~0); 943807#L1318-1 assume !(0 == ~T9_E~0); 943810#L1323-1 assume !(0 == ~T10_E~0); 943811#L1328-1 assume !(0 == ~T11_E~0); 943995#L1333-1 assume !(0 == ~T12_E~0); 945036#L1338-1 assume !(0 == ~T13_E~0); 945037#L1343-1 assume !(0 == ~E_M~0); 945216#L1348-1 assume !(0 == ~E_1~0); 945629#L1353-1 assume !(0 == ~E_2~0); 944740#L1358-1 assume !(0 == ~E_3~0); 944741#L1363-1 assume !(0 == ~E_4~0); 945077#L1368-1 assume !(0 == ~E_5~0); 943637#L1373-1 assume !(0 == ~E_6~0); 943638#L1378-1 assume !(0 == ~E_7~0); 943949#L1383-1 assume !(0 == ~E_8~0); 943950#L1388-1 assume !(0 == ~E_9~0); 945128#L1393-1 assume !(0 == ~E_10~0); 945129#L1398-1 assume !(0 == ~E_11~0); 945136#L1403-1 assume !(0 == ~E_12~0); 945446#L1408-1 assume !(0 == ~E_13~0); 943919#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 943920#L627 assume !(1 == ~m_pc~0); 945082#L627-2 is_master_triggered_~__retres1~0 := 0; 944282#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 944283#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 944923#L1590 assume !(0 != activate_threads_~tmp~1); 945494#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 943851#L646 assume !(1 == ~t1_pc~0); 943852#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 945427#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 945726#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 945352#L1598 assume !(0 != activate_threads_~tmp___0~0); 943723#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 943724#L665 assume !(1 == ~t2_pc~0); 944400#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 944401#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 943937#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 943938#L1606 assume !(0 != activate_threads_~tmp___1~0); 944513#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 944836#L684 assume !(1 == ~t3_pc~0); 944795#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 944796#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 944876#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 945592#L1614 assume !(0 != activate_threads_~tmp___2~0); 945667#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 945637#L703 assume !(1 == ~t4_pc~0); 944077#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 944078#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 944731#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 944170#L1622 assume !(0 != activate_threads_~tmp___3~0); 944171#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 945358#L722 assume !(1 == ~t5_pc~0); 944128#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 944129#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 944498#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 943463#L1630 assume !(0 != activate_threads_~tmp___4~0); 943464#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 943672#L741 assume !(1 == ~t6_pc~0); 943673#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 944790#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 944127#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 943789#L1638 assume !(0 != activate_threads_~tmp___5~0); 943790#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 944100#L760 assume !(1 == ~t7_pc~0); 944215#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 944692#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 943932#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 943933#L1646 assume !(0 != activate_threads_~tmp___6~0); 944310#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 944311#L779 assume !(1 == ~t8_pc~0); 943715#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 945512#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 943970#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 943971#L1654 assume !(0 != activate_threads_~tmp___7~0); 944783#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 944784#L798 assume !(1 == ~t9_pc~0); 945591#L798-2 is_transmit9_triggered_~__retres1~9 := 0; 945310#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 943716#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 943717#L1662 assume !(0 != activate_threads_~tmp___8~0); 943504#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 943505#L817 assume !(1 == ~t10_pc~0); 943551#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 944331#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 944332#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 943791#L1670 assume !(0 != activate_threads_~tmp___9~0); 943792#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 944732#L836 assume !(1 == ~t11_pc~0); 943965#L836-2 is_transmit11_triggered_~__retres1~11 := 0; 943889#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 943890#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 943854#L1678 assume !(0 != activate_threads_~tmp___10~0); 943855#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 945325#L855 assume !(1 == ~t12_pc~0); 944540#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 944541#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 945179#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 945210#L1686 assume !(0 != activate_threads_~tmp___11~0); 945135#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 943840#L874 assume !(1 == ~t13_pc~0); 943842#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 944005#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 944006#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 944130#L1694 assume !(0 != activate_threads_~tmp___12~0); 945291#L1694-2 assume !(1 == ~M_E~0); 944047#L1426-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 944048#L1431-1 assume !(1 == ~T2_E~0); 943570#L1436-1 assume !(1 == ~T3_E~0); 943571#L1441-1 assume !(1 == ~T4_E~0); 944362#L1446-1 assume !(1 == ~T5_E~0); 944363#L1451-1 assume !(1 == ~T6_E~0); 945214#L1456-1 assume !(1 == ~T7_E~0); 944777#L1461-1 assume !(1 == ~T8_E~0); 944272#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 944273#L1471-1 assume !(1 == ~T10_E~0); 945180#L1476-1 assume !(1 == ~T11_E~0); 945181#L1481-1 assume !(1 == ~T12_E~0); 945390#L1486-1 assume !(1 == ~T13_E~0); 943893#L1491-1 assume !(1 == ~E_M~0); 943513#L1496-1 assume !(1 == ~E_1~0); 943514#L1501-1 assume !(1 == ~E_2~0); 944358#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 944359#L1511-1 assume !(1 == ~E_4~0); 944309#L1516-1 assume !(1 == ~E_5~0); 943467#L1521-1 assume !(1 == ~E_6~0); 943468#L1526-1 assume !(1 == ~E_7~0); 943512#L1531-1 assume !(1 == ~E_8~0); 944068#L1536-1 assume !(1 == ~E_9~0); 943785#L1541-1 assume !(1 == ~E_10~0); 943786#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 945464#L1551-1 assume !(1 == ~E_12~0); 943954#L1556-1 assume !(1 == ~E_13~0); 943955#L1927-1 [2021-11-02 23:09:19,340 INFO L793 eck$LassoCheckResult]: Loop: 943955#L1927-1 assume !false; 1033034#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1033030#L1253 assume !false; 1033029#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1033020#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1033014#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1033013#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1033011#L1066 assume !(0 != eval_~tmp~0); 1033012#L1268 start_simulation_~kernel_st~0 := 2; 1037635#L894-1 start_simulation_~kernel_st~0 := 3; 1037605#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1037588#L1278-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1037585#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1037582#L1288-3 assume !(0 == ~T3_E~0); 1037581#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1037578#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1037575#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1037570#L1308-3 assume !(0 == ~T7_E~0); 1037566#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1037562#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1037556#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1037552#L1328-3 assume !(0 == ~T11_E~0); 1037548#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1037543#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1037539#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1037535#L1348-3 assume !(0 == ~E_1~0); 1037531#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1037527#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1037523#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1037520#L1368-3 assume !(0 == ~E_5~0); 1037516#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1037509#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1037505#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1037501#L1388-3 assume !(0 == ~E_9~0); 1037497#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1037492#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1037488#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1037484#L1408-3 assume !(0 == ~E_13~0); 1037479#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1037476#L627-45 assume !(1 == ~m_pc~0); 1037473#L627-47 is_master_triggered_~__retres1~0 := 0; 1037471#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1037469#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1037467#L1590-45 assume !(0 != activate_threads_~tmp~1); 1037459#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1037455#L646-45 assume !(1 == ~t1_pc~0); 1037452#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 1037448#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1037444#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1037440#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 1037436#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1037433#L665-45 assume !(1 == ~t2_pc~0); 1036952#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 1037426#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1037382#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1037379#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1037377#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1037375#L684-45 assume !(1 == ~t3_pc~0); 1037374#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 1037371#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1037369#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1037367#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1037361#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1037356#L703-45 assume !(1 == ~t4_pc~0); 1037349#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 1037345#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1037340#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1037334#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1037328#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1037323#L722-45 assume !(1 == ~t5_pc~0); 1037317#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 1037311#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1037305#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1037300#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1037294#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1037286#L741-45 assume !(1 == ~t6_pc~0); 1032011#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 1037274#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1037268#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1037262#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1037252#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1033243#L760-45 assume !(1 == ~t7_pc~0); 1033241#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 1033239#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1033237#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1033235#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1033233#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1033232#L779-45 assume 1 == ~t8_pc~0; 1033231#L780-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1033229#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1033227#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1033224#L1654-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1033223#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1033222#L798-45 assume !(1 == ~t9_pc~0); 1025430#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 1033221#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1033220#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1033218#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 1033217#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1033216#L817-45 assume !(1 == ~t10_pc~0); 1033215#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 1033213#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1033211#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1033210#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1033209#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1033208#L836-45 assume !(1 == ~t11_pc~0); 981441#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 1033206#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1033205#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1033204#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1033203#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1033201#L855-45 assume !(1 == ~t12_pc~0); 1033199#L855-47 is_transmit12_triggered_~__retres1~12 := 0; 1033196#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1033194#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1033192#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1033190#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1033186#L874-45 assume !(1 == ~t13_pc~0); 1033182#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 1033180#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1033178#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1033176#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1033173#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1033171#L1426-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1033169#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1033168#L1436-3 assume !(1 == ~T3_E~0); 1033166#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1033164#L1446-3 assume !(1 == ~T5_E~0); 1033162#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1033160#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1033158#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1033156#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1033154#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1033152#L1476-3 assume !(1 == ~T11_E~0); 1033150#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1033148#L1486-3 assume !(1 == ~T13_E~0); 1033144#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1033142#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1033140#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1033138#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1033135#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1033133#L1516-3 assume !(1 == ~E_5~0); 1033131#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1033129#L1526-3 assume !(1 == ~E_7~0); 1033127#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1033125#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1033123#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1033119#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1033117#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1033115#L1556-3 assume !(1 == ~E_13~0); 1033113#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1033093#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1033085#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1033083#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1033080#L1946 assume !(0 == start_simulation_~tmp~3); 1033077#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1033058#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1033049#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1033047#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1033045#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1033043#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 1033041#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1033040#L1959 assume !(0 != start_simulation_~tmp___0~1); 943955#L1927-1 [2021-11-02 23:09:19,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:19,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1349430073, now seen corresponding path program 1 times [2021-11-02 23:09:19,341 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:19,341 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142904896] [2021-11-02 23:09:19,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:19,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:19,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:19,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:19,403 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:19,403 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142904896] [2021-11-02 23:09:19,403 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142904896] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:19,403 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:19,404 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:09:19,404 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318195953] [2021-11-02 23:09:19,404 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:19,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:19,405 INFO L85 PathProgramCache]: Analyzing trace with hash -49615231, now seen corresponding path program 1 times [2021-11-02 23:09:19,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:19,405 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594008065] [2021-11-02 23:09:19,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:19,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:19,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:19,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:19,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:19,452 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594008065] [2021-11-02 23:09:19,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594008065] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:19,452 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:19,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:19,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360553262] [2021-11-02 23:09:19,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:19,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:19,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:09:19,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:09:19,454 INFO L87 Difference]: Start difference. First operand 191402 states and 266678 transitions. cyclomatic complexity: 75280 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:20,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:20,144 INFO L93 Difference]: Finished difference Result 191402 states and 266292 transitions. [2021-11-02 23:09:20,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:09:20,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 266292 transitions. [2021-11-02 23:09:21,877 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-02 23:09:22,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191402 states to 191402 states and 266292 transitions. [2021-11-02 23:09:22,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191402 [2021-11-02 23:09:22,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191402 [2021-11-02 23:09:22,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191402 states and 266292 transitions. [2021-11-02 23:09:22,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:09:22,601 INFO L681 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-02 23:09:22,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191402 states and 266292 transitions. [2021-11-02 23:09:24,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191402 to 191402. [2021-11-02 23:09:24,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3912707286235253) internal successors, (266292), 191401 states have internal predecessors, (266292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:26,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 266292 transitions. [2021-11-02 23:09:26,210 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-02 23:09:26,210 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-02 23:09:26,210 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-02 23:09:26,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 266292 transitions. [2021-11-02 23:09:26,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-02 23:09:26,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:26,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:26,866 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:26,867 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:26,867 INFO L791 eck$LassoCheckResult]: Stem: 1327147#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1327148#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1328582#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1328379#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 1327313#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1327104#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1327105#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1326861#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1326862#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1327318#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1327523#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1327707#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1327730#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1326870#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1326871#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1326595#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1326596#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1327053#L966-1 assume !(0 == ~M_E~0); 1327054#L1278-1 assume !(0 == ~T1_E~0); 1328127#L1283-1 assume !(0 == ~T2_E~0); 1328128#L1288-1 assume !(0 == ~T3_E~0); 1328450#L1293-1 assume !(0 == ~T4_E~0); 1328427#L1298-1 assume !(0 == ~T5_E~0); 1328316#L1303-1 assume !(0 == ~T6_E~0); 1326693#L1308-1 assume !(0 == ~T7_E~0); 1326618#L1313-1 assume !(0 == ~T8_E~0); 1326619#L1318-1 assume !(0 == ~T9_E~0); 1326621#L1323-1 assume !(0 == ~T10_E~0); 1326622#L1328-1 assume !(0 == ~T11_E~0); 1326807#L1333-1 assume !(0 == ~T12_E~0); 1327877#L1338-1 assume !(0 == ~T13_E~0); 1327878#L1343-1 assume !(0 == ~E_M~0); 1328068#L1348-1 assume !(0 == ~E_1~0); 1328510#L1353-1 assume !(0 == ~E_2~0); 1327572#L1358-1 assume !(0 == ~E_3~0); 1327573#L1363-1 assume !(0 == ~E_4~0); 1327923#L1368-1 assume !(0 == ~E_5~0); 1326448#L1373-1 assume !(0 == ~E_6~0); 1326449#L1378-1 assume !(0 == ~E_7~0); 1326761#L1383-1 assume !(0 == ~E_8~0); 1326762#L1388-1 assume !(0 == ~E_9~0); 1327976#L1393-1 assume !(0 == ~E_10~0); 1327977#L1398-1 assume !(0 == ~E_11~0); 1327985#L1403-1 assume !(0 == ~E_12~0); 1328314#L1408-1 assume !(0 == ~E_13~0); 1326731#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1326732#L627 assume !(1 == ~m_pc~0); 1327926#L627-2 is_master_triggered_~__retres1~0 := 0; 1327110#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1327111#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1327756#L1590 assume !(0 != activate_threads_~tmp~1); 1328365#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1326663#L646 assume !(1 == ~t1_pc~0); 1326664#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 1328291#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1328617#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1328215#L1598 assume !(0 != activate_threads_~tmp___0~0); 1326535#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1326536#L665 assume !(1 == ~t2_pc~0); 1327219#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 1327220#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1326749#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1326750#L1606 assume !(0 != activate_threads_~tmp___1~0); 1327340#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1327667#L684 assume !(1 == ~t3_pc~0); 1327629#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 1327630#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1327711#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1328473#L1614 assume !(0 != activate_threads_~tmp___2~0); 1328556#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1328516#L703 assume !(1 == ~t4_pc~0); 1326893#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 1326894#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1327561#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1326991#L1622 assume !(0 != activate_threads_~tmp___3~0); 1326992#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1328223#L722 assume !(1 == ~t5_pc~0); 1326945#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 1326946#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1327325#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1326273#L1630 assume !(0 != activate_threads_~tmp___4~0); 1326274#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1326484#L741 assume !(1 == ~t6_pc~0); 1326485#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 1327624#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1326944#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1326601#L1638 assume !(0 != activate_threads_~tmp___5~0); 1326602#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1326915#L760 assume !(1 == ~t7_pc~0); 1327038#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 1327520#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1326744#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1326745#L1646 assume !(0 != activate_threads_~tmp___6~0); 1327135#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1327136#L779 assume !(1 == ~t8_pc~0); 1326527#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 1328383#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1326782#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1326783#L1654 assume !(0 != activate_threads_~tmp___7~0); 1327616#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1327617#L798 assume !(1 == ~t9_pc~0); 1328472#L798-2 is_transmit9_triggered_~__retres1~9 := 0; 1328174#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1326528#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1326529#L1662 assume !(0 != activate_threads_~tmp___8~0); 1326314#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1326315#L817 assume !(1 == ~t10_pc~0); 1326361#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 1327155#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1327156#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1326603#L1670 assume !(0 != activate_threads_~tmp___9~0); 1326604#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1327562#L836 assume !(1 == ~t11_pc~0); 1326777#L836-2 is_transmit11_triggered_~__retres1~11 := 0; 1326701#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1326702#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1326666#L1678 assume !(0 != activate_threads_~tmp___10~0); 1326667#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1328189#L855 assume !(1 == ~t12_pc~0); 1327368#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 1327369#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1328028#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1328062#L1686 assume !(0 != activate_threads_~tmp___11~0); 1327983#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1326652#L874 assume !(1 == ~t13_pc~0); 1326654#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 1326817#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1326818#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1326947#L1694 assume !(0 != activate_threads_~tmp___12~0); 1328153#L1694-2 assume !(1 == ~M_E~0); 1326859#L1426-1 assume !(1 == ~T1_E~0); 1326860#L1431-1 assume !(1 == ~T2_E~0); 1326382#L1436-1 assume !(1 == ~T3_E~0); 1326383#L1441-1 assume !(1 == ~T4_E~0); 1327185#L1446-1 assume !(1 == ~T5_E~0); 1327186#L1451-1 assume !(1 == ~T6_E~0); 1328066#L1456-1 assume !(1 == ~T7_E~0); 1327610#L1461-1 assume !(1 == ~T8_E~0); 1327098#L1466-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1327099#L1471-1 assume !(1 == ~T10_E~0); 1328029#L1476-1 assume !(1 == ~T11_E~0); 1328030#L1481-1 assume !(1 == ~T12_E~0); 1328258#L1486-1 assume !(1 == ~T13_E~0); 1326705#L1491-1 assume !(1 == ~E_M~0); 1326323#L1496-1 assume !(1 == ~E_1~0); 1326324#L1501-1 assume !(1 == ~E_2~0); 1327181#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1327182#L1511-1 assume !(1 == ~E_4~0); 1327134#L1516-1 assume !(1 == ~E_5~0); 1326277#L1521-1 assume !(1 == ~E_6~0); 1326278#L1526-1 assume !(1 == ~E_7~0); 1326322#L1531-1 assume !(1 == ~E_8~0); 1326884#L1536-1 assume !(1 == ~E_9~0); 1326597#L1541-1 assume !(1 == ~E_10~0); 1326598#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1328331#L1551-1 assume !(1 == ~E_12~0); 1326767#L1556-1 assume !(1 == ~E_13~0); 1326510#L1927-1 [2021-11-02 23:09:26,868 INFO L793 eck$LassoCheckResult]: Loop: 1326510#L1927-1 assume !false; 1326793#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1326806#L1253 assume !false; 1326265#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1326266#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1326953#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1326878#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1326879#L1066 assume !(0 != eval_~tmp~0); 1328514#L1268 start_simulation_~kernel_st~0 := 2; 1510886#L894-1 start_simulation_~kernel_st~0 := 3; 1510885#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1510884#L1278-4 assume !(0 == ~T1_E~0); 1510883#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1510881#L1288-3 assume !(0 == ~T3_E~0); 1510878#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1510876#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1510874#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1510872#L1308-3 assume !(0 == ~T7_E~0); 1510870#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1510866#L1318-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1510864#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1510862#L1328-3 assume !(0 == ~T11_E~0); 1510860#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1510857#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1510855#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1510853#L1348-3 assume !(0 == ~E_1~0); 1510852#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1510850#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1510848#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1510846#L1368-3 assume !(0 == ~E_5~0); 1510844#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1510842#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1510839#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1510837#L1388-3 assume !(0 == ~E_9~0); 1510835#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1510833#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1510831#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1510829#L1408-3 assume !(0 == ~E_13~0); 1510827#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1510825#L627-45 assume !(1 == ~m_pc~0); 1510823#L627-47 is_master_triggered_~__retres1~0 := 0; 1510821#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1510819#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1510816#L1590-45 assume !(0 != activate_threads_~tmp~1); 1510814#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1510812#L646-45 assume !(1 == ~t1_pc~0); 1510810#L646-47 is_transmit1_triggered_~__retres1~1 := 0; 1512918#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1512916#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1510766#L1598-45 assume !(0 != activate_threads_~tmp___0~0); 1510763#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1495259#L665-45 assume !(1 == ~t2_pc~0); 1495257#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 1495255#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1495254#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1495252#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1495250#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1495248#L684-45 assume !(1 == ~t3_pc~0); 1495246#L684-47 is_transmit3_triggered_~__retres1~3 := 0; 1495241#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1495239#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1495237#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1495235#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1495232#L703-45 assume !(1 == ~t4_pc~0); 1495230#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 1495228#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1495227#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1495226#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1495225#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1495223#L722-45 assume !(1 == ~t5_pc~0); 1495221#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 1495220#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1495218#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1495217#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1495216#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1495215#L741-45 assume !(1 == ~t6_pc~0); 1495214#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 1495213#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1495212#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1495211#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1495210#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1495209#L760-45 assume !(1 == ~t7_pc~0); 1480399#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 1495204#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1495202#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1495199#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1495197#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1495195#L779-45 assume !(1 == ~t8_pc~0); 1495191#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 1495189#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1495185#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1495183#L1654-45 assume !(0 != activate_threads_~tmp___7~0); 1495180#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1495178#L798-45 assume !(1 == ~t9_pc~0); 1474152#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 1495171#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1495169#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1495166#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 1495164#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1495162#L817-45 assume 1 == ~t10_pc~0; 1495159#L818-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1495157#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1495155#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1495152#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1326940#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1326941#L836-45 assume !(1 == ~t11_pc~0); 1326446#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 1326447#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1327227#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1327228#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1327782#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1327882#L855-45 assume 1 == ~t12_pc~0; 1327175#L856-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1326607#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1326608#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1327598#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1327599#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1327279#L874-45 assume !(1 == ~t13_pc~0); 1327280#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 1327179#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1327180#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1326753#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1326754#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1327604#L1426-3 assume !(1 == ~T1_E~0); 1326706#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1326707#L1436-3 assume !(1 == ~T3_E~0); 1326281#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1326282#L1446-3 assume !(1 == ~T5_E~0); 1328103#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1327269#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1326865#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1326866#L1466-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1328479#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1326815#L1476-3 assume !(1 == ~T11_E~0); 1326816#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1327237#L1486-3 assume !(1 == ~T13_E~0); 1326832#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1326833#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1327308#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1327309#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1327786#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1327777#L1516-3 assume !(1 == ~E_5~0); 1327778#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1327440#L1526-3 assume !(1 == ~E_7~0); 1327441#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1327872#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1326851#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1326852#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1326892#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1328386#L1556-3 assume !(1 == ~E_13~0); 1326427#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1326428#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1326533#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1328039#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1327832#L1946 assume !(0 == start_simulation_~tmp~3); 1327512#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1327513#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1326773#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1328424#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1327950#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1326260#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 1326261#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1326509#L1959 assume !(0 != start_simulation_~tmp___0~1); 1326510#L1927-1 [2021-11-02 23:09:26,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:26,869 INFO L85 PathProgramCache]: Analyzing trace with hash -1022309189, now seen corresponding path program 1 times [2021-11-02 23:09:26,869 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:26,869 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652350381] [2021-11-02 23:09:26,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:26,870 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:26,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:26,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:26,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:26,922 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652350381] [2021-11-02 23:09:26,922 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652350381] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:26,922 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:26,922 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:09:26,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338542837] [2021-11-02 23:09:26,923 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:26,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:26,924 INFO L85 PathProgramCache]: Analyzing trace with hash 625579548, now seen corresponding path program 1 times [2021-11-02 23:09:26,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:26,924 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330840038] [2021-11-02 23:09:26,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:26,925 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:26,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:26,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:26,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:26,967 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330840038] [2021-11-02 23:09:26,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330840038] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:26,967 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:26,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:26,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221691143] [2021-11-02 23:09:26,968 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:26,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:26,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:09:26,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:09:26,969 INFO L87 Difference]: Start difference. First operand 191402 states and 266292 transitions. cyclomatic complexity: 74894 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:27,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:27,585 INFO L93 Difference]: Finished difference Result 191402 states and 265906 transitions. [2021-11-02 23:09:27,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:09:27,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 265906 transitions. [2021-11-02 23:09:29,471 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-02 23:09:30,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191402 states to 191402 states and 265906 transitions. [2021-11-02 23:09:30,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191402 [2021-11-02 23:09:30,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191402 [2021-11-02 23:09:30,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191402 states and 265906 transitions. [2021-11-02 23:09:30,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-02 23:09:30,265 INFO L681 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-02 23:09:30,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191402 states and 265906 transitions. [2021-11-02 23:09:32,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191402 to 191402. [2021-11-02 23:09:32,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3892540307833774) internal successors, (265906), 191401 states have internal predecessors, (265906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:33,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 265906 transitions. [2021-11-02 23:09:33,830 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-02 23:09:33,830 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-02 23:09:33,830 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-02 23:09:33,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 265906 transitions. [2021-11-02 23:09:34,385 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-02 23:09:34,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-02 23:09:34,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-02 23:09:34,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:34,393 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-02 23:09:34,393 INFO L791 eck$LassoCheckResult]: Stem: 1709952#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1709953#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1711423#L1890 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1711212#L894 assume 1 == ~m_i~0;~m_st~0 := 0; 1710119#L901-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1709908#L906-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1709909#L911-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1709670#L916-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1709671#L921-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1710127#L926-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1710332#L931-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1710520#L936-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1710543#L941-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1709680#L946-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1709681#L951-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1709406#L956-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1709407#L961-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1709856#L966-1 assume !(0 == ~M_E~0); 1709857#L1278-1 assume !(0 == ~T1_E~0); 1710935#L1283-1 assume !(0 == ~T2_E~0); 1710936#L1288-1 assume !(0 == ~T3_E~0); 1711294#L1293-1 assume !(0 == ~T4_E~0); 1711266#L1298-1 assume !(0 == ~T5_E~0); 1711144#L1303-1 assume !(0 == ~T6_E~0); 1709505#L1308-1 assume !(0 == ~T7_E~0); 1709429#L1313-1 assume !(0 == ~T8_E~0); 1709430#L1318-1 assume !(0 == ~T9_E~0); 1709434#L1323-1 assume !(0 == ~T10_E~0); 1709435#L1328-1 assume !(0 == ~T11_E~0); 1709615#L1333-1 assume !(0 == ~T12_E~0); 1710687#L1338-1 assume !(0 == ~T13_E~0); 1710688#L1343-1 assume !(0 == ~E_M~0); 1710875#L1348-1 assume !(0 == ~E_1~0); 1711355#L1353-1 assume !(0 == ~E_2~0); 1710382#L1358-1 assume !(0 == ~E_3~0); 1710383#L1363-1 assume !(0 == ~E_4~0); 1710730#L1368-1 assume !(0 == ~E_5~0); 1709259#L1373-1 assume !(0 == ~E_6~0); 1709260#L1378-1 assume !(0 == ~E_7~0); 1709570#L1383-1 assume !(0 == ~E_8~0); 1709571#L1388-1 assume !(0 == ~E_9~0); 1710781#L1393-1 assume !(0 == ~E_10~0); 1710782#L1398-1 assume !(0 == ~E_11~0); 1710790#L1403-1 assume !(0 == ~E_12~0); 1711140#L1408-1 assume !(0 == ~E_13~0); 1709541#L1413-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1709542#L627 assume !(1 == ~m_pc~0); 1710733#L627-2 is_master_triggered_~__retres1~0 := 0; 1709916#L638 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1709917#L639 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1710568#L1590 assume !(0 != activate_threads_~tmp~1); 1711202#L1590-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1709479#L646 assume !(1 == ~t1_pc~0); 1709480#L646-2 is_transmit1_triggered_~__retres1~1 := 0; 1711115#L657 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1711456#L658 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1711027#L1598 assume !(0 != activate_threads_~tmp___0~0); 1709345#L1598-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1709346#L665 assume !(1 == ~t2_pc~0); 1710024#L665-2 is_transmit2_triggered_~__retres1~2 := 0; 1710025#L676 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1709558#L677 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1709559#L1606 assume !(0 != activate_threads_~tmp___1~0); 1710145#L1606-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1710478#L684 assume !(1 == ~t3_pc~0); 1710437#L684-2 is_transmit3_triggered_~__retres1~3 := 0; 1710438#L695 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1710522#L696 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1711315#L1614 assume !(0 != activate_threads_~tmp___2~0); 1711396#L1614-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1711361#L703 assume !(1 == ~t4_pc~0); 1709700#L703-2 is_transmit4_triggered_~__retres1~4 := 0; 1709701#L714 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1710369#L715 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1709795#L1622 assume !(0 != activate_threads_~tmp___3~0); 1709796#L1622-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1711035#L722 assume !(1 == ~t5_pc~0); 1709750#L722-2 is_transmit5_triggered_~__retres1~5 := 0; 1709751#L733 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1710130#L734 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1709087#L1630 assume !(0 != activate_threads_~tmp___4~0); 1709088#L1630-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1709295#L741 assume !(1 == ~t6_pc~0); 1709296#L741-2 is_transmit6_triggered_~__retres1~6 := 0; 1710432#L752 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1709749#L753 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1709412#L1638 assume !(0 != activate_threads_~tmp___5~0); 1709413#L1638-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1709722#L760 assume !(1 == ~t7_pc~0); 1709842#L760-2 is_transmit7_triggered_~__retres1~7 := 0; 1710331#L771 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1709556#L772 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1709557#L1646 assume !(0 != activate_threads_~tmp___6~0); 1709940#L1646-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1709941#L779 assume !(1 == ~t8_pc~0); 1709337#L779-2 is_transmit8_triggered_~__retres1~8 := 0; 1711218#L790 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1709589#L791 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1709590#L1654 assume !(0 != activate_threads_~tmp___7~0); 1710424#L1654-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1710425#L798 assume !(1 == ~t9_pc~0); 1711314#L798-2 is_transmit9_triggered_~__retres1~9 := 0; 1710980#L809 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1709338#L810 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1709339#L1662 assume !(0 != activate_threads_~tmp___8~0); 1709126#L1662-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1709127#L817 assume !(1 == ~t10_pc~0); 1709173#L817-2 is_transmit10_triggered_~__retres1~10 := 0; 1709960#L828 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1709961#L829 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1709414#L1670 assume !(0 != activate_threads_~tmp___9~0); 1709415#L1670-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1710370#L836 assume !(1 == ~t11_pc~0); 1709586#L836-2 is_transmit11_triggered_~__retres1~11 := 0; 1709511#L847 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1709512#L848 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1709482#L1678 assume !(0 != activate_threads_~tmp___10~0); 1709483#L1678-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1710996#L855 assume !(1 == ~t12_pc~0); 1710172#L855-2 is_transmit12_triggered_~__retres1~12 := 0; 1710173#L866 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1710836#L867 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1710872#L1686 assume !(0 != activate_threads_~tmp___11~0); 1710789#L1686-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1709464#L874 assume !(1 == ~t13_pc~0); 1709466#L874-2 is_transmit13_triggered_~__retres1~13 := 0; 1709625#L885 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1709626#L886 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1709752#L1694 assume !(0 != activate_threads_~tmp___12~0); 1710960#L1694-2 assume !(1 == ~M_E~0); 1709668#L1426-1 assume !(1 == ~T1_E~0); 1709669#L1431-1 assume !(1 == ~T2_E~0); 1709196#L1436-1 assume !(1 == ~T3_E~0); 1709197#L1441-1 assume !(1 == ~T4_E~0); 1709990#L1446-1 assume !(1 == ~T5_E~0); 1709991#L1451-1 assume !(1 == ~T6_E~0); 1710873#L1456-1 assume !(1 == ~T7_E~0); 1710416#L1461-1 assume !(1 == ~T8_E~0); 1709902#L1466-1 assume !(1 == ~T9_E~0); 1709903#L1471-1 assume !(1 == ~T10_E~0); 1710837#L1476-1 assume !(1 == ~T11_E~0); 1710838#L1481-1 assume !(1 == ~T12_E~0); 1711075#L1486-1 assume !(1 == ~T13_E~0); 1709515#L1491-1 assume !(1 == ~E_M~0); 1709135#L1496-1 assume !(1 == ~E_1~0); 1709136#L1501-1 assume !(1 == ~E_2~0); 1709986#L1506-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1709987#L1511-1 assume !(1 == ~E_4~0); 1709939#L1516-1 assume !(1 == ~E_5~0); 1709091#L1521-1 assume !(1 == ~E_6~0); 1709092#L1526-1 assume !(1 == ~E_7~0); 1709134#L1531-1 assume !(1 == ~E_8~0); 1709691#L1536-1 assume !(1 == ~E_9~0); 1709408#L1541-1 assume !(1 == ~E_10~0); 1709409#L1546-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1711161#L1551-1 assume !(1 == ~E_12~0); 1709575#L1556-1 assume !(1 == ~E_13~0); 1709576#L1927-1 [2021-11-02 23:09:34,393 INFO L793 eck$LassoCheckResult]: Loop: 1709576#L1927-1 assume !false; 1778904#L1928 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1778900#L1253 assume !false; 1778898#L1062 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1778873#L979 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1778866#L1051 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1778864#L1052 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1778860#L1066 assume !(0 != eval_~tmp~0); 1778861#L1268 start_simulation_~kernel_st~0 := 2; 1897224#L894-1 start_simulation_~kernel_st~0 := 3; 1897223#L1278-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1896477#L1278-4 assume !(0 == ~T1_E~0); 1896476#L1283-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1896475#L1288-3 assume !(0 == ~T3_E~0); 1894437#L1293-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1886134#L1298-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1886133#L1303-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1886132#L1308-3 assume !(0 == ~T7_E~0); 1886130#L1313-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1886128#L1318-3 assume !(0 == ~T9_E~0); 1886126#L1323-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1886124#L1328-3 assume !(0 == ~T11_E~0); 1886123#L1333-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1886122#L1338-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1886121#L1343-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1886120#L1348-3 assume !(0 == ~E_1~0); 1886119#L1353-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1886117#L1358-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1886116#L1363-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1886115#L1368-3 assume !(0 == ~E_5~0); 1886114#L1373-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1886112#L1378-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1886111#L1383-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1886110#L1388-3 assume !(0 == ~E_9~0); 1886109#L1393-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1886108#L1398-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1886106#L1403-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1886104#L1408-3 assume !(0 == ~E_13~0); 1886102#L1413-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1886100#L627-45 assume !(1 == ~m_pc~0); 1886098#L627-47 is_master_triggered_~__retres1~0 := 0; 1886096#L638-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1886093#L639-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1886091#L1590-45 assume !(0 != activate_threads_~tmp~1); 1886089#L1590-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1886087#L646-45 assume 1 == ~t1_pc~0; 1886085#L647-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1886086#L657-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1886113#L658-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1886076#L1598-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1886074#L1598-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1886070#L665-45 assume !(1 == ~t2_pc~0); 1882702#L665-47 is_transmit2_triggered_~__retres1~2 := 0; 1886067#L676-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1886065#L677-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1886062#L1606-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1886060#L1606-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1886058#L684-45 assume 1 == ~t3_pc~0; 1886054#L685-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1886052#L695-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1886050#L696-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1886048#L1614-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1886046#L1614-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1886044#L703-45 assume !(1 == ~t4_pc~0); 1886041#L703-47 is_transmit4_triggered_~__retres1~4 := 0; 1886039#L714-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1886037#L715-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1886035#L1622-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1886033#L1622-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1814989#L722-45 assume !(1 == ~t5_pc~0); 1814986#L722-47 is_transmit5_triggered_~__retres1~5 := 0; 1814984#L733-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1814983#L734-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1814981#L1630-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1814979#L1630-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1814977#L741-45 assume !(1 == ~t6_pc~0); 1791289#L741-47 is_transmit6_triggered_~__retres1~6 := 0; 1814974#L752-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1814971#L753-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1814969#L1638-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1814967#L1638-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1814965#L760-45 assume !(1 == ~t7_pc~0); 1784157#L760-47 is_transmit7_triggered_~__retres1~7 := 0; 1814961#L771-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1814959#L772-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1814957#L1646-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1814955#L1646-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1814953#L779-45 assume !(1 == ~t8_pc~0); 1814950#L779-47 is_transmit8_triggered_~__retres1~8 := 0; 1814993#L790-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1814991#L791-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1782970#L1654-45 assume !(0 != activate_threads_~tmp___7~0); 1781188#L1654-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1779189#L798-45 assume !(1 == ~t9_pc~0); 1779187#L798-47 is_transmit9_triggered_~__retres1~9 := 0; 1779184#L809-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1779182#L810-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1779180#L1662-45 assume !(0 != activate_threads_~tmp___8~0); 1779178#L1662-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1779176#L817-45 assume !(1 == ~t10_pc~0); 1779174#L817-47 is_transmit10_triggered_~__retres1~10 := 0; 1779172#L828-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1779170#L829-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1779168#L1670-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1779166#L1670-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1779164#L836-45 assume !(1 == ~t11_pc~0); 1777891#L836-47 is_transmit11_triggered_~__retres1~11 := 0; 1779160#L847-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1779158#L848-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1779156#L1678-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1779154#L1678-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1779152#L855-45 assume !(1 == ~t12_pc~0); 1779149#L855-47 is_transmit12_triggered_~__retres1~12 := 0; 1779146#L866-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1779144#L867-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1779142#L1686-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1779140#L1686-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1779136#L874-45 assume !(1 == ~t13_pc~0); 1779134#L874-47 is_transmit13_triggered_~__retres1~13 := 0; 1779132#L885-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1779130#L886-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1779128#L1694-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1779126#L1694-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1779124#L1426-3 assume !(1 == ~T1_E~0); 1779122#L1431-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1779120#L1436-3 assume !(1 == ~T3_E~0); 1779118#L1441-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1779116#L1446-3 assume !(1 == ~T5_E~0); 1779114#L1451-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1779112#L1456-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1779110#L1461-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1779108#L1466-3 assume !(1 == ~T9_E~0); 1779106#L1471-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1779104#L1476-3 assume !(1 == ~T11_E~0); 1779102#L1481-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1779100#L1486-3 assume !(1 == ~T13_E~0); 1779098#L1491-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1779096#L1496-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1779094#L1501-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1779092#L1506-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1779090#L1511-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1779088#L1516-3 assume !(1 == ~E_5~0); 1779086#L1521-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1779085#L1526-3 assume !(1 == ~E_7~0); 1779084#L1531-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1779083#L1536-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1779082#L1541-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1779081#L1546-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1779079#L1551-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1779077#L1556-3 assume !(1 == ~E_13~0); 1779075#L1561-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1779055#L979-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1779047#L1051-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1779045#L1052-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1779042#L1946 assume !(0 == start_simulation_~tmp~3); 1779039#L1946-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1779019#L979-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1779011#L1051-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1779008#L1052-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1779006#L1901 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1779004#L1908 stop_simulation_#res := stop_simulation_~__retres2~0; 1779002#L1909 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1779001#L1959 assume !(0 != start_simulation_~tmp___0~1); 1709576#L1927-1 [2021-11-02 23:09:34,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:34,394 INFO L85 PathProgramCache]: Analyzing trace with hash 1583714365, now seen corresponding path program 1 times [2021-11-02 23:09:34,394 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:34,394 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139598534] [2021-11-02 23:09:34,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:34,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:34,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:34,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:34,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:34,448 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139598534] [2021-11-02 23:09:34,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139598534] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:34,448 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:34,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-02 23:09:34,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031262375] [2021-11-02 23:09:34,449 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-02 23:09:34,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-02 23:09:34,450 INFO L85 PathProgramCache]: Analyzing trace with hash -203976742, now seen corresponding path program 1 times [2021-11-02 23:09:34,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-02 23:09:34,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62006610] [2021-11-02 23:09:34,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-02 23:09:34,450 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-02 23:09:34,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-02 23:09:34,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-02 23:09:34,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-02 23:09:34,493 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62006610] [2021-11-02 23:09:34,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62006610] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-02 23:09:34,494 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-02 23:09:34,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-02 23:09:34,494 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599731939] [2021-11-02 23:09:34,495 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-02 23:09:34,495 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-02 23:09:34,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-02 23:09:34,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-02 23:09:34,496 INFO L87 Difference]: Start difference. First operand 191402 states and 265906 transitions. cyclomatic complexity: 74508 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-02 23:09:35,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-02 23:09:35,111 INFO L93 Difference]: Finished difference Result 191402 states and 263983 transitions. [2021-11-02 23:09:35,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-02 23:09:35,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 263983 transitions.