./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-15/array12_alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-15/array12_alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 08:31:53,782 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 08:31:53,784 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 08:31:53,815 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 08:31:53,816 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 08:31:53,817 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 08:31:53,819 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 08:31:53,822 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 08:31:53,824 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 08:31:53,826 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 08:31:53,827 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 08:31:53,828 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 08:31:53,829 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 08:31:53,830 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 08:31:53,832 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 08:31:53,834 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 08:31:53,835 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 08:31:53,837 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 08:31:53,839 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 08:31:53,843 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 08:31:53,845 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 08:31:53,847 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 08:31:53,849 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 08:31:53,850 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 08:31:53,855 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 08:31:53,856 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 08:31:53,856 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 08:31:53,858 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 08:31:53,858 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 08:31:53,860 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 08:31:53,860 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 08:31:53,861 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 08:31:53,862 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 08:31:53,863 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 08:31:53,865 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 08:31:53,865 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 08:31:53,866 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 08:31:53,867 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 08:31:53,867 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 08:31:53,868 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 08:31:53,869 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 08:31:53,878 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-11-07 08:31:53,924 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 08:31:53,932 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 08:31:53,933 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 08:31:53,934 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 08:31:53,935 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 08:31:53,936 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 08:31:53,936 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 08:31:53,936 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 08:31:53,937 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 08:31:53,937 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 08:31:53,938 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 08:31:53,938 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 08:31:53,939 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 08:31:53,939 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 08:31:53,939 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 08:31:53,940 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 08:31:53,940 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 08:31:53,940 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 08:31:53,940 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 08:31:53,942 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 08:31:53,942 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 08:31:53,943 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 08:31:53,944 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 08:31:53,944 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 08:31:53,944 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 08:31:53,945 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 08:31:53,947 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 08:31:53,947 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 08:31:53,947 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 08:31:53,949 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 08:31:53,949 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b994a1ec31b8c037535d8c99bc15e7231c0aea3fc6bbd2fe006bfaa61a5800c0 [2021-11-07 08:31:54,214 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 08:31:54,268 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 08:31:54,271 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 08:31:54,274 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 08:31:54,275 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 08:31:54,276 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/termination-15/array12_alloca.i [2021-11-07 08:31:54,366 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/data/7d9a47208/3992cf99e9f94ab98339d8fa19137611/FLAG299e62a16 [2021-11-07 08:31:54,921 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 08:31:54,921 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/sv-benchmarks/c/termination-15/array12_alloca.i [2021-11-07 08:31:54,933 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/data/7d9a47208/3992cf99e9f94ab98339d8fa19137611/FLAG299e62a16 [2021-11-07 08:31:55,229 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/data/7d9a47208/3992cf99e9f94ab98339d8fa19137611 [2021-11-07 08:31:55,232 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 08:31:55,234 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 08:31:55,236 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 08:31:55,236 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 08:31:55,240 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 08:31:55,241 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,242 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c01f567 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55, skipping insertion in model container [2021-11-07 08:31:55,243 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,249 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 08:31:55,292 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 08:31:55,611 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 08:31:55,620 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 08:31:55,702 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 08:31:55,750 INFO L208 MainTranslator]: Completed translation [2021-11-07 08:31:55,751 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55 WrapperNode [2021-11-07 08:31:55,751 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 08:31:55,752 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 08:31:55,753 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 08:31:55,753 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 08:31:55,763 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,793 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,824 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 08:31:55,825 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 08:31:55,825 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 08:31:55,826 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 08:31:55,834 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,835 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,847 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,848 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,855 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,862 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,874 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,878 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 08:31:55,882 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 08:31:55,882 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 08:31:55,883 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 08:31:55,884 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (1/1) ... [2021-11-07 08:31:55,895 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:55,910 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:55,931 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:55,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 08:31:55,984 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-07 08:31:55,984 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-07 08:31:55,984 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 08:31:55,984 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-07 08:31:55,985 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 08:31:55,985 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 08:31:56,195 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 08:31:56,195 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2021-11-07 08:31:56,198 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 08:31:56 BoogieIcfgContainer [2021-11-07 08:31:56,198 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 08:31:56,199 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 08:31:56,199 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 08:31:56,204 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 08:31:56,205 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:31:56,205 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 08:31:55" (1/3) ... [2021-11-07 08:31:56,206 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fc21d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 08:31:56, skipping insertion in model container [2021-11-07 08:31:56,206 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:31:56,206 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:31:55" (2/3) ... [2021-11-07 08:31:56,207 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fc21d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 08:31:56, skipping insertion in model container [2021-11-07 08:31:56,207 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:31:56,207 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 08:31:56" (3/3) ... [2021-11-07 08:31:56,208 INFO L389 chiAutomizerObserver]: Analyzing ICFG array12_alloca.i [2021-11-07 08:31:56,259 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 08:31:56,260 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 08:31:56,260 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 08:31:56,260 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 08:31:56,260 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 08:31:56,260 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 08:31:56,260 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 08:31:56,261 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 08:31:56,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:56,298 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-07 08:31:56,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:31:56,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:31:56,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-07 08:31:56,306 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-07 08:31:56,306 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 08:31:56,306 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:56,309 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-07 08:31:56,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:31:56,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:31:56,310 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2021-11-07 08:31:56,310 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-07 08:31:56,318 INFO L791 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7#L-1true havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 11#L367true assume !(main_~length~0 < 1); 8#L367-2true call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 5#L369true assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 6#L370-3true [2021-11-07 08:31:56,318 INFO L793 eck$LassoCheckResult]: Loop: 6#L370-3true assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13#L372true assume main_#t~mem209 < 0;havoc main_#t~mem209;call write~int(0, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16#L370-2true main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6#L370-3true [2021-11-07 08:31:56,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:56,325 INFO L85 PathProgramCache]: Analyzing trace with hash 28695753, now seen corresponding path program 1 times [2021-11-07 08:31:56,335 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:56,335 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764225274] [2021-11-07 08:31:56,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:56,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:56,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,486 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:56,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,523 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:56,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:56,528 INFO L85 PathProgramCache]: Analyzing trace with hash 51737, now seen corresponding path program 1 times [2021-11-07 08:31:56,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:56,528 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383717601] [2021-11-07 08:31:56,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:56,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:56,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,547 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:56,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,566 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:56,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:56,569 INFO L85 PathProgramCache]: Analyzing trace with hash 176707665, now seen corresponding path program 1 times [2021-11-07 08:31:56,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:56,570 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20188137] [2021-11-07 08:31:56,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:56,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:56,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,599 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:56,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:56,630 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:57,073 INFO L210 LassoAnalysis]: Preferences: [2021-11-07 08:31:57,074 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-07 08:31:57,074 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-07 08:31:57,074 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-07 08:31:57,074 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-07 08:31:57,074 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,074 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-07 08:31:57,075 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-07 08:31:57,075 INFO L133 ssoRankerPreferences]: Filename of dumped script: array12_alloca.i_Iteration1_Lasso [2021-11-07 08:31:57,075 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-07 08:31:57,076 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-07 08:31:57,102 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,113 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,116 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,119 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,131 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,273 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,281 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 08:31:57,501 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-07 08:31:57,507 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-07 08:31:57,509 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,514 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,525 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-07 08:31:57,537 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,537 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:57,538 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,538 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,538 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,541 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:57,541 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:57,557 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,603 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,604 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,606 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,613 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,613 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-07 08:31:57,624 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,624 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:57,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,628 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:57,629 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:57,653 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,694 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,695 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,695 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,697 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,703 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-07 08:31:57,703 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,722 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,722 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:57,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,722 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,723 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:57,723 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:57,735 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,764 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,764 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,764 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,765 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,774 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,785 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,786 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:57,786 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,786 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,786 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,787 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:57,787 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:57,789 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-07 08:31:57,793 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,815 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,816 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,816 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,817 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-07 08:31:57,841 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,849 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,849 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,849 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,849 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,853 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 08:31:57,854 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 08:31:57,868 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,912 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,912 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,912 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,914 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,917 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:57,919 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-07 08:31:57,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:57,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:57,929 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:57,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:57,929 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:57,930 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:57,930 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:57,953 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:57,989 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:57,989 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:57,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:57,991 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:57,994 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:58,004 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:58,004 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:58,004 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:58,005 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:58,011 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 08:31:58,011 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 08:31:58,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-07 08:31:58,033 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:58,058 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-11-07 08:31:58,058 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:58,058 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:58,060 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:58,061 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-11-07 08:31:58,064 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:58,075 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:58,076 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:58,076 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:58,076 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:58,082 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 08:31:58,083 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 08:31:58,096 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:58,136 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2021-11-07 08:31:58,136 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:58,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:58,138 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:58,148 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:58,158 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:58,159 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 08:31:58,159 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:58,159 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:58,159 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:58,160 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 08:31:58,160 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 08:31:58,162 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-11-07 08:31:58,177 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 08:31:58,220 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:58,220 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:58,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:58,221 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:58,229 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 08:31:58,233 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-11-07 08:31:58,240 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 08:31:58,240 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 08:31:58,241 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 08:31:58,241 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 08:31:58,261 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 08:31:58,262 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 08:31:58,289 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-07 08:31:58,314 INFO L443 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2021-11-07 08:31:58,315 INFO L444 ModelExtractionUtils]: 11 out of 22 variables were initially zero. Simplification set additionally 8 variables to zero. [2021-11-07 08:31:58,317 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:31:58,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:58,319 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:31:58,324 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-11-07 08:31:58,325 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-07 08:31:58,353 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-07 08:31:58,354 INFO L513 LassoAnalysis]: Proved termination. [2021-11-07 08:31:58,354 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, ULTIMATE.start_main_~length~0) = -1*ULTIMATE.start_main_~i~0 + 1*ULTIMATE.start_main_~length~0 Supporting invariants [] [2021-11-07 08:31:58,395 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:58,408 INFO L297 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2021-11-07 08:31:58,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:58,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:58,459 INFO L263 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-07 08:31:58,461 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:31:58,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:58,509 INFO L263 TraceCheckSpWp]: Trace formula consists of 18 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-07 08:31:58,510 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:31:58,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:31:58,576 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-07 08:31:58,578 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:58,642 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 14 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 35 states and 50 transitions. Complement of second has 7 states. [2021-11-07 08:31:58,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-07 08:31:58,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:58,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2021-11-07 08:31:58,650 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 3 letters. [2021-11-07 08:31:58,652 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 08:31:58,652 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 8 letters. Loop has 3 letters. [2021-11-07 08:31:58,652 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 08:31:58,652 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 5 letters. Loop has 6 letters. [2021-11-07 08:31:58,653 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 08:31:58,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 50 transitions. [2021-11-07 08:31:58,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:31:58,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 12 states and 17 transitions. [2021-11-07 08:31:58,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-07 08:31:58,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-07 08:31:58,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2021-11-07 08:31:58,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:31:58,669 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-07 08:31:58,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2021-11-07 08:31:58,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-11-07 08:31:58,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:58,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 17 transitions. [2021-11-07 08:31:58,698 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-07 08:31:58,698 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 17 transitions. [2021-11-07 08:31:58,698 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 08:31:58,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 17 transitions. [2021-11-07 08:31:58,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:31:58,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:31:58,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:31:58,702 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:31:58,702 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:31:58,702 INFO L791 eck$LassoCheckResult]: Stem: 113#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 114#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 121#L367 assume !(main_~length~0 < 1); 115#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 116#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 117#L370-3 assume !(main_~i~0 < main_~length~0); 118#L370-4 main_~j~0 := 0; 119#L378-2 [2021-11-07 08:31:58,702 INFO L793 eck$LassoCheckResult]: Loop: 119#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 120#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 119#L378-2 [2021-11-07 08:31:58,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:58,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1806815510, now seen corresponding path program 1 times [2021-11-07 08:31:58,703 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:58,704 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359749443] [2021-11-07 08:31:58,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:58,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:58,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:58,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:31:58,783 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:31:58,783 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359749443] [2021-11-07 08:31:58,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359749443] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:31:58,784 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:31:58,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-11-07 08:31:58,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919878895] [2021-11-07 08:31:58,787 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:31:58,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:58,788 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 1 times [2021-11-07 08:31:58,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:58,788 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109723979] [2021-11-07 08:31:58,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:58,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:58,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:58,796 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:58,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:58,804 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:58,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:31:58,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:31:58,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:31:58,862 INFO L87 Difference]: Start difference. First operand 12 states and 17 transitions. cyclomatic complexity: 7 Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:58,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:31:58,892 INFO L93 Difference]: Finished difference Result 14 states and 19 transitions. [2021-11-07 08:31:58,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:31:58,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 19 transitions. [2021-11-07 08:31:58,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:31:58,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 19 transitions. [2021-11-07 08:31:58,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-11-07 08:31:58,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-07 08:31:58,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 19 transitions. [2021-11-07 08:31:58,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:31:58,895 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 19 transitions. [2021-11-07 08:31:58,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 19 transitions. [2021-11-07 08:31:58,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 12. [2021-11-07 08:31:58,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 11 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:58,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 16 transitions. [2021-11-07 08:31:58,897 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-07 08:31:58,897 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2021-11-07 08:31:58,898 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 08:31:58,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 16 transitions. [2021-11-07 08:31:58,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:31:58,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:31:58,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:31:58,899 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:31:58,899 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:31:58,899 INFO L791 eck$LassoCheckResult]: Stem: 146#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 147#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 154#L367 assume !(main_~length~0 < 1); 148#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 149#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 150#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 155#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 157#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 156#L370-3 assume !(main_~i~0 < main_~length~0); 151#L370-4 main_~j~0 := 0; 152#L378-2 [2021-11-07 08:31:58,900 INFO L793 eck$LassoCheckResult]: Loop: 152#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 153#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 152#L378-2 [2021-11-07 08:31:58,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:58,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1982565540, now seen corresponding path program 1 times [2021-11-07 08:31:58,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:58,901 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328764953] [2021-11-07 08:31:58,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:58,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:58,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:58,933 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:58,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:58,966 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:58,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:58,967 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 2 times [2021-11-07 08:31:58,967 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:58,967 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418098376] [2021-11-07 08:31:58,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:58,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:58,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:58,987 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:58,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:59,000 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:59,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:59,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996831, now seen corresponding path program 1 times [2021-11-07 08:31:59,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:59,001 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21576809] [2021-11-07 08:31:59,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,001 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:59,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:59,197 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-11-07 08:31:59,304 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:31:59,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:31:59,305 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21576809] [2021-11-07 08:31:59,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21576809] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:31:59,306 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1962679869] [2021-11-07 08:31:59,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,306 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:31:59,306 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:59,307 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:31:59,309 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-11-07 08:31:59,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:59,370 INFO L263 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-07 08:31:59,371 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:31:59,465 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-11-07 08:31:59,586 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:31:59,596 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:31:59,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1962679869] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:31:59,597 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:31:59,597 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 11 [2021-11-07 08:31:59,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598566094] [2021-11-07 08:31:59,656 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:31:59,657 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-07 08:31:59,657 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2021-11-07 08:31:59,658 INFO L87 Difference]: Start difference. First operand 12 states and 16 transitions. cyclomatic complexity: 6 Second operand has 12 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:59,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:31:59,775 INFO L93 Difference]: Finished difference Result 20 states and 27 transitions. [2021-11-07 08:31:59,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-07 08:31:59,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 27 transitions. [2021-11-07 08:31:59,783 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:31:59,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 20 states and 27 transitions. [2021-11-07 08:31:59,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-11-07 08:31:59,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-11-07 08:31:59,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 27 transitions. [2021-11-07 08:31:59,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:31:59,785 INFO L681 BuchiCegarLoop]: Abstraction has 20 states and 27 transitions. [2021-11-07 08:31:59,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 27 transitions. [2021-11-07 08:31:59,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 18. [2021-11-07 08:31:59,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.3333333333333333) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:31:59,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 24 transitions. [2021-11-07 08:31:59,798 INFO L704 BuchiCegarLoop]: Abstraction has 18 states and 24 transitions. [2021-11-07 08:31:59,798 INFO L587 BuchiCegarLoop]: Abstraction has 18 states and 24 transitions. [2021-11-07 08:31:59,798 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 08:31:59,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 24 transitions. [2021-11-07 08:31:59,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:31:59,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:31:59,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:31:59,801 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:31:59,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:31:59,802 INFO L791 eck$LassoCheckResult]: Stem: 230#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 231#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 238#L367 assume !(main_~length~0 < 1); 232#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 233#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 234#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 239#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 244#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 240#L370-3 assume !(main_~i~0 < main_~length~0); 241#L370-4 main_~j~0 := 0; 245#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 237#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 236#L378-2 [2021-11-07 08:31:59,802 INFO L793 eck$LassoCheckResult]: Loop: 236#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 243#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 236#L378-2 [2021-11-07 08:31:59,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:59,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1719996833, now seen corresponding path program 1 times [2021-11-07 08:31:59,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:59,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151004575] [2021-11-07 08:31:59,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:59,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:59,834 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:59,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:59,858 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:59,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:59,859 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 3 times [2021-11-07 08:31:59,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:59,859 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084052564] [2021-11-07 08:31:59,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:59,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:59,875 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:31:59,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:31:59,880 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:31:59,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:31:59,889 INFO L85 PathProgramCache]: Analyzing trace with hash -645451100, now seen corresponding path program 1 times [2021-11-07 08:31:59,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:31:59,889 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542847151] [2021-11-07 08:31:59,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:31:59,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:31:59,970 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:31:59,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:31:59,970 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542847151] [2021-11-07 08:31:59,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542847151] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:31:59,970 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1332287144] [2021-11-07 08:31:59,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:31:59,971 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:31:59,971 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:31:59,972 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:31:59,973 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-11-07 08:32:00,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:00,053 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-07 08:32:00,054 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:00,129 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:00,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1332287144] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:00,130 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:00,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 10 [2021-11-07 08:32:00,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175008832] [2021-11-07 08:32:00,170 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:00,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-07 08:32:00,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2021-11-07 08:32:00,171 INFO L87 Difference]: Start difference. First operand 18 states and 24 transitions. cyclomatic complexity: 8 Second operand has 10 states, 10 states have (on average 2.2) internal successors, (22), 10 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:00,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:00,293 INFO L93 Difference]: Finished difference Result 34 states and 45 transitions. [2021-11-07 08:32:00,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-07 08:32:00,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 45 transitions. [2021-11-07 08:32:00,297 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:00,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 30 states and 39 transitions. [2021-11-07 08:32:00,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-07 08:32:00,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-07 08:32:00,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 39 transitions. [2021-11-07 08:32:00,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:00,299 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 39 transitions. [2021-11-07 08:32:00,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 39 transitions. [2021-11-07 08:32:00,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 27. [2021-11-07 08:32:00,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2962962962962963) internal successors, (35), 26 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:00,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 35 transitions. [2021-11-07 08:32:00,305 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2021-11-07 08:32:00,305 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 35 transitions. [2021-11-07 08:32:00,305 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 08:32:00,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 35 transitions. [2021-11-07 08:32:00,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:00,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:00,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:00,309 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:00,309 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:00,309 INFO L791 eck$LassoCheckResult]: Stem: 346#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 347#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 355#L367 assume main_~length~0 < 1;main_~length~0 := 1; 348#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 349#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 357#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 358#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 366#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 367#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 371#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 372#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 370#L370-3 assume !(main_~i~0 < main_~length~0); 352#L370-4 main_~j~0 := 0; 353#L378-2 [2021-11-07 08:32:00,309 INFO L793 eck$LassoCheckResult]: Loop: 353#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 354#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 353#L378-2 [2021-11-07 08:32:00,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:00,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1080884692, now seen corresponding path program 1 times [2021-11-07 08:32:00,311 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:00,316 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932174450] [2021-11-07 08:32:00,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:00,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:00,433 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:00,433 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:00,433 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932174450] [2021-11-07 08:32:00,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932174450] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:00,434 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846822382] [2021-11-07 08:32:00,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,434 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:00,434 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:00,438 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:00,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-11-07 08:32:00,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:00,505 INFO L263 TraceCheckSpWp]: Trace formula consists of 53 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-07 08:32:00,506 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:00,589 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:00,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1846822382] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:32:00,590 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2021-11-07 08:32:00,590 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2021-11-07 08:32:00,590 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496287108] [2021-11-07 08:32:00,591 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:32:00,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:00,591 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 4 times [2021-11-07 08:32:00,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:00,592 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405647316] [2021-11-07 08:32:00,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:00,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,597 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:00,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,602 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:00,655 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:00,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 08:32:00,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2021-11-07 08:32:00,656 INFO L87 Difference]: Start difference. First operand 27 states and 35 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:00,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:00,684 INFO L93 Difference]: Finished difference Result 21 states and 26 transitions. [2021-11-07 08:32:00,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-07 08:32:00,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 26 transitions. [2021-11-07 08:32:00,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:00,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 15 states and 19 transitions. [2021-11-07 08:32:00,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-11-07 08:32:00,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-07 08:32:00,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 19 transitions. [2021-11-07 08:32:00,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:00,687 INFO L681 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2021-11-07 08:32:00,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 19 transitions. [2021-11-07 08:32:00,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2021-11-07 08:32:00,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.2666666666666666) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:00,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 19 transitions. [2021-11-07 08:32:00,689 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2021-11-07 08:32:00,689 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2021-11-07 08:32:00,689 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 08:32:00,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 19 transitions. [2021-11-07 08:32:00,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:00,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:00,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:00,691 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:00,691 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:00,691 INFO L791 eck$LassoCheckResult]: Stem: 441#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 442#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 449#L367 assume !(main_~length~0 < 1); 443#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 444#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 445#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 450#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 453#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 451#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 452#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 455#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 454#L370-3 assume !(main_~i~0 < main_~length~0); 446#L370-4 main_~j~0 := 0; 447#L378-2 [2021-11-07 08:32:00,691 INFO L793 eck$LassoCheckResult]: Loop: 447#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 448#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 447#L378-2 [2021-11-07 08:32:00,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:00,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1781949270, now seen corresponding path program 2 times [2021-11-07 08:32:00,692 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:00,692 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757770387] [2021-11-07 08:32:00,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,692 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:00,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,703 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:00,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,723 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:00,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:00,727 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 5 times [2021-11-07 08:32:00,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:00,728 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081757063] [2021-11-07 08:32:00,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:00,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,738 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:00,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:00,744 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:00,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:00,746 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701287, now seen corresponding path program 2 times [2021-11-07 08:32:00,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:00,746 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027735986] [2021-11-07 08:32:00,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:00,747 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:00,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:00,944 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:00,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:00,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027735986] [2021-11-07 08:32:00,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027735986] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:00,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [708481078] [2021-11-07 08:32:00,945 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:00,945 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:00,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:00,950 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:00,975 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-07 08:32:01,041 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:01,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:01,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-07 08:32:01,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:01,086 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:01,185 INFO L354 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2021-11-07 08:32:01,185 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 25 [2021-11-07 08:32:01,266 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:01,277 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:01,279 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [708481078] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:01,279 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:01,279 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 12 [2021-11-07 08:32:01,280 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392373278] [2021-11-07 08:32:01,322 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:01,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-07 08:32:01,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2021-11-07 08:32:01,323 INFO L87 Difference]: Start difference. First operand 15 states and 19 transitions. cyclomatic complexity: 6 Second operand has 13 states, 12 states have (on average 1.75) internal successors, (21), 13 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:01,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:01,445 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2021-11-07 08:32:01,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-07 08:32:01,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 21 transitions. [2021-11-07 08:32:01,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:01,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 17 states and 21 transitions. [2021-11-07 08:32:01,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-07 08:32:01,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-07 08:32:01,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 21 transitions. [2021-11-07 08:32:01,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:01,447 INFO L681 BuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2021-11-07 08:32:01,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 21 transitions. [2021-11-07 08:32:01,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2021-11-07 08:32:01,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:01,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2021-11-07 08:32:01,449 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2021-11-07 08:32:01,449 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2021-11-07 08:32:01,449 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 08:32:01,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2021-11-07 08:32:01,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:01,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:01,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:01,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:01,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:01,450 INFO L791 eck$LassoCheckResult]: Stem: 537#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 538#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 546#L367 assume !(main_~length~0 < 1); 539#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 540#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 541#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 547#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 550#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 548#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 549#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 553#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 552#L370-3 assume !(main_~i~0 < main_~length~0); 542#L370-4 main_~j~0 := 0; 543#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 544#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 545#L378-2 [2021-11-07 08:32:01,452 INFO L793 eck$LassoCheckResult]: Loop: 545#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 551#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 545#L378-2 [2021-11-07 08:32:01,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:01,453 INFO L85 PathProgramCache]: Analyzing trace with hash -1238701285, now seen corresponding path program 2 times [2021-11-07 08:32:01,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:01,453 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038501195] [2021-11-07 08:32:01,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:01,454 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:01,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:01,469 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:01,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:01,495 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:01,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:01,496 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 6 times [2021-11-07 08:32:01,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:01,496 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323399689] [2021-11-07 08:32:01,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:01,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:01,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:01,507 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:01,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:01,513 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:01,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:01,515 INFO L85 PathProgramCache]: Analyzing trace with hash -685992546, now seen corresponding path program 2 times [2021-11-07 08:32:01,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:01,515 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203139770] [2021-11-07 08:32:01,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:01,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:01,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:01,678 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:01,678 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:01,678 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203139770] [2021-11-07 08:32:01,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203139770] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:01,678 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1854504722] [2021-11-07 08:32:01,679 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:01,679 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:01,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:01,681 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:01,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-07 08:32:01,776 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:01,776 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:01,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-07 08:32:01,778 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:01,846 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:02,016 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:02,020 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:02,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1854504722] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:02,020 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:02,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 11 [2021-11-07 08:32:02,021 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499359786] [2021-11-07 08:32:02,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:02,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-07 08:32:02,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2021-11-07 08:32:02,077 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 6 Second operand has 12 states, 11 states have (on average 2.0) internal successors, (22), 12 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:02,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:02,211 INFO L93 Difference]: Finished difference Result 27 states and 34 transitions. [2021-11-07 08:32:02,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-07 08:32:02,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 34 transitions. [2021-11-07 08:32:02,213 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:02,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 34 transitions. [2021-11-07 08:32:02,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-07 08:32:02,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-07 08:32:02,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2021-11-07 08:32:02,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:02,215 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 34 transitions. [2021-11-07 08:32:02,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2021-11-07 08:32:02,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 23. [2021-11-07 08:32:02,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 22 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:02,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 29 transitions. [2021-11-07 08:32:02,218 INFO L704 BuchiCegarLoop]: Abstraction has 23 states and 29 transitions. [2021-11-07 08:32:02,218 INFO L587 BuchiCegarLoop]: Abstraction has 23 states and 29 transitions. [2021-11-07 08:32:02,218 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 08:32:02,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 29 transitions. [2021-11-07 08:32:02,219 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:02,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:02,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:02,220 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:02,220 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:02,220 INFO L791 eck$LassoCheckResult]: Stem: 648#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 649#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 656#L367 assume !(main_~length~0 < 1); 650#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 651#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 652#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 657#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 665#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 658#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 659#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 661#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 662#L370-3 assume !(main_~i~0 < main_~length~0); 663#L370-4 main_~j~0 := 0; 668#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 653#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 654#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 660#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 667#L378-2 [2021-11-07 08:32:02,220 INFO L793 eck$LassoCheckResult]: Loop: 667#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 666#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 667#L378-2 [2021-11-07 08:32:02,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,220 INFO L85 PathProgramCache]: Analyzing trace with hash -685992544, now seen corresponding path program 3 times [2021-11-07 08:32:02,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,221 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149003527] [2021-11-07 08:32:02,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,235 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:02,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,263 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:02,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,264 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 7 times [2021-11-07 08:32:02,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,264 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410385417] [2021-11-07 08:32:02,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,271 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:02,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,278 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:02,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,280 INFO L85 PathProgramCache]: Analyzing trace with hash -2108837149, now seen corresponding path program 3 times [2021-11-07 08:32:02,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,280 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256044390] [2021-11-07 08:32:02,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,281 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:02,367 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:02,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:02,368 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256044390] [2021-11-07 08:32:02,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256044390] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:02,368 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1104373582] [2021-11-07 08:32:02,369 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:32:02,369 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:02,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:02,374 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:02,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-07 08:32:02,481 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2021-11-07 08:32:02,481 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:02,482 INFO L263 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-07 08:32:02,483 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:02,640 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:02,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1104373582] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:02,641 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:02,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 13 [2021-11-07 08:32:02,641 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563923727] [2021-11-07 08:32:02,694 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:02,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-07 08:32:02,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2021-11-07 08:32:02,696 INFO L87 Difference]: Start difference. First operand 23 states and 29 transitions. cyclomatic complexity: 8 Second operand has 13 states, 13 states have (on average 2.230769230769231) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:02,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:02,805 INFO L93 Difference]: Finished difference Result 28 states and 34 transitions. [2021-11-07 08:32:02,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-07 08:32:02,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 34 transitions. [2021-11-07 08:32:02,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:02,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 22 states and 28 transitions. [2021-11-07 08:32:02,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-07 08:32:02,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-07 08:32:02,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2021-11-07 08:32:02,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:02,807 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 28 transitions. [2021-11-07 08:32:02,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2021-11-07 08:32:02,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 20. [2021-11-07 08:32:02,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.25) internal successors, (25), 19 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:02,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 25 transitions. [2021-11-07 08:32:02,809 INFO L704 BuchiCegarLoop]: Abstraction has 20 states and 25 transitions. [2021-11-07 08:32:02,809 INFO L587 BuchiCegarLoop]: Abstraction has 20 states and 25 transitions. [2021-11-07 08:32:02,810 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 08:32:02,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 25 transitions. [2021-11-07 08:32:02,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:02,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:02,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:02,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:02,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:02,811 INFO L791 eck$LassoCheckResult]: Stem: 779#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 780#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 788#L367 assume !(main_~length~0 < 1); 781#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 782#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 783#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 789#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 792#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 790#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 791#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 798#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 796#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 794#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 795#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 793#L370-3 assume !(main_~i~0 < main_~length~0); 784#L370-4 main_~j~0 := 0; 785#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 786#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 787#L378-2 [2021-11-07 08:32:02,811 INFO L793 eck$LassoCheckResult]: Loop: 787#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 797#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 787#L378-2 [2021-11-07 08:32:02,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1799481185, now seen corresponding path program 4 times [2021-11-07 08:32:02,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,812 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717794454] [2021-11-07 08:32:02,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,825 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:02,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,838 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:02,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,838 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 8 times [2021-11-07 08:32:02,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,839 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730113701] [2021-11-07 08:32:02,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,843 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:02,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:02,848 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:02,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:02,853 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400156, now seen corresponding path program 4 times [2021-11-07 08:32:02,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:02,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796737658] [2021-11-07 08:32:02,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:02,854 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:02,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:03,021 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:03,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:03,023 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796737658] [2021-11-07 08:32:03,023 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796737658] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:03,023 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [423081035] [2021-11-07 08:32:03,023 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:32:03,023 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:03,024 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:03,030 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:03,054 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-07 08:32:03,141 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:32:03,142 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:03,143 INFO L263 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-07 08:32:03,144 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:03,238 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:03,358 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:03,358 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:03,511 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:03,515 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:03,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [423081035] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:03,515 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:03,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2021-11-07 08:32:03,516 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062890969] [2021-11-07 08:32:03,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:03,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-07 08:32:03,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=311, Unknown=0, NotChecked=0, Total=380 [2021-11-07 08:32:03,568 INFO L87 Difference]: Start difference. First operand 20 states and 25 transitions. cyclomatic complexity: 7 Second operand has 20 states, 19 states have (on average 1.894736842105263) internal successors, (36), 20 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:03,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:03,755 INFO L93 Difference]: Finished difference Result 22 states and 27 transitions. [2021-11-07 08:32:03,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-07 08:32:03,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 27 transitions. [2021-11-07 08:32:03,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:03,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 27 transitions. [2021-11-07 08:32:03,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-07 08:32:03,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-07 08:32:03,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 27 transitions. [2021-11-07 08:32:03,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:03,757 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2021-11-07 08:32:03,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 27 transitions. [2021-11-07 08:32:03,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2021-11-07 08:32:03,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:03,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 27 transitions. [2021-11-07 08:32:03,759 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2021-11-07 08:32:03,759 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 27 transitions. [2021-11-07 08:32:03,759 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 08:32:03,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 27 transitions. [2021-11-07 08:32:03,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:03,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:03,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:03,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:03,761 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:03,761 INFO L791 eck$LassoCheckResult]: Stem: 911#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 912#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 920#L367 assume !(main_~length~0 < 1); 913#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 914#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 915#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 921#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 925#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 922#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 923#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 930#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 929#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 927#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 928#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 926#L370-3 assume !(main_~i~0 < main_~length~0); 916#L370-4 main_~j~0 := 0; 917#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 918#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 919#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 924#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 932#L378-2 [2021-11-07 08:32:03,761 INFO L793 eck$LassoCheckResult]: Loop: 932#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 931#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 932#L378-2 [2021-11-07 08:32:03,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:03,762 INFO L85 PathProgramCache]: Analyzing trace with hash -1570400154, now seen corresponding path program 5 times [2021-11-07 08:32:03,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:03,762 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330825686] [2021-11-07 08:32:03,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:03,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:03,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:03,775 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:03,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:03,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:03,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:03,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 9 times [2021-11-07 08:32:03,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:03,789 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452411924] [2021-11-07 08:32:03,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:03,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:03,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:03,793 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:03,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:03,796 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:03,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:03,796 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025751, now seen corresponding path program 5 times [2021-11-07 08:32:03,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:03,797 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517800016] [2021-11-07 08:32:03,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:03,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:03,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:03,943 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:03,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:03,943 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517800016] [2021-11-07 08:32:03,943 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517800016] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:03,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1561108436] [2021-11-07 08:32:03,944 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:32:03,944 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:03,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:03,950 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:03,965 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-07 08:32:04,068 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-11-07 08:32:04,070 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:04,071 INFO L263 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-07 08:32:04,072 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:04,142 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:04,364 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:04,368 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:04,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1561108436] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:04,369 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:04,369 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 15 [2021-11-07 08:32:04,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178812277] [2021-11-07 08:32:04,425 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:04,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-07 08:32:04,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=200, Unknown=0, NotChecked=0, Total=240 [2021-11-07 08:32:04,426 INFO L87 Difference]: Start difference. First operand 22 states and 27 transitions. cyclomatic complexity: 7 Second operand has 16 states, 15 states have (on average 2.066666666666667) internal successors, (31), 16 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:04,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:04,624 INFO L93 Difference]: Finished difference Result 34 states and 42 transitions. [2021-11-07 08:32:04,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-07 08:32:04,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 42 transitions. [2021-11-07 08:32:04,626 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:04,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 42 transitions. [2021-11-07 08:32:04,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-11-07 08:32:04,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-11-07 08:32:04,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2021-11-07 08:32:04,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:04,627 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 42 transitions. [2021-11-07 08:32:04,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2021-11-07 08:32:04,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 28. [2021-11-07 08:32:04,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:04,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2021-11-07 08:32:04,639 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2021-11-07 08:32:04,639 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2021-11-07 08:32:04,639 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 08:32:04,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2021-11-07 08:32:04,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:04,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:04,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:04,643 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:04,643 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:04,644 INFO L791 eck$LassoCheckResult]: Stem: 1053#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1054#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1061#L367 assume !(main_~length~0 < 1); 1055#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1056#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1057#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1062#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1070#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1071#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1072#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1073#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1063#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1064#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1065#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1067#L370-3 assume !(main_~i~0 < main_~length~0); 1068#L370-4 main_~j~0 := 0; 1078#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1060#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1059#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1066#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1077#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1076#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1075#L378-2 [2021-11-07 08:32:04,644 INFO L793 eck$LassoCheckResult]: Loop: 1075#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1074#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1075#L378-2 [2021-11-07 08:32:04,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:04,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1621025749, now seen corresponding path program 6 times [2021-11-07 08:32:04,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:04,646 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33677473] [2021-11-07 08:32:04,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:04,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:04,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:04,659 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:04,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:04,674 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:04,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:04,675 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 10 times [2021-11-07 08:32:04,675 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:04,675 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579663111] [2021-11-07 08:32:04,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:04,675 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:04,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:04,680 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:04,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:04,683 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:04,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:04,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1267385006, now seen corresponding path program 6 times [2021-11-07 08:32:04,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:04,684 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483364463] [2021-11-07 08:32:04,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:04,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:04,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:04,763 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 7 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:04,764 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:04,764 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483364463] [2021-11-07 08:32:04,764 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483364463] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:04,764 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1983224561] [2021-11-07 08:32:04,764 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:32:04,765 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:04,765 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:04,769 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:04,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-07 08:32:04,911 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2021-11-07 08:32:04,911 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:04,912 INFO L263 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-07 08:32:04,915 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:05,064 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:05,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1983224561] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:05,064 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:05,065 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 16 [2021-11-07 08:32:05,065 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391628938] [2021-11-07 08:32:05,114 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:05,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-07 08:32:05,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2021-11-07 08:32:05,116 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 9 Second operand has 16 states, 16 states have (on average 2.25) internal successors, (36), 16 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:05,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:05,243 INFO L93 Difference]: Finished difference Result 35 states and 42 transitions. [2021-11-07 08:32:05,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-07 08:32:05,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 42 transitions. [2021-11-07 08:32:05,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:05,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 27 states and 34 transitions. [2021-11-07 08:32:05,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-07 08:32:05,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-07 08:32:05,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 34 transitions. [2021-11-07 08:32:05,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:05,245 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 34 transitions. [2021-11-07 08:32:05,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 34 transitions. [2021-11-07 08:32:05,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2021-11-07 08:32:05,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.24) internal successors, (31), 24 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:05,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 31 transitions. [2021-11-07 08:32:05,247 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2021-11-07 08:32:05,247 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 31 transitions. [2021-11-07 08:32:05,247 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 08:32:05,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 31 transitions. [2021-11-07 08:32:05,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:05,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:05,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:05,249 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:05,249 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:05,249 INFO L791 eck$LassoCheckResult]: Stem: 1216#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1217#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1225#L367 assume !(main_~length~0 < 1); 1218#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1219#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1220#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1226#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1238#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1227#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1228#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1229#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1231#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1237#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1236#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1235#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1233#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1234#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1232#L370-3 assume !(main_~i~0 < main_~length~0); 1221#L370-4 main_~j~0 := 0; 1222#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1223#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1224#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1230#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1240#L378-2 [2021-11-07 08:32:05,249 INFO L793 eck$LassoCheckResult]: Loop: 1240#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1239#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1240#L378-2 [2021-11-07 08:32:05,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:05,249 INFO L85 PathProgramCache]: Analyzing trace with hash 666851296, now seen corresponding path program 7 times [2021-11-07 08:32:05,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:05,250 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333215643] [2021-11-07 08:32:05,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:05,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:05,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:05,277 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:05,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:05,293 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:05,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:05,294 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 11 times [2021-11-07 08:32:05,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:05,294 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255182528] [2021-11-07 08:32:05,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:05,295 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:05,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:05,299 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:05,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:05,302 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:05,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:05,302 INFO L85 PathProgramCache]: Analyzing trace with hash 893969699, now seen corresponding path program 7 times [2021-11-07 08:32:05,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:05,303 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791994223] [2021-11-07 08:32:05,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:05,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:05,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:05,490 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:05,491 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:05,491 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791994223] [2021-11-07 08:32:05,491 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791994223] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:05,491 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1758943398] [2021-11-07 08:32:05,491 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:32:05,491 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:05,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:05,498 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:05,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-07 08:32:05,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:05,641 INFO L263 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-07 08:32:05,643 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:05,785 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:05,915 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:05,916 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:06,132 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:06,135 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:06,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1758943398] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:06,135 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:06,136 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 23 [2021-11-07 08:32:06,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567910234] [2021-11-07 08:32:06,189 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:06,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-07 08:32:06,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2021-11-07 08:32:06,190 INFO L87 Difference]: Start difference. First operand 25 states and 31 transitions. cyclomatic complexity: 8 Second operand has 24 states, 23 states have (on average 2.0) internal successors, (46), 24 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:06,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:06,495 INFO L93 Difference]: Finished difference Result 27 states and 33 transitions. [2021-11-07 08:32:06,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-07 08:32:06,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 33 transitions. [2021-11-07 08:32:06,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:06,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 33 transitions. [2021-11-07 08:32:06,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-07 08:32:06,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-07 08:32:06,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 33 transitions. [2021-11-07 08:32:06,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:06,498 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2021-11-07 08:32:06,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 33 transitions. [2021-11-07 08:32:06,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2021-11-07 08:32:06,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:06,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2021-11-07 08:32:06,501 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2021-11-07 08:32:06,501 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2021-11-07 08:32:06,501 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 08:32:06,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2021-11-07 08:32:06,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:06,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:06,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:06,503 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:06,503 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:06,503 INFO L791 eck$LassoCheckResult]: Stem: 1381#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1382#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1388#L367 assume !(main_~length~0 < 1); 1379#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1380#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1383#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1389#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1401#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1390#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1391#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1392#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1394#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1400#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1399#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1398#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1396#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1397#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1395#L370-3 assume !(main_~i~0 < main_~length~0); 1384#L370-4 main_~j~0 := 0; 1385#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1386#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1387#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1393#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1405#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1404#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1403#L378-2 [2021-11-07 08:32:06,503 INFO L793 eck$LassoCheckResult]: Loop: 1403#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1402#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1403#L378-2 [2021-11-07 08:32:06,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:06,504 INFO L85 PathProgramCache]: Analyzing trace with hash 893969701, now seen corresponding path program 8 times [2021-11-07 08:32:06,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:06,504 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197405607] [2021-11-07 08:32:06,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:06,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:06,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:06,518 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:06,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:06,538 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:06,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:06,539 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 12 times [2021-11-07 08:32:06,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:06,540 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [208368037] [2021-11-07 08:32:06,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:06,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:06,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:06,544 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:06,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:06,547 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:06,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:06,547 INFO L85 PathProgramCache]: Analyzing trace with hash 111424808, now seen corresponding path program 8 times [2021-11-07 08:32:06,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:06,548 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621726960] [2021-11-07 08:32:06,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:06,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:06,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:06,725 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:06,726 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:06,726 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621726960] [2021-11-07 08:32:06,726 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621726960] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:06,726 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1698206132] [2021-11-07 08:32:06,726 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:06,727 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:06,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:06,734 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:06,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-07 08:32:06,880 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:06,880 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:06,882 INFO L263 TraceCheckSpWp]: Trace formula consists of 117 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-07 08:32:06,883 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:06,960 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:07,153 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:07,158 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:07,159 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1698206132] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:07,159 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:07,159 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12] total 17 [2021-11-07 08:32:07,159 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886154464] [2021-11-07 08:32:07,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:07,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-07 08:32:07,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=262, Unknown=0, NotChecked=0, Total=306 [2021-11-07 08:32:07,211 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 8 Second operand has 18 states, 17 states have (on average 2.1176470588235294) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:07,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:07,424 INFO L93 Difference]: Finished difference Result 41 states and 50 transitions. [2021-11-07 08:32:07,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-07 08:32:07,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 50 transitions. [2021-11-07 08:32:07,425 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:07,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 41 states and 50 transitions. [2021-11-07 08:32:07,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2021-11-07 08:32:07,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2021-11-07 08:32:07,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 50 transitions. [2021-11-07 08:32:07,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:07,427 INFO L681 BuchiCegarLoop]: Abstraction has 41 states and 50 transitions. [2021-11-07 08:32:07,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 50 transitions. [2021-11-07 08:32:07,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 33. [2021-11-07 08:32:07,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:07,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 41 transitions. [2021-11-07 08:32:07,430 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 41 transitions. [2021-11-07 08:32:07,430 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 41 transitions. [2021-11-07 08:32:07,430 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 08:32:07,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 41 transitions. [2021-11-07 08:32:07,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:07,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:07,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:07,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:07,432 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:07,432 INFO L791 eck$LassoCheckResult]: Stem: 1550#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1551#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1558#L367 assume !(main_~length~0 < 1); 1552#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1553#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1554#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1559#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1573#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1560#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1561#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1563#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1564#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1572#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1571#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1570#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1569#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1568#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1565#L370-3 assume !(main_~i~0 < main_~length~0); 1566#L370-4 main_~j~0 := 0; 1580#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1555#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1556#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1562#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1579#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1578#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1577#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1576#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1575#L378-2 [2021-11-07 08:32:07,432 INFO L793 eck$LassoCheckResult]: Loop: 1575#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1574#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1575#L378-2 [2021-11-07 08:32:07,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:07,433 INFO L85 PathProgramCache]: Analyzing trace with hash 111424810, now seen corresponding path program 9 times [2021-11-07 08:32:07,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:07,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674493806] [2021-11-07 08:32:07,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:07,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:07,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:07,452 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:07,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:07,480 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:07,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:07,482 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 13 times [2021-11-07 08:32:07,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:07,482 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464972986] [2021-11-07 08:32:07,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:07,483 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:07,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:07,490 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:07,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:07,494 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:07,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:07,495 INFO L85 PathProgramCache]: Analyzing trace with hash -294938643, now seen corresponding path program 9 times [2021-11-07 08:32:07,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:07,496 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059722742] [2021-11-07 08:32:07,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:07,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:07,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:07,605 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 13 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:07,605 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:07,605 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059722742] [2021-11-07 08:32:07,605 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059722742] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:07,606 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [340286055] [2021-11-07 08:32:07,606 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:32:07,606 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:07,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:07,607 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:07,608 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-07 08:32:07,775 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2021-11-07 08:32:07,776 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:07,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-07 08:32:07,778 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:08,015 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:08,015 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [340286055] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:08,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:08,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 19 [2021-11-07 08:32:08,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924751162] [2021-11-07 08:32:08,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:08,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-07 08:32:08,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=259, Unknown=0, NotChecked=0, Total=342 [2021-11-07 08:32:08,054 INFO L87 Difference]: Start difference. First operand 33 states and 41 transitions. cyclomatic complexity: 10 Second operand has 19 states, 19 states have (on average 2.263157894736842) internal successors, (43), 19 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:08,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:08,200 INFO L93 Difference]: Finished difference Result 42 states and 50 transitions. [2021-11-07 08:32:08,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-07 08:32:08,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 50 transitions. [2021-11-07 08:32:08,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:08,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 32 states and 40 transitions. [2021-11-07 08:32:08,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-07 08:32:08,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-07 08:32:08,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 40 transitions. [2021-11-07 08:32:08,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:08,202 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2021-11-07 08:32:08,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 40 transitions. [2021-11-07 08:32:08,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 30. [2021-11-07 08:32:08,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.2333333333333334) internal successors, (37), 29 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:08,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 37 transitions. [2021-11-07 08:32:08,204 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 37 transitions. [2021-11-07 08:32:08,204 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 37 transitions. [2021-11-07 08:32:08,205 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 08:32:08,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 37 transitions. [2021-11-07 08:32:08,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:08,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:08,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:08,206 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:08,206 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:08,206 INFO L791 eck$LassoCheckResult]: Stem: 1745#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1746#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1754#L367 assume !(main_~length~0 < 1); 1747#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1748#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1749#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1755#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1770#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1756#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1757#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1759#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1760#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1769#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1768#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1767#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1766#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1765#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1764#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1762#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1763#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1761#L370-3 assume !(main_~i~0 < main_~length~0); 1752#L370-4 main_~j~0 := 0; 1753#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1750#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1751#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1758#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1774#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1773#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1772#L378-2 [2021-11-07 08:32:08,206 INFO L793 eck$LassoCheckResult]: Loop: 1772#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1771#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1772#L378-2 [2021-11-07 08:32:08,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:08,207 INFO L85 PathProgramCache]: Analyzing trace with hash -581058069, now seen corresponding path program 10 times [2021-11-07 08:32:08,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:08,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601188911] [2021-11-07 08:32:08,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:08,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:08,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:08,221 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:08,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:08,238 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:08,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:08,238 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 14 times [2021-11-07 08:32:08,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:08,239 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091266883] [2021-11-07 08:32:08,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:08,239 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:08,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:08,243 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:08,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:08,246 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:08,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:08,246 INFO L85 PathProgramCache]: Analyzing trace with hash -51054482, now seen corresponding path program 10 times [2021-11-07 08:32:08,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:08,247 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783777233] [2021-11-07 08:32:08,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:08,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:08,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:08,462 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:08,462 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:08,462 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783777233] [2021-11-07 08:32:08,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783777233] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:08,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1393592963] [2021-11-07 08:32:08,463 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:32:08,463 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:08,463 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:08,470 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:08,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-07 08:32:08,675 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:32:08,675 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:08,677 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-07 08:32:08,678 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:08,854 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:09,005 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:09,006 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:09,298 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:09,302 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:09,303 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1393592963] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:09,303 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:09,303 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 27 [2021-11-07 08:32:09,303 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082717306] [2021-11-07 08:32:09,356 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:09,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-07 08:32:09,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=659, Unknown=0, NotChecked=0, Total=756 [2021-11-07 08:32:09,357 INFO L87 Difference]: Start difference. First operand 30 states and 37 transitions. cyclomatic complexity: 9 Second operand has 28 states, 27 states have (on average 2.074074074074074) internal successors, (56), 28 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:09,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:09,749 INFO L93 Difference]: Finished difference Result 32 states and 39 transitions. [2021-11-07 08:32:09,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-07 08:32:09,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 39 transitions. [2021-11-07 08:32:09,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:09,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 32 states and 39 transitions. [2021-11-07 08:32:09,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-07 08:32:09,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-07 08:32:09,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 39 transitions. [2021-11-07 08:32:09,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:09,751 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 39 transitions. [2021-11-07 08:32:09,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 39 transitions. [2021-11-07 08:32:09,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2021-11-07 08:32:09,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.21875) internal successors, (39), 31 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:09,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 39 transitions. [2021-11-07 08:32:09,757 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 39 transitions. [2021-11-07 08:32:09,757 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 39 transitions. [2021-11-07 08:32:09,758 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 08:32:09,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 39 transitions. [2021-11-07 08:32:09,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:09,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:09,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:09,759 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:09,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:09,759 INFO L791 eck$LassoCheckResult]: Stem: 1939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1940#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 1948#L367 assume !(main_~length~0 < 1); 1941#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 1942#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 1943#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1949#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1964#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1950#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1951#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1953#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1954#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1963#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1962#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1961#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1960#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1959#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1958#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 1956#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 1957#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 1955#L370-3 assume !(main_~i~0 < main_~length~0); 1946#L370-4 main_~j~0 := 0; 1947#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1944#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1945#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1952#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1970#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1969#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1968#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1967#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 1966#L378-2 [2021-11-07 08:32:09,759 INFO L793 eck$LassoCheckResult]: Loop: 1966#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 1965#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 1966#L378-2 [2021-11-07 08:32:09,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:09,760 INFO L85 PathProgramCache]: Analyzing trace with hash -51054480, now seen corresponding path program 11 times [2021-11-07 08:32:09,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:09,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313160281] [2021-11-07 08:32:09,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:09,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:09,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:09,796 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:09,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:09,823 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:09,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:09,823 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 15 times [2021-11-07 08:32:09,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:09,824 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811611686] [2021-11-07 08:32:09,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:09,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:09,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:09,828 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:09,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:09,836 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:09,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:09,836 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713677, now seen corresponding path program 11 times [2021-11-07 08:32:09,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:09,837 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272779533] [2021-11-07 08:32:09,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:09,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:09,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:10,053 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:10,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:10,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272779533] [2021-11-07 08:32:10,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272779533] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:10,054 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [320688502] [2021-11-07 08:32:10,054 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:32:10,054 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:10,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:10,056 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:10,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-07 08:32:10,334 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-11-07 08:32:10,334 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:10,336 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-07 08:32:10,337 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:10,442 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:10,726 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:10,729 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:10,730 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [320688502] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:10,730 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:10,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 21 [2021-11-07 08:32:10,732 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627423655] [2021-11-07 08:32:10,778 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:10,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-07 08:32:10,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=406, Unknown=0, NotChecked=0, Total=462 [2021-11-07 08:32:10,779 INFO L87 Difference]: Start difference. First operand 32 states and 39 transitions. cyclomatic complexity: 9 Second operand has 22 states, 21 states have (on average 2.142857142857143) internal successors, (45), 22 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:11,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:11,099 INFO L93 Difference]: Finished difference Result 48 states and 58 transitions. [2021-11-07 08:32:11,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-07 08:32:11,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 58 transitions. [2021-11-07 08:32:11,100 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:11,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 48 states and 58 transitions. [2021-11-07 08:32:11,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2021-11-07 08:32:11,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2021-11-07 08:32:11,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 58 transitions. [2021-11-07 08:32:11,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:11,102 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 58 transitions. [2021-11-07 08:32:11,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 58 transitions. [2021-11-07 08:32:11,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 38. [2021-11-07 08:32:11,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.236842105263158) internal successors, (47), 37 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:11,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 47 transitions. [2021-11-07 08:32:11,105 INFO L704 BuchiCegarLoop]: Abstraction has 38 states and 47 transitions. [2021-11-07 08:32:11,105 INFO L587 BuchiCegarLoop]: Abstraction has 38 states and 47 transitions. [2021-11-07 08:32:11,105 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 08:32:11,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 47 transitions. [2021-11-07 08:32:11,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:11,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:11,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:11,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:11,107 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:11,107 INFO L791 eck$LassoCheckResult]: Stem: 2141#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2142#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 2149#L367 assume !(main_~length~0 < 1); 2143#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 2144#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 2145#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2150#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2167#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2151#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2152#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2153#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2155#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2166#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2165#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2164#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2163#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2162#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2161#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2160#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2159#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2156#L370-3 assume !(main_~i~0 < main_~length~0); 2157#L370-4 main_~j~0 := 0; 2176#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2148#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2147#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2154#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2175#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2174#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2173#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2172#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2171#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2170#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2169#L378-2 [2021-11-07 08:32:11,107 INFO L793 eck$LassoCheckResult]: Loop: 2169#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2168#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 2169#L378-2 [2021-11-07 08:32:11,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:11,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1818713675, now seen corresponding path program 12 times [2021-11-07 08:32:11,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:11,108 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279483117] [2021-11-07 08:32:11,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:11,108 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:11,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:11,126 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:11,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:11,145 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:11,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:11,146 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 16 times [2021-11-07 08:32:11,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:11,146 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123314400] [2021-11-07 08:32:11,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:11,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:11,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:11,151 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:11,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:11,154 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:11,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:11,154 INFO L85 PathProgramCache]: Analyzing trace with hash 267849144, now seen corresponding path program 12 times [2021-11-07 08:32:11,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:11,155 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994476674] [2021-11-07 08:32:11,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:11,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:11,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:11,277 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:11,278 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:11,278 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994476674] [2021-11-07 08:32:11,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994476674] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:11,278 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [920380340] [2021-11-07 08:32:11,278 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:32:11,278 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:11,279 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:11,293 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:11,300 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-07 08:32:11,573 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2021-11-07 08:32:11,573 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:11,574 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-07 08:32:11,575 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:11,818 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:11,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [920380340] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:11,819 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:11,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 22 [2021-11-07 08:32:11,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104576198] [2021-11-07 08:32:11,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:11,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-07 08:32:11,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=352, Unknown=0, NotChecked=0, Total=462 [2021-11-07 08:32:11,870 INFO L87 Difference]: Start difference. First operand 38 states and 47 transitions. cyclomatic complexity: 11 Second operand has 22 states, 22 states have (on average 2.272727272727273) internal successors, (50), 22 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:12,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:12,047 INFO L93 Difference]: Finished difference Result 49 states and 58 transitions. [2021-11-07 08:32:12,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-07 08:32:12,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 58 transitions. [2021-11-07 08:32:12,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:12,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 37 states and 46 transitions. [2021-11-07 08:32:12,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-07 08:32:12,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-07 08:32:12,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 46 transitions. [2021-11-07 08:32:12,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:12,050 INFO L681 BuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2021-11-07 08:32:12,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 46 transitions. [2021-11-07 08:32:12,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 35. [2021-11-07 08:32:12,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.2285714285714286) internal successors, (43), 34 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:12,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 43 transitions. [2021-11-07 08:32:12,052 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 43 transitions. [2021-11-07 08:32:12,052 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 43 transitions. [2021-11-07 08:32:12,053 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 08:32:12,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 43 transitions. [2021-11-07 08:32:12,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:12,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:12,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:12,054 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:12,054 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:12,054 INFO L791 eck$LassoCheckResult]: Stem: 2368#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2369#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 2377#L367 assume !(main_~length~0 < 1); 2370#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 2371#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 2372#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2378#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2396#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2379#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2380#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2381#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2383#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2395#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2394#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2393#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2392#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2391#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2390#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2389#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2388#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2387#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2385#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2386#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2384#L370-3 assume !(main_~i~0 < main_~length~0); 2373#L370-4 main_~j~0 := 0; 2374#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2375#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2376#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2382#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2402#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2401#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2400#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2399#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2398#L378-2 [2021-11-07 08:32:12,054 INFO L793 eck$LassoCheckResult]: Loop: 2398#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2397#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 2398#L378-2 [2021-11-07 08:32:12,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:12,055 INFO L85 PathProgramCache]: Analyzing trace with hash -43440278, now seen corresponding path program 13 times [2021-11-07 08:32:12,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:12,055 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721446230] [2021-11-07 08:32:12,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:12,055 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:12,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:12,074 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:12,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:12,093 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:12,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:12,094 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 17 times [2021-11-07 08:32:12,094 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:12,094 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65802042] [2021-11-07 08:32:12,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:12,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:12,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:12,099 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:12,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:12,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:12,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:12,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567149, now seen corresponding path program 13 times [2021-11-07 08:32:12,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:12,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768391610] [2021-11-07 08:32:12,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:12,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:12,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:12,343 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:12,343 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:12,344 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768391610] [2021-11-07 08:32:12,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768391610] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:12,344 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [170789604] [2021-11-07 08:32:12,344 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:32:12,344 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:12,344 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:12,350 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:12,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-07 08:32:12,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:12,671 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 31 conjunts are in the unsatisfiable core [2021-11-07 08:32:12,672 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:12,868 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:12,984 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:12,984 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:13,252 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:13,255 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:13,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [170789604] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:13,255 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:13,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17] total 31 [2021-11-07 08:32:13,256 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168918896] [2021-11-07 08:32:13,291 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:13,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-07 08:32:13,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=881, Unknown=0, NotChecked=0, Total=992 [2021-11-07 08:32:13,298 INFO L87 Difference]: Start difference. First operand 35 states and 43 transitions. cyclomatic complexity: 10 Second operand has 32 states, 31 states have (on average 2.129032258064516) internal successors, (66), 32 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:13,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:13,751 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2021-11-07 08:32:13,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-07 08:32:13,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 45 transitions. [2021-11-07 08:32:13,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:13,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 37 states and 45 transitions. [2021-11-07 08:32:13,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-07 08:32:13,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-07 08:32:13,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 45 transitions. [2021-11-07 08:32:13,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:13,753 INFO L681 BuchiCegarLoop]: Abstraction has 37 states and 45 transitions. [2021-11-07 08:32:13,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 45 transitions. [2021-11-07 08:32:13,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2021-11-07 08:32:13,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 36 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:13,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 45 transitions. [2021-11-07 08:32:13,755 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 45 transitions. [2021-11-07 08:32:13,755 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 45 transitions. [2021-11-07 08:32:13,755 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 08:32:13,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 45 transitions. [2021-11-07 08:32:13,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:13,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:13,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:13,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:13,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:13,757 INFO L791 eck$LassoCheckResult]: Stem: 2593#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2594#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 2602#L367 assume !(main_~length~0 < 1); 2595#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 2596#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 2597#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2603#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2621#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2604#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2605#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2606#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2608#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2620#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2619#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2618#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2617#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2616#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2615#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2614#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2613#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2612#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2610#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2611#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2609#L370-3 assume !(main_~i~0 < main_~length~0); 2598#L370-4 main_~j~0 := 0; 2599#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2600#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2601#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2607#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2629#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2628#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2627#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2626#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2625#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2624#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2623#L378-2 [2021-11-07 08:32:13,757 INFO L793 eck$LassoCheckResult]: Loop: 2623#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2622#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 2623#L378-2 [2021-11-07 08:32:13,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:13,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1203567151, now seen corresponding path program 14 times [2021-11-07 08:32:13,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:13,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605926664] [2021-11-07 08:32:13,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:13,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:13,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:13,807 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:13,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:13,836 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:13,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:13,836 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 18 times [2021-11-07 08:32:13,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:13,837 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245779952] [2021-11-07 08:32:13,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:13,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:13,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:13,841 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:13,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:13,847 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:13,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:13,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1281830834, now seen corresponding path program 14 times [2021-11-07 08:32:13,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:13,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655654127] [2021-11-07 08:32:13,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:13,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:13,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:14,104 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:14,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:14,105 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655654127] [2021-11-07 08:32:14,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655654127] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:14,105 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [17742801] [2021-11-07 08:32:14,105 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:14,105 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:14,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:14,111 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:14,117 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-07 08:32:14,445 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:14,445 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:14,447 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-07 08:32:14,448 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:14,579 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:14,861 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:14,864 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:14,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [17742801] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:14,864 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:14,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16] total 23 [2021-11-07 08:32:14,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554665058] [2021-11-07 08:32:14,907 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:14,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-07 08:32:14,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2021-11-07 08:32:14,908 INFO L87 Difference]: Start difference. First operand 37 states and 45 transitions. cyclomatic complexity: 10 Second operand has 24 states, 23 states have (on average 2.1739130434782608) internal successors, (50), 24 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:15,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:15,315 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2021-11-07 08:32:15,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-07 08:32:15,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 66 transitions. [2021-11-07 08:32:15,316 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:15,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 66 transitions. [2021-11-07 08:32:15,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2021-11-07 08:32:15,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34 [2021-11-07 08:32:15,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 66 transitions. [2021-11-07 08:32:15,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:15,317 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 66 transitions. [2021-11-07 08:32:15,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 66 transitions. [2021-11-07 08:32:15,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 43. [2021-11-07 08:32:15,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.2325581395348837) internal successors, (53), 42 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:15,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 53 transitions. [2021-11-07 08:32:15,320 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 53 transitions. [2021-11-07 08:32:15,320 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 53 transitions. [2021-11-07 08:32:15,320 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 08:32:15,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 53 transitions. [2021-11-07 08:32:15,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:15,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:15,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:15,321 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:15,322 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:15,322 INFO L791 eck$LassoCheckResult]: Stem: 2824#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2825#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 2832#L367 assume !(main_~length~0 < 1); 2826#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 2827#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 2828#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2833#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2853#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2834#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2835#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2837#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2838#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2852#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2851#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2850#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2849#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2848#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2847#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2846#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2845#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2844#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 2843#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 2842#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 2839#L370-3 assume !(main_~i~0 < main_~length~0); 2840#L370-4 main_~j~0 := 0; 2864#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2829#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2830#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2836#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2863#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2862#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2861#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2860#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2859#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2858#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2857#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2856#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 2855#L378-2 [2021-11-07 08:32:15,322 INFO L793 eck$LassoCheckResult]: Loop: 2855#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 2854#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 2855#L378-2 [2021-11-07 08:32:15,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:15,323 INFO L85 PathProgramCache]: Analyzing trace with hash 1281830836, now seen corresponding path program 15 times [2021-11-07 08:32:15,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:15,323 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101128158] [2021-11-07 08:32:15,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:15,323 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:15,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:15,343 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:15,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:15,364 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:15,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:15,365 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 19 times [2021-11-07 08:32:15,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:15,365 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349620316] [2021-11-07 08:32:15,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:15,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:15,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:15,370 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:15,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:15,372 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:15,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:15,373 INFO L85 PathProgramCache]: Analyzing trace with hash -816179209, now seen corresponding path program 15 times [2021-11-07 08:32:15,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:15,373 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054436603] [2021-11-07 08:32:15,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:15,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:15,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:15,510 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 31 proven. 62 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:15,511 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:15,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054436603] [2021-11-07 08:32:15,511 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054436603] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:15,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [817972697] [2021-11-07 08:32:15,512 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:32:15,512 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:15,512 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:15,516 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:15,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-07 08:32:15,948 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2021-11-07 08:32:15,948 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:15,950 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-07 08:32:15,951 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:16,244 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 42 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:16,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [817972697] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:16,244 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:16,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 25 [2021-11-07 08:32:16,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831427202] [2021-11-07 08:32:16,292 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:16,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-07 08:32:16,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=459, Unknown=0, NotChecked=0, Total=600 [2021-11-07 08:32:16,293 INFO L87 Difference]: Start difference. First operand 43 states and 53 transitions. cyclomatic complexity: 12 Second operand has 25 states, 25 states have (on average 2.28) internal successors, (57), 25 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:16,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:16,451 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2021-11-07 08:32:16,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-07 08:32:16,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 66 transitions. [2021-11-07 08:32:16,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:16,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 42 states and 52 transitions. [2021-11-07 08:32:16,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-07 08:32:16,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-07 08:32:16,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 52 transitions. [2021-11-07 08:32:16,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:16,453 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 52 transitions. [2021-11-07 08:32:16,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 52 transitions. [2021-11-07 08:32:16,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 40. [2021-11-07 08:32:16,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.225) internal successors, (49), 39 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:16,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 49 transitions. [2021-11-07 08:32:16,455 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 49 transitions. [2021-11-07 08:32:16,456 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 49 transitions. [2021-11-07 08:32:16,456 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 08:32:16,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 49 transitions. [2021-11-07 08:32:16,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:16,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:16,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:16,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:16,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:16,458 INFO L791 eck$LassoCheckResult]: Stem: 3083#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3084#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 3092#L367 assume !(main_~length~0 < 1); 3085#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 3086#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 3087#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3093#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3114#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3094#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3095#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3097#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3098#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3113#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3112#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3111#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3110#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3109#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3108#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3107#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3106#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3105#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3104#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3103#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3102#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3100#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3101#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3099#L370-3 assume !(main_~i~0 < main_~length~0); 3090#L370-4 main_~j~0 := 0; 3091#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3088#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3089#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3096#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3122#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3121#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3120#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3119#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3118#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3117#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3116#L378-2 [2021-11-07 08:32:16,458 INFO L793 eck$LassoCheckResult]: Loop: 3116#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3115#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 3116#L378-2 [2021-11-07 08:32:16,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:16,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1722738827, now seen corresponding path program 16 times [2021-11-07 08:32:16,459 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:16,459 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882855295] [2021-11-07 08:32:16,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:16,459 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:16,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:16,479 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:16,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:16,499 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:16,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:16,499 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 20 times [2021-11-07 08:32:16,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:16,500 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44281580] [2021-11-07 08:32:16,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:16,500 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:16,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:16,505 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:16,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:16,507 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:16,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:16,507 INFO L85 PathProgramCache]: Analyzing trace with hash -1989602440, now seen corresponding path program 16 times [2021-11-07 08:32:16,507 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:16,508 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211245947] [2021-11-07 08:32:16,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:16,508 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:16,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:16,798 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:16,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:16,799 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211245947] [2021-11-07 08:32:16,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211245947] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:16,799 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [502665340] [2021-11-07 08:32:16,799 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:32:16,799 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:16,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:16,800 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:16,801 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-07 08:32:17,113 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:32:17,113 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:17,115 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-07 08:32:17,116 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:17,365 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:17,495 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:17,496 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:17,847 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:17,851 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:17,851 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [502665340] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:17,851 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:17,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19] total 35 [2021-11-07 08:32:17,852 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801614852] [2021-11-07 08:32:17,898 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:17,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-07 08:32:17,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=1135, Unknown=0, NotChecked=0, Total=1260 [2021-11-07 08:32:17,899 INFO L87 Difference]: Start difference. First operand 40 states and 49 transitions. cyclomatic complexity: 11 Second operand has 36 states, 35 states have (on average 2.1714285714285713) internal successors, (76), 36 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:18,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:18,721 INFO L93 Difference]: Finished difference Result 42 states and 51 transitions. [2021-11-07 08:32:18,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-07 08:32:18,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 51 transitions. [2021-11-07 08:32:18,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:18,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 42 states and 51 transitions. [2021-11-07 08:32:18,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-07 08:32:18,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-07 08:32:18,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 51 transitions. [2021-11-07 08:32:18,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:18,723 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 51 transitions. [2021-11-07 08:32:18,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 51 transitions. [2021-11-07 08:32:18,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2021-11-07 08:32:18,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2142857142857142) internal successors, (51), 41 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:18,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 51 transitions. [2021-11-07 08:32:18,726 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 51 transitions. [2021-11-07 08:32:18,726 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 51 transitions. [2021-11-07 08:32:18,726 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-07 08:32:18,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 51 transitions. [2021-11-07 08:32:18,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:18,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:18,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:18,728 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:18,728 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:18,728 INFO L791 eck$LassoCheckResult]: Stem: 3339#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3340#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 3348#L367 assume !(main_~length~0 < 1); 3341#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 3342#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 3343#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3349#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3370#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3350#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3351#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3353#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3354#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3369#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3368#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3367#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3366#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3365#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3364#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3363#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3362#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3361#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3360#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3359#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3358#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3356#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3357#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3355#L370-3 assume !(main_~i~0 < main_~length~0); 3346#L370-4 main_~j~0 := 0; 3347#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3344#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3345#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3352#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3380#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3379#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3378#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3377#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3376#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3375#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3374#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3373#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3372#L378-2 [2021-11-07 08:32:18,728 INFO L793 eck$LassoCheckResult]: Loop: 3372#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3371#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 3372#L378-2 [2021-11-07 08:32:18,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:18,729 INFO L85 PathProgramCache]: Analyzing trace with hash -1989602438, now seen corresponding path program 17 times [2021-11-07 08:32:18,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:18,729 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029208071] [2021-11-07 08:32:18,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:18,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:18,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:18,750 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:18,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:18,789 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:18,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:18,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 21 times [2021-11-07 08:32:18,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:18,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834433535] [2021-11-07 08:32:18,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:18,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:18,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:18,821 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:18,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:18,833 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:18,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:18,837 INFO L85 PathProgramCache]: Analyzing trace with hash -747494851, now seen corresponding path program 17 times [2021-11-07 08:32:18,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:18,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908531110] [2021-11-07 08:32:18,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:18,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:18,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:19,123 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:19,123 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:19,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908531110] [2021-11-07 08:32:19,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908531110] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:19,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2090262133] [2021-11-07 08:32:19,125 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:32:19,126 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:19,126 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:19,128 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:19,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-07 08:32:19,511 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2021-11-07 08:32:19,511 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:19,513 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-07 08:32:19,514 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:19,660 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:20,027 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:20,029 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:20,029 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2090262133] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:20,030 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:20,030 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 27 [2021-11-07 08:32:20,030 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610238337] [2021-11-07 08:32:20,072 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:20,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-07 08:32:20,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=684, Unknown=0, NotChecked=0, Total=756 [2021-11-07 08:32:20,073 INFO L87 Difference]: Start difference. First operand 42 states and 51 transitions. cyclomatic complexity: 11 Second operand has 28 states, 27 states have (on average 2.185185185185185) internal successors, (59), 28 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:20,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:20,648 INFO L93 Difference]: Finished difference Result 62 states and 74 transitions. [2021-11-07 08:32:20,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-07 08:32:20,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 74 transitions. [2021-11-07 08:32:20,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:20,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 62 states and 74 transitions. [2021-11-07 08:32:20,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38 [2021-11-07 08:32:20,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38 [2021-11-07 08:32:20,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 74 transitions. [2021-11-07 08:32:20,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:20,651 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 74 transitions. [2021-11-07 08:32:20,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 74 transitions. [2021-11-07 08:32:20,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 48. [2021-11-07 08:32:20,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.2291666666666667) internal successors, (59), 47 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:20,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 59 transitions. [2021-11-07 08:32:20,653 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 59 transitions. [2021-11-07 08:32:20,653 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 59 transitions. [2021-11-07 08:32:20,653 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-07 08:32:20,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 59 transitions. [2021-11-07 08:32:20,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:20,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:20,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:20,655 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:20,655 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:20,655 INFO L791 eck$LassoCheckResult]: Stem: 3601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3602#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 3609#L367 assume !(main_~length~0 < 1); 3603#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 3604#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 3605#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3610#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3633#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3611#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3612#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3614#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3615#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3632#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3631#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3630#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3629#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3628#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3627#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3626#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3625#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3624#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3623#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3622#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3621#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3620#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3619#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3616#L370-3 assume !(main_~i~0 < main_~length~0); 3617#L370-4 main_~j~0 := 0; 3646#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3606#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3607#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3613#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3645#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3644#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3643#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3642#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3641#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3640#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3639#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3638#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3637#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3636#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3635#L378-2 [2021-11-07 08:32:20,656 INFO L793 eck$LassoCheckResult]: Loop: 3635#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3634#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 3635#L378-2 [2021-11-07 08:32:20,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:20,656 INFO L85 PathProgramCache]: Analyzing trace with hash -747494849, now seen corresponding path program 18 times [2021-11-07 08:32:20,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:20,656 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109198924] [2021-11-07 08:32:20,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:20,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:20,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:20,695 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:20,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:20,726 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:20,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:20,727 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 22 times [2021-11-07 08:32:20,728 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:20,728 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739067590] [2021-11-07 08:32:20,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:20,728 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:20,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:20,735 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:20,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:20,737 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:20,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:20,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1083010110, now seen corresponding path program 18 times [2021-11-07 08:32:20,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:20,739 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157059048] [2021-11-07 08:32:20,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:20,739 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:20,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:20,924 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 43 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:20,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:20,924 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157059048] [2021-11-07 08:32:20,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157059048] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:20,925 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1267687174] [2021-11-07 08:32:20,925 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:32:20,925 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:20,925 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:20,926 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:20,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-07 08:32:21,392 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2021-11-07 08:32:21,392 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:21,394 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-07 08:32:21,395 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:21,789 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 56 proven. 70 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:21,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1267687174] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:21,789 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:21,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 28 [2021-11-07 08:32:21,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174126316] [2021-11-07 08:32:21,839 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:21,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-07 08:32:21,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=580, Unknown=0, NotChecked=0, Total=756 [2021-11-07 08:32:21,840 INFO L87 Difference]: Start difference. First operand 48 states and 59 transitions. cyclomatic complexity: 13 Second operand has 28 states, 28 states have (on average 2.2857142857142856) internal successors, (64), 28 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:22,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:22,027 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2021-11-07 08:32:22,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-07 08:32:22,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2021-11-07 08:32:22,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:22,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 47 states and 58 transitions. [2021-11-07 08:32:22,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-07 08:32:22,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-07 08:32:22,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2021-11-07 08:32:22,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:22,028 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 58 transitions. [2021-11-07 08:32:22,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2021-11-07 08:32:22,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2021-11-07 08:32:22,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 44 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:22,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 55 transitions. [2021-11-07 08:32:22,030 INFO L704 BuchiCegarLoop]: Abstraction has 45 states and 55 transitions. [2021-11-07 08:32:22,030 INFO L587 BuchiCegarLoop]: Abstraction has 45 states and 55 transitions. [2021-11-07 08:32:22,031 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-07 08:32:22,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 55 transitions. [2021-11-07 08:32:22,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:22,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:22,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:22,032 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:22,032 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:22,032 INFO L791 eck$LassoCheckResult]: Stem: 3892#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3893#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 3901#L367 assume !(main_~length~0 < 1); 3894#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 3895#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 3896#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3902#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3926#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3903#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3904#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3905#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3907#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3925#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3924#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3923#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3922#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3921#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3920#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3919#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3918#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3917#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3916#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3915#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3914#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3913#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3912#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3911#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 3909#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 3910#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 3908#L370-3 assume !(main_~i~0 < main_~length~0); 3897#L370-4 main_~j~0 := 0; 3898#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3899#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3900#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3906#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3936#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3935#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3934#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3933#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3932#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3931#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3930#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3929#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 3928#L378-2 [2021-11-07 08:32:22,033 INFO L793 eck$LassoCheckResult]: Loop: 3928#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 3927#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 3928#L378-2 [2021-11-07 08:32:22,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:22,033 INFO L85 PathProgramCache]: Analyzing trace with hash 139612660, now seen corresponding path program 19 times [2021-11-07 08:32:22,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:22,034 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631526829] [2021-11-07 08:32:22,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:22,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:22,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:22,057 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:22,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:22,085 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:22,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:22,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 23 times [2021-11-07 08:32:22,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:22,086 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362477432] [2021-11-07 08:32:22,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:22,086 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:22,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:22,091 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:22,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:22,094 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:22,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:22,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1023781431, now seen corresponding path program 19 times [2021-11-07 08:32:22,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:22,095 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190603801] [2021-11-07 08:32:22,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:22,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:22,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:22,513 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:22,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:22,514 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190603801] [2021-11-07 08:32:22,514 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190603801] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:22,514 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [594198165] [2021-11-07 08:32:22,514 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:32:22,514 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:22,515 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:22,517 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:22,533 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-07 08:32:23,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:23,011 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 39 conjunts are in the unsatisfiable core [2021-11-07 08:32:23,012 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:23,296 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:23,420 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:23,421 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:23,800 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:23,802 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:23,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [594198165] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:23,802 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:23,802 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21] total 39 [2021-11-07 08:32:23,803 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193486513] [2021-11-07 08:32:23,839 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:23,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-07 08:32:23,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=139, Invalid=1421, Unknown=0, NotChecked=0, Total=1560 [2021-11-07 08:32:23,840 INFO L87 Difference]: Start difference. First operand 45 states and 55 transitions. cyclomatic complexity: 12 Second operand has 40 states, 39 states have (on average 2.2051282051282053) internal successors, (86), 40 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:24,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:24,492 INFO L93 Difference]: Finished difference Result 47 states and 57 transitions. [2021-11-07 08:32:24,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-07 08:32:24,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 57 transitions. [2021-11-07 08:32:24,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:24,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 57 transitions. [2021-11-07 08:32:24,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-07 08:32:24,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-07 08:32:24,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 57 transitions. [2021-11-07 08:32:24,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:24,495 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 57 transitions. [2021-11-07 08:32:24,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 57 transitions. [2021-11-07 08:32:24,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2021-11-07 08:32:24,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.2127659574468086) internal successors, (57), 46 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:24,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 57 transitions. [2021-11-07 08:32:24,497 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 57 transitions. [2021-11-07 08:32:24,497 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 57 transitions. [2021-11-07 08:32:24,497 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-07 08:32:24,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 57 transitions. [2021-11-07 08:32:24,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:24,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:24,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:24,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:24,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:24,499 INFO L791 eck$LassoCheckResult]: Stem: 4179#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4180#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 4188#L367 assume !(main_~length~0 < 1); 4181#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 4182#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 4183#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4189#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4213#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4190#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4191#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4193#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4194#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4212#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4211#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4210#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4209#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4208#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4207#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4206#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4205#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4204#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4203#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4202#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4201#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4200#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4199#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4198#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4196#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4197#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4195#L370-3 assume !(main_~i~0 < main_~length~0); 4186#L370-4 main_~j~0 := 0; 4187#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4184#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4185#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4192#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4225#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4224#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4223#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4222#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4221#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4220#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4219#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4218#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4217#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4216#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4215#L378-2 [2021-11-07 08:32:24,499 INFO L793 eck$LassoCheckResult]: Loop: 4215#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4214#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 4215#L378-2 [2021-11-07 08:32:24,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:24,500 INFO L85 PathProgramCache]: Analyzing trace with hash 1023781433, now seen corresponding path program 20 times [2021-11-07 08:32:24,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:24,500 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114054066] [2021-11-07 08:32:24,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:24,501 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:24,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:24,530 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:24,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:24,559 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:24,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:24,560 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 24 times [2021-11-07 08:32:24,560 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:24,560 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855668543] [2021-11-07 08:32:24,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:24,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:24,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:24,570 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:24,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:24,572 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:24,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:24,573 INFO L85 PathProgramCache]: Analyzing trace with hash 306447676, now seen corresponding path program 20 times [2021-11-07 08:32:24,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:24,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319731754] [2021-11-07 08:32:24,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:24,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:24,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:24,984 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:24,985 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:24,985 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319731754] [2021-11-07 08:32:24,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319731754] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:24,985 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1945111174] [2021-11-07 08:32:24,985 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:24,985 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:24,985 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:24,987 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:25,003 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-07 08:32:25,503 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:25,503 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:25,505 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 37 conjunts are in the unsatisfiable core [2021-11-07 08:32:25,506 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:25,641 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:25,960 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:25,962 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:25,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1945111174] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:25,962 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:25,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20] total 29 [2021-11-07 08:32:25,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122184629] [2021-11-07 08:32:26,009 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:26,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-07 08:32:26,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=794, Unknown=0, NotChecked=0, Total=870 [2021-11-07 08:32:26,010 INFO L87 Difference]: Start difference. First operand 47 states and 57 transitions. cyclomatic complexity: 12 Second operand has 30 states, 29 states have (on average 2.206896551724138) internal successors, (64), 30 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:26,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:26,460 INFO L93 Difference]: Finished difference Result 69 states and 82 transitions. [2021-11-07 08:32:26,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-07 08:32:26,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 82 transitions. [2021-11-07 08:32:26,461 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:26,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 69 states and 82 transitions. [2021-11-07 08:32:26,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2021-11-07 08:32:26,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2021-11-07 08:32:26,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 82 transitions. [2021-11-07 08:32:26,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:26,462 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 82 transitions. [2021-11-07 08:32:26,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 82 transitions. [2021-11-07 08:32:26,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 53. [2021-11-07 08:32:26,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.2264150943396226) internal successors, (65), 52 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:26,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 65 transitions. [2021-11-07 08:32:26,463 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 65 transitions. [2021-11-07 08:32:26,464 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 65 transitions. [2021-11-07 08:32:26,464 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-07 08:32:26,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 65 transitions. [2021-11-07 08:32:26,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:26,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:26,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:26,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:26,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:26,465 INFO L791 eck$LassoCheckResult]: Stem: 4470#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4471#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 4478#L367 assume !(main_~length~0 < 1); 4472#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 4473#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 4474#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4479#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4505#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4480#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4481#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4482#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4484#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4504#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4503#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4502#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4501#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4500#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4499#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4498#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4497#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4496#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4495#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4494#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4493#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4492#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4491#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4490#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4489#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4488#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4485#L370-3 assume !(main_~i~0 < main_~length~0); 4486#L370-4 main_~j~0 := 0; 4520#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4477#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4476#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4483#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4519#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4518#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4517#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4516#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4515#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4514#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4513#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4512#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4511#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4510#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4509#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4508#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4507#L378-2 [2021-11-07 08:32:26,465 INFO L793 eck$LassoCheckResult]: Loop: 4507#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4506#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 4507#L378-2 [2021-11-07 08:32:26,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:26,466 INFO L85 PathProgramCache]: Analyzing trace with hash 306447678, now seen corresponding path program 21 times [2021-11-07 08:32:26,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:26,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110451178] [2021-11-07 08:32:26,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:26,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:26,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:26,523 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:26,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:26,555 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:26,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:26,556 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 25 times [2021-11-07 08:32:26,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:26,556 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012060672] [2021-11-07 08:32:26,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:26,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:26,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:26,576 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:26,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:26,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:26,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:26,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1856523519, now seen corresponding path program 21 times [2021-11-07 08:32:26,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:26,580 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161768183] [2021-11-07 08:32:26,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:26,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:26,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:26,809 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 57 proven. 107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:26,809 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:26,809 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161768183] [2021-11-07 08:32:26,809 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161768183] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:26,810 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1997867278] [2021-11-07 08:32:26,810 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:32:26,810 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:26,810 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:26,817 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:26,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-07 08:32:27,377 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2021-11-07 08:32:27,377 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:27,379 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-07 08:32:27,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:27,727 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 72 proven. 92 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:27,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1997867278] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:27,727 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:27,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 31 [2021-11-07 08:32:27,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679336622] [2021-11-07 08:32:27,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:27,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-07 08:32:27,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=215, Invalid=715, Unknown=0, NotChecked=0, Total=930 [2021-11-07 08:32:27,764 INFO L87 Difference]: Start difference. First operand 53 states and 65 transitions. cyclomatic complexity: 14 Second operand has 31 states, 31 states have (on average 2.2903225806451615) internal successors, (71), 31 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:27,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:27,988 INFO L93 Difference]: Finished difference Result 70 states and 82 transitions. [2021-11-07 08:32:27,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-07 08:32:27,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 82 transitions. [2021-11-07 08:32:27,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:27,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 52 states and 64 transitions. [2021-11-07 08:32:27,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-07 08:32:27,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-07 08:32:27,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2021-11-07 08:32:27,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:27,991 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 64 transitions. [2021-11-07 08:32:27,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2021-11-07 08:32:27,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 50. [2021-11-07 08:32:27,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.22) internal successors, (61), 49 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:27,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 61 transitions. [2021-11-07 08:32:27,993 INFO L704 BuchiCegarLoop]: Abstraction has 50 states and 61 transitions. [2021-11-07 08:32:27,993 INFO L587 BuchiCegarLoop]: Abstraction has 50 states and 61 transitions. [2021-11-07 08:32:27,993 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-07 08:32:27,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 61 transitions. [2021-11-07 08:32:27,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:27,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:27,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:27,995 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:27,995 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:27,995 INFO L791 eck$LassoCheckResult]: Stem: 4793#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4794#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 4802#L367 assume !(main_~length~0 < 1); 4795#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 4796#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 4797#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4803#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4830#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4804#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4805#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4806#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4808#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4829#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4828#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4827#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4826#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4825#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4824#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4823#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4822#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4821#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4820#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4819#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4818#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4817#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4816#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4815#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4814#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4813#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4812#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 4810#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 4811#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 4809#L370-3 assume !(main_~i~0 < main_~length~0); 4798#L370-4 main_~j~0 := 0; 4799#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4800#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4801#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4807#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4842#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4841#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4840#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4839#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4838#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4837#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4836#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4835#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4834#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4833#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 4832#L378-2 [2021-11-07 08:32:27,995 INFO L793 eck$LassoCheckResult]: Loop: 4832#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 4831#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 4832#L378-2 [2021-11-07 08:32:27,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:27,996 INFO L85 PathProgramCache]: Analyzing trace with hash 1147299839, now seen corresponding path program 22 times [2021-11-07 08:32:27,996 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:27,996 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777930342] [2021-11-07 08:32:27,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:27,997 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:28,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:28,021 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:28,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:28,074 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:28,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:28,075 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 26 times [2021-11-07 08:32:28,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:28,076 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051049351] [2021-11-07 08:32:28,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:28,076 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:28,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:28,086 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:28,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:28,088 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:28,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:28,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1251448446, now seen corresponding path program 22 times [2021-11-07 08:32:28,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:28,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476495265] [2021-11-07 08:32:28,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:28,091 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:28,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:28,501 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:28,502 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:28,502 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476495265] [2021-11-07 08:32:28,502 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476495265] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:28,502 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998252763] [2021-11-07 08:32:28,502 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:32:28,502 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:28,502 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:28,503 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:28,505 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-07 08:32:28,939 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:32:28,939 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:28,941 INFO L263 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 43 conjunts are in the unsatisfiable core [2021-11-07 08:32:28,942 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:29,306 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:29,486 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:29,486 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:30,017 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:30,024 INFO L134 CoverageAnalysis]: Checked inductivity of 173 backedges. 0 proven. 173 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:30,024 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998252763] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:30,024 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:30,024 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23] total 43 [2021-11-07 08:32:30,025 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975389220] [2021-11-07 08:32:30,065 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:30,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-07 08:32:30,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1739, Unknown=0, NotChecked=0, Total=1892 [2021-11-07 08:32:30,066 INFO L87 Difference]: Start difference. First operand 50 states and 61 transitions. cyclomatic complexity: 13 Second operand has 44 states, 43 states have (on average 2.2325581395348837) internal successors, (96), 44 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:30,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:30,888 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2021-11-07 08:32:30,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-07 08:32:30,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 63 transitions. [2021-11-07 08:32:30,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:30,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 63 transitions. [2021-11-07 08:32:30,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-07 08:32:30,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-07 08:32:30,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 63 transitions. [2021-11-07 08:32:30,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:30,890 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 63 transitions. [2021-11-07 08:32:30,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 63 transitions. [2021-11-07 08:32:30,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2021-11-07 08:32:30,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.2115384615384615) internal successors, (63), 51 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:30,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 63 transitions. [2021-11-07 08:32:30,892 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 63 transitions. [2021-11-07 08:32:30,892 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 63 transitions. [2021-11-07 08:32:30,892 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-07 08:32:30,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 63 transitions. [2021-11-07 08:32:30,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:30,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:30,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:30,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:30,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:30,894 INFO L791 eck$LassoCheckResult]: Stem: 5111#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5112#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 5120#L367 assume !(main_~length~0 < 1); 5113#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 5114#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 5115#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5121#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5148#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5122#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5123#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5124#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5126#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5147#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5146#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5145#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5144#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5143#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5142#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5141#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5140#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5139#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5138#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5137#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5136#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5135#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5134#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5133#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5132#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5131#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5130#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5128#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5129#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5127#L370-3 assume !(main_~i~0 < main_~length~0); 5116#L370-4 main_~j~0 := 0; 5117#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5118#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5119#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5125#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5162#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5161#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5160#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5159#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5158#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5157#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5156#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5155#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5154#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5153#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5152#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5151#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5150#L378-2 [2021-11-07 08:32:30,894 INFO L793 eck$LassoCheckResult]: Loop: 5150#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5149#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 5150#L378-2 [2021-11-07 08:32:30,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:30,894 INFO L85 PathProgramCache]: Analyzing trace with hash -1251448444, now seen corresponding path program 23 times [2021-11-07 08:32:30,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:30,894 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405136449] [2021-11-07 08:32:30,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:30,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:30,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:30,921 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:30,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:30,952 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:30,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:30,953 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 27 times [2021-11-07 08:32:30,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:30,953 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728803828] [2021-11-07 08:32:30,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:30,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:30,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:30,960 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:30,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:30,962 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:30,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:30,963 INFO L85 PathProgramCache]: Analyzing trace with hash -51110457, now seen corresponding path program 23 times [2021-11-07 08:32:30,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:30,963 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067844834] [2021-11-07 08:32:30,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:30,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:30,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:31,456 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:31,456 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:31,456 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067844834] [2021-11-07 08:32:31,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067844834] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:31,457 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1489059084] [2021-11-07 08:32:31,457 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:32:31,457 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:31,457 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:31,469 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:31,475 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-07 08:32:32,109 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-11-07 08:32:32,109 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:32,111 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 41 conjunts are in the unsatisfiable core [2021-11-07 08:32:32,113 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:32,281 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:32,786 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:32,788 INFO L134 CoverageAnalysis]: Checked inductivity of 189 backedges. 0 proven. 189 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:32,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1489059084] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:32,789 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:32,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 33 [2021-11-07 08:32:32,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776172123] [2021-11-07 08:32:32,836 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:32,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-07 08:32:32,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=1034, Unknown=0, NotChecked=0, Total=1122 [2021-11-07 08:32:32,838 INFO L87 Difference]: Start difference. First operand 52 states and 63 transitions. cyclomatic complexity: 13 Second operand has 34 states, 33 states have (on average 2.212121212121212) internal successors, (73), 34 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:33,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:33,453 INFO L93 Difference]: Finished difference Result 76 states and 90 transitions. [2021-11-07 08:32:33,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-07 08:32:33,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76 states and 90 transitions. [2021-11-07 08:32:33,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:33,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76 states to 76 states and 90 transitions. [2021-11-07 08:32:33,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2021-11-07 08:32:33,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2021-11-07 08:32:33,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 90 transitions. [2021-11-07 08:32:33,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:33,456 INFO L681 BuchiCegarLoop]: Abstraction has 76 states and 90 transitions. [2021-11-07 08:32:33,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 90 transitions. [2021-11-07 08:32:33,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 58. [2021-11-07 08:32:33,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2241379310344827) internal successors, (71), 57 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:33,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 71 transitions. [2021-11-07 08:32:33,458 INFO L704 BuchiCegarLoop]: Abstraction has 58 states and 71 transitions. [2021-11-07 08:32:33,458 INFO L587 BuchiCegarLoop]: Abstraction has 58 states and 71 transitions. [2021-11-07 08:32:33,458 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-07 08:32:33,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 71 transitions. [2021-11-07 08:32:33,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:33,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:33,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:33,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:33,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:33,460 INFO L791 eck$LassoCheckResult]: Stem: 5433#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5434#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 5441#L367 assume !(main_~length~0 < 1); 5435#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 5436#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 5437#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5442#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5471#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5443#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5444#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5445#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5447#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5470#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5469#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5468#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5467#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5466#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5465#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5464#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5463#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5462#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5461#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5460#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5459#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5458#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5457#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5456#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5455#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5454#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5453#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5452#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5451#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5448#L370-3 assume !(main_~i~0 < main_~length~0); 5449#L370-4 main_~j~0 := 0; 5488#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5440#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5439#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5446#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5487#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5486#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5485#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5484#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5483#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5482#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5481#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5480#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5479#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5478#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5477#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5476#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5475#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5474#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5473#L378-2 [2021-11-07 08:32:33,461 INFO L793 eck$LassoCheckResult]: Loop: 5473#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5472#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 5473#L378-2 [2021-11-07 08:32:33,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:33,461 INFO L85 PathProgramCache]: Analyzing trace with hash -51110455, now seen corresponding path program 24 times [2021-11-07 08:32:33,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:33,461 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094015095] [2021-11-07 08:32:33,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:33,462 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:33,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:33,492 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:33,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:33,521 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:33,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:33,522 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 28 times [2021-11-07 08:32:33,522 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:33,522 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918653814] [2021-11-07 08:32:33,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:33,523 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:33,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:33,529 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:33,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:33,532 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:33,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:33,532 INFO L85 PathProgramCache]: Analyzing trace with hash -1872505652, now seen corresponding path program 24 times [2021-11-07 08:32:33,533 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:33,533 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249531921] [2021-11-07 08:32:33,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:33,533 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:33,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:33,796 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 73 proven. 134 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:33,796 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:33,796 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249531921] [2021-11-07 08:32:33,796 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249531921] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:33,796 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1284311128] [2021-11-07 08:32:33,796 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:32:33,797 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:33,797 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:33,802 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:33,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-07 08:32:34,609 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2021-11-07 08:32:34,609 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:34,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-07 08:32:34,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:34,723 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:35,647 INFO L354 Elim1Store]: treesize reduction 15, result has 6.3 percent of original size [2021-11-07 08:32:35,649 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 18 [2021-11-07 08:32:35,654 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 90 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:35,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1284311128] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:35,655 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:35,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 25] total 38 [2021-11-07 08:32:35,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43511272] [2021-11-07 08:32:35,695 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:35,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-07 08:32:35,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=282, Invalid=1124, Unknown=0, NotChecked=0, Total=1406 [2021-11-07 08:32:35,696 INFO L87 Difference]: Start difference. First operand 58 states and 71 transitions. cyclomatic complexity: 15 Second operand has 38 states, 38 states have (on average 2.1578947368421053) internal successors, (82), 38 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:38,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:38,582 INFO L93 Difference]: Finished difference Result 77 states and 90 transitions. [2021-11-07 08:32:38,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-07 08:32:38,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 90 transitions. [2021-11-07 08:32:38,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:38,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 57 states and 70 transitions. [2021-11-07 08:32:38,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-07 08:32:38,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-07 08:32:38,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 70 transitions. [2021-11-07 08:32:38,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:38,584 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 70 transitions. [2021-11-07 08:32:38,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 70 transitions. [2021-11-07 08:32:38,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 55. [2021-11-07 08:32:38,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 54 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:38,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 67 transitions. [2021-11-07 08:32:38,586 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 67 transitions. [2021-11-07 08:32:38,586 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 67 transitions. [2021-11-07 08:32:38,586 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-07 08:32:38,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 67 transitions. [2021-11-07 08:32:38,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:38,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:38,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:38,588 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:38,588 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:38,588 INFO L791 eck$LassoCheckResult]: Stem: 5840#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5841#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 5849#L367 assume !(main_~length~0 < 1); 5842#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 5843#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 5844#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5850#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5880#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5851#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5852#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5853#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5855#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5879#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5878#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5877#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5876#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5875#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5874#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5873#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5872#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5871#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5870#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5869#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5868#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5867#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5866#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5865#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5864#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5863#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5862#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5861#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5860#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5859#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 5857#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 5858#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 5856#L370-3 assume !(main_~i~0 < main_~length~0); 5845#L370-4 main_~j~0 := 0; 5846#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5847#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5848#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5854#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5894#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5893#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5892#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5891#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5890#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5889#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5888#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5887#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5886#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5885#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5884#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5883#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 5882#L378-2 [2021-11-07 08:32:38,588 INFO L793 eck$LassoCheckResult]: Loop: 5882#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 5881#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 5882#L378-2 [2021-11-07 08:32:38,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:38,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1118218370, now seen corresponding path program 25 times [2021-11-07 08:32:38,589 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:38,589 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135895929] [2021-11-07 08:32:38,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:38,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:38,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:38,630 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:38,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:38,663 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:38,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:38,664 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 29 times [2021-11-07 08:32:38,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:38,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920243496] [2021-11-07 08:32:38,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:38,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:38,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:38,707 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:38,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:38,709 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:38,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:38,709 INFO L85 PathProgramCache]: Analyzing trace with hash -866028223, now seen corresponding path program 25 times [2021-11-07 08:32:38,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:38,709 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088263692] [2021-11-07 08:32:38,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:38,710 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:38,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:39,158 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:39,158 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:39,159 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088263692] [2021-11-07 08:32:39,159 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088263692] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:39,159 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1399634268] [2021-11-07 08:32:39,159 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:32:39,159 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:39,159 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:39,161 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:39,178 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-07 08:32:39,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:39,711 INFO L263 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-07 08:32:39,712 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:40,081 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:40,211 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:40,211 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:40,680 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:40,682 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 0 proven. 217 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:40,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1399634268] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:40,683 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:40,683 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25] total 47 [2021-11-07 08:32:40,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37162838] [2021-11-07 08:32:40,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:40,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-11-07 08:32:40,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=2089, Unknown=0, NotChecked=0, Total=2256 [2021-11-07 08:32:40,717 INFO L87 Difference]: Start difference. First operand 55 states and 67 transitions. cyclomatic complexity: 14 Second operand has 48 states, 47 states have (on average 2.25531914893617) internal successors, (106), 48 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:41,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:41,726 INFO L93 Difference]: Finished difference Result 57 states and 69 transitions. [2021-11-07 08:32:41,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-07 08:32:41,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2021-11-07 08:32:41,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:41,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 69 transitions. [2021-11-07 08:32:41,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2021-11-07 08:32:41,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2021-11-07 08:32:41,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 69 transitions. [2021-11-07 08:32:41,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:41,728 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 69 transitions. [2021-11-07 08:32:41,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 69 transitions. [2021-11-07 08:32:41,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2021-11-07 08:32:41,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.2105263157894737) internal successors, (69), 56 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:41,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 69 transitions. [2021-11-07 08:32:41,730 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 69 transitions. [2021-11-07 08:32:41,730 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 69 transitions. [2021-11-07 08:32:41,730 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-07 08:32:41,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 69 transitions. [2021-11-07 08:32:41,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:41,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:41,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:41,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:41,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:41,732 INFO L791 eck$LassoCheckResult]: Stem: 6189#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 6190#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 6198#L367 assume !(main_~length~0 < 1); 6191#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 6192#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 6193#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6199#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6229#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6200#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6201#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6202#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6204#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6228#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6227#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6226#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6225#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6224#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6223#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6222#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6221#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6220#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6219#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6218#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6217#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6216#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6215#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6214#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6213#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6212#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6211#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6210#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6209#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6208#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6206#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6207#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6205#L370-3 assume !(main_~i~0 < main_~length~0); 6194#L370-4 main_~j~0 := 0; 6195#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6196#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6197#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6203#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6245#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6244#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6243#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6242#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6241#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6240#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6239#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6238#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6237#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6236#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6235#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6234#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6233#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6232#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6231#L378-2 [2021-11-07 08:32:41,732 INFO L793 eck$LassoCheckResult]: Loop: 6231#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6230#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 6231#L378-2 [2021-11-07 08:32:41,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:41,732 INFO L85 PathProgramCache]: Analyzing trace with hash -866028221, now seen corresponding path program 26 times [2021-11-07 08:32:41,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:41,732 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333664602] [2021-11-07 08:32:41,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:41,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:41,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:41,761 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:41,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:41,792 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:41,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:41,793 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 30 times [2021-11-07 08:32:41,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:41,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822862320] [2021-11-07 08:32:41,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:41,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:41,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:41,800 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:41,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:41,802 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:41,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:41,802 INFO L85 PathProgramCache]: Analyzing trace with hash 970536390, now seen corresponding path program 26 times [2021-11-07 08:32:41,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:41,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625371368] [2021-11-07 08:32:41,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:41,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:41,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:42,254 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:42,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:42,254 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625371368] [2021-11-07 08:32:42,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625371368] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:42,255 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [384828566] [2021-11-07 08:32:42,255 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:32:42,255 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:42,255 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:42,261 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:42,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-07 08:32:42,909 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:32:42,909 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:42,911 INFO L263 TraceCheckSpWp]: Trace formula consists of 249 conjuncts, 45 conjunts are in the unsatisfiable core [2021-11-07 08:32:42,912 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:43,146 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:43,642 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:43,646 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 0 proven. 235 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:43,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [384828566] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:43,647 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:43,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 35 [2021-11-07 08:32:43,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575249606] [2021-11-07 08:32:43,698 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:43,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-07 08:32:43,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=1168, Unknown=0, NotChecked=0, Total=1260 [2021-11-07 08:32:43,699 INFO L87 Difference]: Start difference. First operand 57 states and 69 transitions. cyclomatic complexity: 14 Second operand has 36 states, 35 states have (on average 2.2285714285714286) internal successors, (78), 36 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:44,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:44,673 INFO L93 Difference]: Finished difference Result 83 states and 98 transitions. [2021-11-07 08:32:44,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-07 08:32:44,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 98 transitions. [2021-11-07 08:32:44,674 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:44,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 83 states and 98 transitions. [2021-11-07 08:32:44,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50 [2021-11-07 08:32:44,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50 [2021-11-07 08:32:44,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 98 transitions. [2021-11-07 08:32:44,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:44,675 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 98 transitions. [2021-11-07 08:32:44,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 98 transitions. [2021-11-07 08:32:44,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 63. [2021-11-07 08:32:44,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.2222222222222223) internal successors, (77), 62 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:44,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 77 transitions. [2021-11-07 08:32:44,677 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 77 transitions. [2021-11-07 08:32:44,677 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 77 transitions. [2021-11-07 08:32:44,677 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-07 08:32:44,677 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 77 transitions. [2021-11-07 08:32:44,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:44,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:44,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:44,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:44,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:44,680 INFO L791 eck$LassoCheckResult]: Stem: 6540#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 6541#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 6548#L367 assume !(main_~length~0 < 1); 6542#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 6543#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 6544#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6549#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6581#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6550#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6551#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6553#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6554#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6580#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6579#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6578#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6577#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6576#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6575#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6574#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6573#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6572#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6571#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6570#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6569#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6568#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6567#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6566#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6565#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6564#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6563#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6562#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6561#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6560#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6559#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6558#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6555#L370-3 assume !(main_~i~0 < main_~length~0); 6556#L370-4 main_~j~0 := 0; 6600#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6545#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6546#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6552#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6599#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6598#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6597#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6596#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6595#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6594#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6593#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6592#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6591#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6590#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6589#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6588#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6587#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6586#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6585#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6584#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6583#L378-2 [2021-11-07 08:32:44,680 INFO L793 eck$LassoCheckResult]: Loop: 6583#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6582#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 6583#L378-2 [2021-11-07 08:32:44,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:44,680 INFO L85 PathProgramCache]: Analyzing trace with hash 970536392, now seen corresponding path program 27 times [2021-11-07 08:32:44,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:44,681 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122259782] [2021-11-07 08:32:44,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:44,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:44,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:44,712 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:44,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:44,746 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:44,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:44,746 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 31 times [2021-11-07 08:32:44,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:44,747 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113059691] [2021-11-07 08:32:44,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:44,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:44,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:44,756 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:44,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:44,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:44,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:44,759 INFO L85 PathProgramCache]: Analyzing trace with hash 677570827, now seen corresponding path program 27 times [2021-11-07 08:32:44,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:44,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028738418] [2021-11-07 08:32:44,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:44,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:44,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:45,122 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 91 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:45,123 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:45,123 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028738418] [2021-11-07 08:32:45,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028738418] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:45,123 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [361576672] [2021-11-07 08:32:45,123 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:32:45,123 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:45,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:45,130 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:45,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-07 08:32:45,931 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2021-11-07 08:32:45,931 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:45,934 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-07 08:32:45,935 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:46,440 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 110 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:46,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [361576672] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:46,440 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:46,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 37 [2021-11-07 08:32:46,441 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408488957] [2021-11-07 08:32:46,476 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:46,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-11-07 08:32:46,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=305, Invalid=1027, Unknown=0, NotChecked=0, Total=1332 [2021-11-07 08:32:46,477 INFO L87 Difference]: Start difference. First operand 63 states and 77 transitions. cyclomatic complexity: 16 Second operand has 37 states, 37 states have (on average 2.2972972972972974) internal successors, (85), 37 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:46,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:46,767 INFO L93 Difference]: Finished difference Result 84 states and 98 transitions. [2021-11-07 08:32:46,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-07 08:32:46,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 98 transitions. [2021-11-07 08:32:46,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:46,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 62 states and 76 transitions. [2021-11-07 08:32:46,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2021-11-07 08:32:46,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2021-11-07 08:32:46,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 76 transitions. [2021-11-07 08:32:46,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:46,770 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 76 transitions. [2021-11-07 08:32:46,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 76 transitions. [2021-11-07 08:32:46,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2021-11-07 08:32:46,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.2166666666666666) internal successors, (73), 59 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:46,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 73 transitions. [2021-11-07 08:32:46,772 INFO L704 BuchiCegarLoop]: Abstraction has 60 states and 73 transitions. [2021-11-07 08:32:46,773 INFO L587 BuchiCegarLoop]: Abstraction has 60 states and 73 transitions. [2021-11-07 08:32:46,773 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-07 08:32:46,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 73 transitions. [2021-11-07 08:32:46,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:46,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:46,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:46,775 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:46,775 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:46,775 INFO L791 eck$LassoCheckResult]: Stem: 6927#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 6928#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 6936#L367 assume !(main_~length~0 < 1); 6929#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 6930#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 6931#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6937#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6970#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6938#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6939#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6941#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6942#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6969#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6968#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6967#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6966#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6965#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6964#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6963#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6962#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6961#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6960#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6959#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6958#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6957#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6956#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6955#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6954#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6953#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6952#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6951#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6950#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6949#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6948#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6947#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6946#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 6944#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 6945#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 6943#L370-3 assume !(main_~i~0 < main_~length~0); 6934#L370-4 main_~j~0 := 0; 6935#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6932#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6933#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6940#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6986#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6985#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6984#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6983#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6982#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6981#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6980#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6979#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6978#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6977#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6976#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6975#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6974#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6973#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 6972#L378-2 [2021-11-07 08:32:46,776 INFO L793 eck$LassoCheckResult]: Loop: 6972#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 6971#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 6972#L378-2 [2021-11-07 08:32:46,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:46,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1368929161, now seen corresponding path program 28 times [2021-11-07 08:32:46,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:46,777 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543519735] [2021-11-07 08:32:46,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:46,777 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:46,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:46,821 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:46,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:46,867 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:46,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:46,867 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 32 times [2021-11-07 08:32:46,868 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:46,868 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232978229] [2021-11-07 08:32:46,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:46,868 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:46,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:46,883 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:46,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:46,886 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:46,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:46,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1280932492, now seen corresponding path program 28 times [2021-11-07 08:32:46,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:46,887 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643125499] [2021-11-07 08:32:46,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:46,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:46,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:47,486 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:47,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:47,487 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643125499] [2021-11-07 08:32:47,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643125499] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:47,487 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [10112519] [2021-11-07 08:32:47,489 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:32:47,490 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:47,491 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:47,493 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:47,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-07 08:32:48,139 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:32:48,139 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:48,141 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 51 conjunts are in the unsatisfiable core [2021-11-07 08:32:48,142 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:48,563 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:48,696 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:48,696 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:49,322 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:49,324 INFO L134 CoverageAnalysis]: Checked inductivity of 266 backedges. 0 proven. 266 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:49,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [10112519] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:49,325 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:49,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 51 [2021-11-07 08:32:49,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059384776] [2021-11-07 08:32:49,357 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:49,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-11-07 08:32:49,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=2471, Unknown=0, NotChecked=0, Total=2652 [2021-11-07 08:32:49,359 INFO L87 Difference]: Start difference. First operand 60 states and 73 transitions. cyclomatic complexity: 15 Second operand has 52 states, 51 states have (on average 2.2745098039215685) internal successors, (116), 52 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:50,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:50,373 INFO L93 Difference]: Finished difference Result 62 states and 75 transitions. [2021-11-07 08:32:50,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-07 08:32:50,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 75 transitions. [2021-11-07 08:32:50,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:50,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 62 states and 75 transitions. [2021-11-07 08:32:50,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-11-07 08:32:50,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-11-07 08:32:50,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 75 transitions. [2021-11-07 08:32:50,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:50,375 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 75 transitions. [2021-11-07 08:32:50,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 75 transitions. [2021-11-07 08:32:50,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2021-11-07 08:32:50,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.2096774193548387) internal successors, (75), 61 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:50,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 75 transitions. [2021-11-07 08:32:50,378 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 75 transitions. [2021-11-07 08:32:50,378 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 75 transitions. [2021-11-07 08:32:50,378 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-07 08:32:50,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 75 transitions. [2021-11-07 08:32:50,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:50,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:50,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:50,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:50,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:50,380 INFO L791 eck$LassoCheckResult]: Stem: 7307#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7308#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 7316#L367 assume !(main_~length~0 < 1); 7309#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 7310#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 7311#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7317#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7350#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7318#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7319#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7321#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7322#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7349#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7348#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7347#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7346#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7345#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7344#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7343#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7342#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7341#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7340#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7339#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7338#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7337#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7336#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7335#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7334#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7333#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7332#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7331#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7330#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7329#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7328#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7327#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7326#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7324#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7325#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7323#L370-3 assume !(main_~i~0 < main_~length~0); 7314#L370-4 main_~j~0 := 0; 7315#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7312#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7313#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7320#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7368#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7367#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7366#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7365#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7364#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7363#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7362#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7361#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7360#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7359#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7358#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7357#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7356#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7355#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7354#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7353#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7352#L378-2 [2021-11-07 08:32:50,380 INFO L793 eck$LassoCheckResult]: Loop: 7352#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7351#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 7352#L378-2 [2021-11-07 08:32:50,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:50,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1280932494, now seen corresponding path program 29 times [2021-11-07 08:32:50,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:50,381 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507643167] [2021-11-07 08:32:50,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:50,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:50,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:50,412 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:50,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:50,445 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:50,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:50,445 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 33 times [2021-11-07 08:32:50,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:50,446 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547432468] [2021-11-07 08:32:50,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:50,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:50,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:50,454 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:50,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:50,456 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:50,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:50,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485871, now seen corresponding path program 29 times [2021-11-07 08:32:50,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:50,457 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183860859] [2021-11-07 08:32:50,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:50,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:50,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:50,954 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:50,954 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:50,954 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183860859] [2021-11-07 08:32:50,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183860859] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:50,954 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1056601862] [2021-11-07 08:32:50,954 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:32:50,954 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:50,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:50,956 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:50,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-07 08:32:51,700 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2021-11-07 08:32:51,700 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:51,703 INFO L263 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 49 conjunts are in the unsatisfiable core [2021-11-07 08:32:51,704 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:51,868 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:32:52,485 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:32:52,487 INFO L134 CoverageAnalysis]: Checked inductivity of 286 backedges. 0 proven. 286 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:52,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1056601862] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:52,488 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:52,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 39 [2021-11-07 08:32:52,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405712138] [2021-11-07 08:32:52,522 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:52,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-07 08:32:52,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=1456, Unknown=0, NotChecked=0, Total=1560 [2021-11-07 08:32:52,524 INFO L87 Difference]: Start difference. First operand 62 states and 75 transitions. cyclomatic complexity: 15 Second operand has 40 states, 39 states have (on average 2.230769230769231) internal successors, (87), 40 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:53,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:53,377 INFO L93 Difference]: Finished difference Result 90 states and 106 transitions. [2021-11-07 08:32:53,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-07 08:32:53,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 106 transitions. [2021-11-07 08:32:53,378 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:32:53,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 106 transitions. [2021-11-07 08:32:53,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54 [2021-11-07 08:32:53,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54 [2021-11-07 08:32:53,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 106 transitions. [2021-11-07 08:32:53,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:53,379 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 106 transitions. [2021-11-07 08:32:53,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 106 transitions. [2021-11-07 08:32:53,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 68. [2021-11-07 08:32:53,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.2205882352941178) internal successors, (83), 67 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:53,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 83 transitions. [2021-11-07 08:32:53,382 INFO L704 BuchiCegarLoop]: Abstraction has 68 states and 83 transitions. [2021-11-07 08:32:53,382 INFO L587 BuchiCegarLoop]: Abstraction has 68 states and 83 transitions. [2021-11-07 08:32:53,382 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-07 08:32:53,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 83 transitions. [2021-11-07 08:32:53,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:53,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:53,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:53,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:53,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:53,384 INFO L791 eck$LassoCheckResult]: Stem: 7689#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7690#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 7697#L367 assume !(main_~length~0 < 1); 7691#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 7692#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 7693#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7698#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7733#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7699#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7700#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7702#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7703#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7732#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7731#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7730#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7729#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7728#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7727#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7726#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7725#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7724#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7723#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7722#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7721#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7720#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7719#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7718#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7717#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7716#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7715#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7714#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7713#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7712#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7711#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7710#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7709#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 7708#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 7707#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 7704#L370-3 assume !(main_~i~0 < main_~length~0); 7705#L370-4 main_~j~0 := 0; 7754#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7694#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7695#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7701#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7753#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7752#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7751#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7750#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7749#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7748#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7747#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7746#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7745#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7744#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7743#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7742#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7741#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7740#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7739#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7738#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7737#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7736#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 7735#L378-2 [2021-11-07 08:32:53,384 INFO L793 eck$LassoCheckResult]: Loop: 7735#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 7734#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 7735#L378-2 [2021-11-07 08:32:53,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:53,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1679485869, now seen corresponding path program 30 times [2021-11-07 08:32:53,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:53,385 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639939196] [2021-11-07 08:32:53,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:53,385 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:53,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:53,420 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:53,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:53,455 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:53,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:53,456 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 34 times [2021-11-07 08:32:53,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:53,456 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451187589] [2021-11-07 08:32:53,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:53,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:53,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:53,465 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:53,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:53,467 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:53,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:53,468 INFO L85 PathProgramCache]: Analyzing trace with hash 921784534, now seen corresponding path program 30 times [2021-11-07 08:32:53,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:53,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059025706] [2021-11-07 08:32:53,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:53,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:53,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:53,783 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 111 proven. 197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:53,783 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:53,783 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059025706] [2021-11-07 08:32:53,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059025706] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:53,784 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1178086535] [2021-11-07 08:32:53,784 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:32:53,784 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:53,784 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:53,786 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:53,812 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-07 08:32:55,018 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2021-11-07 08:32:55,018 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:32:55,021 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-07 08:32:55,025 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:55,547 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 132 proven. 176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:55,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1178086535] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:55,547 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:55,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 40 [2021-11-07 08:32:55,548 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643946577] [2021-11-07 08:32:55,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:55,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-07 08:32:55,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=356, Invalid=1204, Unknown=0, NotChecked=0, Total=1560 [2021-11-07 08:32:55,593 INFO L87 Difference]: Start difference. First operand 68 states and 83 transitions. cyclomatic complexity: 17 Second operand has 40 states, 40 states have (on average 2.3) internal successors, (92), 40 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:55,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:32:55,888 INFO L93 Difference]: Finished difference Result 91 states and 106 transitions. [2021-11-07 08:32:55,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-07 08:32:55,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 106 transitions. [2021-11-07 08:32:55,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:55,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 67 states and 82 transitions. [2021-11-07 08:32:55,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-11-07 08:32:55,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-11-07 08:32:55,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 82 transitions. [2021-11-07 08:32:55,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:32:55,891 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 82 transitions. [2021-11-07 08:32:55,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 82 transitions. [2021-11-07 08:32:55,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2021-11-07 08:32:55,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.2153846153846153) internal successors, (79), 64 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:32:55,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 79 transitions. [2021-11-07 08:32:55,893 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 79 transitions. [2021-11-07 08:32:55,893 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 79 transitions. [2021-11-07 08:32:55,894 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-07 08:32:55,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 79 transitions. [2021-11-07 08:32:55,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:32:55,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:32:55,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:32:55,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:32:55,895 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:32:55,896 INFO L791 eck$LassoCheckResult]: Stem: 8108#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8109#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 8117#L367 assume !(main_~length~0 < 1); 8110#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 8111#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 8112#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8118#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8154#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8119#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8120#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8122#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8123#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8153#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8152#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8151#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8150#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8149#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8148#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8147#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8146#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8145#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8144#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8143#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8142#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8141#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8140#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8139#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8138#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8137#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8136#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8135#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8134#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8133#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8132#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8131#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8130#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8129#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8128#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8127#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8125#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8126#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8124#L370-3 assume !(main_~i~0 < main_~length~0); 8115#L370-4 main_~j~0 := 0; 8116#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8113#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8114#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8121#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8172#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8171#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8170#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8169#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8168#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8167#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8166#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8165#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8164#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8163#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8162#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8161#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8160#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8159#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8158#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8157#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8156#L378-2 [2021-11-07 08:32:55,896 INFO L793 eck$LassoCheckResult]: Loop: 8156#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8155#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 8156#L378-2 [2021-11-07 08:32:55,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:55,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1226618888, now seen corresponding path program 31 times [2021-11-07 08:32:55,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:55,897 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608995981] [2021-11-07 08:32:55,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:55,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:55,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:55,944 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:55,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:55,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:55,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:55,985 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 35 times [2021-11-07 08:32:55,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:55,985 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386971070] [2021-11-07 08:32:55,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:55,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:56,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:56,000 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:32:56,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:32:56,002 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:32:56,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:32:56,003 INFO L85 PathProgramCache]: Analyzing trace with hash 1959713611, now seen corresponding path program 31 times [2021-11-07 08:32:56,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:32:56,003 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699350761] [2021-11-07 08:32:56,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:32:56,004 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:32:56,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:56,593 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:56,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:32:56,594 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699350761] [2021-11-07 08:32:56,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699350761] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:56,594 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [643349835] [2021-11-07 08:32:56,594 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:32:56,594 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:32:56,595 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:32:56,600 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:32:56,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-07 08:32:57,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:32:57,504 INFO L263 TraceCheckSpWp]: Trace formula consists of 282 conjuncts, 55 conjunts are in the unsatisfiable core [2021-11-07 08:32:57,505 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:32:58,025 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:32:58,170 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:32:58,170 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:32:58,899 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:32:58,901 INFO L134 CoverageAnalysis]: Checked inductivity of 320 backedges. 0 proven. 320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:32:58,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [643349835] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:32:58,901 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:32:58,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29] total 55 [2021-11-07 08:32:58,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175710856] [2021-11-07 08:32:58,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:32:58,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2021-11-07 08:32:58,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=2885, Unknown=0, NotChecked=0, Total=3080 [2021-11-07 08:32:58,936 INFO L87 Difference]: Start difference. First operand 65 states and 79 transitions. cyclomatic complexity: 16 Second operand has 56 states, 55 states have (on average 2.290909090909091) internal successors, (126), 56 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:00,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:00,265 INFO L93 Difference]: Finished difference Result 67 states and 81 transitions. [2021-11-07 08:33:00,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-07 08:33:00,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 81 transitions. [2021-11-07 08:33:00,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:00,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 67 states and 81 transitions. [2021-11-07 08:33:00,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-07 08:33:00,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-07 08:33:00,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 81 transitions. [2021-11-07 08:33:00,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:00,267 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 81 transitions. [2021-11-07 08:33:00,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 81 transitions. [2021-11-07 08:33:00,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2021-11-07 08:33:00,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.208955223880597) internal successors, (81), 66 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:00,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 81 transitions. [2021-11-07 08:33:00,270 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 81 transitions. [2021-11-07 08:33:00,270 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 81 transitions. [2021-11-07 08:33:00,270 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-07 08:33:00,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 81 transitions. [2021-11-07 08:33:00,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:00,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:00,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:00,272 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:00,272 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:00,272 INFO L791 eck$LassoCheckResult]: Stem: 8519#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8520#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 8528#L367 assume !(main_~length~0 < 1); 8521#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 8522#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 8523#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8529#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8565#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8530#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8531#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8532#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8534#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8564#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8563#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8562#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8561#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8560#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8559#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8558#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8557#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8556#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8555#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8554#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8553#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8552#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8551#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8550#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8549#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8548#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8547#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8546#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8545#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8544#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8543#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8542#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8541#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8540#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8539#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8538#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8536#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8537#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8535#L370-3 assume !(main_~i~0 < main_~length~0); 8524#L370-4 main_~j~0 := 0; 8525#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8526#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8527#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8533#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8585#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8584#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8583#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8582#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8581#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8580#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8579#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8578#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8577#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8576#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8575#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8574#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8573#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8572#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8571#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8570#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8569#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8568#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8567#L378-2 [2021-11-07 08:33:00,272 INFO L793 eck$LassoCheckResult]: Loop: 8567#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8566#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 8567#L378-2 [2021-11-07 08:33:00,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:00,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1959713613, now seen corresponding path program 32 times [2021-11-07 08:33:00,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:00,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202162341] [2021-11-07 08:33:00,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:00,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:00,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:00,308 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:00,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:00,343 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:00,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:00,343 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 36 times [2021-11-07 08:33:00,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:00,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720615203] [2021-11-07 08:33:00,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:00,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:00,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:00,353 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:00,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:00,355 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:00,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:00,355 INFO L85 PathProgramCache]: Analyzing trace with hash 2089107792, now seen corresponding path program 32 times [2021-11-07 08:33:00,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:00,356 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180476144] [2021-11-07 08:33:00,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:00,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:00,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:00,900 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:00,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:00,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180476144] [2021-11-07 08:33:00,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180476144] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:00,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2121407043] [2021-11-07 08:33:00,901 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:33:00,901 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:00,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:00,902 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:00,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-07 08:33:01,676 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:33:01,677 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:01,679 INFO L263 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 53 conjunts are in the unsatisfiable core [2021-11-07 08:33:01,680 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:01,943 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:33:02,519 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:33:02,525 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:02,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2121407043] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:02,525 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:02,525 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 28] total 41 [2021-11-07 08:33:02,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957300466] [2021-11-07 08:33:02,559 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:02,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-11-07 08:33:02,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=108, Invalid=1614, Unknown=0, NotChecked=0, Total=1722 [2021-11-07 08:33:02,560 INFO L87 Difference]: Start difference. First operand 67 states and 81 transitions. cyclomatic complexity: 16 Second operand has 42 states, 41 states have (on average 2.2439024390243905) internal successors, (92), 42 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:03,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:03,581 INFO L93 Difference]: Finished difference Result 97 states and 114 transitions. [2021-11-07 08:33:03,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-07 08:33:03,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 114 transitions. [2021-11-07 08:33:03,582 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:33:03,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 114 transitions. [2021-11-07 08:33:03,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58 [2021-11-07 08:33:03,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58 [2021-11-07 08:33:03,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 114 transitions. [2021-11-07 08:33:03,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:03,583 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 114 transitions. [2021-11-07 08:33:03,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 114 transitions. [2021-11-07 08:33:03,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 73. [2021-11-07 08:33:03,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.2191780821917808) internal successors, (89), 72 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:03,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 89 transitions. [2021-11-07 08:33:03,585 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 89 transitions. [2021-11-07 08:33:03,585 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 89 transitions. [2021-11-07 08:33:03,585 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-11-07 08:33:03,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 89 transitions. [2021-11-07 08:33:03,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:03,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:03,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:03,586 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:03,586 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:03,586 INFO L791 eck$LassoCheckResult]: Stem: 8930#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8931#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 8938#L367 assume !(main_~length~0 < 1); 8932#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 8933#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 8934#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8939#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8977#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8940#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8941#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8942#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8944#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8976#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8975#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8974#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8973#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8972#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8971#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8970#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8969#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8968#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8967#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8966#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8965#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8964#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8963#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8962#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8961#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8960#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8959#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8958#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8957#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8956#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8955#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8954#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8953#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8952#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8951#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8950#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 8949#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 8948#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 8945#L370-3 assume !(main_~i~0 < main_~length~0); 8946#L370-4 main_~j~0 := 0; 9000#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8937#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8936#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8943#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8999#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8998#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8997#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8996#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8995#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8994#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8993#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8992#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8991#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8990#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8989#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8988#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8987#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8986#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8985#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8984#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8983#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8982#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8981#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8980#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 8979#L378-2 [2021-11-07 08:33:03,586 INFO L793 eck$LassoCheckResult]: Loop: 8979#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 8978#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 8979#L378-2 [2021-11-07 08:33:03,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:03,586 INFO L85 PathProgramCache]: Analyzing trace with hash 2089107794, now seen corresponding path program 33 times [2021-11-07 08:33:03,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:03,587 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800706596] [2021-11-07 08:33:03,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:03,587 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:03,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:03,625 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:03,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:03,664 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:03,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:03,664 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 37 times [2021-11-07 08:33:03,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:03,665 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262305439] [2021-11-07 08:33:03,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:03,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:03,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:03,674 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:03,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:03,721 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:03,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:03,722 INFO L85 PathProgramCache]: Analyzing trace with hash 1882864149, now seen corresponding path program 33 times [2021-11-07 08:33:03,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:03,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044790076] [2021-11-07 08:33:03,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:03,722 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:03,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:04,074 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 133 proven. 233 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:04,074 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:04,074 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044790076] [2021-11-07 08:33:04,074 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044790076] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:04,075 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1366725912] [2021-11-07 08:33:04,075 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:33:04,075 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:04,075 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:04,080 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:04,080 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-07 08:33:05,130 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2021-11-07 08:33:05,130 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:05,133 INFO L263 TraceCheckSpWp]: Trace formula consists of 304 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-07 08:33:05,134 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:05,789 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 156 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:05,790 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1366725912] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:05,790 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:05,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 43 [2021-11-07 08:33:05,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072281426] [2021-11-07 08:33:05,828 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:05,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-07 08:33:05,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=411, Invalid=1395, Unknown=0, NotChecked=0, Total=1806 [2021-11-07 08:33:05,829 INFO L87 Difference]: Start difference. First operand 73 states and 89 transitions. cyclomatic complexity: 18 Second operand has 43 states, 43 states have (on average 2.302325581395349) internal successors, (99), 43 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:06,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:06,190 INFO L93 Difference]: Finished difference Result 98 states and 114 transitions. [2021-11-07 08:33:06,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-07 08:33:06,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 114 transitions. [2021-11-07 08:33:06,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:06,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 72 states and 88 transitions. [2021-11-07 08:33:06,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-07 08:33:06,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-07 08:33:06,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 88 transitions. [2021-11-07 08:33:06,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:06,194 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 88 transitions. [2021-11-07 08:33:06,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 88 transitions. [2021-11-07 08:33:06,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 70. [2021-11-07 08:33:06,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 69 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:06,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 85 transitions. [2021-11-07 08:33:06,196 INFO L704 BuchiCegarLoop]: Abstraction has 70 states and 85 transitions. [2021-11-07 08:33:06,197 INFO L587 BuchiCegarLoop]: Abstraction has 70 states and 85 transitions. [2021-11-07 08:33:06,197 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-11-07 08:33:06,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 85 transitions. [2021-11-07 08:33:06,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:06,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:06,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:06,199 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:06,199 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:06,199 INFO L791 eck$LassoCheckResult]: Stem: 9381#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 9382#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 9390#L367 assume !(main_~length~0 < 1); 9383#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 9384#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 9385#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9391#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9430#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9392#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9393#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9395#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9396#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9429#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9428#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9427#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9426#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9425#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9424#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9423#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9422#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9421#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9420#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9419#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9418#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9417#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9416#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9415#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9414#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9413#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9412#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9411#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9410#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9409#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9408#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9407#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9406#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9405#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9404#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9403#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9402#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9401#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9400#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9398#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9399#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9397#L370-3 assume !(main_~i~0 < main_~length~0); 9388#L370-4 main_~j~0 := 0; 9389#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9386#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9387#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9394#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9450#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9449#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9448#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9447#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9446#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9445#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9444#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9443#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9442#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9441#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9440#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9439#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9438#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9437#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9436#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9435#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9434#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9433#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9432#L378-2 [2021-11-07 08:33:06,200 INFO L793 eck$LassoCheckResult]: Loop: 9432#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9431#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 9432#L378-2 [2021-11-07 08:33:06,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:06,200 INFO L85 PathProgramCache]: Analyzing trace with hash -507971053, now seen corresponding path program 34 times [2021-11-07 08:33:06,200 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:06,201 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985899507] [2021-11-07 08:33:06,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:06,201 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:06,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:06,255 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:06,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:06,301 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:06,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:06,302 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 38 times [2021-11-07 08:33:06,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:06,303 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114963643] [2021-11-07 08:33:06,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:06,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:06,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:06,320 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:06,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:06,323 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:06,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:06,324 INFO L85 PathProgramCache]: Analyzing trace with hash 1466091158, now seen corresponding path program 34 times [2021-11-07 08:33:06,324 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:06,324 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658836928] [2021-11-07 08:33:06,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:06,324 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:06,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:07,090 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:07,091 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:07,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658836928] [2021-11-07 08:33:07,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658836928] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:07,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [863182592] [2021-11-07 08:33:07,091 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:33:07,091 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:07,092 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:07,094 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:07,113 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-07 08:33:08,059 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:33:08,059 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:08,061 INFO L263 TraceCheckSpWp]: Trace formula consists of 304 conjuncts, 59 conjunts are in the unsatisfiable core [2021-11-07 08:33:08,062 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:08,647 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:33:08,794 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:33:08,794 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:33:09,543 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:33:09,547 INFO L134 CoverageAnalysis]: Checked inductivity of 379 backedges. 0 proven. 379 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:09,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [863182592] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:09,548 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:09,548 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31] total 59 [2021-11-07 08:33:09,548 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775402245] [2021-11-07 08:33:09,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:09,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2021-11-07 08:33:09,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=209, Invalid=3331, Unknown=0, NotChecked=0, Total=3540 [2021-11-07 08:33:09,599 INFO L87 Difference]: Start difference. First operand 70 states and 85 transitions. cyclomatic complexity: 17 Second operand has 60 states, 59 states have (on average 2.305084745762712) internal successors, (136), 60 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:11,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:11,325 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2021-11-07 08:33:11,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-07 08:33:11,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 87 transitions. [2021-11-07 08:33:11,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:11,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 72 states and 87 transitions. [2021-11-07 08:33:11,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2021-11-07 08:33:11,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2021-11-07 08:33:11,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 87 transitions. [2021-11-07 08:33:11,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:11,327 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 87 transitions. [2021-11-07 08:33:11,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 87 transitions. [2021-11-07 08:33:11,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2021-11-07 08:33:11,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.2083333333333333) internal successors, (87), 71 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:11,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 87 transitions. [2021-11-07 08:33:11,330 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 87 transitions. [2021-11-07 08:33:11,330 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 87 transitions. [2021-11-07 08:33:11,330 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-11-07 08:33:11,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 87 transitions. [2021-11-07 08:33:11,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:11,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:11,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:11,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:11,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:11,332 INFO L791 eck$LassoCheckResult]: Stem: 9823#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 9824#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 9832#L367 assume !(main_~length~0 < 1); 9825#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 9826#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 9827#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9833#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9872#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9834#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9835#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9836#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9838#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9871#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9870#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9869#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9868#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9867#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9866#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9865#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9864#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9863#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9862#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9861#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9860#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9859#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9858#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9857#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9856#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9855#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9854#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9853#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9852#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9851#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9850#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9849#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9848#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9847#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9846#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9845#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9844#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9843#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9842#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 9840#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 9841#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 9839#L370-3 assume !(main_~i~0 < main_~length~0); 9828#L370-4 main_~j~0 := 0; 9829#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9830#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9831#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9837#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9894#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9893#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9892#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9891#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9890#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9889#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9888#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9887#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9886#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9885#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9884#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9883#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9882#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9881#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9880#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9879#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9878#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9877#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9876#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9875#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 9874#L378-2 [2021-11-07 08:33:11,332 INFO L793 eck$LassoCheckResult]: Loop: 9874#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 9873#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 9874#L378-2 [2021-11-07 08:33:11,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:11,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1466091160, now seen corresponding path program 35 times [2021-11-07 08:33:11,333 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:11,333 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845585456] [2021-11-07 08:33:11,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:11,333 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:11,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:11,379 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:11,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:11,422 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:11,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:11,422 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 39 times [2021-11-07 08:33:11,423 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:11,423 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582994581] [2021-11-07 08:33:11,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:11,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:11,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:11,433 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:11,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:11,435 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:11,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:11,436 INFO L85 PathProgramCache]: Analyzing trace with hash 164333019, now seen corresponding path program 35 times [2021-11-07 08:33:11,436 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:11,436 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904862656] [2021-11-07 08:33:11,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:11,437 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:11,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:11,999 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:11,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:11,999 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904862656] [2021-11-07 08:33:11,999 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904862656] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:11,999 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1710075729] [2021-11-07 08:33:11,999 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:33:11,999 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:11,999 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:12,001 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:12,002 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-07 08:33:13,098 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2021-11-07 08:33:13,098 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:13,101 INFO L263 TraceCheckSpWp]: Trace formula consists of 315 conjuncts, 59 conjunts are in the unsatisfiable core [2021-11-07 08:33:13,102 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:13,906 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2021-11-07 08:33:16,177 INFO L354 Elim1Store]: treesize reduction 13, result has 18.8 percent of original size [2021-11-07 08:33:16,177 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 29 [2021-11-07 08:33:16,182 INFO L134 CoverageAnalysis]: Checked inductivity of 403 backedges. 0 proven. 403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:16,182 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1710075729] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:16,183 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:16,183 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 33] total 62 [2021-11-07 08:33:16,183 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962803304] [2021-11-07 08:33:16,223 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:16,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2021-11-07 08:33:16,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=3692, Unknown=0, NotChecked=0, Total=3906 [2021-11-07 08:33:16,225 INFO L87 Difference]: Start difference. First operand 72 states and 87 transitions. cyclomatic complexity: 17 Second operand has 63 states, 62 states have (on average 2.2580645161290325) internal successors, (140), 63 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:17,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:17,838 INFO L93 Difference]: Finished difference Result 104 states and 122 transitions. [2021-11-07 08:33:17,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-07 08:33:17,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104 states and 122 transitions. [2021-11-07 08:33:17,839 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:33:17,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104 states to 104 states and 122 transitions. [2021-11-07 08:33:17,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2021-11-07 08:33:17,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2021-11-07 08:33:17,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 122 transitions. [2021-11-07 08:33:17,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:17,841 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 122 transitions. [2021-11-07 08:33:17,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 122 transitions. [2021-11-07 08:33:17,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 78. [2021-11-07 08:33:17,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.2179487179487178) internal successors, (95), 77 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:17,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 95 transitions. [2021-11-07 08:33:17,847 INFO L704 BuchiCegarLoop]: Abstraction has 78 states and 95 transitions. [2021-11-07 08:33:17,848 INFO L587 BuchiCegarLoop]: Abstraction has 78 states and 95 transitions. [2021-11-07 08:33:17,848 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-11-07 08:33:17,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 95 transitions. [2021-11-07 08:33:17,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:17,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:17,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:17,850 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:17,850 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:17,851 INFO L791 eck$LassoCheckResult]: Stem: 10288#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 10289#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 10296#L367 assume !(main_~length~0 < 1); 10290#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 10291#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 10292#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10297#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10338#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10298#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10299#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10301#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10302#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10337#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10336#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10335#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10334#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10333#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10332#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10331#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10330#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10329#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10328#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10327#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10326#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10325#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10324#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10323#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10322#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10321#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10320#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10319#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10318#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10317#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10316#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10315#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10314#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10313#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10312#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10311#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10310#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10309#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10308#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10307#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10306#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10303#L370-3 assume !(main_~i~0 < main_~length~0); 10304#L370-4 main_~j~0 := 0; 10363#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10293#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10294#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10300#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10362#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10361#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10360#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10359#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10358#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10357#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10356#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10355#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10354#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10353#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10352#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10351#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10350#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10349#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10348#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10347#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10346#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10345#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10344#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10343#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10342#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10341#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10340#L378-2 [2021-11-07 08:33:17,851 INFO L793 eck$LassoCheckResult]: Loop: 10340#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10339#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 10340#L378-2 [2021-11-07 08:33:17,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:17,852 INFO L85 PathProgramCache]: Analyzing trace with hash 164333021, now seen corresponding path program 36 times [2021-11-07 08:33:17,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:17,852 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535749019] [2021-11-07 08:33:17,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:17,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:17,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:17,923 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:17,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:17,981 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:17,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:17,982 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 40 times [2021-11-07 08:33:17,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:17,982 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514578799] [2021-11-07 08:33:17,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:17,983 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:18,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:18,002 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:18,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:18,005 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:18,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:18,005 INFO L85 PathProgramCache]: Analyzing trace with hash -989755424, now seen corresponding path program 36 times [2021-11-07 08:33:18,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:18,006 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043190556] [2021-11-07 08:33:18,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:18,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:18,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:18,560 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 157 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:18,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:18,561 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043190556] [2021-11-07 08:33:18,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043190556] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:18,561 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1188765957] [2021-11-07 08:33:18,561 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:33:18,561 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:18,561 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:18,564 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:18,585 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-11-07 08:33:20,233 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2021-11-07 08:33:20,233 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:20,238 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-07 08:33:20,239 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:20,891 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 182 proven. 247 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:20,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1188765957] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:20,891 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:20,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 46 [2021-11-07 08:33:20,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238993421] [2021-11-07 08:33:20,926 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:20,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-11-07 08:33:20,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=470, Invalid=1600, Unknown=0, NotChecked=0, Total=2070 [2021-11-07 08:33:20,928 INFO L87 Difference]: Start difference. First operand 78 states and 95 transitions. cyclomatic complexity: 19 Second operand has 46 states, 46 states have (on average 2.3043478260869565) internal successors, (106), 46 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:21,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:21,319 INFO L93 Difference]: Finished difference Result 105 states and 122 transitions. [2021-11-07 08:33:21,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-07 08:33:21,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 122 transitions. [2021-11-07 08:33:21,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:21,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 77 states and 94 transitions. [2021-11-07 08:33:21,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2021-11-07 08:33:21,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2021-11-07 08:33:21,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 94 transitions. [2021-11-07 08:33:21,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:21,322 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 94 transitions. [2021-11-07 08:33:21,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 94 transitions. [2021-11-07 08:33:21,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 75. [2021-11-07 08:33:21,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.2133333333333334) internal successors, (91), 74 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:21,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 91 transitions. [2021-11-07 08:33:21,325 INFO L704 BuchiCegarLoop]: Abstraction has 75 states and 91 transitions. [2021-11-07 08:33:21,325 INFO L587 BuchiCegarLoop]: Abstraction has 75 states and 91 transitions. [2021-11-07 08:33:21,325 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-11-07 08:33:21,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 91 transitions. [2021-11-07 08:33:21,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:21,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:21,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:21,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 14, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:21,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:21,326 INFO L791 eck$LassoCheckResult]: Stem: 10771#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 10772#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 10780#L367 assume !(main_~length~0 < 1); 10773#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 10774#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 10775#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10781#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10823#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10782#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10783#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10785#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10786#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10822#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10821#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10820#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10819#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10818#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10817#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10816#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10815#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10814#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10813#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10812#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10811#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10810#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10809#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10808#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10807#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10806#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10805#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10804#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10803#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10802#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10801#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10800#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10799#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10798#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10797#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10796#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10795#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10794#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10793#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10792#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10791#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10790#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 10788#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 10789#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 10787#L370-3 assume !(main_~i~0 < main_~length~0); 10778#L370-4 main_~j~0 := 0; 10779#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10776#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10777#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10784#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10845#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10844#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10843#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10842#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10841#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10840#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10839#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10838#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10837#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10836#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10835#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10834#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10833#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10832#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10831#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10830#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10829#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10828#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10827#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10826#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 10825#L378-2 [2021-11-07 08:33:21,326 INFO L793 eck$LassoCheckResult]: Loop: 10825#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 10824#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 10825#L378-2 [2021-11-07 08:33:21,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:21,326 INFO L85 PathProgramCache]: Analyzing trace with hash -268766318, now seen corresponding path program 37 times [2021-11-07 08:33:21,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:21,327 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185823696] [2021-11-07 08:33:21,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:21,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:21,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:21,368 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:21,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:21,412 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:21,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:21,413 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 41 times [2021-11-07 08:33:21,413 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:21,413 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546732453] [2021-11-07 08:33:21,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:21,413 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:21,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:21,425 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:21,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:21,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:21,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:21,427 INFO L85 PathProgramCache]: Analyzing trace with hash -586392491, now seen corresponding path program 37 times [2021-11-07 08:33:21,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:21,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456267585] [2021-11-07 08:33:21,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:21,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:21,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:22,163 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 0 proven. 443 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:22,164 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:22,164 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456267585] [2021-11-07 08:33:22,164 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456267585] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:22,164 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [972973132] [2021-11-07 08:33:22,164 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:33:22,164 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:22,164 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:22,166 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:22,166 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-11-07 08:33:23,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:23,320 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 63 conjunts are in the unsatisfiable core [2021-11-07 08:33:23,322 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:24,039 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:33:24,221 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:33:24,222 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:33:25,083 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:33:25,092 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 0 proven. 443 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:25,092 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [972973132] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:25,092 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:25,092 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33] total 63 [2021-11-07 08:33:25,093 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538780788] [2021-11-07 08:33:25,129 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:25,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2021-11-07 08:33:25,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=3809, Unknown=0, NotChecked=0, Total=4032 [2021-11-07 08:33:25,132 INFO L87 Difference]: Start difference. First operand 75 states and 91 transitions. cyclomatic complexity: 18 Second operand has 64 states, 63 states have (on average 2.3174603174603177) internal successors, (146), 64 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:27,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:27,003 INFO L93 Difference]: Finished difference Result 77 states and 93 transitions. [2021-11-07 08:33:27,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-07 08:33:27,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 93 transitions. [2021-11-07 08:33:27,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:27,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 77 states and 93 transitions. [2021-11-07 08:33:27,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2021-11-07 08:33:27,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2021-11-07 08:33:27,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 93 transitions. [2021-11-07 08:33:27,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:27,006 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 93 transitions. [2021-11-07 08:33:27,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 93 transitions. [2021-11-07 08:33:27,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2021-11-07 08:33:27,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.2077922077922079) internal successors, (93), 76 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:27,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 93 transitions. [2021-11-07 08:33:27,009 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 93 transitions. [2021-11-07 08:33:27,009 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 93 transitions. [2021-11-07 08:33:27,009 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-11-07 08:33:27,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 93 transitions. [2021-11-07 08:33:27,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:27,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:27,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:27,010 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:27,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:27,011 INFO L791 eck$LassoCheckResult]: Stem: 11244#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 11245#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 11253#L367 assume !(main_~length~0 < 1); 11246#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 11247#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 11248#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11254#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11296#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11255#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11256#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11257#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11259#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11295#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11294#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11293#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11292#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11291#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11290#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11289#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11288#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11287#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11286#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11285#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11284#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11283#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11282#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11281#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11280#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11279#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11278#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11277#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11276#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11275#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11274#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11273#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11272#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11271#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11270#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11269#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11268#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11267#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11266#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11265#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11264#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11263#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11261#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11262#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11260#L370-3 assume !(main_~i~0 < main_~length~0); 11249#L370-4 main_~j~0 := 0; 11250#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11251#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11252#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11258#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11320#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11319#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11318#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11317#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11316#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11315#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11314#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11313#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11312#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11311#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11310#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11309#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11308#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11307#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11306#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11305#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11304#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11303#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11302#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11301#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11300#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11299#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11298#L378-2 [2021-11-07 08:33:27,011 INFO L793 eck$LassoCheckResult]: Loop: 11298#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11297#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 11298#L378-2 [2021-11-07 08:33:27,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:27,012 INFO L85 PathProgramCache]: Analyzing trace with hash -586392489, now seen corresponding path program 38 times [2021-11-07 08:33:27,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:27,012 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642700381] [2021-11-07 08:33:27,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:27,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:27,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:27,059 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:27,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:27,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:27,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:27,105 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 42 times [2021-11-07 08:33:27,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:27,106 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672199820] [2021-11-07 08:33:27,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:27,106 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:27,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:27,118 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:27,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:27,120 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:27,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:27,121 INFO L85 PathProgramCache]: Analyzing trace with hash -882464806, now seen corresponding path program 38 times [2021-11-07 08:33:27,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:27,121 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916918123] [2021-11-07 08:33:27,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:27,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:27,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:27,837 INFO L134 CoverageAnalysis]: Checked inductivity of 469 backedges. 0 proven. 469 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:27,838 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:27,838 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916918123] [2021-11-07 08:33:27,838 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916918123] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:27,838 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [911800155] [2021-11-07 08:33:27,838 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:33:27,838 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:27,838 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:27,840 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:27,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-11-07 08:33:28,942 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:33:28,942 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:28,944 INFO L263 TraceCheckSpWp]: Trace formula consists of 337 conjuncts, 61 conjunts are in the unsatisfiable core [2021-11-07 08:33:28,945 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:29,159 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:33:29,929 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:33:29,931 INFO L134 CoverageAnalysis]: Checked inductivity of 469 backedges. 0 proven. 469 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:29,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [911800155] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:29,932 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:29,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 32] total 47 [2021-11-07 08:33:29,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714871352] [2021-11-07 08:33:29,967 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:29,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-11-07 08:33:29,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=2132, Unknown=0, NotChecked=0, Total=2256 [2021-11-07 08:33:29,968 INFO L87 Difference]: Start difference. First operand 77 states and 93 transitions. cyclomatic complexity: 18 Second operand has 48 states, 47 states have (on average 2.25531914893617) internal successors, (106), 48 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:31,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:31,225 INFO L93 Difference]: Finished difference Result 111 states and 130 transitions. [2021-11-07 08:33:31,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-07 08:33:31,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111 states and 130 transitions. [2021-11-07 08:33:31,227 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:33:31,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111 states to 111 states and 130 transitions. [2021-11-07 08:33:31,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2021-11-07 08:33:31,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2021-11-07 08:33:31,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 130 transitions. [2021-11-07 08:33:31,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:31,229 INFO L681 BuchiCegarLoop]: Abstraction has 111 states and 130 transitions. [2021-11-07 08:33:31,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 130 transitions. [2021-11-07 08:33:31,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 83. [2021-11-07 08:33:31,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.216867469879518) internal successors, (101), 82 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:31,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 101 transitions. [2021-11-07 08:33:31,232 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 101 transitions. [2021-11-07 08:33:31,232 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 101 transitions. [2021-11-07 08:33:31,232 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-11-07 08:33:31,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 101 transitions. [2021-11-07 08:33:31,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:31,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:31,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:31,234 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:31,234 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:31,235 INFO L791 eck$LassoCheckResult]: Stem: 11715#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 11716#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 11723#L367 assume !(main_~length~0 < 1); 11717#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 11718#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 11719#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11724#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11768#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11725#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11726#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11727#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11729#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11767#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11766#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11765#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11764#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11763#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11762#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11761#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11760#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11759#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11758#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11757#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11756#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11755#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11754#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11753#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11752#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11751#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11750#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11749#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11748#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11747#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11746#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11745#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11744#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11743#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11742#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11741#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11740#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11739#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11738#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11737#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11736#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11735#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 11734#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 11733#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 11730#L370-3 assume !(main_~i~0 < main_~length~0); 11731#L370-4 main_~j~0 := 0; 11795#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11722#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11721#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11728#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11794#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11793#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11792#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11791#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11790#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11789#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11788#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11787#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11786#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11785#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11784#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11783#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11782#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11781#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11780#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11779#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11778#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11777#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11776#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11775#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11774#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11773#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11772#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11771#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 11770#L378-2 [2021-11-07 08:33:31,235 INFO L793 eck$LassoCheckResult]: Loop: 11770#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 11769#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 11770#L378-2 [2021-11-07 08:33:31,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:31,235 INFO L85 PathProgramCache]: Analyzing trace with hash -882464804, now seen corresponding path program 39 times [2021-11-07 08:33:31,236 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:31,236 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620571595] [2021-11-07 08:33:31,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:31,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:31,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:31,288 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:31,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:31,343 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:31,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:31,343 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 43 times [2021-11-07 08:33:31,344 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:31,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775138345] [2021-11-07 08:33:31,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:31,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:31,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:31,358 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:31,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:31,360 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:31,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:31,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1940117985, now seen corresponding path program 39 times [2021-11-07 08:33:31,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:31,360 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790263758] [2021-11-07 08:33:31,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:31,361 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:31,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:31,937 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 183 proven. 314 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:31,938 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:31,938 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790263758] [2021-11-07 08:33:31,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790263758] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:31,938 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [694043503] [2021-11-07 08:33:31,938 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:33:31,938 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:31,939 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:31,941 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:31,965 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-11-07 08:33:33,512 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2021-11-07 08:33:33,512 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:33,515 INFO L263 TraceCheckSpWp]: Trace formula consists of 348 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-07 08:33:33,517 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:34,188 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 210 proven. 287 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:34,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [694043503] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:34,189 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:34,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 49 [2021-11-07 08:33:34,189 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135545102] [2021-11-07 08:33:34,239 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:34,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-11-07 08:33:34,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=533, Invalid=1819, Unknown=0, NotChecked=0, Total=2352 [2021-11-07 08:33:34,241 INFO L87 Difference]: Start difference. First operand 83 states and 101 transitions. cyclomatic complexity: 20 Second operand has 49 states, 49 states have (on average 2.306122448979592) internal successors, (113), 49 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:34,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:34,695 INFO L93 Difference]: Finished difference Result 112 states and 130 transitions. [2021-11-07 08:33:34,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-07 08:33:34,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 130 transitions. [2021-11-07 08:33:34,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:34,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 82 states and 100 transitions. [2021-11-07 08:33:34,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2021-11-07 08:33:34,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2021-11-07 08:33:34,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 100 transitions. [2021-11-07 08:33:34,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:34,700 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 100 transitions. [2021-11-07 08:33:34,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 100 transitions. [2021-11-07 08:33:34,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2021-11-07 08:33:34,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.2125) internal successors, (97), 79 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:34,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 97 transitions. [2021-11-07 08:33:34,702 INFO L704 BuchiCegarLoop]: Abstraction has 80 states and 97 transitions. [2021-11-07 08:33:34,702 INFO L587 BuchiCegarLoop]: Abstraction has 80 states and 97 transitions. [2021-11-07 08:33:34,702 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-11-07 08:33:34,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 97 transitions. [2021-11-07 08:33:34,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:34,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:34,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:34,703 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 15, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:34,703 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:34,703 INFO L791 eck$LassoCheckResult]: Stem: 12230#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 12231#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 12239#L367 assume !(main_~length~0 < 1); 12232#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 12233#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 12234#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12240#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12285#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12241#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12242#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12244#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12245#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12284#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12283#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12282#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12281#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12280#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12279#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12278#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12277#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12276#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12275#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12274#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12273#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12272#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12271#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12270#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12269#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12268#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12267#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12266#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12265#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12264#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12263#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12262#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12261#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12260#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12259#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12258#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12257#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12256#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12255#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12254#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12253#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12252#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12251#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12250#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12249#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12247#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12248#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12246#L370-3 assume !(main_~i~0 < main_~length~0); 12237#L370-4 main_~j~0 := 0; 12238#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12235#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12236#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12243#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12309#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12308#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12307#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12306#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12305#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12304#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12303#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12302#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12301#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12300#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12299#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12298#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12297#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12296#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12295#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12294#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12293#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12292#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12291#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12290#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12289#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12288#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12287#L378-2 [2021-11-07 08:33:34,704 INFO L793 eck$LassoCheckResult]: Loop: 12287#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12286#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 12287#L378-2 [2021-11-07 08:33:34,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:34,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1555350627, now seen corresponding path program 40 times [2021-11-07 08:33:34,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:34,705 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609253567] [2021-11-07 08:33:34,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:34,705 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:34,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:34,767 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:34,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:34,826 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:34,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:34,827 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 44 times [2021-11-07 08:33:34,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:34,827 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83434750] [2021-11-07 08:33:34,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:34,828 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:34,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:34,854 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:34,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:34,856 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:34,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:34,857 INFO L85 PathProgramCache]: Analyzing trace with hash -43332192, now seen corresponding path program 40 times [2021-11-07 08:33:34,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:34,857 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700239281] [2021-11-07 08:33:34,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:34,858 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:34,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:35,755 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:35,755 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:35,755 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700239281] [2021-11-07 08:33:35,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700239281] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:35,756 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1722037236] [2021-11-07 08:33:35,756 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:33:35,756 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:35,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:35,757 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:35,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-11-07 08:33:37,033 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:33:37,033 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:37,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 348 conjuncts, 67 conjunts are in the unsatisfiable core [2021-11-07 08:33:37,037 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:37,772 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:33:37,950 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:33:37,950 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:33:39,010 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:33:39,014 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:39,014 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1722037236] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:39,014 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:39,015 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35] total 67 [2021-11-07 08:33:39,015 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39135970] [2021-11-07 08:33:39,055 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:39,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2021-11-07 08:33:39,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=4319, Unknown=0, NotChecked=0, Total=4556 [2021-11-07 08:33:39,058 INFO L87 Difference]: Start difference. First operand 80 states and 97 transitions. cyclomatic complexity: 19 Second operand has 68 states, 67 states have (on average 2.328358208955224) internal successors, (156), 68 states have internal predecessors, (156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:41,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:41,293 INFO L93 Difference]: Finished difference Result 82 states and 99 transitions. [2021-11-07 08:33:41,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-07 08:33:41,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 99 transitions. [2021-11-07 08:33:41,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:41,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 82 states and 99 transitions. [2021-11-07 08:33:41,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-11-07 08:33:41,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-11-07 08:33:41,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 99 transitions. [2021-11-07 08:33:41,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:41,294 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 99 transitions. [2021-11-07 08:33:41,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 99 transitions. [2021-11-07 08:33:41,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2021-11-07 08:33:41,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.2073170731707317) internal successors, (99), 81 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:41,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 99 transitions. [2021-11-07 08:33:41,299 INFO L704 BuchiCegarLoop]: Abstraction has 82 states and 99 transitions. [2021-11-07 08:33:41,299 INFO L587 BuchiCegarLoop]: Abstraction has 82 states and 99 transitions. [2021-11-07 08:33:41,299 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-11-07 08:33:41,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 99 transitions. [2021-11-07 08:33:41,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:41,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:41,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:41,301 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:41,301 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:41,302 INFO L791 eck$LassoCheckResult]: Stem: 12734#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 12735#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 12743#L367 assume !(main_~length~0 < 1); 12736#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 12737#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 12738#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12744#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12789#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12745#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12746#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12748#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12749#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12788#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12787#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12786#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12785#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12784#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12783#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12782#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12781#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12780#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12779#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12778#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12777#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12776#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12775#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12774#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12773#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12772#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12771#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12770#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12769#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12768#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12767#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12766#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12765#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12764#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12763#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12762#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12761#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12760#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12759#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12758#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12757#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12756#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12755#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12754#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12753#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 12751#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 12752#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 12750#L370-3 assume !(main_~i~0 < main_~length~0); 12739#L370-4 main_~j~0 := 0; 12740#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12741#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12742#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12747#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12815#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12814#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12813#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12812#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12811#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12810#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12809#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12808#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12807#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12806#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12805#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12804#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12803#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12802#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12801#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12800#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12799#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12798#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12797#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12796#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12795#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12794#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12793#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12792#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 12791#L378-2 [2021-11-07 08:33:41,303 INFO L793 eck$LassoCheckResult]: Loop: 12791#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 12790#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 12791#L378-2 [2021-11-07 08:33:41,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:41,303 INFO L85 PathProgramCache]: Analyzing trace with hash -43332190, now seen corresponding path program 41 times [2021-11-07 08:33:41,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:41,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343166787] [2021-11-07 08:33:41,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:41,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:41,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:41,354 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:41,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:41,408 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:41,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:41,409 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 45 times [2021-11-07 08:33:41,409 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:41,409 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632822614] [2021-11-07 08:33:41,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:41,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:41,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:41,424 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:41,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:41,426 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:41,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:41,427 INFO L85 PathProgramCache]: Analyzing trace with hash 1307439717, now seen corresponding path program 41 times [2021-11-07 08:33:41,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:41,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344475847] [2021-11-07 08:33:41,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:41,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:41,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:42,194 INFO L134 CoverageAnalysis]: Checked inductivity of 540 backedges. 0 proven. 540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:42,194 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:42,194 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344475847] [2021-11-07 08:33:42,194 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344475847] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:42,195 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [486459807] [2021-11-07 08:33:42,195 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:33:42,195 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:42,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:42,196 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:42,197 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-11-07 08:33:43,743 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2021-11-07 08:33:43,744 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:43,748 INFO L263 TraceCheckSpWp]: Trace formula consists of 359 conjuncts, 65 conjunts are in the unsatisfiable core [2021-11-07 08:33:43,750 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:43,993 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:33:44,884 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:33:44,888 INFO L134 CoverageAnalysis]: Checked inductivity of 540 backedges. 0 proven. 540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:44,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [486459807] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:44,889 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:44,889 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 51 [2021-11-07 08:33:44,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652056401] [2021-11-07 08:33:44,927 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:44,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-11-07 08:33:44,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=2516, Unknown=0, NotChecked=0, Total=2652 [2021-11-07 08:33:44,929 INFO L87 Difference]: Start difference. First operand 82 states and 99 transitions. cyclomatic complexity: 19 Second operand has 52 states, 51 states have (on average 2.2549019607843137) internal successors, (115), 52 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:46,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:46,496 INFO L93 Difference]: Finished difference Result 118 states and 138 transitions. [2021-11-07 08:33:46,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-07 08:33:46,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 138 transitions. [2021-11-07 08:33:46,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:33:46,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 138 transitions. [2021-11-07 08:33:46,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2021-11-07 08:33:46,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2021-11-07 08:33:46,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 138 transitions. [2021-11-07 08:33:46,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:46,499 INFO L681 BuchiCegarLoop]: Abstraction has 118 states and 138 transitions. [2021-11-07 08:33:46,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 138 transitions. [2021-11-07 08:33:46,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 88. [2021-11-07 08:33:46,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.2159090909090908) internal successors, (107), 87 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:46,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 107 transitions. [2021-11-07 08:33:46,502 INFO L704 BuchiCegarLoop]: Abstraction has 88 states and 107 transitions. [2021-11-07 08:33:46,502 INFO L587 BuchiCegarLoop]: Abstraction has 88 states and 107 transitions. [2021-11-07 08:33:46,502 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-11-07 08:33:46,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 107 transitions. [2021-11-07 08:33:46,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:46,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:46,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:46,504 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:46,504 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:46,504 INFO L791 eck$LassoCheckResult]: Stem: 13236#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 13237#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 13244#L367 assume !(main_~length~0 < 1); 13238#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 13239#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 13240#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13245#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13292#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13246#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13247#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13248#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13250#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13291#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13290#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13289#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13288#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13287#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13286#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13285#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13284#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13283#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13282#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13281#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13280#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13279#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13278#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13277#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13276#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13275#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13274#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13273#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13272#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13271#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13270#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13269#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13268#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13267#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13266#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13265#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13264#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13263#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13262#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13261#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13260#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13259#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13258#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13257#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13256#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13255#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13254#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13251#L370-3 assume !(main_~i~0 < main_~length~0); 13252#L370-4 main_~j~0 := 0; 13321#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13243#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13242#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13249#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13320#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13319#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13318#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13317#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13316#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13315#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13314#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13313#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13312#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13311#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13310#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13309#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13308#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13307#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13306#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13305#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13304#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13303#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13302#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13301#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13300#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13299#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13298#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13297#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13296#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13295#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13294#L378-2 [2021-11-07 08:33:46,505 INFO L793 eck$LassoCheckResult]: Loop: 13294#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13293#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 13294#L378-2 [2021-11-07 08:33:46,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:46,505 INFO L85 PathProgramCache]: Analyzing trace with hash 1307439719, now seen corresponding path program 42 times [2021-11-07 08:33:46,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:46,506 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739788879] [2021-11-07 08:33:46,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:46,506 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:46,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:46,622 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:46,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:46,679 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:46,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:46,680 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 46 times [2021-11-07 08:33:46,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:46,681 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95204905] [2021-11-07 08:33:46,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:46,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:46,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:46,696 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:46,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:46,698 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:46,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:46,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1975846422, now seen corresponding path program 42 times [2021-11-07 08:33:46,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:46,699 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747448183] [2021-11-07 08:33:46,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:46,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:46,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:47,207 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 211 proven. 359 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:47,208 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:47,208 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1747448183] [2021-11-07 08:33:47,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1747448183] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:47,208 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [359031666] [2021-11-07 08:33:47,208 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:33:47,208 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:47,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:47,221 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:47,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-11-07 08:33:48,828 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2021-11-07 08:33:48,828 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:48,832 INFO L263 TraceCheckSpWp]: Trace formula consists of 370 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-07 08:33:48,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:49,600 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 240 proven. 330 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:49,600 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [359031666] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:49,600 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:49,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 52 [2021-11-07 08:33:49,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419870833] [2021-11-07 08:33:49,639 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:49,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-11-07 08:33:49,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=600, Invalid=2052, Unknown=0, NotChecked=0, Total=2652 [2021-11-07 08:33:49,641 INFO L87 Difference]: Start difference. First operand 88 states and 107 transitions. cyclomatic complexity: 21 Second operand has 52 states, 52 states have (on average 2.3076923076923075) internal successors, (120), 52 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:50,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:50,174 INFO L93 Difference]: Finished difference Result 119 states and 138 transitions. [2021-11-07 08:33:50,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-07 08:33:50,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 138 transitions. [2021-11-07 08:33:50,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:50,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 87 states and 106 transitions. [2021-11-07 08:33:50,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-11-07 08:33:50,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-11-07 08:33:50,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 106 transitions. [2021-11-07 08:33:50,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:50,182 INFO L681 BuchiCegarLoop]: Abstraction has 87 states and 106 transitions. [2021-11-07 08:33:50,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 106 transitions. [2021-11-07 08:33:50,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 85. [2021-11-07 08:33:50,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.2117647058823529) internal successors, (103), 84 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:50,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 103 transitions. [2021-11-07 08:33:50,185 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 103 transitions. [2021-11-07 08:33:50,185 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 103 transitions. [2021-11-07 08:33:50,185 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-11-07 08:33:50,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 103 transitions. [2021-11-07 08:33:50,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:50,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:50,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:50,187 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 16, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:50,187 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:50,187 INFO L791 eck$LassoCheckResult]: Stem: 13783#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 13784#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 13792#L367 assume !(main_~length~0 < 1); 13785#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 13786#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 13787#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13793#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13841#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13794#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13795#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13797#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13798#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13840#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13839#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13838#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13837#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13836#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13835#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13834#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13833#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13832#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13831#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13830#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13829#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13828#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13827#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13826#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13825#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13824#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13823#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13822#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13821#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13820#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13819#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13818#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13817#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13816#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13815#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13814#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13813#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13812#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13811#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13810#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13809#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13808#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13807#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13806#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13805#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13804#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13803#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13802#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 13800#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 13801#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 13799#L370-3 assume !(main_~i~0 < main_~length~0); 13790#L370-4 main_~j~0 := 0; 13791#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13788#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13789#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13796#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13867#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13866#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13865#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13864#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13863#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13862#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13861#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13860#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13859#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13858#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13857#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13856#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13855#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13854#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13853#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13852#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13851#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13850#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13849#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13848#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13847#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13846#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13845#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13844#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 13843#L378-2 [2021-11-07 08:33:50,188 INFO L793 eck$LassoCheckResult]: Loop: 13843#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 13842#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 13843#L378-2 [2021-11-07 08:33:50,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:50,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1846708764, now seen corresponding path program 43 times [2021-11-07 08:33:50,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:50,188 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512210184] [2021-11-07 08:33:50,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:50,189 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:50,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:50,244 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:50,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:50,302 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:50,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:50,302 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 47 times [2021-11-07 08:33:50,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:50,303 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958062523] [2021-11-07 08:33:50,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:50,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:50,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:50,317 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:50,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:50,319 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:50,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:50,319 INFO L85 PathProgramCache]: Analyzing trace with hash 865630303, now seen corresponding path program 43 times [2021-11-07 08:33:50,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:50,319 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021194988] [2021-11-07 08:33:50,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:50,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:50,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:51,270 INFO L134 CoverageAnalysis]: Checked inductivity of 586 backedges. 0 proven. 586 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:51,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:51,270 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021194988] [2021-11-07 08:33:51,270 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021194988] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:51,270 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1045181132] [2021-11-07 08:33:51,271 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:33:51,271 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:51,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:51,274 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:51,275 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-11-07 08:33:52,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:52,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 370 conjuncts, 71 conjunts are in the unsatisfiable core [2021-11-07 08:33:52,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:33:53,615 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:33:53,811 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:33:53,811 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:33:55,002 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:33:55,005 INFO L134 CoverageAnalysis]: Checked inductivity of 586 backedges. 0 proven. 586 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:55,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1045181132] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:55,005 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:33:55,005 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 37] total 71 [2021-11-07 08:33:55,006 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168067300] [2021-11-07 08:33:55,044 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:33:55,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2021-11-07 08:33:55,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=4861, Unknown=0, NotChecked=0, Total=5112 [2021-11-07 08:33:55,046 INFO L87 Difference]: Start difference. First operand 85 states and 103 transitions. cyclomatic complexity: 20 Second operand has 72 states, 71 states have (on average 2.3380281690140845) internal successors, (166), 72 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:57,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:33:57,406 INFO L93 Difference]: Finished difference Result 87 states and 105 transitions. [2021-11-07 08:33:57,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-07 08:33:57,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 105 transitions. [2021-11-07 08:33:57,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:57,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 105 transitions. [2021-11-07 08:33:57,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2021-11-07 08:33:57,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2021-11-07 08:33:57,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 105 transitions. [2021-11-07 08:33:57,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:33:57,408 INFO L681 BuchiCegarLoop]: Abstraction has 87 states and 105 transitions. [2021-11-07 08:33:57,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 105 transitions. [2021-11-07 08:33:57,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2021-11-07 08:33:57,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.206896551724138) internal successors, (105), 86 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:33:57,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 105 transitions. [2021-11-07 08:33:57,410 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 105 transitions. [2021-11-07 08:33:57,410 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 105 transitions. [2021-11-07 08:33:57,410 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-11-07 08:33:57,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 105 transitions. [2021-11-07 08:33:57,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:33:57,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:33:57,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:33:57,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:33:57,412 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:33:57,412 INFO L791 eck$LassoCheckResult]: Stem: 14318#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 14319#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 14327#L367 assume !(main_~length~0 < 1); 14320#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 14321#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 14322#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14328#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14376#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14329#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14330#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14331#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14333#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14375#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14374#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14373#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14372#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14371#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14370#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14369#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14368#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14367#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14366#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14365#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14364#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14363#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14362#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14361#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14360#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14359#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14358#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14357#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14356#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14355#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14354#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14353#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14352#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14351#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14350#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14349#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14348#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14347#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14346#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14345#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14344#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14343#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14342#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14341#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14340#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14339#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14338#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14337#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14335#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14336#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14334#L370-3 assume !(main_~i~0 < main_~length~0); 14323#L370-4 main_~j~0 := 0; 14324#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14325#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14326#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14332#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14404#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14403#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14402#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14401#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14400#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14399#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14398#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14397#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14396#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14395#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14394#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14393#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14392#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14391#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14390#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14389#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14388#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14387#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14386#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14385#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14384#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14383#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14382#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14381#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14380#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14379#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14378#L378-2 [2021-11-07 08:33:57,412 INFO L793 eck$LassoCheckResult]: Loop: 14378#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14377#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 14378#L378-2 [2021-11-07 08:33:57,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:57,412 INFO L85 PathProgramCache]: Analyzing trace with hash 865630305, now seen corresponding path program 44 times [2021-11-07 08:33:57,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:57,413 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61865051] [2021-11-07 08:33:57,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:57,413 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:57,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:57,493 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:57,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:57,552 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:57,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:57,552 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 48 times [2021-11-07 08:33:57,552 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:57,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306119256] [2021-11-07 08:33:57,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:57,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:57,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:57,568 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:33:57,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:33:57,570 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:33:57,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:33:57,571 INFO L85 PathProgramCache]: Analyzing trace with hash -1352930972, now seen corresponding path program 44 times [2021-11-07 08:33:57,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:33:57,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735232429] [2021-11-07 08:33:57,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:33:57,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:33:57,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:33:58,437 INFO L134 CoverageAnalysis]: Checked inductivity of 616 backedges. 0 proven. 616 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:33:58,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:33:58,437 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735232429] [2021-11-07 08:33:58,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735232429] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:33:58,437 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1236866177] [2021-11-07 08:33:58,438 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:33:58,439 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:33:58,439 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:33:58,441 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:33:58,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-11-07 08:33:59,888 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:33:59,888 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:33:59,891 INFO L263 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 69 conjunts are in the unsatisfiable core [2021-11-07 08:33:59,894 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:00,270 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:34:01,300 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:34:01,305 INFO L134 CoverageAnalysis]: Checked inductivity of 616 backedges. 0 proven. 616 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:01,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1236866177] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:01,306 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:01,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36] total 53 [2021-11-07 08:34:01,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531820306] [2021-11-07 08:34:01,361 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:01,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2021-11-07 08:34:01,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=2722, Unknown=0, NotChecked=0, Total=2862 [2021-11-07 08:34:01,363 INFO L87 Difference]: Start difference. First operand 87 states and 105 transitions. cyclomatic complexity: 20 Second operand has 54 states, 53 states have (on average 2.2641509433962264) internal successors, (120), 54 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:02,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:02,983 INFO L93 Difference]: Finished difference Result 125 states and 146 transitions. [2021-11-07 08:34:02,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-11-07 08:34:02,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125 states and 146 transitions. [2021-11-07 08:34:02,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:34:02,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125 states to 125 states and 146 transitions. [2021-11-07 08:34:02,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74 [2021-11-07 08:34:02,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74 [2021-11-07 08:34:02,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125 states and 146 transitions. [2021-11-07 08:34:02,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:02,985 INFO L681 BuchiCegarLoop]: Abstraction has 125 states and 146 transitions. [2021-11-07 08:34:02,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states and 146 transitions. [2021-11-07 08:34:02,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 93. [2021-11-07 08:34:02,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.2150537634408602) internal successors, (113), 92 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:02,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 113 transitions. [2021-11-07 08:34:02,988 INFO L704 BuchiCegarLoop]: Abstraction has 93 states and 113 transitions. [2021-11-07 08:34:02,988 INFO L587 BuchiCegarLoop]: Abstraction has 93 states and 113 transitions. [2021-11-07 08:34:02,988 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-11-07 08:34:02,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 113 transitions. [2021-11-07 08:34:02,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:02,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:02,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:02,990 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:02,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:02,990 INFO L791 eck$LassoCheckResult]: Stem: 14849#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 14850#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 14857#L367 assume !(main_~length~0 < 1); 14851#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 14852#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 14853#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14858#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14908#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14859#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14860#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14861#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14863#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14907#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14906#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14905#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14904#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14903#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14902#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14901#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14900#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14899#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14898#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14897#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14896#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14895#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14894#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14893#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14892#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14891#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14890#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14889#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14888#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14887#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14886#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14885#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14884#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14883#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14882#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14881#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14880#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14879#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14878#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14877#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14876#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14875#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14874#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14873#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14872#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14871#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14870#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14869#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 14868#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 14867#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 14864#L370-3 assume !(main_~i~0 < main_~length~0); 14865#L370-4 main_~j~0 := 0; 14939#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14854#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14855#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14862#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14938#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14937#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14936#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14935#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14934#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14933#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14932#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14931#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14930#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14929#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14928#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14927#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14926#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14925#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14924#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14923#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14922#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14921#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14920#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14919#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14918#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14917#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14916#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14915#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14914#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14913#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14912#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14911#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 14910#L378-2 [2021-11-07 08:34:02,990 INFO L793 eck$LassoCheckResult]: Loop: 14910#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 14909#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 14910#L378-2 [2021-11-07 08:34:02,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:02,991 INFO L85 PathProgramCache]: Analyzing trace with hash -1352930970, now seen corresponding path program 45 times [2021-11-07 08:34:02,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:02,991 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703943359] [2021-11-07 08:34:02,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:02,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:03,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:03,051 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:03,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:03,111 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:03,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:03,113 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 49 times [2021-11-07 08:34:03,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:03,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308957927] [2021-11-07 08:34:03,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:03,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:03,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:03,133 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:03,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:03,136 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:03,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:03,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1208429865, now seen corresponding path program 45 times [2021-11-07 08:34:03,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:03,137 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139965167] [2021-11-07 08:34:03,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:03,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:03,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:03,788 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 241 proven. 407 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:03,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:03,789 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139965167] [2021-11-07 08:34:03,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139965167] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:03,789 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [210604037] [2021-11-07 08:34:03,789 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:34:03,790 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:03,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:03,795 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:03,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-11-07 08:34:05,554 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2021-11-07 08:34:05,554 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:05,558 INFO L263 TraceCheckSpWp]: Trace formula consists of 392 conjuncts, 36 conjunts are in the unsatisfiable core [2021-11-07 08:34:05,560 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:06,385 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 272 proven. 376 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:06,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [210604037] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:06,386 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:06,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 55 [2021-11-07 08:34:06,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252052331] [2021-11-07 08:34:06,422 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:06,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2021-11-07 08:34:06,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=671, Invalid=2299, Unknown=0, NotChecked=0, Total=2970 [2021-11-07 08:34:06,423 INFO L87 Difference]: Start difference. First operand 93 states and 113 transitions. cyclomatic complexity: 22 Second operand has 55 states, 55 states have (on average 2.309090909090909) internal successors, (127), 55 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:06,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:06,949 INFO L93 Difference]: Finished difference Result 126 states and 146 transitions. [2021-11-07 08:34:06,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-07 08:34:06,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 146 transitions. [2021-11-07 08:34:06,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:06,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 92 states and 112 transitions. [2021-11-07 08:34:06,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2021-11-07 08:34:06,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2021-11-07 08:34:06,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 112 transitions. [2021-11-07 08:34:06,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:06,953 INFO L681 BuchiCegarLoop]: Abstraction has 92 states and 112 transitions. [2021-11-07 08:34:06,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 112 transitions. [2021-11-07 08:34:06,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 90. [2021-11-07 08:34:06,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.211111111111111) internal successors, (109), 89 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:06,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 109 transitions. [2021-11-07 08:34:06,956 INFO L704 BuchiCegarLoop]: Abstraction has 90 states and 109 transitions. [2021-11-07 08:34:06,956 INFO L587 BuchiCegarLoop]: Abstraction has 90 states and 109 transitions. [2021-11-07 08:34:06,956 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-11-07 08:34:06,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 109 transitions. [2021-11-07 08:34:06,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:06,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:06,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:06,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 17, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:06,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:06,958 INFO L791 eck$LassoCheckResult]: Stem: 15428#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 15429#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 15437#L367 assume !(main_~length~0 < 1); 15430#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 15431#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 15432#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15438#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15489#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15439#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15440#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15442#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15443#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15488#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15487#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15486#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15485#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15484#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15483#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15482#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15481#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15480#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15479#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15478#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15477#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15476#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15475#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15474#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15473#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15472#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15471#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15470#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15469#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15468#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15467#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15466#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15465#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15464#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15463#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15462#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15461#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15460#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15459#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15458#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15457#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15456#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15455#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15454#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15453#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15452#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15451#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15450#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15449#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15448#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15447#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 15445#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 15446#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 15444#L370-3 assume !(main_~i~0 < main_~length~0); 15435#L370-4 main_~j~0 := 0; 15436#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15433#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15434#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15441#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15517#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15516#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15515#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15514#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15513#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15512#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15511#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15510#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15509#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15508#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15507#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15506#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15505#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15504#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15503#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15502#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15501#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15500#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15499#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15498#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15497#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15496#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15495#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15494#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15493#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15492#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 15491#L378-2 [2021-11-07 08:34:06,959 INFO L793 eck$LassoCheckResult]: Loop: 15491#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 15490#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 15491#L378-2 [2021-11-07 08:34:06,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:06,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1298827225, now seen corresponding path program 46 times [2021-11-07 08:34:06,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:06,959 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136803483] [2021-11-07 08:34:06,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:06,960 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:07,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:07,102 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:07,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:07,174 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:07,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:07,175 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 50 times [2021-11-07 08:34:07,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:07,176 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097220207] [2021-11-07 08:34:07,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:07,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:07,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:07,192 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:07,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:07,194 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:07,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:07,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1662521258, now seen corresponding path program 46 times [2021-11-07 08:34:07,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:07,195 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662161880] [2021-11-07 08:34:07,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:07,196 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:07,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:08,153 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 665 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:08,153 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:08,153 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662161880] [2021-11-07 08:34:08,153 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662161880] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:08,154 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [452117768] [2021-11-07 08:34:08,154 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:34:08,154 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:08,154 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:08,156 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:08,157 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-11-07 08:34:09,713 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:34:09,713 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:09,716 INFO L263 TraceCheckSpWp]: Trace formula consists of 392 conjuncts, 75 conjunts are in the unsatisfiable core [2021-11-07 08:34:09,717 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:10,752 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:34:10,944 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:34:10,944 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:34:12,186 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:34:12,196 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 665 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:12,196 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [452117768] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:12,196 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:12,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 39] total 75 [2021-11-07 08:34:12,197 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406366627] [2021-11-07 08:34:12,232 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:12,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2021-11-07 08:34:12,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=5435, Unknown=0, NotChecked=0, Total=5700 [2021-11-07 08:34:12,233 INFO L87 Difference]: Start difference. First operand 90 states and 109 transitions. cyclomatic complexity: 21 Second operand has 76 states, 75 states have (on average 2.3466666666666667) internal successors, (176), 76 states have internal predecessors, (176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:14,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:14,829 INFO L93 Difference]: Finished difference Result 92 states and 111 transitions. [2021-11-07 08:34:14,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-11-07 08:34:14,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92 states and 111 transitions. [2021-11-07 08:34:14,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:14,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92 states to 92 states and 111 transitions. [2021-11-07 08:34:14,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-11-07 08:34:14,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-11-07 08:34:14,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 111 transitions. [2021-11-07 08:34:14,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:14,833 INFO L681 BuchiCegarLoop]: Abstraction has 92 states and 111 transitions. [2021-11-07 08:34:14,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 111 transitions. [2021-11-07 08:34:14,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2021-11-07 08:34:14,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.2065217391304348) internal successors, (111), 91 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:14,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 111 transitions. [2021-11-07 08:34:14,835 INFO L704 BuchiCegarLoop]: Abstraction has 92 states and 111 transitions. [2021-11-07 08:34:14,836 INFO L587 BuchiCegarLoop]: Abstraction has 92 states and 111 transitions. [2021-11-07 08:34:14,836 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-11-07 08:34:14,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 111 transitions. [2021-11-07 08:34:14,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:14,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:14,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:14,837 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:14,837 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:14,837 INFO L791 eck$LassoCheckResult]: Stem: 15994#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 15995#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 16003#L367 assume !(main_~length~0 < 1); 15996#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 15997#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 15998#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16004#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16055#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16005#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16006#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16007#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16009#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16054#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16053#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16052#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16051#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16050#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16049#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16048#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16047#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16046#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16045#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16044#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16043#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16042#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16041#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16040#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16039#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16038#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16037#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16036#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16035#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16034#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16033#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16032#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16031#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16030#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16029#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16028#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16027#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16026#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16025#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16024#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16023#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16022#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16021#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16020#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16019#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16018#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16017#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16016#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16015#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16014#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16013#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16011#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16012#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16010#L370-3 assume !(main_~i~0 < main_~length~0); 15999#L370-4 main_~j~0 := 0; 16000#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16001#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16002#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16008#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16085#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16084#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16083#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16082#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16081#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16080#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16079#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16078#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16077#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16076#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16075#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16074#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16073#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16072#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16071#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16070#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16069#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16068#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16067#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16066#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16065#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16064#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16063#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16062#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16061#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16060#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16059#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16058#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16057#L378-2 [2021-11-07 08:34:14,837 INFO L793 eck$LassoCheckResult]: Loop: 16057#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16056#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 16057#L378-2 [2021-11-07 08:34:14,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:14,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1662521260, now seen corresponding path program 47 times [2021-11-07 08:34:14,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:14,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265216776] [2021-11-07 08:34:14,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:14,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:14,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:14,950 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:14,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:15,008 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:15,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:15,009 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 51 times [2021-11-07 08:34:15,009 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:15,009 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499649719] [2021-11-07 08:34:15,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:15,009 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:15,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:15,025 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:15,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:15,027 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:15,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:15,028 INFO L85 PathProgramCache]: Analyzing trace with hash -44901905, now seen corresponding path program 47 times [2021-11-07 08:34:15,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:15,028 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247762493] [2021-11-07 08:34:15,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:15,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:15,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:16,002 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 697 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:16,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:16,003 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247762493] [2021-11-07 08:34:16,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247762493] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:16,003 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2018624282] [2021-11-07 08:34:16,003 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:34:16,003 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:16,004 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:16,006 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:16,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-11-07 08:34:18,227 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2021-11-07 08:34:18,228 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:18,233 INFO L263 TraceCheckSpWp]: Trace formula consists of 403 conjuncts, 73 conjunts are in the unsatisfiable core [2021-11-07 08:34:18,235 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:18,534 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:34:19,686 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:34:19,690 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 697 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:19,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2018624282] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:19,691 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:19,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 57 [2021-11-07 08:34:19,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211065777] [2021-11-07 08:34:19,734 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:19,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2021-11-07 08:34:19,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=3154, Unknown=0, NotChecked=0, Total=3306 [2021-11-07 08:34:19,736 INFO L87 Difference]: Start difference. First operand 92 states and 111 transitions. cyclomatic complexity: 21 Second operand has 58 states, 57 states have (on average 2.263157894736842) internal successors, (129), 58 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:21,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:21,880 INFO L93 Difference]: Finished difference Result 132 states and 154 transitions. [2021-11-07 08:34:21,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-11-07 08:34:21,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 154 transitions. [2021-11-07 08:34:21,881 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:34:21,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 132 states and 154 transitions. [2021-11-07 08:34:21,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78 [2021-11-07 08:34:21,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78 [2021-11-07 08:34:21,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 154 transitions. [2021-11-07 08:34:21,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:21,882 INFO L681 BuchiCegarLoop]: Abstraction has 132 states and 154 transitions. [2021-11-07 08:34:21,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 154 transitions. [2021-11-07 08:34:21,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 98. [2021-11-07 08:34:21,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.2142857142857142) internal successors, (119), 97 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:21,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 119 transitions. [2021-11-07 08:34:21,885 INFO L704 BuchiCegarLoop]: Abstraction has 98 states and 119 transitions. [2021-11-07 08:34:21,885 INFO L587 BuchiCegarLoop]: Abstraction has 98 states and 119 transitions. [2021-11-07 08:34:21,885 INFO L425 BuchiCegarLoop]: ======== Iteration 53============ [2021-11-07 08:34:21,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 119 transitions. [2021-11-07 08:34:21,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:21,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:21,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:21,887 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:21,887 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:21,887 INFO L791 eck$LassoCheckResult]: Stem: 16556#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 16557#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 16564#L367 assume !(main_~length~0 < 1); 16558#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 16559#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 16560#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16565#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16618#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16566#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16567#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16568#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16570#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16617#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16616#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16615#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16614#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16613#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16612#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16611#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16610#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16609#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16608#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16607#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16606#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16605#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16604#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16603#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16602#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16601#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16600#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16599#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16598#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16597#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16596#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16595#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16594#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16593#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16592#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16591#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16590#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16589#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16588#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16587#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16586#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16585#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16584#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16583#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16582#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16581#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16580#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16579#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16578#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16577#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16576#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 16575#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 16574#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 16571#L370-3 assume !(main_~i~0 < main_~length~0); 16572#L370-4 main_~j~0 := 0; 16651#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16563#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16562#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16569#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16650#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16649#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16648#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16647#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16646#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16645#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16644#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16643#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16642#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16641#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16640#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16639#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16638#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16637#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16636#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16635#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16634#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16633#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16632#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16631#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16630#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16629#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16628#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16627#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16626#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16625#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16624#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16623#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16622#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16621#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 16620#L378-2 [2021-11-07 08:34:21,888 INFO L793 eck$LassoCheckResult]: Loop: 16620#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 16619#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 16620#L378-2 [2021-11-07 08:34:21,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:21,888 INFO L85 PathProgramCache]: Analyzing trace with hash -44901903, now seen corresponding path program 48 times [2021-11-07 08:34:21,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:21,889 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776567498] [2021-11-07 08:34:21,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:21,889 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:21,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:21,958 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:22,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:22,030 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:22,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:22,031 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 52 times [2021-11-07 08:34:22,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:22,031 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666911625] [2021-11-07 08:34:22,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:22,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:22,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:22,050 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:22,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:22,053 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:22,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:22,053 INFO L85 PathProgramCache]: Analyzing trace with hash -201054476, now seen corresponding path program 48 times [2021-11-07 08:34:22,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:22,054 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148622761] [2021-11-07 08:34:22,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:22,054 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:22,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:22,677 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 273 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:22,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:22,677 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148622761] [2021-11-07 08:34:22,678 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148622761] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:22,678 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1168545395] [2021-11-07 08:34:22,678 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:34:22,678 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:22,678 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:22,680 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:22,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-11-07 08:34:25,248 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 18 check-sat command(s) [2021-11-07 08:34:25,248 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:25,254 INFO L263 TraceCheckSpWp]: Trace formula consists of 414 conjuncts, 38 conjunts are in the unsatisfiable core [2021-11-07 08:34:25,256 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:26,305 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 306 proven. 425 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:26,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1168545395] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:26,305 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:26,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 58 [2021-11-07 08:34:26,305 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537422581] [2021-11-07 08:34:26,341 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:26,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2021-11-07 08:34:26,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=746, Invalid=2560, Unknown=0, NotChecked=0, Total=3306 [2021-11-07 08:34:26,342 INFO L87 Difference]: Start difference. First operand 98 states and 119 transitions. cyclomatic complexity: 23 Second operand has 58 states, 58 states have (on average 2.310344827586207) internal successors, (134), 58 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:26,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:26,883 INFO L93 Difference]: Finished difference Result 133 states and 154 transitions. [2021-11-07 08:34:26,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-11-07 08:34:26,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 154 transitions. [2021-11-07 08:34:26,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:26,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 97 states and 118 transitions. [2021-11-07 08:34:26,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-11-07 08:34:26,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-11-07 08:34:26,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 118 transitions. [2021-11-07 08:34:26,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:26,886 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 118 transitions. [2021-11-07 08:34:26,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 118 transitions. [2021-11-07 08:34:26,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 95. [2021-11-07 08:34:26,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.2105263157894737) internal successors, (115), 94 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:26,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 115 transitions. [2021-11-07 08:34:26,888 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 115 transitions. [2021-11-07 08:34:26,888 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 115 transitions. [2021-11-07 08:34:26,888 INFO L425 BuchiCegarLoop]: ======== Iteration 54============ [2021-11-07 08:34:26,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 115 transitions. [2021-11-07 08:34:26,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:26,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:26,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:26,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 18, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:26,890 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:26,891 INFO L791 eck$LassoCheckResult]: Stem: 17167#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 17168#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 17176#L367 assume !(main_~length~0 < 1); 17169#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 17170#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 17171#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17177#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17231#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17178#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17179#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17181#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17182#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17230#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17229#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17228#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17227#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17226#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17225#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17224#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17223#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17222#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17221#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17220#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17219#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17218#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17217#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17216#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17215#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17214#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17213#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17212#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17211#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17210#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17209#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17208#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17207#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17206#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17205#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17204#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17203#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17202#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17201#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17200#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17199#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17198#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17197#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17196#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17195#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17194#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17193#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17192#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17191#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17190#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17189#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17188#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17187#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17186#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17184#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17185#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17183#L370-3 assume !(main_~i~0 < main_~length~0); 17174#L370-4 main_~j~0 := 0; 17175#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17172#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17173#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17180#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17261#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17260#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17259#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17258#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17257#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17256#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17255#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17254#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17253#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17252#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17251#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17250#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17249#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17248#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17247#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17246#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17245#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17244#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17243#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17242#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17241#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17240#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17239#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17238#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17237#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17236#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17235#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17234#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17233#L378-2 [2021-11-07 08:34:26,891 INFO L793 eck$LassoCheckResult]: Loop: 17233#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17232#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 17233#L378-2 [2021-11-07 08:34:26,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:26,891 INFO L85 PathProgramCache]: Analyzing trace with hash 1463942054, now seen corresponding path program 49 times [2021-11-07 08:34:26,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:26,892 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670761498] [2021-11-07 08:34:26,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:26,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:26,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:26,951 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:27,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:27,009 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:27,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:27,010 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 53 times [2021-11-07 08:34:27,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:27,010 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126664288] [2021-11-07 08:34:27,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:27,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:27,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:27,027 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:27,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:27,029 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:27,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:27,029 INFO L85 PathProgramCache]: Analyzing trace with hash -1900957847, now seen corresponding path program 49 times [2021-11-07 08:34:27,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:27,030 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622773855] [2021-11-07 08:34:27,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:27,030 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:27,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:27,974 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 0 proven. 749 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:27,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:27,974 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622773855] [2021-11-07 08:34:27,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622773855] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:27,975 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [984901795] [2021-11-07 08:34:27,975 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:34:27,975 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:27,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:27,977 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:27,979 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-11-07 08:34:29,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:29,748 INFO L263 TraceCheckSpWp]: Trace formula consists of 414 conjuncts, 79 conjunts are in the unsatisfiable core [2021-11-07 08:34:29,750 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:30,743 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:34:30,942 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:34:30,943 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:34:32,301 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:34:32,304 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 0 proven. 749 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:32,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [984901795] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:32,304 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:32,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 41] total 79 [2021-11-07 08:34:32,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757744532] [2021-11-07 08:34:32,357 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:32,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2021-11-07 08:34:32,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=279, Invalid=6041, Unknown=0, NotChecked=0, Total=6320 [2021-11-07 08:34:32,358 INFO L87 Difference]: Start difference. First operand 95 states and 115 transitions. cyclomatic complexity: 22 Second operand has 80 states, 79 states have (on average 2.3544303797468356) internal successors, (186), 80 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:35,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:35,440 INFO L93 Difference]: Finished difference Result 97 states and 117 transitions. [2021-11-07 08:34:35,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-07 08:34:35,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 117 transitions. [2021-11-07 08:34:35,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:35,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 117 transitions. [2021-11-07 08:34:35,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2021-11-07 08:34:35,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2021-11-07 08:34:35,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 117 transitions. [2021-11-07 08:34:35,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:35,445 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 117 transitions. [2021-11-07 08:34:35,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 117 transitions. [2021-11-07 08:34:35,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2021-11-07 08:34:35,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.2061855670103092) internal successors, (117), 96 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:35,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 117 transitions. [2021-11-07 08:34:35,447 INFO L704 BuchiCegarLoop]: Abstraction has 97 states and 117 transitions. [2021-11-07 08:34:35,447 INFO L587 BuchiCegarLoop]: Abstraction has 97 states and 117 transitions. [2021-11-07 08:34:35,447 INFO L425 BuchiCegarLoop]: ======== Iteration 55============ [2021-11-07 08:34:35,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 117 transitions. [2021-11-07 08:34:35,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:35,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:35,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:35,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:35,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:35,450 INFO L791 eck$LassoCheckResult]: Stem: 17764#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 17765#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 17773#L367 assume !(main_~length~0 < 1); 17766#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 17767#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 17768#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17774#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17828#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17775#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17776#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17777#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17779#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17827#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17826#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17825#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17824#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17823#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17822#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17821#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17820#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17819#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17818#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17817#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17816#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17815#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17814#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17813#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17812#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17811#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17810#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17809#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17808#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17807#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17806#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17805#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17804#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17803#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17802#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17801#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17800#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17799#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17798#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17797#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17796#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17795#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17794#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17793#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17792#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17791#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17790#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17789#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17788#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17787#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17786#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17785#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17784#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17783#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 17781#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 17782#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 17780#L370-3 assume !(main_~i~0 < main_~length~0); 17769#L370-4 main_~j~0 := 0; 17770#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17771#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17772#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17778#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17860#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17859#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17858#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17857#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17856#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17855#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17854#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17853#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17852#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17851#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17850#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17849#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17848#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17847#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17846#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17845#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17844#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17843#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17842#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17841#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17840#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17839#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17838#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17837#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17836#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17835#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17834#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17833#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17832#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17831#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 17830#L378-2 [2021-11-07 08:34:35,450 INFO L793 eck$LassoCheckResult]: Loop: 17830#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 17829#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 17830#L378-2 [2021-11-07 08:34:35,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:35,450 INFO L85 PathProgramCache]: Analyzing trace with hash -1900957845, now seen corresponding path program 50 times [2021-11-07 08:34:35,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:35,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322195904] [2021-11-07 08:34:35,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:35,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:35,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:35,518 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:35,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:35,590 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:35,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:35,591 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 54 times [2021-11-07 08:34:35,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:35,591 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960815884] [2021-11-07 08:34:35,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:35,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:35,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:35,609 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:35,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:35,611 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:35,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:35,612 INFO L85 PathProgramCache]: Analyzing trace with hash -1459386898, now seen corresponding path program 50 times [2021-11-07 08:34:35,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:35,612 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106512899] [2021-11-07 08:34:35,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:35,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:35,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:36,878 INFO L134 CoverageAnalysis]: Checked inductivity of 783 backedges. 0 proven. 783 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:36,878 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:36,878 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106512899] [2021-11-07 08:34:36,878 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106512899] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:36,878 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [833638168] [2021-11-07 08:34:36,879 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:34:36,879 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:36,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:36,881 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:36,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-11-07 08:34:38,940 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:34:38,940 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:38,943 INFO L263 TraceCheckSpWp]: Trace formula consists of 425 conjuncts, 77 conjunts are in the unsatisfiable core [2021-11-07 08:34:38,945 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:39,280 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:34:40,471 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:34:40,474 INFO L134 CoverageAnalysis]: Checked inductivity of 783 backedges. 0 proven. 783 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:40,474 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [833638168] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:40,474 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:40,474 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 40] total 59 [2021-11-07 08:34:40,474 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902063922] [2021-11-07 08:34:40,516 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:40,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2021-11-07 08:34:40,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=156, Invalid=3384, Unknown=0, NotChecked=0, Total=3540 [2021-11-07 08:34:40,517 INFO L87 Difference]: Start difference. First operand 97 states and 117 transitions. cyclomatic complexity: 22 Second operand has 60 states, 59 states have (on average 2.2711864406779663) internal successors, (134), 60 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:42,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:42,777 INFO L93 Difference]: Finished difference Result 139 states and 162 transitions. [2021-11-07 08:34:42,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-07 08:34:42,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 162 transitions. [2021-11-07 08:34:42,778 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:34:42,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 139 states and 162 transitions. [2021-11-07 08:34:42,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82 [2021-11-07 08:34:42,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82 [2021-11-07 08:34:42,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 162 transitions. [2021-11-07 08:34:42,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:42,779 INFO L681 BuchiCegarLoop]: Abstraction has 139 states and 162 transitions. [2021-11-07 08:34:42,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 162 transitions. [2021-11-07 08:34:42,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 103. [2021-11-07 08:34:42,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.2135922330097086) internal successors, (125), 102 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:42,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 125 transitions. [2021-11-07 08:34:42,782 INFO L704 BuchiCegarLoop]: Abstraction has 103 states and 125 transitions. [2021-11-07 08:34:42,782 INFO L587 BuchiCegarLoop]: Abstraction has 103 states and 125 transitions. [2021-11-07 08:34:42,783 INFO L425 BuchiCegarLoop]: ======== Iteration 56============ [2021-11-07 08:34:42,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 125 transitions. [2021-11-07 08:34:42,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:42,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:42,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:42,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:42,785 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:42,785 INFO L791 eck$LassoCheckResult]: Stem: 18355#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 18356#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 18363#L367 assume !(main_~length~0 < 1); 18357#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 18358#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 18359#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18364#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18420#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18365#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18366#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18367#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18369#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18419#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18418#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18417#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18416#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18415#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18414#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18413#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18412#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18411#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18410#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18409#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18408#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18407#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18406#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18405#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18404#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18403#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18402#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18401#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18400#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18399#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18398#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18397#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18396#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18395#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18394#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18393#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18392#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18391#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18390#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18389#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18388#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18387#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18386#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18385#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18384#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18383#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18382#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18381#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18380#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18379#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18378#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18377#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18376#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18375#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 18374#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 18373#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 18370#L370-3 assume !(main_~i~0 < main_~length~0); 18371#L370-4 main_~j~0 := 0; 18455#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18362#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18361#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18368#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18454#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18453#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18452#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18451#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18450#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18449#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18448#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18447#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18446#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18445#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18444#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18443#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18442#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18441#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18440#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18439#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18438#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18437#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18436#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18435#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18434#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18433#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18432#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18431#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18430#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18429#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18428#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18427#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18426#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18425#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18424#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18423#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 18422#L378-2 [2021-11-07 08:34:42,785 INFO L793 eck$LassoCheckResult]: Loop: 18422#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 18421#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 18422#L378-2 [2021-11-07 08:34:42,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:42,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1459386896, now seen corresponding path program 51 times [2021-11-07 08:34:42,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:42,786 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61025573] [2021-11-07 08:34:42,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:42,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:42,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:42,908 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:42,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:42,975 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:42,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:42,976 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 55 times [2021-11-07 08:34:42,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:42,976 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275944973] [2021-11-07 08:34:42,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:42,976 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:42,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:42,996 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:42,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:42,998 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:42,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:42,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1983500083, now seen corresponding path program 51 times [2021-11-07 08:34:42,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:42,999 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409415103] [2021-11-07 08:34:42,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:43,000 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:43,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:43,773 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 307 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:43,774 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:43,774 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409415103] [2021-11-07 08:34:43,774 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409415103] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:43,774 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [210268267] [2021-11-07 08:34:43,774 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:34:43,774 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:43,774 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:43,781 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:43,800 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-11-07 08:34:46,780 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2021-11-07 08:34:46,780 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:46,788 INFO L263 TraceCheckSpWp]: Trace formula consists of 436 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-07 08:34:46,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:47,795 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 342 proven. 477 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:47,795 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [210268267] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:47,795 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:47,795 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 61 [2021-11-07 08:34:47,796 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470641146] [2021-11-07 08:34:47,831 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:47,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2021-11-07 08:34:47,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=825, Invalid=2835, Unknown=0, NotChecked=0, Total=3660 [2021-11-07 08:34:47,832 INFO L87 Difference]: Start difference. First operand 103 states and 125 transitions. cyclomatic complexity: 24 Second operand has 61 states, 61 states have (on average 2.3114754098360657) internal successors, (141), 61 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:48,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:48,466 INFO L93 Difference]: Finished difference Result 140 states and 162 transitions. [2021-11-07 08:34:48,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-07 08:34:48,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 162 transitions. [2021-11-07 08:34:48,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:48,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 102 states and 124 transitions. [2021-11-07 08:34:48,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2021-11-07 08:34:48,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2021-11-07 08:34:48,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 124 transitions. [2021-11-07 08:34:48,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:48,468 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 124 transitions. [2021-11-07 08:34:48,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 124 transitions. [2021-11-07 08:34:48,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 100. [2021-11-07 08:34:48,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.21) internal successors, (121), 99 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:48,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 121 transitions. [2021-11-07 08:34:48,470 INFO L704 BuchiCegarLoop]: Abstraction has 100 states and 121 transitions. [2021-11-07 08:34:48,471 INFO L587 BuchiCegarLoop]: Abstraction has 100 states and 121 transitions. [2021-11-07 08:34:48,471 INFO L425 BuchiCegarLoop]: ======== Iteration 57============ [2021-11-07 08:34:48,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 121 transitions. [2021-11-07 08:34:48,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:48,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:48,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:48,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 19, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:48,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:48,473 INFO L791 eck$LassoCheckResult]: Stem: 18998#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 18999#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 19007#L367 assume !(main_~length~0 < 1); 19000#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 19001#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 19002#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19008#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19065#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19009#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19010#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19012#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19013#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19064#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19063#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19062#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19061#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19060#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19059#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19058#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19057#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19056#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19055#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19054#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19053#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19052#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19051#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19050#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19049#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19048#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19047#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19046#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19045#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19044#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19043#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19042#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19041#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19040#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19039#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19038#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19037#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19036#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19035#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19034#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19033#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19032#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19031#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19030#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19029#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19028#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19027#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19026#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19025#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19024#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19023#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19022#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19021#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19020#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19019#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19018#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19017#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19015#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19016#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19014#L370-3 assume !(main_~i~0 < main_~length~0); 19005#L370-4 main_~j~0 := 0; 19006#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19003#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19004#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19011#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19097#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19096#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19095#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19094#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19093#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19092#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19091#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19090#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19089#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19088#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19087#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19086#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19085#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19084#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19083#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19082#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19081#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19080#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19079#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19078#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19077#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19076#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19075#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19074#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19073#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19072#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19071#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19070#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19069#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19068#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19067#L378-2 [2021-11-07 08:34:48,473 INFO L793 eck$LassoCheckResult]: Loop: 19067#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19066#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 19067#L378-2 [2021-11-07 08:34:48,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:48,474 INFO L85 PathProgramCache]: Analyzing trace with hash 2040410033, now seen corresponding path program 52 times [2021-11-07 08:34:48,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:48,474 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170162002] [2021-11-07 08:34:48,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:48,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:48,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:48,594 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:48,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:48,661 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:48,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:48,662 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 56 times [2021-11-07 08:34:48,662 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:48,662 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963045868] [2021-11-07 08:34:48,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:48,663 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:48,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:48,681 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:48,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:48,683 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:48,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:48,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1966011212, now seen corresponding path program 52 times [2021-11-07 08:34:48,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:48,684 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218473428] [2021-11-07 08:34:48,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:48,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:48,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:50,088 INFO L134 CoverageAnalysis]: Checked inductivity of 838 backedges. 0 proven. 838 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:50,089 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:50,089 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218473428] [2021-11-07 08:34:50,089 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218473428] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:50,089 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1591443377] [2021-11-07 08:34:50,089 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:34:50,089 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:50,089 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:50,091 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:50,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-11-07 08:34:51,969 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:34:51,969 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:34:51,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 436 conjuncts, 83 conjunts are in the unsatisfiable core [2021-11-07 08:34:51,974 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:34:53,286 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:34:53,498 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:34:53,499 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:34:55,023 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:34:55,026 INFO L134 CoverageAnalysis]: Checked inductivity of 838 backedges. 0 proven. 838 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:55,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1591443377] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:55,027 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:34:55,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 43] total 83 [2021-11-07 08:34:55,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713970042] [2021-11-07 08:34:55,067 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:34:55,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2021-11-07 08:34:55,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=293, Invalid=6679, Unknown=0, NotChecked=0, Total=6972 [2021-11-07 08:34:55,068 INFO L87 Difference]: Start difference. First operand 100 states and 121 transitions. cyclomatic complexity: 23 Second operand has 84 states, 83 states have (on average 2.36144578313253) internal successors, (196), 84 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:58,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:34:58,109 INFO L93 Difference]: Finished difference Result 102 states and 123 transitions. [2021-11-07 08:34:58,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-11-07 08:34:58,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 123 transitions. [2021-11-07 08:34:58,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:58,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 102 states and 123 transitions. [2021-11-07 08:34:58,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2021-11-07 08:34:58,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2021-11-07 08:34:58,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 123 transitions. [2021-11-07 08:34:58,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:34:58,111 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 123 transitions. [2021-11-07 08:34:58,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 123 transitions. [2021-11-07 08:34:58,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2021-11-07 08:34:58,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.2058823529411764) internal successors, (123), 101 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:34:58,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 123 transitions. [2021-11-07 08:34:58,113 INFO L704 BuchiCegarLoop]: Abstraction has 102 states and 123 transitions. [2021-11-07 08:34:58,113 INFO L587 BuchiCegarLoop]: Abstraction has 102 states and 123 transitions. [2021-11-07 08:34:58,113 INFO L425 BuchiCegarLoop]: ======== Iteration 58============ [2021-11-07 08:34:58,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 123 transitions. [2021-11-07 08:34:58,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:34:58,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:34:58,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:34:58,115 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:34:58,115 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:34:58,115 INFO L791 eck$LassoCheckResult]: Stem: 19626#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 19627#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 19635#L367 assume !(main_~length~0 < 1); 19628#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 19629#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 19630#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19636#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19693#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19637#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19638#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19639#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19641#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19692#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19691#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19690#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19689#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19688#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19687#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19686#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19685#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19684#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19683#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19682#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19681#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19680#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19679#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19678#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19677#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19676#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19675#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19674#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19673#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19672#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19671#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19670#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19669#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19668#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19667#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19666#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19665#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19664#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19663#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19662#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19661#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19660#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19659#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19658#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19657#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19656#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19655#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19654#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19653#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19652#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19651#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19650#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19649#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19648#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19647#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19646#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19645#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 19643#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 19644#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 19642#L370-3 assume !(main_~i~0 < main_~length~0); 19631#L370-4 main_~j~0 := 0; 19632#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19633#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19634#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19640#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19727#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19726#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19725#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19724#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19723#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19722#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19721#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19720#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19719#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19718#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19717#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19716#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19715#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19714#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19713#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19712#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19711#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19710#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19709#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19708#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19707#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19706#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19705#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19704#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19703#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19702#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19701#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19700#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19699#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19698#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19697#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19696#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 19695#L378-2 [2021-11-07 08:34:58,115 INFO L793 eck$LassoCheckResult]: Loop: 19695#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 19694#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 19695#L378-2 [2021-11-07 08:34:58,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:58,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1966011210, now seen corresponding path program 53 times [2021-11-07 08:34:58,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:58,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030223916] [2021-11-07 08:34:58,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:58,116 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:58,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:58,217 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:58,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:58,291 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:58,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:58,292 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 57 times [2021-11-07 08:34:58,292 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:58,292 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302306849] [2021-11-07 08:34:58,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:58,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:58,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:58,311 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:34:58,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:34:58,312 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:34:58,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:34:58,313 INFO L85 PathProgramCache]: Analyzing trace with hash 448838777, now seen corresponding path program 53 times [2021-11-07 08:34:58,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:34:58,313 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255523560] [2021-11-07 08:34:58,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:34:58,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:34:58,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:34:59,601 INFO L134 CoverageAnalysis]: Checked inductivity of 874 backedges. 0 proven. 874 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:34:59,601 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:34:59,601 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255523560] [2021-11-07 08:34:59,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255523560] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:34:59,601 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [379963049] [2021-11-07 08:34:59,601 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:34:59,602 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:34:59,602 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:34:59,603 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:34:59,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-11-07 08:35:02,042 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2021-11-07 08:35:02,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:02,047 INFO L263 TraceCheckSpWp]: Trace formula consists of 447 conjuncts, 81 conjunts are in the unsatisfiable core [2021-11-07 08:35:02,054 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:02,414 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:35:04,178 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:35:04,181 INFO L134 CoverageAnalysis]: Checked inductivity of 874 backedges. 0 proven. 874 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:04,182 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [379963049] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:04,182 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:04,182 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 63 [2021-11-07 08:35:04,182 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080073279] [2021-11-07 08:35:04,226 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:04,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2021-11-07 08:35:04,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=3864, Unknown=0, NotChecked=0, Total=4032 [2021-11-07 08:35:04,228 INFO L87 Difference]: Start difference. First operand 102 states and 123 transitions. cyclomatic complexity: 23 Second operand has 64 states, 63 states have (on average 2.2698412698412698) internal successors, (143), 64 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:07,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:07,596 INFO L93 Difference]: Finished difference Result 146 states and 170 transitions. [2021-11-07 08:35:07,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-11-07 08:35:07,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146 states and 170 transitions. [2021-11-07 08:35:07,597 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:35:07,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146 states to 146 states and 170 transitions. [2021-11-07 08:35:07,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86 [2021-11-07 08:35:07,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86 [2021-11-07 08:35:07,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 170 transitions. [2021-11-07 08:35:07,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:07,599 INFO L681 BuchiCegarLoop]: Abstraction has 146 states and 170 transitions. [2021-11-07 08:35:07,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 170 transitions. [2021-11-07 08:35:07,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 108. [2021-11-07 08:35:07,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.212962962962963) internal successors, (131), 107 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:07,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 131 transitions. [2021-11-07 08:35:07,602 INFO L704 BuchiCegarLoop]: Abstraction has 108 states and 131 transitions. [2021-11-07 08:35:07,602 INFO L587 BuchiCegarLoop]: Abstraction has 108 states and 131 transitions. [2021-11-07 08:35:07,602 INFO L425 BuchiCegarLoop]: ======== Iteration 59============ [2021-11-07 08:35:07,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 131 transitions. [2021-11-07 08:35:07,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:07,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:07,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:07,604 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:07,604 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:07,604 INFO L791 eck$LassoCheckResult]: Stem: 20248#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 20249#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 20256#L367 assume !(main_~length~0 < 1); 20250#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 20251#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 20252#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20257#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20316#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20258#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20259#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20261#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20262#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20315#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20314#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20313#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20312#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20311#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20310#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20309#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20308#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20307#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20306#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20305#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20304#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20303#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20302#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20301#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20300#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20299#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20298#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20297#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20296#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20295#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20294#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20293#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20292#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20291#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20290#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20289#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20288#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20287#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20286#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20285#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20284#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20283#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20282#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20281#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20280#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20279#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20278#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20277#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20276#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20275#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20274#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20273#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20272#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20271#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20270#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20269#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20268#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20267#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20266#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20263#L370-3 assume !(main_~i~0 < main_~length~0); 20264#L370-4 main_~j~0 := 0; 20353#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20253#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20254#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20260#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20352#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20351#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20350#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20349#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20348#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20347#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20346#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20345#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20344#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20343#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20342#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20341#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20340#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20339#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20338#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20337#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20336#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20335#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20334#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20333#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20332#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20331#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20330#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20329#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20328#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20327#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20326#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20325#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20324#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20323#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20322#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20321#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20320#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20319#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20318#L378-2 [2021-11-07 08:35:07,605 INFO L793 eck$LassoCheckResult]: Loop: 20318#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20317#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 20318#L378-2 [2021-11-07 08:35:07,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:07,605 INFO L85 PathProgramCache]: Analyzing trace with hash 448838779, now seen corresponding path program 54 times [2021-11-07 08:35:07,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:07,606 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89221142] [2021-11-07 08:35:07,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:07,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:07,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:07,685 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:07,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:07,792 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:07,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:07,793 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 58 times [2021-11-07 08:35:07,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:07,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057881949] [2021-11-07 08:35:07,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:07,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:07,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:07,858 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:07,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:07,860 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:07,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:07,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1837338366, now seen corresponding path program 54 times [2021-11-07 08:35:07,861 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:07,861 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949090770] [2021-11-07 08:35:07,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:07,861 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:07,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:08,702 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 343 proven. 569 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:08,702 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:08,702 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949090770] [2021-11-07 08:35:08,702 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949090770] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:08,702 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [761252663] [2021-11-07 08:35:08,703 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:35:08,703 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:08,703 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:08,711 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:08,712 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-11-07 08:35:11,889 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2021-11-07 08:35:11,889 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:11,897 INFO L263 TraceCheckSpWp]: Trace formula consists of 458 conjuncts, 42 conjunts are in the unsatisfiable core [2021-11-07 08:35:11,898 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:12,937 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 380 proven. 532 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:12,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [761252663] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:12,938 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:12,938 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 64 [2021-11-07 08:35:12,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657608855] [2021-11-07 08:35:12,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:12,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2021-11-07 08:35:12,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=908, Invalid=3124, Unknown=0, NotChecked=0, Total=4032 [2021-11-07 08:35:12,990 INFO L87 Difference]: Start difference. First operand 108 states and 131 transitions. cyclomatic complexity: 25 Second operand has 64 states, 64 states have (on average 2.3125) internal successors, (148), 64 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:13,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:13,737 INFO L93 Difference]: Finished difference Result 147 states and 170 transitions. [2021-11-07 08:35:13,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-11-07 08:35:13,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147 states and 170 transitions. [2021-11-07 08:35:13,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:13,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147 states to 107 states and 130 transitions. [2021-11-07 08:35:13,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2021-11-07 08:35:13,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2021-11-07 08:35:13,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 130 transitions. [2021-11-07 08:35:13,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:13,739 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 130 transitions. [2021-11-07 08:35:13,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 130 transitions. [2021-11-07 08:35:13,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 105. [2021-11-07 08:35:13,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.2095238095238094) internal successors, (127), 104 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:13,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 127 transitions. [2021-11-07 08:35:13,741 INFO L704 BuchiCegarLoop]: Abstraction has 105 states and 127 transitions. [2021-11-07 08:35:13,741 INFO L587 BuchiCegarLoop]: Abstraction has 105 states and 127 transitions. [2021-11-07 08:35:13,741 INFO L425 BuchiCegarLoop]: ======== Iteration 60============ [2021-11-07 08:35:13,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 127 transitions. [2021-11-07 08:35:13,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:13,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:13,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:13,742 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 20, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:13,742 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:13,742 INFO L791 eck$LassoCheckResult]: Stem: 20925#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 20926#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 20932#L367 assume !(main_~length~0 < 1); 20923#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 20924#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 20927#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20933#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20993#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20934#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20935#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20936#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20938#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20992#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20991#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20990#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20989#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20988#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20987#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20986#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20985#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20984#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20983#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20982#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20981#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20980#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20979#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20978#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20977#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20976#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20975#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20974#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20973#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20972#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20971#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20970#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20969#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20968#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20967#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20966#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20965#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20964#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20963#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20962#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20961#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20960#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20959#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20958#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20957#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20956#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20955#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20954#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20953#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20952#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20951#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20950#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20949#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20948#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20947#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20946#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20945#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20944#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20943#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20942#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 20940#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 20941#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 20939#L370-3 assume !(main_~i~0 < main_~length~0); 20928#L370-4 main_~j~0 := 0; 20929#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20930#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20931#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20937#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21027#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21026#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21025#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21024#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21023#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21022#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21021#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21020#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21019#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21018#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21017#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21016#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21015#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21014#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21013#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21012#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21011#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21010#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21009#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21008#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21007#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21006#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21005#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21004#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21003#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21002#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21001#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21000#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20999#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20998#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20997#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20996#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 20995#L378-2 [2021-11-07 08:35:13,742 INFO L793 eck$LassoCheckResult]: Loop: 20995#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 20994#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 20995#L378-2 [2021-11-07 08:35:13,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:13,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1999095856, now seen corresponding path program 55 times [2021-11-07 08:35:13,743 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:13,743 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909501438] [2021-11-07 08:35:13,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:13,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:13,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:13,833 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:13,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:13,918 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:13,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:13,919 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 59 times [2021-11-07 08:35:13,919 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:13,919 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968935468] [2021-11-07 08:35:13,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:13,920 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:14,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:14,013 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:14,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:14,015 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:14,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:14,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1280737651, now seen corresponding path program 55 times [2021-11-07 08:35:14,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:14,017 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272046640] [2021-11-07 08:35:14,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:14,017 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:14,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:15,611 INFO L134 CoverageAnalysis]: Checked inductivity of 932 backedges. 0 proven. 932 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:15,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:15,612 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272046640] [2021-11-07 08:35:15,612 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272046640] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:15,612 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [844332969] [2021-11-07 08:35:15,612 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:35:15,612 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:15,612 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:15,621 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:15,637 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-11-07 08:35:18,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:18,547 INFO L263 TraceCheckSpWp]: Trace formula consists of 458 conjuncts, 87 conjunts are in the unsatisfiable core [2021-11-07 08:35:18,549 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:20,052 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:35:20,286 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:35:20,286 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:35:21,970 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:35:21,973 INFO L134 CoverageAnalysis]: Checked inductivity of 932 backedges. 0 proven. 932 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:21,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [844332969] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:21,974 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:21,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 45] total 87 [2021-11-07 08:35:21,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858326805] [2021-11-07 08:35:22,029 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:22,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2021-11-07 08:35:22,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=307, Invalid=7349, Unknown=0, NotChecked=0, Total=7656 [2021-11-07 08:35:22,031 INFO L87 Difference]: Start difference. First operand 105 states and 127 transitions. cyclomatic complexity: 24 Second operand has 88 states, 87 states have (on average 2.367816091954023) internal successors, (206), 88 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:25,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:25,816 INFO L93 Difference]: Finished difference Result 107 states and 129 transitions. [2021-11-07 08:35:25,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-07 08:35:25,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 129 transitions. [2021-11-07 08:35:25,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:25,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 129 transitions. [2021-11-07 08:35:25,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47 [2021-11-07 08:35:25,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2021-11-07 08:35:25,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 129 transitions. [2021-11-07 08:35:25,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:25,819 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 129 transitions. [2021-11-07 08:35:25,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 129 transitions. [2021-11-07 08:35:25,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2021-11-07 08:35:25,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107 states, 107 states have (on average 1.205607476635514) internal successors, (129), 106 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:25,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 129 transitions. [2021-11-07 08:35:25,822 INFO L704 BuchiCegarLoop]: Abstraction has 107 states and 129 transitions. [2021-11-07 08:35:25,822 INFO L587 BuchiCegarLoop]: Abstraction has 107 states and 129 transitions. [2021-11-07 08:35:25,822 INFO L425 BuchiCegarLoop]: ======== Iteration 61============ [2021-11-07 08:35:25,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states and 129 transitions. [2021-11-07 08:35:25,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:25,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:25,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:25,824 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:25,824 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:25,824 INFO L791 eck$LassoCheckResult]: Stem: 21582#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 21583#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 21591#L367 assume !(main_~length~0 < 1); 21584#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 21585#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 21586#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21592#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21652#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21593#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21594#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21596#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21597#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21651#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21650#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21649#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21648#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21647#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21646#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21645#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21644#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21643#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21642#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21641#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21640#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21639#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21638#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21637#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21636#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21635#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21634#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21633#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21632#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21631#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21630#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21629#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21628#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21627#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21626#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21625#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21624#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21623#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21622#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21621#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21620#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21619#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21618#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21617#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21616#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21615#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21614#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21613#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21612#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21611#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21610#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21609#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21608#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21607#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21606#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21605#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21604#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21603#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21602#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21601#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 21599#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 21600#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 21598#L370-3 assume !(main_~i~0 < main_~length~0); 21589#L370-4 main_~j~0 := 0; 21590#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21587#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21588#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21595#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21688#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21687#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21686#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21685#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21684#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21683#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21682#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21681#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21680#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21679#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21678#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21677#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21676#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21675#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21674#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21673#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21672#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21671#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21670#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21669#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21668#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21667#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21666#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21665#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21664#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21663#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21662#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21661#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21660#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21659#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21658#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21657#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21656#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21655#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 21654#L378-2 [2021-11-07 08:35:25,824 INFO L793 eck$LassoCheckResult]: Loop: 21654#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 21653#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 21654#L378-2 [2021-11-07 08:35:25,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:25,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1280737653, now seen corresponding path program 56 times [2021-11-07 08:35:25,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:25,826 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718252479] [2021-11-07 08:35:25,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:25,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:26,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:26,021 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:26,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:26,131 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:26,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:26,145 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 60 times [2021-11-07 08:35:26,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:26,145 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808269731] [2021-11-07 08:35:26,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:26,146 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:26,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:26,170 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:26,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:26,172 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:26,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:26,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1866728072, now seen corresponding path program 56 times [2021-11-07 08:35:26,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:26,173 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022817279] [2021-11-07 08:35:26,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:26,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:26,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:27,757 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 0 proven. 970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:27,757 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:27,757 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022817279] [2021-11-07 08:35:27,757 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022817279] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:27,758 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1199421243] [2021-11-07 08:35:27,758 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:35:27,758 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:27,758 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:27,760 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:27,776 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-11-07 08:35:30,612 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:35:30,612 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:30,615 INFO L263 TraceCheckSpWp]: Trace formula consists of 469 conjuncts, 85 conjunts are in the unsatisfiable core [2021-11-07 08:35:30,618 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:31,008 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:35:32,538 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:35:32,542 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 0 proven. 970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:32,542 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1199421243] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:32,542 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:32,542 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 44] total 65 [2021-11-07 08:35:32,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970403781] [2021-11-07 08:35:32,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:32,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2021-11-07 08:35:32,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=4118, Unknown=0, NotChecked=0, Total=4290 [2021-11-07 08:35:32,587 INFO L87 Difference]: Start difference. First operand 107 states and 129 transitions. cyclomatic complexity: 24 Second operand has 66 states, 65 states have (on average 2.276923076923077) internal successors, (148), 66 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:36,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:36,028 INFO L93 Difference]: Finished difference Result 153 states and 178 transitions. [2021-11-07 08:35:36,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-11-07 08:35:36,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153 states and 178 transitions. [2021-11-07 08:35:36,029 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:35:36,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153 states to 153 states and 178 transitions. [2021-11-07 08:35:36,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 [2021-11-07 08:35:36,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 [2021-11-07 08:35:36,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153 states and 178 transitions. [2021-11-07 08:35:36,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:36,033 INFO L681 BuchiCegarLoop]: Abstraction has 153 states and 178 transitions. [2021-11-07 08:35:36,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states and 178 transitions. [2021-11-07 08:35:36,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 113. [2021-11-07 08:35:36,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 113 states, 113 states have (on average 1.2123893805309736) internal successors, (137), 112 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:36,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 137 transitions. [2021-11-07 08:35:36,037 INFO L704 BuchiCegarLoop]: Abstraction has 113 states and 137 transitions. [2021-11-07 08:35:36,037 INFO L587 BuchiCegarLoop]: Abstraction has 113 states and 137 transitions. [2021-11-07 08:35:36,037 INFO L425 BuchiCegarLoop]: ======== Iteration 62============ [2021-11-07 08:35:36,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 113 states and 137 transitions. [2021-11-07 08:35:36,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:36,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:36,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:36,039 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:36,039 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:36,039 INFO L791 eck$LassoCheckResult]: Stem: 22233#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 22234#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 22241#L367 assume !(main_~length~0 < 1); 22235#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 22236#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 22237#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22242#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22304#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22243#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22244#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22245#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22247#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22303#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22302#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22301#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22300#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22299#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22298#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22297#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22296#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22295#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22294#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22293#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22292#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22291#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22290#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22289#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22288#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22287#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22286#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22285#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22284#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22283#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22282#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22281#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22280#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22279#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22278#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22277#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22276#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22275#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22274#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22273#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22272#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22271#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22270#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22269#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22268#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22267#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22266#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22265#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22264#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22263#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22262#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22261#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22260#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22259#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22258#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22257#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22256#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22255#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22254#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22253#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22252#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22251#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22248#L370-3 assume !(main_~i~0 < main_~length~0); 22249#L370-4 main_~j~0 := 0; 22343#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22240#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22239#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22246#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22342#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22341#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22340#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22339#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22338#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22337#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22336#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22335#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22334#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22333#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22332#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22331#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22330#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22329#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22328#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22327#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22326#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22325#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22324#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22323#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22322#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22321#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22320#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22319#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22318#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22317#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22316#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22315#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22314#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22313#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22312#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22311#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22310#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22309#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22308#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22307#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22306#L378-2 [2021-11-07 08:35:36,039 INFO L793 eck$LassoCheckResult]: Loop: 22306#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22305#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 22306#L378-2 [2021-11-07 08:35:36,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:36,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1866728070, now seen corresponding path program 57 times [2021-11-07 08:35:36,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:36,040 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286408366] [2021-11-07 08:35:36,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:36,040 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:36,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:36,130 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:36,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:36,221 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:36,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:36,222 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 61 times [2021-11-07 08:35:36,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:36,222 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557913238] [2021-11-07 08:35:36,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:36,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:36,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:36,247 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:36,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:36,249 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:36,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:36,250 INFO L85 PathProgramCache]: Analyzing trace with hash 1370655805, now seen corresponding path program 57 times [2021-11-07 08:35:36,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:36,250 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799814892] [2021-11-07 08:35:36,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:36,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:36,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:37,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 381 proven. 629 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:37,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:37,191 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799814892] [2021-11-07 08:35:37,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799814892] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:37,191 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2073151825] [2021-11-07 08:35:37,191 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:35:37,192 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:37,192 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:37,197 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:37,198 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2021-11-07 08:35:40,457 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2021-11-07 08:35:40,457 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:40,465 INFO L263 TraceCheckSpWp]: Trace formula consists of 480 conjuncts, 44 conjunts are in the unsatisfiable core [2021-11-07 08:35:40,467 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:41,621 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 420 proven. 590 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:41,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2073151825] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:41,622 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:41,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 67 [2021-11-07 08:35:41,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916184026] [2021-11-07 08:35:41,687 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:41,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2021-11-07 08:35:41,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=995, Invalid=3427, Unknown=0, NotChecked=0, Total=4422 [2021-11-07 08:35:41,689 INFO L87 Difference]: Start difference. First operand 113 states and 137 transitions. cyclomatic complexity: 26 Second operand has 67 states, 67 states have (on average 2.3134328358208953) internal successors, (155), 67 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:42,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:42,388 INFO L93 Difference]: Finished difference Result 154 states and 178 transitions. [2021-11-07 08:35:42,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-07 08:35:42,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 178 transitions. [2021-11-07 08:35:42,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:42,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 112 states and 136 transitions. [2021-11-07 08:35:42,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47 [2021-11-07 08:35:42,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2021-11-07 08:35:42,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112 states and 136 transitions. [2021-11-07 08:35:42,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:42,391 INFO L681 BuchiCegarLoop]: Abstraction has 112 states and 136 transitions. [2021-11-07 08:35:42,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states and 136 transitions. [2021-11-07 08:35:42,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 110. [2021-11-07 08:35:42,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.209090909090909) internal successors, (133), 109 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:42,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 133 transitions. [2021-11-07 08:35:42,394 INFO L704 BuchiCegarLoop]: Abstraction has 110 states and 133 transitions. [2021-11-07 08:35:42,394 INFO L587 BuchiCegarLoop]: Abstraction has 110 states and 133 transitions. [2021-11-07 08:35:42,394 INFO L425 BuchiCegarLoop]: ======== Iteration 63============ [2021-11-07 08:35:42,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 133 transitions. [2021-11-07 08:35:42,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:42,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:42,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:42,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 21, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:42,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:42,396 INFO L791 eck$LassoCheckResult]: Stem: 22940#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 22941#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 22949#L367 assume !(main_~length~0 < 1); 22942#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 22943#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 22944#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22950#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23013#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22951#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22952#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22953#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22955#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23012#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23011#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23010#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23009#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23008#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23007#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23006#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23005#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23004#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23003#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23002#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23001#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23000#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22999#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22998#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22997#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22996#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22995#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22994#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22993#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22992#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22991#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22990#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22989#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22988#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22987#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22986#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22985#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22984#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22983#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22982#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22981#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22980#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22979#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22978#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22977#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22976#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22975#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22974#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22973#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22972#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22971#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22970#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22969#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22968#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22967#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22966#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22965#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22964#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22963#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22962#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22961#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22960#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22959#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 22957#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 22958#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 22956#L370-3 assume !(main_~i~0 < main_~length~0); 22945#L370-4 main_~j~0 := 0; 22946#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22947#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 22948#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 22954#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23049#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23048#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23047#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23046#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23045#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23044#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23043#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23042#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23041#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23040#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23039#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23038#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23037#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23036#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23035#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23034#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23033#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23032#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23031#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23030#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23029#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23028#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23027#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23026#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23025#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23024#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23023#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23022#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23021#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23020#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23019#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23018#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23017#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23016#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23015#L378-2 [2021-11-07 08:35:42,396 INFO L793 eck$LassoCheckResult]: Loop: 23015#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23014#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 23015#L378-2 [2021-11-07 08:35:42,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:42,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1876172229, now seen corresponding path program 58 times [2021-11-07 08:35:42,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:42,397 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220035431] [2021-11-07 08:35:42,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:42,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:42,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:42,590 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:42,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:42,675 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:42,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:42,675 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 62 times [2021-11-07 08:35:42,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:42,676 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811942060] [2021-11-07 08:35:42,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:42,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:42,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:42,698 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:42,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:42,699 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:42,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:42,700 INFO L85 PathProgramCache]: Analyzing trace with hash 884753598, now seen corresponding path program 58 times [2021-11-07 08:35:42,700 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:42,700 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414964648] [2021-11-07 08:35:42,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:42,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:42,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:44,037 INFO L134 CoverageAnalysis]: Checked inductivity of 1031 backedges. 0 proven. 1031 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:44,037 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:44,037 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414964648] [2021-11-07 08:35:44,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414964648] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:44,037 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [296809041] [2021-11-07 08:35:44,038 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:35:44,038 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:44,038 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:44,042 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:44,045 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2021-11-07 08:35:46,365 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:35:46,365 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:46,368 INFO L263 TraceCheckSpWp]: Trace formula consists of 480 conjuncts, 91 conjunts are in the unsatisfiable core [2021-11-07 08:35:46,370 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:47,645 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:35:47,860 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:35:47,861 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:35:49,666 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:35:49,670 INFO L134 CoverageAnalysis]: Checked inductivity of 1031 backedges. 0 proven. 1031 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:49,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [296809041] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:49,670 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:35:49,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 47] total 91 [2021-11-07 08:35:49,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94863311] [2021-11-07 08:35:49,712 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:35:49,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2021-11-07 08:35:49,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=8051, Unknown=0, NotChecked=0, Total=8372 [2021-11-07 08:35:49,713 INFO L87 Difference]: Start difference. First operand 110 states and 133 transitions. cyclomatic complexity: 25 Second operand has 92 states, 91 states have (on average 2.3736263736263736) internal successors, (216), 92 states have internal predecessors, (216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:53,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:35:53,135 INFO L93 Difference]: Finished difference Result 112 states and 135 transitions. [2021-11-07 08:35:53,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-11-07 08:35:53,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 135 transitions. [2021-11-07 08:35:53,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:53,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 112 states and 135 transitions. [2021-11-07 08:35:53,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-11-07 08:35:53,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-11-07 08:35:53,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112 states and 135 transitions. [2021-11-07 08:35:53,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:35:53,137 INFO L681 BuchiCegarLoop]: Abstraction has 112 states and 135 transitions. [2021-11-07 08:35:53,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states and 135 transitions. [2021-11-07 08:35:53,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2021-11-07 08:35:53,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 112 states have (on average 1.2053571428571428) internal successors, (135), 111 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:35:53,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 135 transitions. [2021-11-07 08:35:53,139 INFO L704 BuchiCegarLoop]: Abstraction has 112 states and 135 transitions. [2021-11-07 08:35:53,139 INFO L587 BuchiCegarLoop]: Abstraction has 112 states and 135 transitions. [2021-11-07 08:35:53,139 INFO L425 BuchiCegarLoop]: ======== Iteration 64============ [2021-11-07 08:35:53,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112 states and 135 transitions. [2021-11-07 08:35:53,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:35:53,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:35:53,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:35:53,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:35:53,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:35:53,141 INFO L791 eck$LassoCheckResult]: Stem: 23630#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 23631#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 23639#L367 assume !(main_~length~0 < 1); 23632#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 23633#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 23634#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23640#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23703#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23641#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23642#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23644#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23645#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23702#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23701#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23700#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23699#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23698#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23697#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23696#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23695#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23694#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23693#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23692#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23691#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23690#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23689#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23688#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23687#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23686#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23685#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23684#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23683#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23682#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23681#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23680#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23679#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23678#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23677#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23676#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23675#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23674#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23673#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23672#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23671#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23670#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23669#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23668#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23667#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23666#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23665#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23664#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23663#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23662#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23661#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23660#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23659#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23658#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23657#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23656#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23655#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23654#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23653#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23652#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23651#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23650#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23649#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 23647#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 23648#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 23646#L370-3 assume !(main_~i~0 < main_~length~0); 23637#L370-4 main_~j~0 := 0; 23638#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23635#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23636#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23643#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23741#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23740#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23739#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23738#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23737#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23736#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23735#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23734#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23733#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23732#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23731#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23730#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23729#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23728#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23727#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23726#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23725#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23724#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23723#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23722#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23721#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23720#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23719#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23718#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23717#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23716#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23715#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23714#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23713#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23712#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23711#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23710#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23709#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23708#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23707#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23706#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 23705#L378-2 [2021-11-07 08:35:53,141 INFO L793 eck$LassoCheckResult]: Loop: 23705#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 23704#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 23705#L378-2 [2021-11-07 08:35:53,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:53,141 INFO L85 PathProgramCache]: Analyzing trace with hash 884753600, now seen corresponding path program 59 times [2021-11-07 08:35:53,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:53,141 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188559076] [2021-11-07 08:35:53,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:53,141 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:53,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:53,208 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:53,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:53,288 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:53,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:53,289 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 63 times [2021-11-07 08:35:53,289 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:53,289 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629675249] [2021-11-07 08:35:53,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:53,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:53,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:53,313 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:35:53,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:35:53,314 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:35:53,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:35:53,315 INFO L85 PathProgramCache]: Analyzing trace with hash -155313661, now seen corresponding path program 59 times [2021-11-07 08:35:53,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:35:53,315 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535278974] [2021-11-07 08:35:53,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:35:53,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:35:53,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:35:54,823 INFO L134 CoverageAnalysis]: Checked inductivity of 1071 backedges. 0 proven. 1071 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:35:54,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:35:54,824 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535278974] [2021-11-07 08:35:54,824 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535278974] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:35:54,824 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1017704363] [2021-11-07 08:35:54,824 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:35:54,824 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:35:54,825 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:35:54,826 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:35:54,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2021-11-07 08:35:58,071 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2021-11-07 08:35:58,071 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:35:58,079 INFO L263 TraceCheckSpWp]: Trace formula consists of 491 conjuncts, 89 conjunts are in the unsatisfiable core [2021-11-07 08:35:58,082 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:35:58,539 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:36:00,223 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:36:00,226 INFO L134 CoverageAnalysis]: Checked inductivity of 1071 backedges. 0 proven. 1071 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:00,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1017704363] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:00,227 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:00,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 69 [2021-11-07 08:36:00,227 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092114524] [2021-11-07 08:36:00,269 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:00,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2021-11-07 08:36:00,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=4646, Unknown=0, NotChecked=0, Total=4830 [2021-11-07 08:36:00,270 INFO L87 Difference]: Start difference. First operand 112 states and 135 transitions. cyclomatic complexity: 25 Second operand has 70 states, 69 states have (on average 2.2753623188405796) internal successors, (157), 70 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:03,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:03,291 INFO L93 Difference]: Finished difference Result 160 states and 186 transitions. [2021-11-07 08:36:03,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-11-07 08:36:03,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 160 states and 186 transitions. [2021-11-07 08:36:03,293 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:36:03,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 160 states to 160 states and 186 transitions. [2021-11-07 08:36:03,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94 [2021-11-07 08:36:03,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94 [2021-11-07 08:36:03,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 160 states and 186 transitions. [2021-11-07 08:36:03,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:03,295 INFO L681 BuchiCegarLoop]: Abstraction has 160 states and 186 transitions. [2021-11-07 08:36:03,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states and 186 transitions. [2021-11-07 08:36:03,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 118. [2021-11-07 08:36:03,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.2118644067796611) internal successors, (143), 117 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:03,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 143 transitions. [2021-11-07 08:36:03,298 INFO L704 BuchiCegarLoop]: Abstraction has 118 states and 143 transitions. [2021-11-07 08:36:03,298 INFO L587 BuchiCegarLoop]: Abstraction has 118 states and 143 transitions. [2021-11-07 08:36:03,298 INFO L425 BuchiCegarLoop]: ======== Iteration 65============ [2021-11-07 08:36:03,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 143 transitions. [2021-11-07 08:36:03,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:03,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:03,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:03,300 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:03,300 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:03,300 INFO L791 eck$LassoCheckResult]: Stem: 24312#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 24313#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 24320#L367 assume !(main_~length~0 < 1); 24314#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 24315#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 24316#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24321#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24386#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24322#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24323#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24324#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24326#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24385#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24384#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24383#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24382#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24381#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24380#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24379#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24378#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24377#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24376#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24375#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24374#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24373#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24372#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24371#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24370#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24369#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24368#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24367#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24366#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24365#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24364#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24363#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24362#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24361#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24360#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24359#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24358#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24357#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24356#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24355#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24354#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24353#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24352#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24351#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24350#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24349#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24348#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24347#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24346#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24345#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24344#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24343#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24342#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24341#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24340#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24339#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24338#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24337#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24336#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24335#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24334#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24333#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24332#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 24331#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 24330#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 24327#L370-3 assume !(main_~i~0 < main_~length~0); 24328#L370-4 main_~j~0 := 0; 24427#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24319#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24318#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24325#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24426#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24425#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24424#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24423#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24422#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24421#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24420#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24419#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24418#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24417#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24416#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24415#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24414#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24413#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24412#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24411#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24410#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24409#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24408#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24407#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24406#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24405#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24404#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24403#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24402#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24401#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24400#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24399#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24398#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24397#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24396#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24395#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24394#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24393#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24392#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24391#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24390#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24389#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 24388#L378-2 [2021-11-07 08:36:03,301 INFO L793 eck$LassoCheckResult]: Loop: 24388#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 24387#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 24388#L378-2 [2021-11-07 08:36:03,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:03,301 INFO L85 PathProgramCache]: Analyzing trace with hash -155313659, now seen corresponding path program 60 times [2021-11-07 08:36:03,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:03,301 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238022533] [2021-11-07 08:36:03,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:03,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:03,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:03,478 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:03,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:03,568 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:03,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:03,569 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 64 times [2021-11-07 08:36:03,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:03,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189157690] [2021-11-07 08:36:03,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:03,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:03,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:03,595 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:03,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:03,597 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:03,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:03,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1067430408, now seen corresponding path program 60 times [2021-11-07 08:36:03,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:03,599 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725872043] [2021-11-07 08:36:03,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:03,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:03,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:04,530 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 421 proven. 692 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:04,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:04,530 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725872043] [2021-11-07 08:36:04,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725872043] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:04,531 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [156055161] [2021-11-07 08:36:04,531 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:36:04,531 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:04,531 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:04,537 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:04,558 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2021-11-07 08:36:10,118 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2021-11-07 08:36:10,118 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:36:10,131 INFO L263 TraceCheckSpWp]: Trace formula consists of 502 conjuncts, 46 conjunts are in the unsatisfiable core [2021-11-07 08:36:10,133 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:36:11,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 462 proven. 651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:11,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [156055161] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:11,446 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:11,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 70 [2021-11-07 08:36:11,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832016462] [2021-11-07 08:36:11,482 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:11,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2021-11-07 08:36:11,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1086, Invalid=3744, Unknown=0, NotChecked=0, Total=4830 [2021-11-07 08:36:11,483 INFO L87 Difference]: Start difference. First operand 118 states and 143 transitions. cyclomatic complexity: 27 Second operand has 70 states, 70 states have (on average 2.3142857142857145) internal successors, (162), 70 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:12,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:12,154 INFO L93 Difference]: Finished difference Result 161 states and 186 transitions. [2021-11-07 08:36:12,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-11-07 08:36:12,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161 states and 186 transitions. [2021-11-07 08:36:12,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:12,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161 states to 117 states and 142 transitions. [2021-11-07 08:36:12,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-11-07 08:36:12,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-11-07 08:36:12,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 142 transitions. [2021-11-07 08:36:12,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:12,156 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 142 transitions. [2021-11-07 08:36:12,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 142 transitions. [2021-11-07 08:36:12,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 115. [2021-11-07 08:36:12,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.208695652173913) internal successors, (139), 114 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:12,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 139 transitions. [2021-11-07 08:36:12,158 INFO L704 BuchiCegarLoop]: Abstraction has 115 states and 139 transitions. [2021-11-07 08:36:12,159 INFO L587 BuchiCegarLoop]: Abstraction has 115 states and 139 transitions. [2021-11-07 08:36:12,159 INFO L425 BuchiCegarLoop]: ======== Iteration 66============ [2021-11-07 08:36:12,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 139 transitions. [2021-11-07 08:36:12,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:12,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:12,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:12,160 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 22, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:12,160 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:12,161 INFO L791 eck$LassoCheckResult]: Stem: 25051#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 25052#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 25060#L367 assume !(main_~length~0 < 1); 25053#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 25054#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 25055#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25061#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25127#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25062#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25063#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25064#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25066#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25126#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25125#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25124#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25123#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25122#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25121#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25120#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25119#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25118#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25117#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25116#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25115#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25114#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25113#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25112#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25111#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25110#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25109#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25108#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25107#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25106#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25105#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25104#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25103#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25102#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25101#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25100#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25099#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25098#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25097#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25096#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25095#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25094#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25093#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25092#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25091#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25090#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25089#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25088#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25087#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25086#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25085#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25084#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25083#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25082#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25081#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25080#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25079#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25078#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25077#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25076#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25075#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25074#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25073#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25072#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25071#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25070#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25068#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25069#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25067#L370-3 assume !(main_~i~0 < main_~length~0); 25056#L370-4 main_~j~0 := 0; 25057#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25058#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25059#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25065#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25165#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25164#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25163#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25162#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25161#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25160#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25159#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25158#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25157#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25156#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25155#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25154#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25153#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25152#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25151#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25150#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25149#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25148#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25147#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25146#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25145#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25144#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25143#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25142#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25141#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25140#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25139#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25138#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25137#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25136#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25135#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25134#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25133#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25132#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25131#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25130#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25129#L378-2 [2021-11-07 08:36:12,161 INFO L793 eck$LassoCheckResult]: Loop: 25129#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25128#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 25129#L378-2 [2021-11-07 08:36:12,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:12,161 INFO L85 PathProgramCache]: Analyzing trace with hash 824340410, now seen corresponding path program 61 times [2021-11-07 08:36:12,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:12,162 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948410862] [2021-11-07 08:36:12,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:12,162 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:12,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:12,227 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:12,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:12,288 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:12,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:12,289 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 65 times [2021-11-07 08:36:12,289 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:12,289 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989358830] [2021-11-07 08:36:12,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:12,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:12,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:12,313 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:12,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:12,314 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:12,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:12,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1917152893, now seen corresponding path program 61 times [2021-11-07 08:36:12,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:12,315 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667419276] [2021-11-07 08:36:12,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:12,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:12,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:13,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1135 backedges. 0 proven. 1135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:13,653 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:13,653 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667419276] [2021-11-07 08:36:13,653 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667419276] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:13,653 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1774001713] [2021-11-07 08:36:13,653 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 08:36:13,653 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:13,653 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:13,655 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:13,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2021-11-07 08:36:15,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:15,985 INFO L263 TraceCheckSpWp]: Trace formula consists of 502 conjuncts, 95 conjunts are in the unsatisfiable core [2021-11-07 08:36:15,986 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:36:17,333 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:36:17,543 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:36:17,543 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:36:19,330 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:36:19,333 INFO L134 CoverageAnalysis]: Checked inductivity of 1135 backedges. 0 proven. 1135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:19,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1774001713] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:19,334 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:19,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 49] total 95 [2021-11-07 08:36:19,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137380630] [2021-11-07 08:36:19,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:19,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2021-11-07 08:36:19,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=335, Invalid=8785, Unknown=0, NotChecked=0, Total=9120 [2021-11-07 08:36:19,378 INFO L87 Difference]: Start difference. First operand 115 states and 139 transitions. cyclomatic complexity: 26 Second operand has 96 states, 95 states have (on average 2.3789473684210525) internal successors, (226), 96 states have internal predecessors, (226), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:23,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:23,552 INFO L93 Difference]: Finished difference Result 117 states and 141 transitions. [2021-11-07 08:36:23,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-07 08:36:23,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 141 transitions. [2021-11-07 08:36:23,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:23,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 141 transitions. [2021-11-07 08:36:23,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2021-11-07 08:36:23,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2021-11-07 08:36:23,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 141 transitions. [2021-11-07 08:36:23,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:23,555 INFO L681 BuchiCegarLoop]: Abstraction has 117 states and 141 transitions. [2021-11-07 08:36:23,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 141 transitions. [2021-11-07 08:36:23,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2021-11-07 08:36:23,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.205128205128205) internal successors, (141), 116 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:23,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 141 transitions. [2021-11-07 08:36:23,558 INFO L704 BuchiCegarLoop]: Abstraction has 117 states and 141 transitions. [2021-11-07 08:36:23,558 INFO L587 BuchiCegarLoop]: Abstraction has 117 states and 141 transitions. [2021-11-07 08:36:23,559 INFO L425 BuchiCegarLoop]: ======== Iteration 67============ [2021-11-07 08:36:23,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 141 transitions. [2021-11-07 08:36:23,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:23,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:23,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:23,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:23,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:23,560 INFO L791 eck$LassoCheckResult]: Stem: 25772#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 25773#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 25781#L367 assume !(main_~length~0 < 1); 25774#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 25775#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 25776#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25782#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25848#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25783#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25784#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25785#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25787#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25847#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25846#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25845#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25844#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25843#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25842#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25841#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25840#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25839#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25838#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25837#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25836#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25835#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25834#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25833#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25832#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25831#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25830#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25829#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25828#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25827#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25826#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25825#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25824#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25823#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25822#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25821#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25820#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25819#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25818#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25817#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25816#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25815#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25814#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25813#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25812#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25811#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25810#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25809#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25808#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25807#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25806#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25805#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25804#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25803#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25802#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25801#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25800#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25799#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25798#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25797#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25796#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25795#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25794#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25793#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25792#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25791#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 25789#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 25790#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 25788#L370-3 assume !(main_~i~0 < main_~length~0); 25777#L370-4 main_~j~0 := 0; 25778#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25779#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25780#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25786#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25888#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25887#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25886#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25885#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25884#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25883#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25882#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25881#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25880#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25879#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25878#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25877#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25876#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25875#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25874#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25873#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25872#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25871#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25870#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25869#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25868#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25867#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25866#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25865#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25864#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25863#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25862#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25861#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25860#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25859#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25858#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25857#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25856#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25855#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25854#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25853#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25852#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25851#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 25850#L378-2 [2021-11-07 08:36:23,560 INFO L793 eck$LassoCheckResult]: Loop: 25850#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 25849#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 25850#L378-2 [2021-11-07 08:36:23,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:23,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1917152895, now seen corresponding path program 62 times [2021-11-07 08:36:23,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:23,561 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872507607] [2021-11-07 08:36:23,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:23,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:23,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:23,638 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:23,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:23,767 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:23,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:23,767 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 66 times [2021-11-07 08:36:23,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:23,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745867375] [2021-11-07 08:36:23,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:23,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:23,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:23,792 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:23,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:23,794 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:23,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:23,794 INFO L85 PathProgramCache]: Analyzing trace with hash -157036542, now seen corresponding path program 62 times [2021-11-07 08:36:23,794 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:23,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977230518] [2021-11-07 08:36:23,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:23,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:23,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:25,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1177 backedges. 0 proven. 1177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:25,338 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:25,338 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977230518] [2021-11-07 08:36:25,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977230518] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:25,338 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2142638083] [2021-11-07 08:36:25,339 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 08:36:25,339 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:25,339 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:25,340 INFO L229 MonitoredProcess]: Starting monitored process 77 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:25,342 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (77)] Waiting until timeout for monitored process [2021-11-07 08:36:28,126 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 08:36:28,126 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:36:28,130 INFO L263 TraceCheckSpWp]: Trace formula consists of 513 conjuncts, 93 conjunts are in the unsatisfiable core [2021-11-07 08:36:28,132 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:36:28,632 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:36:30,374 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:36:30,377 INFO L134 CoverageAnalysis]: Checked inductivity of 1177 backedges. 0 proven. 1177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:30,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2142638083] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:30,377 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:30,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 48] total 71 [2021-11-07 08:36:30,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249525297] [2021-11-07 08:36:30,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:30,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2021-11-07 08:36:30,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=4924, Unknown=0, NotChecked=0, Total=5112 [2021-11-07 08:36:30,422 INFO L87 Difference]: Start difference. First operand 117 states and 141 transitions. cyclomatic complexity: 26 Second operand has 72 states, 71 states have (on average 2.2816901408450705) internal successors, (162), 72 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:33,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:33,809 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2021-11-07 08:36:33,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-11-07 08:36:33,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2021-11-07 08:36:33,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:36:33,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 167 states and 194 transitions. [2021-11-07 08:36:33,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98 [2021-11-07 08:36:33,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98 [2021-11-07 08:36:33,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167 states and 194 transitions. [2021-11-07 08:36:33,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:33,812 INFO L681 BuchiCegarLoop]: Abstraction has 167 states and 194 transitions. [2021-11-07 08:36:33,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states and 194 transitions. [2021-11-07 08:36:33,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 123. [2021-11-07 08:36:33,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.2113821138211383) internal successors, (149), 122 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:33,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 149 transitions. [2021-11-07 08:36:33,816 INFO L704 BuchiCegarLoop]: Abstraction has 123 states and 149 transitions. [2021-11-07 08:36:33,816 INFO L587 BuchiCegarLoop]: Abstraction has 123 states and 149 transitions. [2021-11-07 08:36:33,816 INFO L425 BuchiCegarLoop]: ======== Iteration 68============ [2021-11-07 08:36:33,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 149 transitions. [2021-11-07 08:36:33,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:33,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:33,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:33,818 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:33,818 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:33,819 INFO L791 eck$LassoCheckResult]: Stem: 26483#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 26484#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 26491#L367 assume !(main_~length~0 < 1); 26485#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 26486#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 26487#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26492#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26560#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26493#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26494#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26495#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26497#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26559#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26558#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26557#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26556#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26555#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26554#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26553#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26552#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26551#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26550#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26549#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26548#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26547#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26546#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26545#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26544#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26543#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26542#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26541#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26540#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26539#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26538#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26537#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26536#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26535#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26534#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26533#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26532#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26531#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26530#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26529#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26528#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26527#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26526#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26525#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26524#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26523#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26522#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26521#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26520#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26519#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26518#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26517#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26516#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26515#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26514#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26513#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26512#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26511#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26510#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26509#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26508#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26507#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26506#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26505#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26504#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26503#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 26502#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 26501#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 26498#L370-3 assume !(main_~i~0 < main_~length~0); 26499#L370-4 main_~j~0 := 0; 26603#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26490#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26489#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26496#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26602#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26601#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26600#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26599#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26598#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26597#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26596#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26595#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26594#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26593#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26592#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26591#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26590#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26589#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26588#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26587#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26586#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26585#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26584#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26583#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26582#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26581#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26580#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26579#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26578#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26577#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26576#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26575#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26574#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26573#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26572#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26571#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26570#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26569#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26568#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26567#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26566#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26565#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26564#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26563#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 26562#L378-2 [2021-11-07 08:36:33,819 INFO L793 eck$LassoCheckResult]: Loop: 26562#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 26561#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 26562#L378-2 [2021-11-07 08:36:33,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:33,820 INFO L85 PathProgramCache]: Analyzing trace with hash -157036540, now seen corresponding path program 63 times [2021-11-07 08:36:33,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:33,820 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664247364] [2021-11-07 08:36:33,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:33,821 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:33,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:33,904 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:34,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:34,037 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:34,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:34,038 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 67 times [2021-11-07 08:36:34,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:34,038 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566263725] [2021-11-07 08:36:34,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:34,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:34,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:34,064 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:34,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:34,067 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:34,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:34,067 INFO L85 PathProgramCache]: Analyzing trace with hash -588258233, now seen corresponding path program 63 times [2021-11-07 08:36:34,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:34,067 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321891023] [2021-11-07 08:36:34,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:34,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:34,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:34,962 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 463 proven. 758 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:34,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:34,963 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321891023] [2021-11-07 08:36:34,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321891023] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:34,963 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1176045122] [2021-11-07 08:36:34,963 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 08:36:34,963 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:34,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:34,965 INFO L229 MonitoredProcess]: Starting monitored process 78 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:34,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (78)] Waiting until timeout for monitored process [2021-11-07 08:36:38,928 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2021-11-07 08:36:38,928 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:36:38,937 INFO L263 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 48 conjunts are in the unsatisfiable core [2021-11-07 08:36:38,939 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:36:40,440 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 506 proven. 715 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:40,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1176045122] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:40,440 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:40,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 73 [2021-11-07 08:36:40,440 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891463796] [2021-11-07 08:36:40,479 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:40,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2021-11-07 08:36:40,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1181, Invalid=4075, Unknown=0, NotChecked=0, Total=5256 [2021-11-07 08:36:40,481 INFO L87 Difference]: Start difference. First operand 123 states and 149 transitions. cyclomatic complexity: 28 Second operand has 73 states, 73 states have (on average 2.315068493150685) internal successors, (169), 73 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:41,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:41,382 INFO L93 Difference]: Finished difference Result 168 states and 194 transitions. [2021-11-07 08:36:41,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-07 08:36:41,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168 states and 194 transitions. [2021-11-07 08:36:41,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:41,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168 states to 122 states and 148 transitions. [2021-11-07 08:36:41,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2021-11-07 08:36:41,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2021-11-07 08:36:41,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 148 transitions. [2021-11-07 08:36:41,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:41,384 INFO L681 BuchiCegarLoop]: Abstraction has 122 states and 148 transitions. [2021-11-07 08:36:41,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 148 transitions. [2021-11-07 08:36:41,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 120. [2021-11-07 08:36:41,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.2083333333333333) internal successors, (145), 119 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:41,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 145 transitions. [2021-11-07 08:36:41,386 INFO L704 BuchiCegarLoop]: Abstraction has 120 states and 145 transitions. [2021-11-07 08:36:41,386 INFO L587 BuchiCegarLoop]: Abstraction has 120 states and 145 transitions. [2021-11-07 08:36:41,386 INFO L425 BuchiCegarLoop]: ======== Iteration 69============ [2021-11-07 08:36:41,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 145 transitions. [2021-11-07 08:36:41,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:41,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:41,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:41,388 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 23, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:41,388 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:41,388 INFO L791 eck$LassoCheckResult]: Stem: 27254#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 27255#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 27263#L367 assume !(main_~length~0 < 1); 27256#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 27257#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 27258#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27264#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27333#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27265#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27266#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27268#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27269#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27332#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27331#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27330#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27329#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27328#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27327#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27326#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27325#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27324#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27323#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27322#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27321#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27320#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27319#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27318#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27317#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27316#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27315#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27314#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27313#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27312#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27311#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27310#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27309#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27308#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27307#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27306#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27305#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27304#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27303#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27302#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27301#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27300#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27299#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27298#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27297#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27296#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27295#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27294#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27293#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27292#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27291#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27290#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27289#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27288#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27287#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27286#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27285#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27284#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27283#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27282#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27281#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27280#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27279#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27278#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27277#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27276#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27275#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27274#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27273#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 27271#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 27272#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 27270#L370-3 assume !(main_~i~0 < main_~length~0); 27261#L370-4 main_~j~0 := 0; 27262#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27259#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27260#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27267#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27373#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27372#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27371#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27370#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27369#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27368#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27367#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27366#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27365#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27364#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27363#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27362#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27361#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27360#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27359#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27358#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27357#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27356#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27355#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27354#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27353#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27352#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27351#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27350#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27349#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27348#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27347#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27346#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27345#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27344#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27343#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27342#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27341#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27340#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27339#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27338#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27337#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27336#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 27335#L378-2 [2021-11-07 08:36:41,388 INFO L793 eck$LassoCheckResult]: Loop: 27335#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 27334#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 27335#L378-2 [2021-11-07 08:36:41,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:41,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1681584187, now seen corresponding path program 64 times [2021-11-07 08:36:41,389 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:41,389 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085514129] [2021-11-07 08:36:41,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:41,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:41,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:41,464 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:41,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:41,533 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:41,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:41,534 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 68 times [2021-11-07 08:36:41,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:41,534 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537157885] [2021-11-07 08:36:41,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:41,534 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:41,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:41,641 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:41,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:41,644 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:41,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:41,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1094699064, now seen corresponding path program 64 times [2021-11-07 08:36:41,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:41,645 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084255969] [2021-11-07 08:36:41,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:41,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:41,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:43,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1244 backedges. 0 proven. 1244 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:43,083 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:43,083 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084255969] [2021-11-07 08:36:43,083 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084255969] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:43,083 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [589024223] [2021-11-07 08:36:43,083 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:36:43,083 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:43,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:43,084 INFO L229 MonitoredProcess]: Starting monitored process 79 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:43,085 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Waiting until timeout for monitored process [2021-11-07 08:36:45,843 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:36:45,843 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:36:45,848 INFO L263 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 99 conjunts are in the unsatisfiable core [2021-11-07 08:36:45,851 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:36:47,916 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2021-11-07 08:36:48,204 INFO L354 Elim1Store]: treesize reduction 31, result has 22.5 percent of original size [2021-11-07 08:36:48,204 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 27 [2021-11-07 08:36:50,724 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-11-07 08:36:50,728 INFO L134 CoverageAnalysis]: Checked inductivity of 1244 backedges. 0 proven. 1244 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:50,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [589024223] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:50,729 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:36:50,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 51] total 99 [2021-11-07 08:36:50,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336238201] [2021-11-07 08:36:50,778 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:36:50,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2021-11-07 08:36:50,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=349, Invalid=9551, Unknown=0, NotChecked=0, Total=9900 [2021-11-07 08:36:50,780 INFO L87 Difference]: Start difference. First operand 120 states and 145 transitions. cyclomatic complexity: 27 Second operand has 100 states, 99 states have (on average 2.3838383838383836) internal successors, (236), 100 states have internal predecessors, (236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:56,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:36:56,568 INFO L93 Difference]: Finished difference Result 122 states and 147 transitions. [2021-11-07 08:36:56,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2021-11-07 08:36:56,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 147 transitions. [2021-11-07 08:36:56,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:56,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 122 states and 147 transitions. [2021-11-07 08:36:56,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2021-11-07 08:36:56,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2021-11-07 08:36:56,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 147 transitions. [2021-11-07 08:36:56,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:36:56,570 INFO L681 BuchiCegarLoop]: Abstraction has 122 states and 147 transitions. [2021-11-07 08:36:56,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 147 transitions. [2021-11-07 08:36:56,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 122. [2021-11-07 08:36:56,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.2049180327868851) internal successors, (147), 121 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:36:56,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 147 transitions. [2021-11-07 08:36:56,572 INFO L704 BuchiCegarLoop]: Abstraction has 122 states and 147 transitions. [2021-11-07 08:36:56,572 INFO L587 BuchiCegarLoop]: Abstraction has 122 states and 147 transitions. [2021-11-07 08:36:56,572 INFO L425 BuchiCegarLoop]: ======== Iteration 70============ [2021-11-07 08:36:56,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 147 transitions. [2021-11-07 08:36:56,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:36:56,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:36:56,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:36:56,575 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:36:56,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:36:56,575 INFO L791 eck$LassoCheckResult]: Stem: 28006#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 28007#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 28015#L367 assume !(main_~length~0 < 1); 28008#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 28009#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 28010#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28016#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28085#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28017#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28018#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28019#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28021#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28084#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28083#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28082#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28081#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28080#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28079#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28078#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28077#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28076#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28075#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28074#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28073#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28072#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28071#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28070#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28069#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28068#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28067#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28066#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28065#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28064#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28063#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28062#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28061#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28060#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28059#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28058#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28057#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28056#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28055#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28054#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28053#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28052#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28051#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28050#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28049#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28048#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28047#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28046#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28045#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28044#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28043#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28042#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28041#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28040#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28039#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28038#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28037#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28036#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28035#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28034#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28033#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28032#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28031#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28030#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28029#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28028#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28027#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28026#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28025#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28023#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28024#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28022#L370-3 assume !(main_~i~0 < main_~length~0); 28011#L370-4 main_~j~0 := 0; 28012#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28013#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28014#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28020#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28127#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28126#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28125#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28124#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28123#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28122#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28121#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28120#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28119#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28118#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28117#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28116#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28115#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28114#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28113#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28112#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28111#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28110#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28109#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28108#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28107#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28106#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28105#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28104#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28103#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28102#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28101#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28100#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28099#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28098#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28097#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28096#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28095#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28094#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28093#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28092#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28091#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28090#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28089#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28088#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28087#L378-2 [2021-11-07 08:36:56,576 INFO L793 eck$LassoCheckResult]: Loop: 28087#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28086#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 28087#L378-2 [2021-11-07 08:36:56,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:56,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1094699062, now seen corresponding path program 65 times [2021-11-07 08:36:56,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:56,577 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235721080] [2021-11-07 08:36:56,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:56,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:56,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:56,709 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:56,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:56,813 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:56,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:56,814 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 69 times [2021-11-07 08:36:56,814 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:56,814 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252185322] [2021-11-07 08:36:56,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:56,815 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:56,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:56,843 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:36:56,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:36:56,845 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:36:56,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:36:56,846 INFO L85 PathProgramCache]: Analyzing trace with hash 261190285, now seen corresponding path program 65 times [2021-11-07 08:36:56,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:36:56,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175821184] [2021-11-07 08:36:56,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:36:56,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:36:57,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:36:58,480 INFO L134 CoverageAnalysis]: Checked inductivity of 1288 backedges. 0 proven. 1288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:36:58,480 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:36:58,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175821184] [2021-11-07 08:36:58,480 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175821184] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:36:58,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1168907659] [2021-11-07 08:36:58,480 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:36:58,480 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:36:58,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:36:58,482 INFO L229 MonitoredProcess]: Starting monitored process 80 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:36:58,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (80)] Waiting until timeout for monitored process [2021-11-07 08:37:02,699 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2021-11-07 08:37:02,699 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:37:02,708 INFO L263 TraceCheckSpWp]: Trace formula consists of 535 conjuncts, 97 conjunts are in the unsatisfiable core [2021-11-07 08:37:02,709 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:37:03,091 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2021-11-07 08:37:04,887 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 7 [2021-11-07 08:37:04,890 INFO L134 CoverageAnalysis]: Checked inductivity of 1288 backedges. 0 proven. 1288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:37:04,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1168907659] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:37:04,891 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:37:04,892 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 75 [2021-11-07 08:37:04,892 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215567664] [2021-11-07 08:37:04,944 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:37:04,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2021-11-07 08:37:04,945 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=200, Invalid=5500, Unknown=0, NotChecked=0, Total=5700 [2021-11-07 08:37:04,945 INFO L87 Difference]: Start difference. First operand 122 states and 147 transitions. cyclomatic complexity: 27 Second operand has 76 states, 75 states have (on average 2.28) internal successors, (171), 76 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:37:08,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:37:08,573 INFO L93 Difference]: Finished difference Result 174 states and 202 transitions. [2021-11-07 08:37:08,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2021-11-07 08:37:08,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 202 transitions. [2021-11-07 08:37:08,575 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 08:37:08,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 174 states and 202 transitions. [2021-11-07 08:37:08,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102 [2021-11-07 08:37:08,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102 [2021-11-07 08:37:08,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 202 transitions. [2021-11-07 08:37:08,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:37:08,578 INFO L681 BuchiCegarLoop]: Abstraction has 174 states and 202 transitions. [2021-11-07 08:37:08,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 202 transitions. [2021-11-07 08:37:08,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 128. [2021-11-07 08:37:08,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.2109375) internal successors, (155), 127 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:37:08,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 155 transitions. [2021-11-07 08:37:08,581 INFO L704 BuchiCegarLoop]: Abstraction has 128 states and 155 transitions. [2021-11-07 08:37:08,581 INFO L587 BuchiCegarLoop]: Abstraction has 128 states and 155 transitions. [2021-11-07 08:37:08,581 INFO L425 BuchiCegarLoop]: ======== Iteration 71============ [2021-11-07 08:37:08,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 155 transitions. [2021-11-07 08:37:08,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:37:08,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:37:08,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:37:08,583 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:37:08,583 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:37:08,584 INFO L791 eck$LassoCheckResult]: Stem: 28748#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 28749#L-1 havoc main_#res;havoc main_#t~nondet205, main_#t~malloc206.base, main_#t~malloc206.offset, main_#t~nondet208, main_#t~mem209, main_#t~post207, main_#t~mem210, main_#t~post211, main_#t~post212, main_~i~0, main_~j~0, main_~length~0, main_~arr~0.base, main_~arr~0.offset;havoc main_~i~0;havoc main_~j~0;main_~length~0 := main_#t~nondet205;havoc main_#t~nondet205; 28756#L367 assume !(main_~length~0 < 1); 28750#L367-2 call main_#t~malloc206.base, main_#t~malloc206.offset := #Ultimate.allocOnStack(4 * main_~length~0);main_~arr~0.base, main_~arr~0.offset := main_#t~malloc206.base, main_#t~malloc206.offset; 28751#L369 assume !(main_~arr~0.base == 0 && main_~arr~0.offset == 0);main_~i~0 := 0; 28752#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28757#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28828#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28758#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28759#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28761#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28762#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28827#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28826#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28825#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28824#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28823#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28822#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28821#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28820#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28819#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28818#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28817#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28816#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28815#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28814#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28813#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28812#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28811#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28810#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28809#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28808#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28807#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28806#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28805#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28804#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28803#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28802#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28801#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28800#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28799#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28798#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28797#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28796#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28795#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28794#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28793#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28792#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28791#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28790#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28789#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28788#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28787#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28786#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28785#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28784#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28783#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28782#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28781#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28780#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28779#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28778#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28777#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28776#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28775#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28774#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28773#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28772#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28771#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28770#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28769#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28768#L370-3 assume !!(main_~i~0 < main_~length~0);call write~int(main_#t~nondet208, main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet208;call main_#t~mem209 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~i~0, 4); 28767#L372 assume !(main_#t~mem209 < 0);havoc main_#t~mem209; 28766#L370-2 main_#t~post207 := main_~i~0;main_~i~0 := 1 + main_#t~post207;havoc main_#t~post207; 28763#L370-3 assume !(main_~i~0 < main_~length~0); 28764#L370-4 main_~j~0 := 0; 28873#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28753#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28754#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28760#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28872#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28871#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28870#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28869#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28868#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28867#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28866#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28865#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28864#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28863#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28862#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28861#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28860#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28859#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28858#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28857#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28856#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28855#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28854#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28853#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28852#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28851#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28850#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28849#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28848#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28847#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28846#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28845#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28844#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28843#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28842#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28841#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28840#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28839#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28838#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28837#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28836#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28835#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28834#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28833#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28832#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28831#L378 assume !(main_#t~mem210 < 0);havoc main_#t~mem210;main_#t~post212 := main_~j~0;main_~j~0 := 1 + main_#t~post212;havoc main_#t~post212; 28830#L378-2 [2021-11-07 08:37:08,584 INFO L793 eck$LassoCheckResult]: Loop: 28830#L378-2 assume !!(0 <= main_~j~0 && main_~j~0 < main_~length~0);call main_#t~mem210 := read~int(main_~arr~0.base, main_~arr~0.offset + 4 * main_~j~0, 4); 28829#L378 assume main_#t~mem210 < 0;havoc main_#t~mem210;main_#t~post211 := main_~j~0;main_~j~0 := main_#t~post211 - 1;havoc main_#t~post211; 28830#L378-2 [2021-11-07 08:37:08,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:37:08,585 INFO L85 PathProgramCache]: Analyzing trace with hash 261190287, now seen corresponding path program 66 times [2021-11-07 08:37:08,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:37:08,585 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211451320] [2021-11-07 08:37:08,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:37:08,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:37:08,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:37:08,732 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:37:08,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:37:08,902 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:37:08,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:37:08,903 INFO L85 PathProgramCache]: Analyzing trace with hash 2308, now seen corresponding path program 70 times [2021-11-07 08:37:08,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:37:08,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848269893] [2021-11-07 08:37:08,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:37:08,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:37:08,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:37:08,971 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:37:08,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:37:08,973 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:37:08,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:37:08,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1895763986, now seen corresponding path program 66 times [2021-11-07 08:37:08,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:37:08,989 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783834669] [2021-11-07 08:37:08,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:37:08,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:37:09,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:37:10,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 507 proven. 827 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:37:10,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:37:10,374 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783834669] [2021-11-07 08:37:10,374 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783834669] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:37:10,374 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1769765992] [2021-11-07 08:37:10,374 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 08:37:10,374 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:37:10,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:37:10,378 INFO L229 MonitoredProcess]: Starting monitored process 81 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:37:10,397 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a0619854-0bc1-43dc-a7ad-1ce01040d8f4/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (81)] Waiting until timeout for monitored process