./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_2-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_2-2.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 866342b97e5be917007cb97e07a0644c7c9d2aa9b428c32cf026d727d672a191 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 07:48:19,294 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 07:48:19,297 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 07:48:19,341 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 07:48:19,342 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 07:48:19,343 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 07:48:19,346 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 07:48:19,349 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 07:48:19,352 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 07:48:19,354 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 07:48:19,355 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 07:48:19,357 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 07:48:19,358 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 07:48:19,360 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 07:48:19,362 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 07:48:19,364 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 07:48:19,366 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 07:48:19,367 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 07:48:19,370 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 07:48:19,374 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 07:48:19,377 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 07:48:19,379 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 07:48:19,381 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 07:48:19,383 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 07:48:19,388 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 07:48:19,389 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 07:48:19,389 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 07:48:19,391 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 07:48:19,392 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 07:48:19,393 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 07:48:19,394 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 07:48:19,395 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 07:48:19,396 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 07:48:19,398 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 07:48:19,399 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 07:48:19,400 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 07:48:19,401 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 07:48:19,402 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 07:48:19,402 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 07:48:19,404 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 07:48:19,405 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 07:48:19,407 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-07 07:48:19,442 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 07:48:19,443 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 07:48:19,443 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 07:48:19,444 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 07:48:19,445 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 07:48:19,446 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 07:48:19,446 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 07:48:19,447 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 07:48:19,447 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 07:48:19,448 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 07:48:19,448 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 07:48:19,449 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 07:48:19,449 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 07:48:19,450 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 07:48:19,450 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-07 07:48:19,451 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 07:48:19,451 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 07:48:19,452 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-07 07:48:19,452 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 07:48:19,452 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 07:48:19,453 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 07:48:19,453 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 07:48:19,454 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-07 07:48:19,454 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 07:48:19,454 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 07:48:19,455 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 07:48:19,455 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 07:48:19,455 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 07:48:19,456 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 07:48:19,457 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 07:48:19,458 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 07:48:19,458 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 07:48:19,459 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 07:48:19,460 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 866342b97e5be917007cb97e07a0644c7c9d2aa9b428c32cf026d727d672a191 [2021-11-07 07:48:19,784 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 07:48:19,815 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 07:48:19,819 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 07:48:19,820 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 07:48:19,822 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 07:48:19,823 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/loop-acceleration/array_2-2.i [2021-11-07 07:48:19,925 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/data/6bee11219/d44bb130a38649dea937d65088231d5f/FLAGc2f24de46 [2021-11-07 07:48:20,517 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 07:48:20,518 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/sv-benchmarks/c/loop-acceleration/array_2-2.i [2021-11-07 07:48:20,525 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/data/6bee11219/d44bb130a38649dea937d65088231d5f/FLAGc2f24de46 [2021-11-07 07:48:20,898 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/data/6bee11219/d44bb130a38649dea937d65088231d5f [2021-11-07 07:48:20,901 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 07:48:20,903 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 07:48:20,913 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 07:48:20,913 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 07:48:20,918 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 07:48:20,919 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:48:20" (1/1) ... [2021-11-07 07:48:20,920 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4346ac31 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:20, skipping insertion in model container [2021-11-07 07:48:20,920 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:48:20" (1/1) ... [2021-11-07 07:48:20,929 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 07:48:20,947 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 07:48:21,166 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/sv-benchmarks/c/loop-acceleration/array_2-2.i[849,862] [2021-11-07 07:48:21,184 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:48:21,195 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 07:48:21,220 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/sv-benchmarks/c/loop-acceleration/array_2-2.i[849,862] [2021-11-07 07:48:21,227 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:48:21,245 INFO L208 MainTranslator]: Completed translation [2021-11-07 07:48:21,246 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21 WrapperNode [2021-11-07 07:48:21,246 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 07:48:21,248 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 07:48:21,248 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 07:48:21,248 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 07:48:21,259 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,273 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,317 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 07:48:21,319 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 07:48:21,319 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 07:48:21,319 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 07:48:21,329 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,329 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,346 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,348 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,354 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,362 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,371 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,381 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 07:48:21,382 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 07:48:21,382 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 07:48:21,383 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 07:48:21,387 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (1/1) ... [2021-11-07 07:48:21,396 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:21,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:21,430 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:21,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 07:48:21,490 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-07 07:48:21,490 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 07:48:21,490 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-07 07:48:21,491 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 07:48:21,491 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 07:48:21,491 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-07 07:48:21,491 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-07 07:48:21,759 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 07:48:21,759 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2021-11-07 07:48:21,761 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:48:21 BoogieIcfgContainer [2021-11-07 07:48:21,761 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 07:48:21,763 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 07:48:21,763 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 07:48:21,767 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 07:48:21,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:48:21,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 07:48:20" (1/3) ... [2021-11-07 07:48:21,770 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@69ebbd55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:48:21, skipping insertion in model container [2021-11-07 07:48:21,770 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:48:21,770 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:48:21" (2/3) ... [2021-11-07 07:48:21,771 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@69ebbd55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:48:21, skipping insertion in model container [2021-11-07 07:48:21,771 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:48:21,771 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:48:21" (3/3) ... [2021-11-07 07:48:21,773 INFO L389 chiAutomizerObserver]: Analyzing ICFG array_2-2.i [2021-11-07 07:48:21,826 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 07:48:21,826 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 07:48:21,826 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 07:48:21,827 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 07:48:21,827 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 07:48:21,827 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 07:48:21,827 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 07:48:21,827 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 07:48:21,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.3846153846153846) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:21,899 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 07:48:21,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:21,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:21,907 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-07 07:48:21,907 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:21,907 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 07:48:21,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.3846153846153846) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:21,915 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2021-11-07 07:48:21,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:21,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:21,926 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-07 07:48:21,927 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:21,935 INFO L791 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 9#L-1true havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 7#L25-3true [2021-11-07 07:48:21,935 INFO L793 eck$LassoCheckResult]: Loop: 7#L25-3true assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 11#L25-2true main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7#L25-3true [2021-11-07 07:48:21,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:21,943 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-11-07 07:48:21,967 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:21,979 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605421816] [2021-11-07 07:48:21,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:21,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:22,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,100 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:22,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,150 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:22,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:22,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2021-11-07 07:48:22,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:22,156 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573937300] [2021-11-07 07:48:22,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:22,156 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:22,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,172 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:22,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,189 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:22,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:22,191 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2021-11-07 07:48:22,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:22,192 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578587225] [2021-11-07 07:48:22,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:22,193 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:22,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,246 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:22,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:22,320 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:23,336 INFO L210 LassoAnalysis]: Preferences: [2021-11-07 07:48:23,337 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-07 07:48:23,337 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-07 07:48:23,338 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-07 07:48:23,338 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-07 07:48:23,338 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:23,338 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-07 07:48:23,339 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-07 07:48:23,339 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_2-2.i_Iteration1_Lasso [2021-11-07 07:48:23,339 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-07 07:48:23,339 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-07 07:48:23,374 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,385 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,392 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,399 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,774 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,778 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,783 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,786 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:23,791 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-07 07:48:24,166 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-07 07:48:24,171 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-07 07:48:24,173 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,175 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-07 07:48:24,181 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,193 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,194 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,194 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,194 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,194 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,198 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,199 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,213 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,260 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,261 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,261 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,263 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,278 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,291 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,291 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,291 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,291 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,291 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,294 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,295 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,296 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-07 07:48:24,297 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,343 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,344 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,344 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,345 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,354 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,365 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,365 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,365 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,365 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,371 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:24,372 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:24,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-07 07:48:24,396 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,436 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2021-11-07 07:48:24,436 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,438 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-07 07:48:24,440 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,449 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,449 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,449 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,449 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,449 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,450 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,450 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,461 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,488 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,489 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,489 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,490 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,492 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-07 07:48:24,493 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,501 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,502 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,502 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,502 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,502 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,503 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,503 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,528 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,558 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2021-11-07 07:48:24,559 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,559 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,560 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-07 07:48:24,562 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,571 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,571 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,571 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,571 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,578 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:24,578 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:24,592 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,620 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,621 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,621 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,623 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-07 07:48:24,626 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,635 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,635 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,635 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,635 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,639 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:24,639 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:24,661 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,688 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2021-11-07 07:48:24,688 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,688 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,690 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,690 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-11-07 07:48:24,699 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,711 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,711 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,711 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,712 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,712 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,714 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,715 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,733 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,784 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,784 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,786 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,803 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-11-07 07:48:24,804 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,817 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,817 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,817 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,817 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,817 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,818 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,819 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,832 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,878 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,878 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,878 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,879 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,894 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,905 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,905 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-07 07:48:24,905 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,906 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,906 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,907 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-07 07:48:24,907 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-07 07:48:24,908 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-11-07 07:48:24,924 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:24,949 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:24,950 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:24,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:24,951 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:24,952 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-11-07 07:48:24,956 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:24,965 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:24,965 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:24,965 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:24,965 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:24,968 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:24,969 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:24,999 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:25,044 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:25,044 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:25,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:25,046 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:25,054 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2021-11-07 07:48:25,055 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:25,066 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:25,066 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:25,066 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:25,066 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:25,070 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:25,070 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:25,099 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:25,144 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:25,144 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:25,144 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:25,145 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:25,151 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2021-11-07 07:48:25,152 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:25,161 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:25,161 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:25,161 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:25,161 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:25,164 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:25,164 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:25,177 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-07 07:48:25,201 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:25,201 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:25,202 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:25,202 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:25,205 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2021-11-07 07:48:25,206 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-07 07:48:25,214 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-07 07:48:25,215 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-07 07:48:25,215 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-07 07:48:25,215 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-07 07:48:25,233 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-07 07:48:25,233 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-07 07:48:25,248 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-07 07:48:25,315 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2021-11-07 07:48:25,315 INFO L444 ModelExtractionUtils]: 6 out of 19 variables were initially zero. Simplification set additionally 10 variables to zero. [2021-11-07 07:48:25,317 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:48:25,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:25,335 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:48:25,397 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-07 07:48:25,397 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2021-11-07 07:48:25,422 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-07 07:48:25,422 INFO L513 LassoAnalysis]: Proved termination. [2021-11-07 07:48:25,423 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, v_rep(select #length ULTIMATE.start_main_~#A~0.base)_1) = -8*ULTIMATE.start_main_~i~0 + 4095*v_rep(select #length ULTIMATE.start_main_~#A~0.base)_1 Supporting invariants [] [2021-11-07 07:48:25,503 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:25,544 INFO L297 tatePredicateManager]: 12 out of 12 supporting invariants were superfluous and have been removed [2021-11-07 07:48:25,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:25,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:25,605 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-07 07:48:25,606 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:25,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:25,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-07 07:48:25,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:25,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:25,694 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-07 07:48:25,695 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.3846153846153846) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:25,745 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.3846153846153846) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 27 states and 37 transitions. Complement of second has 8 states. [2021-11-07 07:48:25,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-07 07:48:25,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:25,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 18 transitions. [2021-11-07 07:48:25,750 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 18 transitions. Stem has 2 letters. Loop has 2 letters. [2021-11-07 07:48:25,750 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 07:48:25,750 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 18 transitions. Stem has 4 letters. Loop has 2 letters. [2021-11-07 07:48:25,750 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 07:48:25,750 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 18 transitions. Stem has 2 letters. Loop has 4 letters. [2021-11-07 07:48:25,751 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-07 07:48:25,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2021-11-07 07:48:25,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:25,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 8 states and 10 transitions. [2021-11-07 07:48:25,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-11-07 07:48:25,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2021-11-07 07:48:25,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 10 transitions. [2021-11-07 07:48:25,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:25,762 INFO L681 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-11-07 07:48:25,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 10 transitions. [2021-11-07 07:48:25,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2021-11-07 07:48:25,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.25) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:25,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 10 transitions. [2021-11-07 07:48:25,802 INFO L704 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-11-07 07:48:25,802 INFO L587 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2021-11-07 07:48:25,802 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 07:48:25,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 10 transitions. [2021-11-07 07:48:25,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:25,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:25,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:25,803 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-11-07 07:48:25,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:25,804 INFO L791 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 132#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 135#L25-3 assume !(main_~i~0 < 2048); 136#L25-4 main_~i~0 := 0; 133#L29-3 [2021-11-07 07:48:25,804 INFO L793 eck$LassoCheckResult]: Loop: 133#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 134#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 133#L29-3 [2021-11-07 07:48:25,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:25,805 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2021-11-07 07:48:25,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:25,805 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228346897] [2021-11-07 07:48:25,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:25,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:25,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:25,883 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2021-11-07 07:48:25,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:25,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:25,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228346897] [2021-11-07 07:48:25,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228346897] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:48:25,901 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:48:25,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:48:25,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324770747] [2021-11-07 07:48:25,905 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:25,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:25,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 1 times [2021-11-07 07:48:25,912 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:25,912 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929852469] [2021-11-07 07:48:25,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:25,913 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:25,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:25,923 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:25,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:25,932 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:26,032 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:26,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:48:26,035 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:48:26,037 INFO L87 Difference]: Start difference. First operand 8 states and 10 transitions. cyclomatic complexity: 4 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:26,062 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2021-11-07 07:48:26,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:48:26,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2021-11-07 07:48:26,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 12 transitions. [2021-11-07 07:48:26,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-07 07:48:26,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-07 07:48:26,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 12 transitions. [2021-11-07 07:48:26,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:26,073 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-07 07:48:26,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 12 transitions. [2021-11-07 07:48:26,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 8. [2021-11-07 07:48:26,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.125) internal successors, (9), 7 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 9 transitions. [2021-11-07 07:48:26,077 INFO L704 BuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2021-11-07 07:48:26,078 INFO L587 BuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2021-11-07 07:48:26,078 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 07:48:26,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 9 transitions. [2021-11-07 07:48:26,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:26,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:26,080 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-11-07 07:48:26,081 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:26,081 INFO L791 eck$LassoCheckResult]: Stem: 158#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 159#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 160#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 154#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 155#L25-3 assume !(main_~i~0 < 2048); 161#L25-4 main_~i~0 := 0; 156#L29-3 [2021-11-07 07:48:26,081 INFO L793 eck$LassoCheckResult]: Loop: 156#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 157#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 156#L29-3 [2021-11-07 07:48:26,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:26,082 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2021-11-07 07:48:26,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:26,083 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287907869] [2021-11-07 07:48:26,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:26,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:26,169 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:26,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:26,170 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287907869] [2021-11-07 07:48:26,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287907869] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:26,171 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [422710932] [2021-11-07 07:48:26,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,175 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:26,175 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:26,176 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:26,188 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-07 07:48:26,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:26,248 INFO L263 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-07 07:48:26,249 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:26,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:26,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [422710932] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:26,284 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:26,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2021-11-07 07:48:26,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245566038] [2021-11-07 07:48:26,285 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:26,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:26,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 2 times [2021-11-07 07:48:26,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:26,286 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219896542] [2021-11-07 07:48:26,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:26,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:26,307 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:26,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:26,315 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:26,418 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:26,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:48:26,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:48:26,419 INFO L87 Difference]: Start difference. First operand 8 states and 9 transitions. cyclomatic complexity: 3 Second operand has 5 states, 5 states have (on average 1.8) internal successors, (9), 5 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:26,456 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2021-11-07 07:48:26,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:48:26,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2021-11-07 07:48:26,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2021-11-07 07:48:26,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-11-07 07:48:26,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2021-11-07 07:48:26,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2021-11-07 07:48:26,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:26,460 INFO L681 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-07 07:48:26,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2021-11-07 07:48:26,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 10. [2021-11-07 07:48:26,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.1) internal successors, (11), 9 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 11 transitions. [2021-11-07 07:48:26,462 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-11-07 07:48:26,462 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-11-07 07:48:26,462 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 07:48:26,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 11 transitions. [2021-11-07 07:48:26,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:26,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:26,464 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1] [2021-11-07 07:48:26,464 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:26,464 INFO L791 eck$LassoCheckResult]: Stem: 204#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 205#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 207#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 200#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 201#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 208#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 209#L25-3 assume !(main_~i~0 < 2048); 206#L25-4 main_~i~0 := 0; 202#L29-3 [2021-11-07 07:48:26,465 INFO L793 eck$LassoCheckResult]: Loop: 202#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 203#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 202#L29-3 [2021-11-07 07:48:26,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:26,465 INFO L85 PathProgramCache]: Analyzing trace with hash 265236367, now seen corresponding path program 2 times [2021-11-07 07:48:26,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:26,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318698879] [2021-11-07 07:48:26,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:26,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:26,517 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:26,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:26,518 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [318698879] [2021-11-07 07:48:26,518 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [318698879] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:26,519 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [113758363] [2021-11-07 07:48:26,519 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:48:26,519 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:26,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:26,521 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:26,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-07 07:48:26,586 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:48:26,586 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:26,587 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-07 07:48:26,588 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:26,624 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:26,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [113758363] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:26,625 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:26,625 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2021-11-07 07:48:26,625 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251848346] [2021-11-07 07:48:26,626 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:26,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:26,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 3 times [2021-11-07 07:48:26,627 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:26,627 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414659610] [2021-11-07 07:48:26,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:26,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:26,634 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:26,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:26,641 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:26,745 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:26,746 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-11-07 07:48:26,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-11-07 07:48:26,747 INFO L87 Difference]: Start difference. First operand 10 states and 11 transitions. cyclomatic complexity: 3 Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:26,789 INFO L93 Difference]: Finished difference Result 19 states and 20 transitions. [2021-11-07 07:48:26,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-07 07:48:26,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 20 transitions. [2021-11-07 07:48:26,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 20 transitions. [2021-11-07 07:48:26,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-11-07 07:48:26,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-11-07 07:48:26,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 20 transitions. [2021-11-07 07:48:26,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:26,792 INFO L681 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-07 07:48:26,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 20 transitions. [2021-11-07 07:48:26,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 12. [2021-11-07 07:48:26,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.0833333333333333) internal successors, (13), 11 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:26,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 13 transitions. [2021-11-07 07:48:26,795 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 13 transitions. [2021-11-07 07:48:26,795 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 13 transitions. [2021-11-07 07:48:26,795 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 07:48:26,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 13 transitions. [2021-11-07 07:48:26,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:26,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:26,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:26,797 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 1, 1, 1, 1] [2021-11-07 07:48:26,797 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:26,798 INFO L791 eck$LassoCheckResult]: Stem: 263#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 264#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 265#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 267#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 259#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 260#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 270#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 269#L25-3 assume !(main_~i~0 < 2048); 268#L25-4 main_~i~0 := 0; 261#L29-3 [2021-11-07 07:48:26,798 INFO L793 eck$LassoCheckResult]: Loop: 261#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 262#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 261#L29-3 [2021-11-07 07:48:26,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:26,799 INFO L85 PathProgramCache]: Analyzing trace with hash 1489134225, now seen corresponding path program 3 times [2021-11-07 07:48:26,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:26,799 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501733035] [2021-11-07 07:48:26,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:26,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:26,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:26,858 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:26,858 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:26,859 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501733035] [2021-11-07 07:48:26,859 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501733035] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:26,859 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1820283297] [2021-11-07 07:48:26,859 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:48:26,860 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:26,860 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:26,888 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:26,915 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-07 07:48:26,964 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-07 07:48:26,964 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:26,965 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 5 conjunts are in the unsatisfiable core [2021-11-07 07:48:26,966 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:27,031 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:27,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1820283297] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:27,032 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:27,032 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2021-11-07 07:48:27,033 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188039920] [2021-11-07 07:48:27,033 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:27,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:27,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 4 times [2021-11-07 07:48:27,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:27,034 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890833969] [2021-11-07 07:48:27,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:27,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:27,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:27,046 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:27,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:27,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:27,164 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:27,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-11-07 07:48:27,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-11-07 07:48:27,165 INFO L87 Difference]: Start difference. First operand 12 states and 13 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:27,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:27,225 INFO L93 Difference]: Finished difference Result 23 states and 24 transitions. [2021-11-07 07:48:27,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:48:27,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 24 transitions. [2021-11-07 07:48:27,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:27,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 24 transitions. [2021-11-07 07:48:27,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-11-07 07:48:27,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-11-07 07:48:27,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 24 transitions. [2021-11-07 07:48:27,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:27,228 INFO L681 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-07 07:48:27,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 24 transitions. [2021-11-07 07:48:27,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 14. [2021-11-07 07:48:27,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 13 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:27,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2021-11-07 07:48:27,231 INFO L704 BuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2021-11-07 07:48:27,231 INFO L587 BuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2021-11-07 07:48:27,231 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 07:48:27,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 15 transitions. [2021-11-07 07:48:27,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:27,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:27,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:27,235 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2021-11-07 07:48:27,235 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:27,235 INFO L791 eck$LassoCheckResult]: Stem: 335#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 336#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 337#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 338#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 339#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 331#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 332#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 344#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 343#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 342#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 341#L25-3 assume !(main_~i~0 < 2048); 340#L25-4 main_~i~0 := 0; 333#L29-3 [2021-11-07 07:48:27,235 INFO L793 eck$LassoCheckResult]: Loop: 333#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 334#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 333#L29-3 [2021-11-07 07:48:27,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:27,236 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 4 times [2021-11-07 07:48:27,236 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:27,237 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153640243] [2021-11-07 07:48:27,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:27,237 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:27,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:27,326 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:27,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:27,326 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153640243] [2021-11-07 07:48:27,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153640243] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:27,327 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1102952840] [2021-11-07 07:48:27,327 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 07:48:27,327 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:27,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:27,329 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:27,360 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-07 07:48:27,410 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 07:48:27,410 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:27,411 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-07 07:48:27,412 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:27,474 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:27,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1102952840] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:27,475 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:27,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2021-11-07 07:48:27,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456453595] [2021-11-07 07:48:27,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:27,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:27,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 5 times [2021-11-07 07:48:27,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:27,483 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364876175] [2021-11-07 07:48:27,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:27,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:27,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:27,498 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:27,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:27,503 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:27,607 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:27,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-11-07 07:48:27,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-11-07 07:48:27,609 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. cyclomatic complexity: 3 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:27,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:27,674 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2021-11-07 07:48:27,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-07 07:48:27,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2021-11-07 07:48:27,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:27,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2021-11-07 07:48:27,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-07 07:48:27,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-07 07:48:27,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2021-11-07 07:48:27,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:27,678 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-07 07:48:27,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2021-11-07 07:48:27,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 16. [2021-11-07 07:48:27,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.0625) internal successors, (17), 15 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:27,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2021-11-07 07:48:27,680 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2021-11-07 07:48:27,680 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2021-11-07 07:48:27,680 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 07:48:27,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 17 transitions. [2021-11-07 07:48:27,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:27,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:27,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:27,682 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 1, 1, 1, 1] [2021-11-07 07:48:27,682 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:27,682 INFO L791 eck$LassoCheckResult]: Stem: 418#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 419#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 422#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 416#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 417#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 423#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 431#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 430#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 429#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 428#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 427#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 426#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 425#L25-3 assume !(main_~i~0 < 2048); 424#L25-4 main_~i~0 := 0; 420#L29-3 [2021-11-07 07:48:27,682 INFO L793 eck$LassoCheckResult]: Loop: 420#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 421#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 420#L29-3 [2021-11-07 07:48:27,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:27,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1745699051, now seen corresponding path program 5 times [2021-11-07 07:48:27,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:27,683 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755015400] [2021-11-07 07:48:27,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:27,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:27,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:27,803 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:27,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:27,804 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755015400] [2021-11-07 07:48:27,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755015400] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:27,804 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1330101621] [2021-11-07 07:48:27,804 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 07:48:27,804 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:27,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:27,811 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:27,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-07 07:48:27,949 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-11-07 07:48:27,949 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:27,951 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 7 conjunts are in the unsatisfiable core [2021-11-07 07:48:27,953 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:28,026 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:28,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1330101621] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:28,026 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:28,026 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2021-11-07 07:48:28,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416517677] [2021-11-07 07:48:28,027 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:28,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:28,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 6 times [2021-11-07 07:48:28,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:28,028 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281402227] [2021-11-07 07:48:28,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:28,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:28,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:28,035 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:28,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:28,042 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:28,144 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:28,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-11-07 07:48:28,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-11-07 07:48:28,145 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. cyclomatic complexity: 3 Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 9 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:28,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:28,217 INFO L93 Difference]: Finished difference Result 31 states and 32 transitions. [2021-11-07 07:48:28,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-11-07 07:48:28,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 32 transitions. [2021-11-07 07:48:28,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:28,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 32 transitions. [2021-11-07 07:48:28,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-07 07:48:28,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-07 07:48:28,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 32 transitions. [2021-11-07 07:48:28,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:28,221 INFO L681 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-07 07:48:28,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 32 transitions. [2021-11-07 07:48:28,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 18. [2021-11-07 07:48:28,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.0555555555555556) internal successors, (19), 17 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:28,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2021-11-07 07:48:28,224 INFO L704 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-07 07:48:28,225 INFO L587 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-07 07:48:28,225 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 07:48:28,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 19 transitions. [2021-11-07 07:48:28,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:28,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:28,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:28,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 1, 1, 1, 1] [2021-11-07 07:48:28,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:28,227 INFO L791 eck$LassoCheckResult]: Stem: 518#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 519#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 520#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 521#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 522#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 514#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 515#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 531#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 530#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 529#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 528#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 527#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 526#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 525#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 524#L25-3 assume !(main_~i~0 < 2048); 523#L25-4 main_~i~0 := 0; 516#L29-3 [2021-11-07 07:48:28,227 INFO L793 eck$LassoCheckResult]: Loop: 516#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 517#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 516#L29-3 [2021-11-07 07:48:28,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:28,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1715480727, now seen corresponding path program 6 times [2021-11-07 07:48:28,227 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:28,228 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145632018] [2021-11-07 07:48:28,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:28,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:28,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:28,354 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:28,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:28,355 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145632018] [2021-11-07 07:48:28,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145632018] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:28,355 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1356527283] [2021-11-07 07:48:28,355 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 07:48:28,356 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:28,356 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:28,358 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:28,382 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-07 07:48:28,483 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-11-07 07:48:28,483 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:28,485 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-07 07:48:28,486 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:28,553 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:28,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1356527283] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:28,554 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:28,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2021-11-07 07:48:28,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745815475] [2021-11-07 07:48:28,555 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:28,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:28,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 7 times [2021-11-07 07:48:28,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:28,556 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692357885] [2021-11-07 07:48:28,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:28,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:28,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:28,563 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:28,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:28,575 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:28,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:28,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-07 07:48:28,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-11-07 07:48:28,672 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. cyclomatic complexity: 3 Second operand has 10 states, 10 states have (on average 1.9) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:28,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:28,746 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2021-11-07 07:48:28,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-07 07:48:28,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 36 transitions. [2021-11-07 07:48:28,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:28,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 35 states and 36 transitions. [2021-11-07 07:48:28,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-11-07 07:48:28,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-11-07 07:48:28,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 36 transitions. [2021-11-07 07:48:28,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:28,750 INFO L681 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-07 07:48:28,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 36 transitions. [2021-11-07 07:48:28,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 20. [2021-11-07 07:48:28,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.05) internal successors, (21), 19 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:28,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2021-11-07 07:48:28,753 INFO L704 BuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2021-11-07 07:48:28,753 INFO L587 BuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2021-11-07 07:48:28,753 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 07:48:28,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 21 transitions. [2021-11-07 07:48:28,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:28,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:28,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:28,754 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 1, 1, 1, 1] [2021-11-07 07:48:28,754 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:28,754 INFO L791 eck$LassoCheckResult]: Stem: 627#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 628#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 631#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 625#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 626#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 632#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 644#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 643#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 642#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 641#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 640#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 639#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 638#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 637#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 636#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 635#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 634#L25-3 assume !(main_~i~0 < 2048); 633#L25-4 main_~i~0 := 0; 629#L29-3 [2021-11-07 07:48:28,755 INFO L793 eck$LassoCheckResult]: Loop: 629#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 630#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 629#L29-3 [2021-11-07 07:48:28,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:28,755 INFO L85 PathProgramCache]: Analyzing trace with hash -690407015, now seen corresponding path program 7 times [2021-11-07 07:48:28,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:28,755 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824146399] [2021-11-07 07:48:28,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:28,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:28,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:28,856 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:28,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:28,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824146399] [2021-11-07 07:48:28,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824146399] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:28,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [935196567] [2021-11-07 07:48:28,857 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 07:48:28,857 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:28,857 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:28,862 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:28,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-07 07:48:28,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:28,958 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 9 conjunts are in the unsatisfiable core [2021-11-07 07:48:28,960 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:29,046 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:29,047 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [935196567] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:29,047 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:29,047 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2021-11-07 07:48:29,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106586749] [2021-11-07 07:48:29,050 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:29,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:29,051 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 8 times [2021-11-07 07:48:29,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:29,051 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110055625] [2021-11-07 07:48:29,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:29,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:29,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:29,067 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:29,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:29,072 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:29,174 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:29,175 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-11-07 07:48:29,175 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-11-07 07:48:29,175 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. cyclomatic complexity: 3 Second operand has 11 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 11 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:29,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:29,271 INFO L93 Difference]: Finished difference Result 39 states and 40 transitions. [2021-11-07 07:48:29,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-07 07:48:29,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 40 transitions. [2021-11-07 07:48:29,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:29,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 40 transitions. [2021-11-07 07:48:29,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-11-07 07:48:29,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-11-07 07:48:29,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 40 transitions. [2021-11-07 07:48:29,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:29,275 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-07 07:48:29,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 40 transitions. [2021-11-07 07:48:29,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 22. [2021-11-07 07:48:29,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.0454545454545454) internal successors, (23), 21 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:29,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 23 transitions. [2021-11-07 07:48:29,299 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 23 transitions. [2021-11-07 07:48:29,299 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 23 transitions. [2021-11-07 07:48:29,299 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 07:48:29,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 23 transitions. [2021-11-07 07:48:29,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:29,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:29,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:29,306 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 1, 1, 1, 1] [2021-11-07 07:48:29,306 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:29,307 INFO L791 eck$LassoCheckResult]: Stem: 751#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 752#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 755#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 749#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 750#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 756#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 770#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 769#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 768#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 767#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 766#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 765#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 764#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 763#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 762#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 761#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 760#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 759#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 758#L25-3 assume !(main_~i~0 < 2048); 757#L25-4 main_~i~0 := 0; 753#L29-3 [2021-11-07 07:48:29,307 INFO L793 eck$LassoCheckResult]: Loop: 753#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 754#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 753#L29-3 [2021-11-07 07:48:29,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:29,309 INFO L85 PathProgramCache]: Analyzing trace with hash -2056121829, now seen corresponding path program 8 times [2021-11-07 07:48:29,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:29,309 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624803770] [2021-11-07 07:48:29,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:29,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:29,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:29,442 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:29,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:29,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624803770] [2021-11-07 07:48:29,443 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624803770] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:29,443 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670624526] [2021-11-07 07:48:29,443 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:48:29,443 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:29,444 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:29,450 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:29,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-07 07:48:29,575 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:48:29,576 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:29,577 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-07 07:48:29,579 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:29,668 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:29,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [670624526] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:29,670 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:29,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2021-11-07 07:48:29,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663601724] [2021-11-07 07:48:29,671 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:29,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:29,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 9 times [2021-11-07 07:48:29,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:29,674 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533220820] [2021-11-07 07:48:29,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:29,675 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:29,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:29,681 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:29,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:29,687 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:29,778 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:29,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-07 07:48:29,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-11-07 07:48:29,779 INFO L87 Difference]: Start difference. First operand 22 states and 23 transitions. cyclomatic complexity: 3 Second operand has 12 states, 12 states have (on average 1.9166666666666667) internal successors, (23), 12 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:29,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:29,880 INFO L93 Difference]: Finished difference Result 43 states and 44 transitions. [2021-11-07 07:48:29,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-07 07:48:29,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 44 transitions. [2021-11-07 07:48:29,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:29,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 44 transitions. [2021-11-07 07:48:29,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2021-11-07 07:48:29,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24 [2021-11-07 07:48:29,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 44 transitions. [2021-11-07 07:48:29,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:29,883 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-07 07:48:29,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 44 transitions. [2021-11-07 07:48:29,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 24. [2021-11-07 07:48:29,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.0416666666666667) internal successors, (25), 23 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:29,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 25 transitions. [2021-11-07 07:48:29,886 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 25 transitions. [2021-11-07 07:48:29,887 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 25 transitions. [2021-11-07 07:48:29,887 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 07:48:29,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 25 transitions. [2021-11-07 07:48:29,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:29,887 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:29,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:29,888 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 1, 1, 1, 1] [2021-11-07 07:48:29,888 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:29,889 INFO L791 eck$LassoCheckResult]: Stem: 888#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 889#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 892#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 886#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 887#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 893#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 909#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 908#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 907#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 906#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 905#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 904#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 903#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 902#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 901#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 900#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 899#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 898#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 897#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 895#L25-3 assume !(main_~i~0 < 2048); 894#L25-4 main_~i~0 := 0; 890#L29-3 [2021-11-07 07:48:29,889 INFO L793 eck$LassoCheckResult]: Loop: 890#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 891#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 890#L29-3 [2021-11-07 07:48:29,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:29,889 INFO L85 PathProgramCache]: Analyzing trace with hash -248065507, now seen corresponding path program 9 times [2021-11-07 07:48:29,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:29,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466169601] [2021-11-07 07:48:29,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:29,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:29,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:30,007 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:30,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:30,008 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466169601] [2021-11-07 07:48:30,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466169601] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:30,008 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1265627755] [2021-11-07 07:48:30,008 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:48:30,009 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:30,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:30,011 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:30,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-07 07:48:30,452 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-11-07 07:48:30,453 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:30,455 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 11 conjunts are in the unsatisfiable core [2021-11-07 07:48:30,457 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:30,568 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:30,568 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1265627755] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:30,569 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:30,569 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2021-11-07 07:48:30,569 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468433855] [2021-11-07 07:48:30,570 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:30,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:30,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 10 times [2021-11-07 07:48:30,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:30,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928702778] [2021-11-07 07:48:30,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:30,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:30,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:30,576 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:30,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:30,580 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:30,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:30,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-07 07:48:30,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-11-07 07:48:30,672 INFO L87 Difference]: Start difference. First operand 24 states and 25 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:30,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:30,809 INFO L93 Difference]: Finished difference Result 47 states and 48 transitions. [2021-11-07 07:48:30,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-07 07:48:30,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 48 transitions. [2021-11-07 07:48:30,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:30,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 48 transitions. [2021-11-07 07:48:30,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2021-11-07 07:48:30,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2021-11-07 07:48:30,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 48 transitions. [2021-11-07 07:48:30,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:30,812 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-07 07:48:30,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 48 transitions. [2021-11-07 07:48:30,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 26. [2021-11-07 07:48:30,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.0384615384615385) internal successors, (27), 25 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:30,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2021-11-07 07:48:30,815 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2021-11-07 07:48:30,815 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2021-11-07 07:48:30,815 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 07:48:30,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 27 transitions. [2021-11-07 07:48:30,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:30,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:30,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:30,817 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2021-11-07 07:48:30,817 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:30,817 INFO L791 eck$LassoCheckResult]: Stem: 1040#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1041#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1042#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1043#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1044#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1036#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1037#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1061#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1060#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1059#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1058#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1057#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1056#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1055#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1054#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1053#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1052#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1051#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1050#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1049#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1048#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1047#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1046#L25-3 assume !(main_~i~0 < 2048); 1045#L25-4 main_~i~0 := 0; 1038#L29-3 [2021-11-07 07:48:30,817 INFO L793 eck$LassoCheckResult]: Loop: 1038#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1039#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1038#L29-3 [2021-11-07 07:48:30,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:30,818 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 10 times [2021-11-07 07:48:30,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:30,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002172699] [2021-11-07 07:48:30,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:30,818 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:30,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:30,949 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:30,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:30,949 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002172699] [2021-11-07 07:48:30,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002172699] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:30,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1591288509] [2021-11-07 07:48:30,950 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 07:48:30,950 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:30,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:30,953 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:30,957 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-07 07:48:31,080 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 07:48:31,081 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:31,082 INFO L263 TraceCheckSpWp]: Trace formula consists of 164 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-07 07:48:31,084 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:31,177 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:31,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1591288509] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:31,177 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:31,177 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2021-11-07 07:48:31,178 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497287722] [2021-11-07 07:48:31,178 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:31,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:31,179 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 11 times [2021-11-07 07:48:31,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:31,179 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905325283] [2021-11-07 07:48:31,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:31,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:31,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:31,184 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:31,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:31,188 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:31,271 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:31,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-07 07:48:31,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-11-07 07:48:31,273 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. cyclomatic complexity: 3 Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:31,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:31,389 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2021-11-07 07:48:31,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-07 07:48:31,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2021-11-07 07:48:31,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:31,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2021-11-07 07:48:31,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2021-11-07 07:48:31,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2021-11-07 07:48:31,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2021-11-07 07:48:31,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:31,393 INFO L681 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-07 07:48:31,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2021-11-07 07:48:31,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 28. [2021-11-07 07:48:31,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 27 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:31,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2021-11-07 07:48:31,396 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-07 07:48:31,396 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-07 07:48:31,396 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 07:48:31,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 29 transitions. [2021-11-07 07:48:31,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:31,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:31,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:31,398 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 1, 1, 1, 1] [2021-11-07 07:48:31,398 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:31,398 INFO L791 eck$LassoCheckResult]: Stem: 1203#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1204#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1205#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1207#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1199#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1200#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1225#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1223#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1221#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1219#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1217#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1215#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1213#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1211#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1210#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1209#L25-3 assume !(main_~i~0 < 2048); 1208#L25-4 main_~i~0 := 0; 1201#L29-3 [2021-11-07 07:48:31,398 INFO L793 eck$LassoCheckResult]: Loop: 1201#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1202#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1201#L29-3 [2021-11-07 07:48:31,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:31,399 INFO L85 PathProgramCache]: Analyzing trace with hash -95647583, now seen corresponding path program 11 times [2021-11-07 07:48:31,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:31,399 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254810545] [2021-11-07 07:48:31,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:31,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:31,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:31,546 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:31,547 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:31,547 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254810545] [2021-11-07 07:48:31,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254810545] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:31,547 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [70862308] [2021-11-07 07:48:31,548 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 07:48:31,548 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:31,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:31,552 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:31,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-07 07:48:32,158 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2021-11-07 07:48:32,159 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:32,163 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-07 07:48:32,165 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:32,302 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:32,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [70862308] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:32,302 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:32,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2021-11-07 07:48:32,303 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154138682] [2021-11-07 07:48:32,303 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:32,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:32,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 12 times [2021-11-07 07:48:32,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:32,304 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150270556] [2021-11-07 07:48:32,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:32,305 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:32,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:32,310 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:32,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:32,314 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:32,395 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:32,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-07 07:48:32,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-11-07 07:48:32,397 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. cyclomatic complexity: 3 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 15 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:32,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:32,516 INFO L93 Difference]: Finished difference Result 55 states and 56 transitions. [2021-11-07 07:48:32,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-07 07:48:32,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 56 transitions. [2021-11-07 07:48:32,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:32,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 56 transitions. [2021-11-07 07:48:32,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2021-11-07 07:48:32,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2021-11-07 07:48:32,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 56 transitions. [2021-11-07 07:48:32,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:32,519 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-07 07:48:32,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 56 transitions. [2021-11-07 07:48:32,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 30. [2021-11-07 07:48:32,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.0333333333333334) internal successors, (31), 29 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:32,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 31 transitions. [2021-11-07 07:48:32,523 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 31 transitions. [2021-11-07 07:48:32,523 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 31 transitions. [2021-11-07 07:48:32,523 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 07:48:32,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 31 transitions. [2021-11-07 07:48:32,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:32,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:32,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:32,526 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 1, 1, 1, 1] [2021-11-07 07:48:32,526 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:32,526 INFO L791 eck$LassoCheckResult]: Stem: 1377#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1378#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1381#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1375#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1376#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1382#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1404#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1403#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1402#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1401#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1400#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1399#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1398#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1397#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1396#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1395#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1394#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1393#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1392#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1391#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1390#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1389#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1388#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1387#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1386#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1385#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1384#L25-3 assume !(main_~i~0 < 2048); 1383#L25-4 main_~i~0 := 0; 1379#L29-3 [2021-11-07 07:48:32,526 INFO L793 eck$LassoCheckResult]: Loop: 1379#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1380#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1379#L29-3 [2021-11-07 07:48:32,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:32,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1722958045, now seen corresponding path program 12 times [2021-11-07 07:48:32,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:32,527 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818082359] [2021-11-07 07:48:32,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:32,528 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:32,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:32,731 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:32,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:32,732 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818082359] [2021-11-07 07:48:32,732 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818082359] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:32,732 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [844186831] [2021-11-07 07:48:32,732 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 07:48:32,732 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:32,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:32,734 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:32,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-07 07:48:34,367 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2021-11-07 07:48:34,367 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:34,372 INFO L263 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-07 07:48:34,375 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:34,502 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:34,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [844186831] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:34,503 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:34,503 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2021-11-07 07:48:34,503 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906607273] [2021-11-07 07:48:34,504 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:34,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:34,505 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 13 times [2021-11-07 07:48:34,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:34,505 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30899853] [2021-11-07 07:48:34,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:34,506 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:34,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:34,512 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:34,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:34,519 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:34,610 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:34,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-07 07:48:34,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-11-07 07:48:34,612 INFO L87 Difference]: Start difference. First operand 30 states and 31 transitions. cyclomatic complexity: 3 Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 16 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:34,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:34,738 INFO L93 Difference]: Finished difference Result 59 states and 60 transitions. [2021-11-07 07:48:34,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-07 07:48:34,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 60 transitions. [2021-11-07 07:48:34,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:34,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 59 states and 60 transitions. [2021-11-07 07:48:34,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2021-11-07 07:48:34,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2021-11-07 07:48:34,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59 states and 60 transitions. [2021-11-07 07:48:34,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:34,742 INFO L681 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-07 07:48:34,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states and 60 transitions. [2021-11-07 07:48:34,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 32. [2021-11-07 07:48:34,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.03125) internal successors, (33), 31 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:34,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 33 transitions. [2021-11-07 07:48:34,745 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 33 transitions. [2021-11-07 07:48:34,746 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 33 transitions. [2021-11-07 07:48:34,746 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 07:48:34,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 33 transitions. [2021-11-07 07:48:34,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:34,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:34,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:34,748 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 1, 1, 1, 1] [2021-11-07 07:48:34,748 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:34,748 INFO L791 eck$LassoCheckResult]: Stem: 1568#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1569#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1570#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1571#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1572#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1564#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1565#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1595#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1594#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1593#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1592#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1591#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1590#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1589#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1588#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1587#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1586#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1585#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1584#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1583#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1582#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1581#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1580#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1579#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1578#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1577#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1576#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1575#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1574#L25-3 assume !(main_~i~0 < 2048); 1573#L25-4 main_~i~0 := 0; 1566#L29-3 [2021-11-07 07:48:34,748 INFO L793 eck$LassoCheckResult]: Loop: 1566#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1567#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1566#L29-3 [2021-11-07 07:48:34,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:34,749 INFO L85 PathProgramCache]: Analyzing trace with hash 2094751013, now seen corresponding path program 13 times [2021-11-07 07:48:34,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:34,750 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359711116] [2021-11-07 07:48:34,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:34,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:34,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:34,952 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:34,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:34,953 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359711116] [2021-11-07 07:48:34,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359711116] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:34,953 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2112022034] [2021-11-07 07:48:34,953 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 07:48:34,954 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:34,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:34,969 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:34,971 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-07 07:48:35,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:35,129 INFO L263 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-07 07:48:35,132 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:35,303 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:35,303 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2112022034] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:35,303 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:35,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2021-11-07 07:48:35,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993353009] [2021-11-07 07:48:35,305 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:35,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:35,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 14 times [2021-11-07 07:48:35,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:35,307 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678693907] [2021-11-07 07:48:35,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:35,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:35,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:35,312 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:35,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:35,325 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:35,419 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:35,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-11-07 07:48:35,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-11-07 07:48:35,420 INFO L87 Difference]: Start difference. First operand 32 states and 33 transitions. cyclomatic complexity: 3 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:35,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:35,542 INFO L93 Difference]: Finished difference Result 63 states and 64 transitions. [2021-11-07 07:48:35,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-07 07:48:35,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 64 transitions. [2021-11-07 07:48:35,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:35,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 63 states and 64 transitions. [2021-11-07 07:48:35,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2021-11-07 07:48:35,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34 [2021-11-07 07:48:35,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 64 transitions. [2021-11-07 07:48:35,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:35,546 INFO L681 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-07 07:48:35,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 64 transitions. [2021-11-07 07:48:35,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 34. [2021-11-07 07:48:35,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.0294117647058822) internal successors, (35), 33 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:35,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2021-11-07 07:48:35,549 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 35 transitions. [2021-11-07 07:48:35,550 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 35 transitions. [2021-11-07 07:48:35,550 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 07:48:35,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 35 transitions. [2021-11-07 07:48:35,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:35,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:35,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:35,552 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 1, 1, 1, 1] [2021-11-07 07:48:35,552 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:35,552 INFO L791 eck$LassoCheckResult]: Stem: 1768#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1769#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1772#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1766#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1767#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1773#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1799#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1798#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1797#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1796#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1795#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1794#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1793#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1792#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1791#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1790#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1789#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1788#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1787#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1786#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1785#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1784#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1783#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1782#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1781#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1780#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1779#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1778#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1777#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1776#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1775#L25-3 assume !(main_~i~0 < 2048); 1774#L25-4 main_~i~0 := 0; 1770#L29-3 [2021-11-07 07:48:35,552 INFO L793 eck$LassoCheckResult]: Loop: 1770#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1771#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1770#L29-3 [2021-11-07 07:48:35,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:35,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1283882329, now seen corresponding path program 14 times [2021-11-07 07:48:35,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:35,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571796009] [2021-11-07 07:48:35,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:35,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:35,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:35,749 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:35,749 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:35,749 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571796009] [2021-11-07 07:48:35,749 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571796009] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:35,749 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [695066425] [2021-11-07 07:48:35,750 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:48:35,750 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:35,750 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:35,752 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:35,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-07 07:48:35,977 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:48:35,977 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:35,979 INFO L263 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-07 07:48:35,981 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:36,121 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:36,122 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [695066425] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:36,122 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:36,122 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2021-11-07 07:48:36,122 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049919444] [2021-11-07 07:48:36,123 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:36,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:36,123 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 15 times [2021-11-07 07:48:36,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:36,124 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594130290] [2021-11-07 07:48:36,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:36,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:36,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:36,131 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:36,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:36,134 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:36,226 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:36,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-07 07:48:36,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-11-07 07:48:36,227 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. cyclomatic complexity: 3 Second operand has 18 states, 18 states have (on average 1.9444444444444444) internal successors, (35), 18 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:36,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:36,373 INFO L93 Difference]: Finished difference Result 67 states and 68 transitions. [2021-11-07 07:48:36,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-07 07:48:36,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 68 transitions. [2021-11-07 07:48:36,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:36,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 67 states and 68 transitions. [2021-11-07 07:48:36,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2021-11-07 07:48:36,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36 [2021-11-07 07:48:36,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 68 transitions. [2021-11-07 07:48:36,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:36,377 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-07 07:48:36,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 68 transitions. [2021-11-07 07:48:36,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 36. [2021-11-07 07:48:36,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.0277777777777777) internal successors, (37), 35 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:36,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 37 transitions. [2021-11-07 07:48:36,381 INFO L704 BuchiCegarLoop]: Abstraction has 36 states and 37 transitions. [2021-11-07 07:48:36,381 INFO L587 BuchiCegarLoop]: Abstraction has 36 states and 37 transitions. [2021-11-07 07:48:36,382 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 07:48:36,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 37 transitions. [2021-11-07 07:48:36,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:36,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:36,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:36,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 1, 1, 1, 1] [2021-11-07 07:48:36,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:36,384 INFO L791 eck$LassoCheckResult]: Stem: 1985#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 1986#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 1987#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1988#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1989#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1981#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1982#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2016#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2015#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2013#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2011#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2009#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2007#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2005#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2003#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2001#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2000#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1999#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1998#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1997#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1996#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1995#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1994#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1993#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 1992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1991#L25-3 assume !(main_~i~0 < 2048); 1990#L25-4 main_~i~0 := 0; 1983#L29-3 [2021-11-07 07:48:36,384 INFO L793 eck$LassoCheckResult]: Loop: 1983#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 1984#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 1983#L29-3 [2021-11-07 07:48:36,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:36,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1155248215, now seen corresponding path program 15 times [2021-11-07 07:48:36,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:36,386 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411060496] [2021-11-07 07:48:36,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:36,386 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:36,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:36,611 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:36,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:36,611 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411060496] [2021-11-07 07:48:36,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411060496] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:36,611 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1654415369] [2021-11-07 07:48:36,612 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:48:36,612 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:36,612 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:36,618 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:36,631 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-07 07:48:42,480 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2021-11-07 07:48:42,481 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:42,492 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-07 07:48:42,493 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:42,615 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:42,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1654415369] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:42,615 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:42,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2021-11-07 07:48:42,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408688467] [2021-11-07 07:48:42,616 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:42,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:42,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 16 times [2021-11-07 07:48:42,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:42,617 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293542958] [2021-11-07 07:48:42,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:42,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:42,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:42,623 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:42,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:42,628 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:42,736 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:42,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-07 07:48:42,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-11-07 07:48:42,737 INFO L87 Difference]: Start difference. First operand 36 states and 37 transitions. cyclomatic complexity: 3 Second operand has 19 states, 19 states have (on average 1.9473684210526316) internal successors, (37), 19 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:42,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:42,876 INFO L93 Difference]: Finished difference Result 71 states and 72 transitions. [2021-11-07 07:48:42,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-07 07:48:42,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 72 transitions. [2021-11-07 07:48:42,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:42,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 71 states and 72 transitions. [2021-11-07 07:48:42,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38 [2021-11-07 07:48:42,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38 [2021-11-07 07:48:42,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 72 transitions. [2021-11-07 07:48:42,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:42,878 INFO L681 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-07 07:48:42,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 72 transitions. [2021-11-07 07:48:42,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 38. [2021-11-07 07:48:42,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.0263157894736843) internal successors, (39), 37 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:42,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2021-11-07 07:48:42,881 INFO L704 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-07 07:48:42,881 INFO L587 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-07 07:48:42,881 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 07:48:42,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 39 transitions. [2021-11-07 07:48:42,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:42,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:42,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:42,883 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 1, 1, 1, 1] [2021-11-07 07:48:42,883 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:42,883 INFO L791 eck$LassoCheckResult]: Stem: 2213#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 2214#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 2215#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2217#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2209#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2210#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2245#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2243#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2241#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2239#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2237#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2235#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2233#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2231#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2230#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2229#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2228#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2227#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2225#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2223#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2221#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2219#L25-3 assume !(main_~i~0 < 2048); 2218#L25-4 main_~i~0 := 0; 2211#L29-3 [2021-11-07 07:48:42,884 INFO L793 eck$LassoCheckResult]: Loop: 2211#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 2212#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 2211#L29-3 [2021-11-07 07:48:42,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:42,884 INFO L85 PathProgramCache]: Analyzing trace with hash -2091916245, now seen corresponding path program 16 times [2021-11-07 07:48:42,884 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:42,885 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031818586] [2021-11-07 07:48:42,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:42,885 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:42,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:43,126 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:43,126 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:43,126 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031818586] [2021-11-07 07:48:43,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031818586] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:43,127 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1004650345] [2021-11-07 07:48:43,127 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 07:48:43,127 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:43,127 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:43,133 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:43,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-07 07:48:43,358 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 07:48:43,358 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:43,360 INFO L263 TraceCheckSpWp]: Trace formula consists of 236 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-07 07:48:43,362 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:43,528 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:43,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1004650345] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:43,528 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:43,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2021-11-07 07:48:43,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862254726] [2021-11-07 07:48:43,530 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:43,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:43,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 17 times [2021-11-07 07:48:43,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:43,531 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203866353] [2021-11-07 07:48:43,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:43,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:43,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:43,538 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:43,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:43,543 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:43,632 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:43,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-07 07:48:43,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-11-07 07:48:43,633 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. cyclomatic complexity: 3 Second operand has 20 states, 20 states have (on average 1.95) internal successors, (39), 20 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:43,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:43,780 INFO L93 Difference]: Finished difference Result 75 states and 76 transitions. [2021-11-07 07:48:43,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-07 07:48:43,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 76 transitions. [2021-11-07 07:48:43,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:43,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 76 transitions. [2021-11-07 07:48:43,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2021-11-07 07:48:43,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2021-11-07 07:48:43,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 76 transitions. [2021-11-07 07:48:43,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:43,784 INFO L681 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-07 07:48:43,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 76 transitions. [2021-11-07 07:48:43,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 40. [2021-11-07 07:48:43,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.025) internal successors, (41), 39 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:43,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 41 transitions. [2021-11-07 07:48:43,787 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 41 transitions. [2021-11-07 07:48:43,787 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 41 transitions. [2021-11-07 07:48:43,787 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 07:48:43,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 41 transitions. [2021-11-07 07:48:43,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:43,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:43,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:43,789 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 1, 1, 1, 1] [2021-11-07 07:48:43,789 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:43,790 INFO L791 eck$LassoCheckResult]: Stem: 2454#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 2455#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 2456#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2457#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2458#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2450#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2451#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2489#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2488#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2487#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2486#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2485#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2484#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2483#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2482#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2481#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2480#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2479#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2478#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2477#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2476#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2475#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2474#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2473#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2472#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2471#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2470#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2469#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2468#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2467#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2466#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2465#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2464#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2463#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2462#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2461#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2460#L25-3 assume !(main_~i~0 < 2048); 2459#L25-4 main_~i~0 := 0; 2452#L29-3 [2021-11-07 07:48:43,790 INFO L793 eck$LassoCheckResult]: Loop: 2452#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 2453#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 2452#L29-3 [2021-11-07 07:48:43,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:43,791 INFO L85 PathProgramCache]: Analyzing trace with hash -286760915, now seen corresponding path program 17 times [2021-11-07 07:48:43,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:43,791 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050058645] [2021-11-07 07:48:43,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:43,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:43,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:44,059 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:44,059 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:44,059 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050058645] [2021-11-07 07:48:44,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050058645] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:44,059 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1984976818] [2021-11-07 07:48:44,060 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 07:48:44,060 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:44,060 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:44,061 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:44,062 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-07 07:48:46,656 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2021-11-07 07:48:46,656 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:46,664 INFO L263 TraceCheckSpWp]: Trace formula consists of 248 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-07 07:48:46,667 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:46,823 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:46,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1984976818] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:46,824 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:46,824 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2021-11-07 07:48:46,824 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134370301] [2021-11-07 07:48:46,826 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:46,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:46,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 18 times [2021-11-07 07:48:46,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:46,827 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140554842] [2021-11-07 07:48:46,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:46,827 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:46,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:46,833 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:46,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:46,838 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:46,915 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:46,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-07 07:48:46,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-11-07 07:48:46,916 INFO L87 Difference]: Start difference. First operand 40 states and 41 transitions. cyclomatic complexity: 3 Second operand has 21 states, 21 states have (on average 1.9523809523809523) internal successors, (41), 21 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:47,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:47,077 INFO L93 Difference]: Finished difference Result 79 states and 80 transitions. [2021-11-07 07:48:47,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-07 07:48:47,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 80 transitions. [2021-11-07 07:48:47,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:47,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 79 states and 80 transitions. [2021-11-07 07:48:47,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2021-11-07 07:48:47,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2021-11-07 07:48:47,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 80 transitions. [2021-11-07 07:48:47,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:47,082 INFO L681 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-07 07:48:47,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 80 transitions. [2021-11-07 07:48:47,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 42. [2021-11-07 07:48:47,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.0238095238095237) internal successors, (43), 41 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:47,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 43 transitions. [2021-11-07 07:48:47,084 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 43 transitions. [2021-11-07 07:48:47,085 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 43 transitions. [2021-11-07 07:48:47,085 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 07:48:47,085 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 43 transitions. [2021-11-07 07:48:47,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:47,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:47,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:47,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 1, 1, 1, 1] [2021-11-07 07:48:47,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:47,087 INFO L791 eck$LassoCheckResult]: Stem: 2708#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 2709#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 2710#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2711#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2712#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2704#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2705#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2745#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2744#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2743#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2742#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2741#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2740#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2739#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2738#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2737#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2736#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2735#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2734#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2733#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2732#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2731#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2730#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2729#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2728#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2727#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2726#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2725#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2724#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2723#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2722#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2721#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2720#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2719#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2718#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2717#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2716#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2715#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2714#L25-3 assume !(main_~i~0 < 2048); 2713#L25-4 main_~i~0 := 0; 2706#L29-3 [2021-11-07 07:48:47,088 INFO L793 eck$LassoCheckResult]: Loop: 2706#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 2707#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 2706#L29-3 [2021-11-07 07:48:47,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:47,088 INFO L85 PathProgramCache]: Analyzing trace with hash -699276369, now seen corresponding path program 18 times [2021-11-07 07:48:47,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:47,089 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007785794] [2021-11-07 07:48:47,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:47,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:47,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:47,392 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:47,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:47,393 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007785794] [2021-11-07 07:48:47,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007785794] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:47,393 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1638683476] [2021-11-07 07:48:47,393 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 07:48:47,393 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:47,393 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:47,396 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:47,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-07 07:48:58,198 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2021-11-07 07:48:58,199 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:48:58,222 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-07 07:48:58,224 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:58,430 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:58,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1638683476] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:58,431 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:58,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 22 [2021-11-07 07:48:58,431 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205247337] [2021-11-07 07:48:58,431 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:58,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:58,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 19 times [2021-11-07 07:48:58,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:58,432 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399056319] [2021-11-07 07:48:58,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:58,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:58,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:58,438 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:58,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:58,445 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:58,543 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:58,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-07 07:48:58,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-11-07 07:48:58,544 INFO L87 Difference]: Start difference. First operand 42 states and 43 transitions. cyclomatic complexity: 3 Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 22 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:58,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:58,724 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2021-11-07 07:48:58,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-07 07:48:58,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 84 transitions. [2021-11-07 07:48:58,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:58,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 83 states and 84 transitions. [2021-11-07 07:48:58,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2021-11-07 07:48:58,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2021-11-07 07:48:58,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 84 transitions. [2021-11-07 07:48:58,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:58,728 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-07 07:48:58,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 84 transitions. [2021-11-07 07:48:58,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 44. [2021-11-07 07:48:58,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.0227272727272727) internal successors, (45), 43 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:58,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 45 transitions. [2021-11-07 07:48:58,731 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 45 transitions. [2021-11-07 07:48:58,731 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 45 transitions. [2021-11-07 07:48:58,731 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 07:48:58,731 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 45 transitions. [2021-11-07 07:48:58,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:58,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:58,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:58,732 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 1, 1, 1, 1] [2021-11-07 07:48:58,732 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:58,733 INFO L791 eck$LassoCheckResult]: Stem: 2975#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 2976#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 2977#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2978#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2979#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2971#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2972#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3013#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3011#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3009#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3007#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3005#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3003#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3001#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3000#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2999#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2998#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2997#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2996#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2995#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2994#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2993#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2991#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2990#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2989#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2988#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2987#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2986#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2985#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2984#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2983#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 2982#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2981#L25-3 assume !(main_~i~0 < 2048); 2980#L25-4 main_~i~0 := 0; 2973#L29-3 [2021-11-07 07:48:58,733 INFO L793 eck$LassoCheckResult]: Loop: 2973#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 2974#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 2973#L29-3 [2021-11-07 07:48:58,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:58,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1989636431, now seen corresponding path program 19 times [2021-11-07 07:48:58,734 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:58,734 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513672094] [2021-11-07 07:48:58,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:58,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:58,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:59,111 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:59,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:48:59,112 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513672094] [2021-11-07 07:48:59,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513672094] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:59,112 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1266994180] [2021-11-07 07:48:59,112 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 07:48:59,112 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:48:59,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:48:59,116 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:48:59,132 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-07 07:48:59,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:48:59,368 INFO L263 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-07 07:48:59,370 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:48:59,531 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:48:59,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1266994180] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:48:59,531 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:48:59,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 23 [2021-11-07 07:48:59,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898805127] [2021-11-07 07:48:59,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:48:59,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:59,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 20 times [2021-11-07 07:48:59,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:59,536 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417684083] [2021-11-07 07:48:59,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:59,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:59,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:59,542 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:48:59,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:48:59,551 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:48:59,644 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:48:59,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-07 07:48:59,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-11-07 07:48:59,646 INFO L87 Difference]: Start difference. First operand 44 states and 45 transitions. cyclomatic complexity: 3 Second operand has 23 states, 23 states have (on average 1.9565217391304348) internal successors, (45), 23 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:59,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:48:59,819 INFO L93 Difference]: Finished difference Result 87 states and 88 transitions. [2021-11-07 07:48:59,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-07 07:48:59,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 88 transitions. [2021-11-07 07:48:59,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:59,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 88 transitions. [2021-11-07 07:48:59,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2021-11-07 07:48:59,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2021-11-07 07:48:59,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 88 transitions. [2021-11-07 07:48:59,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:48:59,823 INFO L681 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-07 07:48:59,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 88 transitions. [2021-11-07 07:48:59,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 46. [2021-11-07 07:48:59,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.0217391304347827) internal successors, (47), 45 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:48:59,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2021-11-07 07:48:59,826 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 47 transitions. [2021-11-07 07:48:59,826 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 47 transitions. [2021-11-07 07:48:59,826 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-07 07:48:59,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 47 transitions. [2021-11-07 07:48:59,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:48:59,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:48:59,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:48:59,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 1, 1, 1, 1] [2021-11-07 07:48:59,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:48:59,828 INFO L791 eck$LassoCheckResult]: Stem: 3255#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 3256#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 3257#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3258#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3259#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3251#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3252#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3295#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3294#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3293#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3292#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3291#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3290#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3289#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3288#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3287#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3286#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3285#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3284#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3283#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3282#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3281#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3280#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3279#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3278#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3277#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3276#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3275#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3274#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3273#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3272#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3271#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3270#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3269#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3268#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3267#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3265#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3264#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3263#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3262#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3261#L25-3 assume !(main_~i~0 < 2048); 3260#L25-4 main_~i~0 := 0; 3253#L29-3 [2021-11-07 07:48:59,828 INFO L793 eck$LassoCheckResult]: Loop: 3253#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 3254#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 3253#L29-3 [2021-11-07 07:48:59,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:48:59,840 INFO L85 PathProgramCache]: Analyzing trace with hash -780107469, now seen corresponding path program 20 times [2021-11-07 07:48:59,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:48:59,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787572760] [2021-11-07 07:48:59,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:48:59,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:48:59,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:49:00,227 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:00,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:49:00,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787572760] [2021-11-07 07:49:00,228 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787572760] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:00,229 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1743730294] [2021-11-07 07:49:00,229 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:49:00,230 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:49:00,230 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:49:00,232 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:49:00,233 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-07 07:49:00,495 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:49:00,495 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:49:00,498 INFO L263 TraceCheckSpWp]: Trace formula consists of 284 conjuncts, 22 conjunts are in the unsatisfiable core [2021-11-07 07:49:00,500 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:49:00,664 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:00,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1743730294] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:00,664 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:49:00,664 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 24 [2021-11-07 07:49:00,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717200328] [2021-11-07 07:49:00,665 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:49:00,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:00,666 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 21 times [2021-11-07 07:49:00,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:00,666 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014523296] [2021-11-07 07:49:00,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:00,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:00,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:00,672 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:49:00,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:00,675 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:49:00,766 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:49:00,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-07 07:49:00,767 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-11-07 07:49:00,767 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. cyclomatic complexity: 3 Second operand has 24 states, 24 states have (on average 1.9583333333333333) internal successors, (47), 24 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:00,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:49:00,948 INFO L93 Difference]: Finished difference Result 91 states and 92 transitions. [2021-11-07 07:49:00,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-07 07:49:00,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 92 transitions. [2021-11-07 07:49:00,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:00,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 91 states and 92 transitions. [2021-11-07 07:49:00,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48 [2021-11-07 07:49:00,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48 [2021-11-07 07:49:00,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 92 transitions. [2021-11-07 07:49:00,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:49:00,952 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-07 07:49:00,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 92 transitions. [2021-11-07 07:49:00,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 48. [2021-11-07 07:49:00,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.0208333333333333) internal successors, (49), 47 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:00,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 49 transitions. [2021-11-07 07:49:00,955 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-07 07:49:00,955 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-07 07:49:00,955 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-07 07:49:00,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 49 transitions. [2021-11-07 07:49:00,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:00,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:49:00,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:49:00,957 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 1, 1, 1, 1] [2021-11-07 07:49:00,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:49:00,958 INFO L791 eck$LassoCheckResult]: Stem: 3548#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 3549#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 3550#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3551#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3552#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3544#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3545#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3591#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3590#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3589#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3588#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3587#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3586#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3585#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3584#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3583#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3582#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3581#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3580#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3579#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3578#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3577#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3576#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3575#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3574#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3573#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3572#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3571#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3570#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3569#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3568#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3567#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3566#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3565#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3564#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3563#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3562#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3561#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3560#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3559#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3558#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3557#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3556#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3555#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3554#L25-3 assume !(main_~i~0 < 2048); 3553#L25-4 main_~i~0 := 0; 3546#L29-3 [2021-11-07 07:49:00,958 INFO L793 eck$LassoCheckResult]: Loop: 3546#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 3547#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 3546#L29-3 [2021-11-07 07:49:00,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:00,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1936055093, now seen corresponding path program 21 times [2021-11-07 07:49:00,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:00,960 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272640210] [2021-11-07 07:49:00,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:00,960 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:00,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:49:01,334 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:01,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:49:01,334 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272640210] [2021-11-07 07:49:01,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272640210] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:01,335 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [892370868] [2021-11-07 07:49:01,335 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:49:01,335 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:49:01,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:49:01,339 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:49:01,347 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-07 07:49:26,209 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2021-11-07 07:49:26,210 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:49:26,240 INFO L263 TraceCheckSpWp]: Trace formula consists of 296 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-07 07:49:26,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:49:26,445 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:26,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [892370868] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:26,445 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:49:26,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 25 [2021-11-07 07:49:26,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415280695] [2021-11-07 07:49:26,446 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:49:26,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:26,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 22 times [2021-11-07 07:49:26,447 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:26,447 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486728090] [2021-11-07 07:49:26,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:26,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:26,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:26,453 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:49:26,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:26,457 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:49:26,539 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:49:26,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-07 07:49:26,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-11-07 07:49:26,541 INFO L87 Difference]: Start difference. First operand 48 states and 49 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:26,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:49:26,733 INFO L93 Difference]: Finished difference Result 95 states and 96 transitions. [2021-11-07 07:49:26,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-07 07:49:26,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 96 transitions. [2021-11-07 07:49:26,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:26,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 95 states and 96 transitions. [2021-11-07 07:49:26,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50 [2021-11-07 07:49:26,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50 [2021-11-07 07:49:26,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 96 transitions. [2021-11-07 07:49:26,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:49:26,737 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-07 07:49:26,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 96 transitions. [2021-11-07 07:49:26,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 50. [2021-11-07 07:49:26,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.02) internal successors, (51), 49 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:26,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2021-11-07 07:49:26,749 INFO L704 BuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2021-11-07 07:49:26,749 INFO L587 BuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2021-11-07 07:49:26,750 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-07 07:49:26,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 51 transitions. [2021-11-07 07:49:26,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:26,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:49:26,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:49:26,754 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2021-11-07 07:49:26,755 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:49:26,755 INFO L791 eck$LassoCheckResult]: Stem: 3854#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 3855#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 3856#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3857#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3858#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3850#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3851#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3899#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3898#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3897#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3896#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3895#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3894#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3893#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3892#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3891#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3890#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3889#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3888#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3887#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3886#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3885#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3884#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3883#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3882#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3881#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3880#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3879#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3878#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3877#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3876#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3875#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3874#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3873#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3872#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3871#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3870#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3869#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3868#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3867#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3866#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3865#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3864#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3863#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3862#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 3861#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3860#L25-3 assume !(main_~i~0 < 2048); 3859#L25-4 main_~i~0 := 0; 3852#L29-3 [2021-11-07 07:49:26,755 INFO L793 eck$LassoCheckResult]: Loop: 3852#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 3853#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 3852#L29-3 [2021-11-07 07:49:26,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:26,756 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 22 times [2021-11-07 07:49:26,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:26,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026368695] [2021-11-07 07:49:26,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:26,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:26,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:49:27,130 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:27,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:49:27,131 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026368695] [2021-11-07 07:49:27,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026368695] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:27,132 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2080424284] [2021-11-07 07:49:27,132 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 07:49:27,132 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:49:27,132 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:49:27,134 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:49:27,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-07 07:49:27,437 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 07:49:27,437 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:49:27,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-07 07:49:27,442 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:49:27,638 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:27,638 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2080424284] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:27,638 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:49:27,638 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 26 [2021-11-07 07:49:27,639 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313746691] [2021-11-07 07:49:27,639 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:49:27,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:27,639 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 23 times [2021-11-07 07:49:27,639 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:27,640 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000196083] [2021-11-07 07:49:27,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:27,640 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:27,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:27,650 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:49:27,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:49:27,653 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:49:27,746 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:49:27,746 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-07 07:49:27,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-11-07 07:49:27,747 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. cyclomatic complexity: 3 Second operand has 26 states, 26 states have (on average 1.9615384615384615) internal successors, (51), 26 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:27,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:49:27,981 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2021-11-07 07:49:27,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-07 07:49:27,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2021-11-07 07:49:27,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:27,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2021-11-07 07:49:27,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 [2021-11-07 07:49:27,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2021-11-07 07:49:27,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2021-11-07 07:49:27,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:49:27,984 INFO L681 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-07 07:49:27,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2021-11-07 07:49:27,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 52. [2021-11-07 07:49:27,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 51 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:49:27,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2021-11-07 07:49:27,987 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2021-11-07 07:49:27,987 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2021-11-07 07:49:27,988 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-07 07:49:27,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 53 transitions. [2021-11-07 07:49:27,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:49:27,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:49:27,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:49:27,989 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 1, 1, 1, 1] [2021-11-07 07:49:27,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:49:27,990 INFO L791 eck$LassoCheckResult]: Stem: 4173#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 4174#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 4175#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4176#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4177#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4169#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4170#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4219#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4217#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4215#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4213#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4211#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4210#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4209#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4208#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4207#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4205#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4204#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4203#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4202#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4201#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4200#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4199#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4198#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4197#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4196#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4195#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4194#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4193#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4192#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4191#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4190#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4189#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4188#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4187#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4186#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4185#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4184#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4183#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4182#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4181#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4180#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4179#L25-3 assume !(main_~i~0 < 2048); 4178#L25-4 main_~i~0 := 0; 4171#L29-3 [2021-11-07 07:49:27,990 INFO L793 eck$LassoCheckResult]: Loop: 4171#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 4172#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 4171#L29-3 [2021-11-07 07:49:27,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:49:27,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1294026169, now seen corresponding path program 23 times [2021-11-07 07:49:27,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:49:27,991 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940870672] [2021-11-07 07:49:27,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:49:27,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:49:28,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:49:28,349 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:49:28,349 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:49:28,349 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940870672] [2021-11-07 07:49:28,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940870672] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:49:28,349 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1002458957] [2021-11-07 07:49:28,349 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 07:49:28,349 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:49:28,349 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:49:28,351 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:49:28,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-07 07:50:01,055 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2021-11-07 07:50:01,055 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:50:01,098 INFO L263 TraceCheckSpWp]: Trace formula consists of 320 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-07 07:50:01,099 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:50:01,308 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:01,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1002458957] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:01,308 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:50:01,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 27 [2021-11-07 07:50:01,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221962478] [2021-11-07 07:50:01,309 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:50:01,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:01,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 24 times [2021-11-07 07:50:01,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:01,309 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366694605] [2021-11-07 07:50:01,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:01,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:01,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:01,314 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:50:01,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:01,317 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:50:01,427 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:50:01,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-07 07:50:01,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-11-07 07:50:01,428 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. cyclomatic complexity: 3 Second operand has 27 states, 27 states have (on average 1.962962962962963) internal successors, (53), 27 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:01,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:50:01,613 INFO L93 Difference]: Finished difference Result 103 states and 104 transitions. [2021-11-07 07:50:01,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-07 07:50:01,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 104 transitions. [2021-11-07 07:50:01,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:01,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 103 states and 104 transitions. [2021-11-07 07:50:01,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54 [2021-11-07 07:50:01,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54 [2021-11-07 07:50:01,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 104 transitions. [2021-11-07 07:50:01,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:50:01,622 INFO L681 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-07 07:50:01,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 104 transitions. [2021-11-07 07:50:01,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 54. [2021-11-07 07:50:01,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.0185185185185186) internal successors, (55), 53 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:01,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2021-11-07 07:50:01,627 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 55 transitions. [2021-11-07 07:50:01,627 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 55 transitions. [2021-11-07 07:50:01,627 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-07 07:50:01,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 55 transitions. [2021-11-07 07:50:01,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:01,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:50:01,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:50:01,633 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 1, 1, 1, 1] [2021-11-07 07:50:01,633 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:50:01,633 INFO L791 eck$LassoCheckResult]: Stem: 4503#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 4504#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 4507#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4501#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4502#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4508#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4554#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4553#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4552#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4551#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4550#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4549#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4548#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4547#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4546#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4545#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4544#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4543#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4542#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4541#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4540#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4539#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4538#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4537#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4536#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4535#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4534#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4533#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4532#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4531#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4530#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4529#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4528#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4527#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4526#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4525#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4524#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4523#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4522#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4521#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4520#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4519#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4518#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4517#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4516#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4515#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4514#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4513#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4512#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4511#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4510#L25-3 assume !(main_~i~0 < 2048); 4509#L25-4 main_~i~0 := 0; 4505#L29-3 [2021-11-07 07:50:01,633 INFO L793 eck$LassoCheckResult]: Loop: 4505#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 4506#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 4505#L29-3 [2021-11-07 07:50:01,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:01,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1981311429, now seen corresponding path program 24 times [2021-11-07 07:50:01,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:01,634 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909706177] [2021-11-07 07:50:01,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:01,634 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:01,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:50:02,088 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:02,088 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:50:02,089 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909706177] [2021-11-07 07:50:02,089 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909706177] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:02,089 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1668071706] [2021-11-07 07:50:02,089 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 07:50:02,089 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:50:02,089 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:50:02,091 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:50:02,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-07 07:50:32,607 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2021-11-07 07:50:32,607 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:50:32,640 INFO L263 TraceCheckSpWp]: Trace formula consists of 332 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-07 07:50:32,641 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:50:32,876 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:32,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1668071706] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:32,877 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:50:32,877 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 28 [2021-11-07 07:50:32,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522718419] [2021-11-07 07:50:32,877 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:50:32,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:32,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 25 times [2021-11-07 07:50:32,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:32,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545374979] [2021-11-07 07:50:32,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:32,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:32,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:32,886 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:50:32,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:32,890 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:50:32,979 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:50:32,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-07 07:50:32,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-11-07 07:50:32,980 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. cyclomatic complexity: 3 Second operand has 28 states, 28 states have (on average 1.9642857142857142) internal successors, (55), 28 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:33,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:50:33,251 INFO L93 Difference]: Finished difference Result 107 states and 108 transitions. [2021-11-07 07:50:33,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-07 07:50:33,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 108 transitions. [2021-11-07 07:50:33,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:33,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 108 transitions. [2021-11-07 07:50:33,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2021-11-07 07:50:33,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2021-11-07 07:50:33,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 108 transitions. [2021-11-07 07:50:33,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:50:33,255 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 108 transitions. [2021-11-07 07:50:33,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 108 transitions. [2021-11-07 07:50:33,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 56. [2021-11-07 07:50:33,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.0178571428571428) internal successors, (57), 55 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:33,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 57 transitions. [2021-11-07 07:50:33,257 INFO L704 BuchiCegarLoop]: Abstraction has 56 states and 57 transitions. [2021-11-07 07:50:33,258 INFO L587 BuchiCegarLoop]: Abstraction has 56 states and 57 transitions. [2021-11-07 07:50:33,258 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-07 07:50:33,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 57 transitions. [2021-11-07 07:50:33,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:33,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:50:33,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:50:33,259 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 1, 1, 1, 1] [2021-11-07 07:50:33,260 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:50:33,260 INFO L791 eck$LassoCheckResult]: Stem: 4848#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 4849#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 4852#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4846#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4847#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4853#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4901#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4900#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4899#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4898#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4897#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4895#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4894#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4893#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4892#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4891#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4890#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4889#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4888#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4887#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4886#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4885#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4884#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4883#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4882#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4881#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4880#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4879#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4878#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4877#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4876#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4875#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4874#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4873#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4872#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4871#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4870#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4869#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4868#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4867#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4866#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4865#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4864#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4863#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4862#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4861#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4860#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4859#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4858#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4857#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 4856#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4855#L25-3 assume !(main_~i~0 < 2048); 4854#L25-4 main_~i~0 := 0; 4850#L29-3 [2021-11-07 07:50:33,260 INFO L793 eck$LassoCheckResult]: Loop: 4850#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 4851#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 4850#L29-3 [2021-11-07 07:50:33,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:33,261 INFO L85 PathProgramCache]: Analyzing trace with hash -1369715139, now seen corresponding path program 25 times [2021-11-07 07:50:33,261 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:33,261 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500094850] [2021-11-07 07:50:33,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:33,261 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:33,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:50:33,704 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:33,704 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:50:33,704 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500094850] [2021-11-07 07:50:33,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500094850] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:33,704 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1859262898] [2021-11-07 07:50:33,704 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 07:50:33,705 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:50:33,705 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:50:33,706 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:50:33,707 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-07 07:50:34,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:50:34,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-07 07:50:34,026 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:50:34,224 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:34,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1859262898] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:34,224 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:50:34,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 29 [2021-11-07 07:50:34,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730980172] [2021-11-07 07:50:34,225 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:50:34,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:34,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 26 times [2021-11-07 07:50:34,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:34,225 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428657333] [2021-11-07 07:50:34,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:34,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:34,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:34,229 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:50:34,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:34,232 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:50:34,308 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:50:34,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-07 07:50:34,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-11-07 07:50:34,309 INFO L87 Difference]: Start difference. First operand 56 states and 57 transitions. cyclomatic complexity: 3 Second operand has 29 states, 29 states have (on average 1.9655172413793103) internal successors, (57), 29 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:34,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:50:34,486 INFO L93 Difference]: Finished difference Result 111 states and 112 transitions. [2021-11-07 07:50:34,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-07 07:50:34,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111 states and 112 transitions. [2021-11-07 07:50:34,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:34,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111 states to 111 states and 112 transitions. [2021-11-07 07:50:34,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58 [2021-11-07 07:50:34,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58 [2021-11-07 07:50:34,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 112 transitions. [2021-11-07 07:50:34,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:50:34,493 INFO L681 BuchiCegarLoop]: Abstraction has 111 states and 112 transitions. [2021-11-07 07:50:34,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 112 transitions. [2021-11-07 07:50:34,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 58. [2021-11-07 07:50:34,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.0172413793103448) internal successors, (59), 57 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:34,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 59 transitions. [2021-11-07 07:50:34,495 INFO L704 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-07 07:50:34,495 INFO L587 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-07 07:50:34,495 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-07 07:50:34,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 59 transitions. [2021-11-07 07:50:34,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:34,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:50:34,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:50:34,497 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 1, 1, 1, 1] [2021-11-07 07:50:34,497 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:50:34,497 INFO L791 eck$LassoCheckResult]: Stem: 5208#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 5209#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 5210#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5211#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5212#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5204#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5205#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5261#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5260#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5259#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5258#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5257#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5256#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5255#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5254#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5253#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5252#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5251#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5250#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5249#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5248#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5247#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5246#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5245#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5244#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5243#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5242#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5241#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5240#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5239#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5238#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5237#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5236#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5235#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5234#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5233#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5232#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5231#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5230#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5229#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5228#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5227#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5226#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5225#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5224#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5223#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5222#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5221#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5220#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5219#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5218#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5217#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5216#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5215#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5214#L25-3 assume !(main_~i~0 < 2048); 5213#L25-4 main_~i~0 := 0; 5206#L29-3 [2021-11-07 07:50:34,498 INFO L793 eck$LassoCheckResult]: Loop: 5206#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 5207#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 5206#L29-3 [2021-11-07 07:50:34,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:34,498 INFO L85 PathProgramCache]: Analyzing trace with hash -2036200001, now seen corresponding path program 26 times [2021-11-07 07:50:34,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:34,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324774563] [2021-11-07 07:50:34,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:34,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:34,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:50:34,926 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:34,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:50:34,927 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324774563] [2021-11-07 07:50:34,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324774563] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:34,927 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1837852892] [2021-11-07 07:50:34,928 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:50:34,928 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:50:34,928 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:50:34,933 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:50:34,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-07 07:50:35,255 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:50:35,255 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:50:35,257 INFO L263 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-07 07:50:35,259 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:50:35,547 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:35,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1837852892] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:35,548 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:50:35,548 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 30 [2021-11-07 07:50:35,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115398878] [2021-11-07 07:50:35,553 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:50:35,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:35,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 27 times [2021-11-07 07:50:35,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:35,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530259498] [2021-11-07 07:50:35,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:35,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:35,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:35,567 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:50:35,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:50:35,570 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:50:35,673 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:50:35,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-07 07:50:35,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-11-07 07:50:35,674 INFO L87 Difference]: Start difference. First operand 58 states and 59 transitions. cyclomatic complexity: 3 Second operand has 30 states, 30 states have (on average 1.9666666666666666) internal successors, (59), 30 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:35,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:50:35,912 INFO L93 Difference]: Finished difference Result 115 states and 116 transitions. [2021-11-07 07:50:35,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-07 07:50:35,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 116 transitions. [2021-11-07 07:50:35,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:35,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 116 transitions. [2021-11-07 07:50:35,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60 [2021-11-07 07:50:35,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60 [2021-11-07 07:50:35,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 116 transitions. [2021-11-07 07:50:35,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:50:35,915 INFO L681 BuchiCegarLoop]: Abstraction has 115 states and 116 transitions. [2021-11-07 07:50:35,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 116 transitions. [2021-11-07 07:50:35,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 60. [2021-11-07 07:50:35,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.0166666666666666) internal successors, (61), 59 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:50:35,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 61 transitions. [2021-11-07 07:50:35,917 INFO L704 BuchiCegarLoop]: Abstraction has 60 states and 61 transitions. [2021-11-07 07:50:35,917 INFO L587 BuchiCegarLoop]: Abstraction has 60 states and 61 transitions. [2021-11-07 07:50:35,918 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-07 07:50:35,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 61 transitions. [2021-11-07 07:50:35,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:50:35,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:50:35,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:50:35,919 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 1, 1, 1, 1] [2021-11-07 07:50:35,919 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:50:35,919 INFO L791 eck$LassoCheckResult]: Stem: 5577#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 5578#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 5581#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5575#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5576#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5582#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5634#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5633#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5632#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5631#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5630#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5629#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5628#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5627#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5626#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5625#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5624#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5623#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5622#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5621#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5620#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5619#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5618#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5617#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5616#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5615#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5614#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5613#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5612#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5611#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5610#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5609#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5608#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5607#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5606#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5605#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5604#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5603#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5602#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5601#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5600#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5599#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5598#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5597#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5596#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5595#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5594#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5593#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5592#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5591#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5590#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5589#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5588#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5587#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5586#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5585#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5584#L25-3 assume !(main_~i~0 < 2048); 5583#L25-4 main_~i~0 := 0; 5579#L29-3 [2021-11-07 07:50:35,919 INFO L793 eck$LassoCheckResult]: Loop: 5579#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 5580#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 5579#L29-3 [2021-11-07 07:50:35,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:50:35,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1716942017, now seen corresponding path program 27 times [2021-11-07 07:50:35,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:50:35,920 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107393336] [2021-11-07 07:50:35,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:50:35,920 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:50:35,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:50:36,436 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:50:36,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:50:36,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107393336] [2021-11-07 07:50:36,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107393336] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:50:36,437 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [591620434] [2021-11-07 07:50:36,437 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:50:36,437 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:50:36,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:50:36,442 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:50:36,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-07 07:52:32,464 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2021-11-07 07:52:32,464 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:52:32,552 INFO L263 TraceCheckSpWp]: Trace formula consists of 368 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-07 07:52:32,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:52:32,727 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:52:32,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [591620434] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:52:32,728 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:52:32,728 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2021-11-07 07:52:32,728 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012702513] [2021-11-07 07:52:32,728 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:52:32,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:52:32,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 28 times [2021-11-07 07:52:32,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:52:32,729 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524547073] [2021-11-07 07:52:32,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:52:32,731 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:52:32,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:52:32,756 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:52:32,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:52:32,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:52:32,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:52:32,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-07 07:52:32,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-11-07 07:52:32,818 INFO L87 Difference]: Start difference. First operand 60 states and 61 transitions. cyclomatic complexity: 3 Second operand has 31 states, 31 states have (on average 1.967741935483871) internal successors, (61), 31 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:52:33,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:52:33,001 INFO L93 Difference]: Finished difference Result 119 states and 120 transitions. [2021-11-07 07:52:33,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-07 07:52:33,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 120 transitions. [2021-11-07 07:52:33,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:52:33,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 119 states and 120 transitions. [2021-11-07 07:52:33,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2021-11-07 07:52:33,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2021-11-07 07:52:33,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 120 transitions. [2021-11-07 07:52:33,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:52:33,005 INFO L681 BuchiCegarLoop]: Abstraction has 119 states and 120 transitions. [2021-11-07 07:52:33,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 120 transitions. [2021-11-07 07:52:33,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 62. [2021-11-07 07:52:33,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.0161290322580645) internal successors, (63), 61 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:52:33,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 63 transitions. [2021-11-07 07:52:33,007 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 63 transitions. [2021-11-07 07:52:33,007 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 63 transitions. [2021-11-07 07:52:33,007 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-07 07:52:33,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 63 transitions. [2021-11-07 07:52:33,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:52:33,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:52:33,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:52:33,009 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 1, 1, 1, 1] [2021-11-07 07:52:33,009 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:52:33,009 INFO L791 eck$LassoCheckResult]: Stem: 5963#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 5964#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 5965#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5966#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5967#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5959#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5960#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6020#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6019#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6018#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6017#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6016#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6015#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6013#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6011#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6009#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6007#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6005#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6003#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6001#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6000#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5999#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5998#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5997#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5996#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5995#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5994#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5993#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5991#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5990#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5989#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5988#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5987#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5986#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5985#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5984#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5983#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5982#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5981#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5980#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5979#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5978#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5977#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5976#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5975#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5974#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5973#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5972#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5971#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 5970#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5969#L25-3 assume !(main_~i~0 < 2048); 5968#L25-4 main_~i~0 := 0; 5961#L29-3 [2021-11-07 07:52:33,009 INFO L793 eck$LassoCheckResult]: Loop: 5961#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 5962#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 5961#L29-3 [2021-11-07 07:52:33,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:52:33,010 INFO L85 PathProgramCache]: Analyzing trace with hash 713892675, now seen corresponding path program 28 times [2021-11-07 07:52:33,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:52:33,010 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579081575] [2021-11-07 07:52:33,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:52:33,011 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:52:33,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:52:33,596 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:52:33,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:52:33,597 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579081575] [2021-11-07 07:52:33,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579081575] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:52:33,597 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1167255757] [2021-11-07 07:52:33,597 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 07:52:33,597 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:52:33,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:52:33,613 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:52:33,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-07 07:52:33,979 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 07:52:33,979 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:52:33,981 INFO L263 TraceCheckSpWp]: Trace formula consists of 380 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-07 07:52:33,982 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:52:34,197 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:52:34,197 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1167255757] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:52:34,198 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:52:34,198 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 32 [2021-11-07 07:52:34,198 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119807825] [2021-11-07 07:52:34,198 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:52:34,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:52:34,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 29 times [2021-11-07 07:52:34,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:52:34,198 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831369603] [2021-11-07 07:52:34,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:52:34,199 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:52:34,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:52:34,203 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:52:34,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:52:34,205 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:52:34,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:52:34,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-07 07:52:34,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-11-07 07:52:34,299 INFO L87 Difference]: Start difference. First operand 62 states and 63 transitions. cyclomatic complexity: 3 Second operand has 32 states, 32 states have (on average 1.96875) internal successors, (63), 32 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:52:34,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:52:34,548 INFO L93 Difference]: Finished difference Result 123 states and 124 transitions. [2021-11-07 07:52:34,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-07 07:52:34,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 124 transitions. [2021-11-07 07:52:34,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:52:34,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 124 transitions. [2021-11-07 07:52:34,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64 [2021-11-07 07:52:34,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64 [2021-11-07 07:52:34,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 124 transitions. [2021-11-07 07:52:34,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:52:34,551 INFO L681 BuchiCegarLoop]: Abstraction has 123 states and 124 transitions. [2021-11-07 07:52:34,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 124 transitions. [2021-11-07 07:52:34,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 64. [2021-11-07 07:52:34,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.015625) internal successors, (65), 63 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:52:34,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 65 transitions. [2021-11-07 07:52:34,553 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 65 transitions. [2021-11-07 07:52:34,553 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 65 transitions. [2021-11-07 07:52:34,553 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-07 07:52:34,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 65 transitions. [2021-11-07 07:52:34,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:52:34,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:52:34,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:52:34,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 1, 1, 1, 1] [2021-11-07 07:52:34,554 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:52:34,554 INFO L791 eck$LassoCheckResult]: Stem: 6358#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 6359#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 6362#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6356#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6357#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6363#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6419#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6418#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6417#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6416#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6415#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6414#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6413#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6412#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6411#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6410#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6409#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6408#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6407#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6406#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6405#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6404#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6403#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6402#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6401#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6400#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6399#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6398#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6397#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6396#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6395#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6394#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6393#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6392#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6391#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6390#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6389#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6388#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6387#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6386#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6385#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6384#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6383#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6382#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6381#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6380#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6379#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6378#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6377#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6376#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6375#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6374#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6373#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6372#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6371#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6370#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6369#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6368#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6367#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6366#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6365#L25-3 assume !(main_~i~0 < 2048); 6364#L25-4 main_~i~0 := 0; 6360#L29-3 [2021-11-07 07:52:34,554 INFO L793 eck$LassoCheckResult]: Loop: 6360#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 6361#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 6360#L29-3 [2021-11-07 07:52:34,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:52:34,554 INFO L85 PathProgramCache]: Analyzing trace with hash -1143850683, now seen corresponding path program 29 times [2021-11-07 07:52:34,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:52:34,555 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123112260] [2021-11-07 07:52:34,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:52:34,555 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:52:34,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:52:35,095 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:52:35,095 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:52:35,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123112260] [2021-11-07 07:52:35,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123112260] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:52:35,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [832063484] [2021-11-07 07:52:35,095 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 07:52:35,096 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:52:35,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:52:35,098 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:52:35,112 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-07 07:53:48,599 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2021-11-07 07:53:48,600 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:53:48,666 INFO L263 TraceCheckSpWp]: Trace formula consists of 392 conjuncts, 31 conjunts are in the unsatisfiable core [2021-11-07 07:53:48,668 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:53:48,936 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:53:48,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [832063484] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:53:48,936 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:53:48,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 33 [2021-11-07 07:53:48,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382187533] [2021-11-07 07:53:48,937 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:53:48,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:53:48,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 30 times [2021-11-07 07:53:48,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:53:48,938 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328397035] [2021-11-07 07:53:48,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:53:48,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:53:48,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:53:48,943 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:53:48,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:53:48,953 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:53:49,024 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:53:49,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-07 07:53:49,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-11-07 07:53:49,026 INFO L87 Difference]: Start difference. First operand 64 states and 65 transitions. cyclomatic complexity: 3 Second operand has 33 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 33 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:53:49,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:53:49,339 INFO L93 Difference]: Finished difference Result 127 states and 128 transitions. [2021-11-07 07:53:49,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-07 07:53:49,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127 states and 128 transitions. [2021-11-07 07:53:49,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:53:49,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127 states to 127 states and 128 transitions. [2021-11-07 07:53:49,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2021-11-07 07:53:49,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2021-11-07 07:53:49,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 128 transitions. [2021-11-07 07:53:49,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:53:49,343 INFO L681 BuchiCegarLoop]: Abstraction has 127 states and 128 transitions. [2021-11-07 07:53:49,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 128 transitions. [2021-11-07 07:53:49,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 66. [2021-11-07 07:53:49,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.0151515151515151) internal successors, (67), 65 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:53:49,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 67 transitions. [2021-11-07 07:53:49,346 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 67 transitions. [2021-11-07 07:53:49,346 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 67 transitions. [2021-11-07 07:53:49,346 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-07 07:53:49,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 67 transitions. [2021-11-07 07:53:49,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:53:49,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:53:49,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:53:49,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 30, 1, 1, 1, 1] [2021-11-07 07:53:49,348 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:53:49,348 INFO L791 eck$LassoCheckResult]: Stem: 6770#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 6771#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 6772#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6773#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6774#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6766#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6767#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6831#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6830#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6829#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6828#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6827#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6826#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6825#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6824#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6823#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6822#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6821#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6820#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6819#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6818#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6817#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6816#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6815#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6814#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6813#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6812#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6811#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6810#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6809#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6808#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6807#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6806#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6805#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6804#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6803#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6802#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6801#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6800#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6799#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6798#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6797#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6796#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6795#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6794#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6793#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6792#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6791#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6790#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6789#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6788#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6787#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6786#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6785#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6784#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6783#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6782#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6781#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6780#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6779#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6778#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 6777#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6776#L25-3 assume !(main_~i~0 < 2048); 6775#L25-4 main_~i~0 := 0; 6768#L29-3 [2021-11-07 07:53:49,348 INFO L793 eck$LassoCheckResult]: Loop: 6768#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 6769#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 6768#L29-3 [2021-11-07 07:53:49,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:53:49,348 INFO L85 PathProgramCache]: Analyzing trace with hash 271177415, now seen corresponding path program 30 times [2021-11-07 07:53:49,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:53:49,349 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780939343] [2021-11-07 07:53:49,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:53:49,349 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:53:49,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:53:49,848 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:53:49,848 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:53:49,848 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780939343] [2021-11-07 07:53:49,848 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780939343] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:53:49,848 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1090997886] [2021-11-07 07:53:49,848 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-07 07:53:49,848 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:53:49,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:53:49,856 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:53:49,874 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-07 07:57:21,660 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2021-11-07 07:57:21,661 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:57:21,816 INFO L263 TraceCheckSpWp]: Trace formula consists of 404 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-07 07:57:21,818 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:57:22,004 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:22,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1090997886] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:22,005 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:57:22,005 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2021-11-07 07:57:22,005 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131909889] [2021-11-07 07:57:22,005 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:57:22,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:22,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 31 times [2021-11-07 07:57:22,006 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:22,006 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851919707] [2021-11-07 07:57:22,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:22,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:22,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:22,022 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:57:22,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:22,027 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:57:22,104 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:57:22,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-07 07:57:22,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-11-07 07:57:22,105 INFO L87 Difference]: Start difference. First operand 66 states and 67 transitions. cyclomatic complexity: 3 Second operand has 34 states, 34 states have (on average 1.9705882352941178) internal successors, (67), 34 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:22,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:57:22,366 INFO L93 Difference]: Finished difference Result 131 states and 132 transitions. [2021-11-07 07:57:22,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-07 07:57:22,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131 states and 132 transitions. [2021-11-07 07:57:22,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:22,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131 states to 131 states and 132 transitions. [2021-11-07 07:57:22,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68 [2021-11-07 07:57:22,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68 [2021-11-07 07:57:22,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 131 states and 132 transitions. [2021-11-07 07:57:22,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:57:22,370 INFO L681 BuchiCegarLoop]: Abstraction has 131 states and 132 transitions. [2021-11-07 07:57:22,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states and 132 transitions. [2021-11-07 07:57:22,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 68. [2021-11-07 07:57:22,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.0147058823529411) internal successors, (69), 67 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:22,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 69 transitions. [2021-11-07 07:57:22,372 INFO L704 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-07 07:57:22,372 INFO L587 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-07 07:57:22,372 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-07 07:57:22,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 69 transitions. [2021-11-07 07:57:22,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:22,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:57:22,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:57:22,373 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 31, 1, 1, 1, 1] [2021-11-07 07:57:22,374 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:57:22,374 INFO L791 eck$LassoCheckResult]: Stem: 7193#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 7194#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 7195#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7196#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7197#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7189#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7190#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7255#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7254#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7253#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7251#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7250#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7249#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7248#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7247#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7245#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7243#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7241#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7239#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7237#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7235#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7233#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7231#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7230#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7229#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7228#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7227#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7225#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7223#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7221#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7219#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7217#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7215#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7213#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7211#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7210#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7209#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7208#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7207#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7205#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7204#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7203#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7202#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7201#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7200#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7199#L25-3 assume !(main_~i~0 < 2048); 7198#L25-4 main_~i~0 := 0; 7191#L29-3 [2021-11-07 07:57:22,374 INFO L793 eck$LassoCheckResult]: Loop: 7191#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 7192#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 7191#L29-3 [2021-11-07 07:57:22,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:22,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1391453239, now seen corresponding path program 31 times [2021-11-07 07:57:22,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:22,375 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024451474] [2021-11-07 07:57:22,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:22,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:22,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:57:22,997 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:22,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:57:22,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024451474] [2021-11-07 07:57:22,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024451474] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:22,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1473126925] [2021-11-07 07:57:22,998 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-07 07:57:22,998 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:57:22,998 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:57:23,004 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:57:23,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-07 07:57:23,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:57:23,439 INFO L263 TraceCheckSpWp]: Trace formula consists of 416 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-07 07:57:23,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:57:23,639 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:23,640 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1473126925] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:23,640 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:57:23,640 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 35 [2021-11-07 07:57:23,640 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067299313] [2021-11-07 07:57:23,640 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:57:23,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:23,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 32 times [2021-11-07 07:57:23,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:23,641 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127807067] [2021-11-07 07:57:23,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:23,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:23,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:23,658 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:57:23,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:23,678 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:57:23,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:57:23,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-07 07:57:23,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-11-07 07:57:23,770 INFO L87 Difference]: Start difference. First operand 68 states and 69 transitions. cyclomatic complexity: 3 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 35 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:24,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:57:24,118 INFO L93 Difference]: Finished difference Result 135 states and 136 transitions. [2021-11-07 07:57:24,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-07 07:57:24,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135 states and 136 transitions. [2021-11-07 07:57:24,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:24,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135 states to 135 states and 136 transitions. [2021-11-07 07:57:24,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2021-11-07 07:57:24,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2021-11-07 07:57:24,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 136 transitions. [2021-11-07 07:57:24,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:57:24,121 INFO L681 BuchiCegarLoop]: Abstraction has 135 states and 136 transitions. [2021-11-07 07:57:24,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 136 transitions. [2021-11-07 07:57:24,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 70. [2021-11-07 07:57:24,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.0142857142857142) internal successors, (71), 69 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:24,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 71 transitions. [2021-11-07 07:57:24,123 INFO L704 BuchiCegarLoop]: Abstraction has 70 states and 71 transitions. [2021-11-07 07:57:24,123 INFO L587 BuchiCegarLoop]: Abstraction has 70 states and 71 transitions. [2021-11-07 07:57:24,123 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-07 07:57:24,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 71 transitions. [2021-11-07 07:57:24,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:24,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:57:24,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:57:24,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [32, 32, 1, 1, 1, 1] [2021-11-07 07:57:24,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:57:24,127 INFO L791 eck$LassoCheckResult]: Stem: 7627#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 7628#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 7631#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7625#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7626#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7632#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7694#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7693#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7692#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7691#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7690#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7689#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7688#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7687#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7686#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7685#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7684#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7683#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7682#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7681#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7680#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7679#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7678#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7677#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7676#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7675#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7674#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7673#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7672#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7671#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7670#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7669#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7668#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7667#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7666#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7665#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7664#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7663#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7662#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7661#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7660#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7659#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7658#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7657#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7656#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7655#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7654#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7653#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7652#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7651#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7650#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7649#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7648#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7647#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7646#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7645#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7644#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7643#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7642#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7641#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7640#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7639#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7638#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7637#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7636#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 7635#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7634#L25-3 assume !(main_~i~0 < 2048); 7633#L25-4 main_~i~0 := 0; 7629#L29-3 [2021-11-07 07:57:24,127 INFO L793 eck$LassoCheckResult]: Loop: 7629#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 7630#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 7629#L29-3 [2021-11-07 07:57:24,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:24,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1451677621, now seen corresponding path program 32 times [2021-11-07 07:57:24,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:24,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281178389] [2021-11-07 07:57:24,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:24,128 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:24,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:57:24,709 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:24,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:57:24,710 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281178389] [2021-11-07 07:57:24,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281178389] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:24,710 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [346215626] [2021-11-07 07:57:24,710 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-07 07:57:24,710 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:57:24,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:57:24,711 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:57:24,712 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-07 07:57:25,157 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-07 07:57:25,157 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 07:57:25,160 INFO L263 TraceCheckSpWp]: Trace formula consists of 428 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-07 07:57:25,162 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 07:57:25,379 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:25,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [346215626] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:25,380 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 07:57:25,380 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 36 [2021-11-07 07:57:25,380 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529706078] [2021-11-07 07:57:25,381 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:57:25,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:25,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 33 times [2021-11-07 07:57:25,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:25,382 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627596148] [2021-11-07 07:57:25,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:25,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:25,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:25,391 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:57:25,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:57:25,397 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:57:25,478 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:57:25,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-07 07:57:25,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-11-07 07:57:25,480 INFO L87 Difference]: Start difference. First operand 70 states and 71 transitions. cyclomatic complexity: 3 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 36 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:25,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:57:25,789 INFO L93 Difference]: Finished difference Result 139 states and 140 transitions. [2021-11-07 07:57:25,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-07 07:57:25,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 140 transitions. [2021-11-07 07:57:25,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:25,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 139 states and 140 transitions. [2021-11-07 07:57:25,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2021-11-07 07:57:25,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2021-11-07 07:57:25,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 140 transitions. [2021-11-07 07:57:25,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:57:25,793 INFO L681 BuchiCegarLoop]: Abstraction has 139 states and 140 transitions. [2021-11-07 07:57:25,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 140 transitions. [2021-11-07 07:57:25,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 72. [2021-11-07 07:57:25,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.0138888888888888) internal successors, (73), 71 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:57:25,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 73 transitions. [2021-11-07 07:57:25,796 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 73 transitions. [2021-11-07 07:57:25,796 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 73 transitions. [2021-11-07 07:57:25,796 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-07 07:57:25,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 73 transitions. [2021-11-07 07:57:25,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 07:57:25,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:57:25,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:57:25,798 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [33, 33, 1, 1, 1, 1] [2021-11-07 07:57:25,798 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 07:57:25,799 INFO L791 eck$LassoCheckResult]: Stem: 8078#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 8079#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 8080#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8081#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8082#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8074#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8075#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8145#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8144#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8143#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8142#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8141#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8140#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8139#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8138#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8137#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8136#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8135#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8134#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8133#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8132#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8131#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8130#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8129#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8128#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8127#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8126#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8125#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8124#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8123#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8122#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8121#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8120#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8119#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8118#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8117#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8116#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8115#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8114#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8113#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8112#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8111#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8110#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8109#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8108#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8107#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8106#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8105#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8104#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8103#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8102#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8101#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8100#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8099#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8098#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8097#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8096#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8095#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8094#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8093#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8092#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8091#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8090#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8089#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8088#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8087#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8086#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8085#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8084#L25-3 assume !(main_~i~0 < 2048); 8083#L25-4 main_~i~0 := 0; 8076#L29-3 [2021-11-07 07:57:25,799 INFO L793 eck$LassoCheckResult]: Loop: 8076#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 8077#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 8076#L29-3 [2021-11-07 07:57:25,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:57:25,799 INFO L85 PathProgramCache]: Analyzing trace with hash 802233421, now seen corresponding path program 33 times [2021-11-07 07:57:25,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:57:25,800 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144019629] [2021-11-07 07:57:25,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:57:25,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:57:25,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:57:26,385 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:57:26,386 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:57:26,386 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144019629] [2021-11-07 07:57:26,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144019629] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 07:57:26,386 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1510617987] [2021-11-07 07:57:26,386 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-07 07:57:26,386 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 07:57:26,386 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:57:26,394 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 07:57:26,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-07 08:01:25,805 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2021-11-07 08:01:25,805 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:01:25,950 INFO L263 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-07 08:01:25,951 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:01:26,140 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:26,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1510617987] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:01:26,141 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:01:26,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 37 [2021-11-07 08:01:26,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096993446] [2021-11-07 08:01:26,141 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:26,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:26,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 34 times [2021-11-07 08:01:26,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:26,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79337780] [2021-11-07 08:01:26,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:26,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:26,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:01:26,148 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:01:26,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:01:26,151 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:01:26,217 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:26,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-11-07 08:01:26,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-11-07 08:01:26,221 INFO L87 Difference]: Start difference. First operand 72 states and 73 transitions. cyclomatic complexity: 3 Second operand has 37 states, 37 states have (on average 1.972972972972973) internal successors, (73), 37 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:26,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:26,469 INFO L93 Difference]: Finished difference Result 143 states and 144 transitions. [2021-11-07 08:01:26,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-07 08:01:26,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143 states and 144 transitions. [2021-11-07 08:01:26,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:01:26,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143 states to 143 states and 144 transitions. [2021-11-07 08:01:26,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74 [2021-11-07 08:01:26,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74 [2021-11-07 08:01:26,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143 states and 144 transitions. [2021-11-07 08:01:26,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:26,473 INFO L681 BuchiCegarLoop]: Abstraction has 143 states and 144 transitions. [2021-11-07 08:01:26,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states and 144 transitions. [2021-11-07 08:01:26,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 74. [2021-11-07 08:01:26,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.0135135135135136) internal successors, (75), 73 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:26,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 75 transitions. [2021-11-07 08:01:26,476 INFO L704 BuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2021-11-07 08:01:26,476 INFO L587 BuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2021-11-07 08:01:26,476 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-07 08:01:26,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 75 transitions. [2021-11-07 08:01:26,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:01:26,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:26,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:26,478 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [34, 34, 1, 1, 1, 1] [2021-11-07 08:01:26,478 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:01:26,478 INFO L791 eck$LassoCheckResult]: Stem: 8540#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 8541#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 8542#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8543#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8544#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8536#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8537#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8609#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8608#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8607#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8606#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8605#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8604#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8603#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8602#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8601#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8600#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8599#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8598#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8597#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8596#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8595#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8594#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8593#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8592#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8591#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8590#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8589#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8588#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8587#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8586#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8585#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8584#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8583#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8582#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8581#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8580#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8579#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8578#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8577#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8576#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8575#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8574#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8573#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8572#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8571#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8570#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8569#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8568#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8567#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8566#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8565#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8564#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8563#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8562#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8561#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8560#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8559#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8558#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8557#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8556#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8555#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8554#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8553#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8552#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8551#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8550#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8549#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8548#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 8547#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8546#L25-3 assume !(main_~i~0 < 2048); 8545#L25-4 main_~i~0 := 0; 8538#L29-3 [2021-11-07 08:01:26,478 INFO L793 eck$LassoCheckResult]: Loop: 8538#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 8539#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 8538#L29-3 [2021-11-07 08:01:26,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:26,479 INFO L85 PathProgramCache]: Analyzing trace with hash 2147227599, now seen corresponding path program 34 times [2021-11-07 08:01:26,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:26,479 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802024689] [2021-11-07 08:01:26,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:26,480 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:26,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:27,290 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:27,290 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:27,290 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802024689] [2021-11-07 08:01:27,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802024689] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:01:27,291 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261011663] [2021-11-07 08:01:27,291 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-07 08:01:27,291 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:01:27,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:01:27,316 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:01:27,318 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-07 08:01:27,856 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-07 08:01:27,856 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-07 08:01:27,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 452 conjuncts, 36 conjunts are in the unsatisfiable core [2021-11-07 08:01:27,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-07 08:01:28,059 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:28,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [261011663] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:01:28,059 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-07 08:01:28,059 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 38 [2021-11-07 08:01:28,059 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459029928] [2021-11-07 08:01:28,060 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:28,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:28,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1731, now seen corresponding path program 35 times [2021-11-07 08:01:28,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:28,060 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529845353] [2021-11-07 08:01:28,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:28,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:28,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:01:28,072 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 08:01:28,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 08:01:28,074 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 08:01:28,150 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:28,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-07 08:01:28,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-11-07 08:01:28,152 INFO L87 Difference]: Start difference. First operand 74 states and 75 transitions. cyclomatic complexity: 3 Second operand has 38 states, 38 states have (on average 1.9736842105263157) internal successors, (75), 38 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:28,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:28,456 INFO L93 Difference]: Finished difference Result 147 states and 148 transitions. [2021-11-07 08:01:28,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-07 08:01:28,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147 states and 148 transitions. [2021-11-07 08:01:28,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:01:28,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147 states to 147 states and 148 transitions. [2021-11-07 08:01:28,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76 [2021-11-07 08:01:28,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76 [2021-11-07 08:01:28,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147 states and 148 transitions. [2021-11-07 08:01:28,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:28,459 INFO L681 BuchiCegarLoop]: Abstraction has 147 states and 148 transitions. [2021-11-07 08:01:28,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states and 148 transitions. [2021-11-07 08:01:28,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 76. [2021-11-07 08:01:28,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.013157894736842) internal successors, (77), 75 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:28,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 77 transitions. [2021-11-07 08:01:28,462 INFO L704 BuchiCegarLoop]: Abstraction has 76 states and 77 transitions. [2021-11-07 08:01:28,462 INFO L587 BuchiCegarLoop]: Abstraction has 76 states and 77 transitions. [2021-11-07 08:01:28,462 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-07 08:01:28,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 77 transitions. [2021-11-07 08:01:28,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2021-11-07 08:01:28,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:28,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:28,464 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [35, 35, 1, 1, 1, 1] [2021-11-07 08:01:28,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-07 08:01:28,465 INFO L791 eck$LassoCheckResult]: Stem: 9015#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(12); 9016#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~nondet5, main_#t~post3, main_#t~mem7, main_#t~post6, main_#t~mem8, main_#t~mem9, main_~#A~0.base, main_~#A~0.offset, main_~#B~0.base, main_~#B~0.offset, main_~i~0, main_~tmp~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(8192);call main_~#B~0.base, main_~#B~0.offset := #Ultimate.allocOnStack(8192);havoc main_~i~0;havoc main_~tmp~0;main_~i~0 := 0; 9017#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9018#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9019#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9011#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9012#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9086#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9085#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9084#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9083#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9082#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9081#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9080#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9079#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9078#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9077#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9076#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9075#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9074#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9073#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9072#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9071#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9070#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9069#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9068#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9067#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9066#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9065#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9064#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9063#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9062#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9061#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9060#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9059#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9058#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9057#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9056#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9055#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9054#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9053#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9052#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9051#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9050#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9049#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9048#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9047#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9046#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9045#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9044#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9043#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9042#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9041#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9040#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9039#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9038#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9037#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9036#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9035#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9034#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9033#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9032#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9031#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9030#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9029#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9028#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9027#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9026#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9025#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9024#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9023#L25-3 assume !!(main_~i~0 < 2048);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4;call write~int(main_#t~nondet5, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet5; 9022#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9021#L25-3 assume !(main_~i~0 < 2048); 9020#L25-4 main_~i~0 := 0; 9013#L29-3 [2021-11-07 08:01:28,465 INFO L793 eck$LassoCheckResult]: Loop: 9013#L29-3 assume !!(main_~i~0 < 2048);call main_#t~mem7 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);main_~tmp~0 := main_#t~mem7;havoc main_#t~mem7;call write~int(main_~tmp~0, main_~#B~0.base, main_~#B~0.offset + 4 * main_~i~0, 4); 9014#L29-2 main_#t~post6 := main_~i~0;main_~i~0 := 1 + main_#t~post6;havoc main_#t~post6; 9013#L29-3 [2021-11-07 08:01:28,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:28,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1901476561, now seen corresponding path program 35 times [2021-11-07 08:01:28,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:28,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700150140] [2021-11-07 08:01:28,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:28,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:28,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:29,250 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:29,250 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:29,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700150140] [2021-11-07 08:01:29,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [700150140] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-07 08:01:29,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1395879178] [2021-11-07 08:01:29,251 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-07 08:01:29,251 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-07 08:01:29,251 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:01:29,254 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-07 08:01:29,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9f826d5c-707d-493b-a08b-c00d21bd40f3/bin/uautomizer-AkOaLMaTGY/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process