./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 07:26:02,430 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 07:26:02,432 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 07:26:02,495 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 07:26:02,496 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 07:26:02,498 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 07:26:02,502 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 07:26:02,511 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 07:26:02,515 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 07:26:02,525 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 07:26:02,526 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 07:26:02,528 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 07:26:02,529 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 07:26:02,530 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 07:26:02,532 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 07:26:02,554 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 07:26:02,555 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 07:26:02,558 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 07:26:02,560 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 07:26:02,563 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 07:26:02,565 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 07:26:02,567 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 07:26:02,569 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 07:26:02,570 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 07:26:02,575 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 07:26:02,575 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 07:26:02,576 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 07:26:02,578 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 07:26:02,578 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 07:26:02,580 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 07:26:02,581 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 07:26:02,589 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 07:26:02,591 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 07:26:02,592 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 07:26:02,594 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 07:26:02,594 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 07:26:02,595 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 07:26:02,596 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 07:26:02,596 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 07:26:02,597 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 07:26:02,598 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 07:26:02,600 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-07 07:26:02,635 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 07:26:02,635 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 07:26:02,639 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 07:26:02,640 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 07:26:02,642 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 07:26:02,643 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 07:26:02,643 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 07:26:02,643 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 07:26:02,644 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 07:26:02,644 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 07:26:02,645 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 07:26:02,646 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 07:26:02,646 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 07:26:02,647 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 07:26:02,647 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-07 07:26:02,647 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 07:26:02,647 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 07:26:02,648 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-07 07:26:02,648 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 07:26:02,648 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 07:26:02,648 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 07:26:02,649 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 07:26:02,649 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-07 07:26:02,650 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 07:26:02,650 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 07:26:02,650 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 07:26:02,653 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 07:26:02,653 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 07:26:02,654 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 07:26:02,654 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 07:26:02,654 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 07:26:02,655 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 07:26:02,656 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 07:26:02,657 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2021-11-07 07:26:02,953 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 07:26:02,985 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 07:26:02,989 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 07:26:02,991 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 07:26:02,992 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 07:26:02,993 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-11-07 07:26:03,073 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/data/c244c2313/82fd082c21614c0a86e76fbfa957cbeb/FLAGe7871ea2e [2021-11-07 07:26:03,739 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 07:26:03,741 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-11-07 07:26:03,759 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/data/c244c2313/82fd082c21614c0a86e76fbfa957cbeb/FLAGe7871ea2e [2021-11-07 07:26:04,056 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/data/c244c2313/82fd082c21614c0a86e76fbfa957cbeb [2021-11-07 07:26:04,059 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 07:26:04,063 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 07:26:04,066 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 07:26:04,067 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 07:26:04,070 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 07:26:04,072 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,075 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@576f2ce6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04, skipping insertion in model container [2021-11-07 07:26:04,076 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,083 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 07:26:04,140 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 07:26:04,270 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-11-07 07:26:04,413 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:26:04,440 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 07:26:04,461 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-11-07 07:26:04,588 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:26:04,625 INFO L208 MainTranslator]: Completed translation [2021-11-07 07:26:04,626 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04 WrapperNode [2021-11-07 07:26:04,626 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 07:26:04,629 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 07:26:04,629 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 07:26:04,629 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 07:26:04,639 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,672 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,835 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 07:26:04,836 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 07:26:04,836 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 07:26:04,836 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 07:26:04,844 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,845 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,852 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,853 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:04,966 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:05,017 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:05,029 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:05,049 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 07:26:05,051 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 07:26:05,052 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 07:26:05,053 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 07:26:05,055 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (1/1) ... [2021-11-07 07:26:05,063 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:26:05,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:26:05,098 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:26:05,119 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d6eb5db-b090-4c71-8ca5-e9d3f5049a0a/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 07:26:05,150 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 07:26:05,150 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-07 07:26:05,150 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 07:26:05,151 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 07:26:07,158 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 07:26:07,159 INFO L299 CfgBuilder]: Removed 376 assume(true) statements. [2021-11-07 07:26:07,163 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:26:07 BoogieIcfgContainer [2021-11-07 07:26:07,164 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 07:26:07,165 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 07:26:07,165 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 07:26:07,168 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 07:26:07,169 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:26:07,170 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 07:26:04" (1/3) ... [2021-11-07 07:26:07,172 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2c1cd10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:26:07, skipping insertion in model container [2021-11-07 07:26:07,172 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:26:07,172 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:26:04" (2/3) ... [2021-11-07 07:26:07,173 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2c1cd10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:26:07, skipping insertion in model container [2021-11-07 07:26:07,173 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:26:07,173 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:26:07" (3/3) ... [2021-11-07 07:26:07,174 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2021-11-07 07:26:07,231 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 07:26:07,231 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 07:26:07,232 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 07:26:07,232 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 07:26:07,232 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 07:26:07,232 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 07:26:07,232 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 07:26:07,232 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 07:26:07,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:07,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1021 [2021-11-07 07:26:07,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:07,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:07,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:07,399 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:07,400 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 07:26:07,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:07,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1021 [2021-11-07 07:26:07,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:07,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:07,429 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:07,429 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:07,446 INFO L791 eck$LassoCheckResult]: Stem: 536#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1034#L-1true havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 487#L1391true havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 844#L651true assume !(1 == ~m_i~0);~m_st~0 := 2; 1001#L658-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 750#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 697#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 265#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 789#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 610#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1005#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 103#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 324#L703-1true assume !(0 == ~M_E~0); 284#L939-1true assume !(0 == ~T1_E~0); 726#L944-1true assume !(0 == ~T2_E~0); 345#L949-1true assume !(0 == ~T3_E~0); 342#L954-1true assume !(0 == ~T4_E~0); 1042#L959-1true assume !(0 == ~T5_E~0); 751#L964-1true assume !(0 == ~T6_E~0); 180#L969-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 865#L974-1true assume !(0 == ~T8_E~0); 684#L979-1true assume !(0 == ~T9_E~0); 1069#L984-1true assume !(0 == ~E_M~0); 271#L989-1true assume !(0 == ~E_1~0); 498#L994-1true assume !(0 == ~E_2~0); 205#L999-1true assume !(0 == ~E_3~0); 652#L1004-1true assume !(0 == ~E_4~0); 40#L1009-1true assume 0 == ~E_5~0;~E_5~0 := 1; 200#L1014-1true assume !(0 == ~E_6~0); 617#L1019-1true assume !(0 == ~E_7~0); 914#L1024-1true assume !(0 == ~E_8~0); 163#L1029-1true assume !(0 == ~E_9~0); 213#L1034-1true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 929#L460true assume !(1 == ~m_pc~0); 1013#L460-2true is_master_triggered_~__retres1~0 := 0; 583#L471true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1024#L472true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 998#L1167true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 334#L1167-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 480#L479true assume 1 == ~t1_pc~0; 325#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1014#L490true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 868#L491true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 170#L1175true assume !(0 != activate_threads_~tmp___0~0); 378#L1175-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 95#L498true assume !(1 == ~t2_pc~0); 626#L498-2true is_transmit2_triggered_~__retres1~2 := 0; 323#L509true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 809#L510true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 653#L1183true assume !(0 != activate_threads_~tmp___1~0); 574#L1183-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1093#L517true assume 1 == ~t3_pc~0; 876#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1036#L528true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 372#L529true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 188#L1191true assume !(0 != activate_threads_~tmp___2~0); 628#L1191-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 790#L536true assume !(1 == ~t4_pc~0); 1071#L536-2true is_transmit4_triggered_~__retres1~4 := 0; 741#L547true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1060#L548true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 362#L1199true assume !(0 != activate_threads_~tmp___3~0); 1058#L1199-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 547#L555true assume 1 == ~t5_pc~0; 1137#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 682#L566true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54#L567true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 164#L1207true assume !(0 != activate_threads_~tmp___4~0); 105#L1207-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 58#L574true assume !(1 == ~t6_pc~0); 619#L574-2true is_transmit6_triggered_~__retres1~6 := 0; 1075#L585true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 108#L586true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 647#L1215true assume !(0 != activate_threads_~tmp___5~0); 1066#L1215-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 944#L593true assume 1 == ~t7_pc~0; 1111#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 756#L604true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1057#L605true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1051#L1223true assume !(0 != activate_threads_~tmp___6~0); 879#L1223-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 269#L612true assume 1 == ~t8_pc~0; 596#L613true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 869#L623true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 461#L624true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 785#L1231true assume !(0 != activate_threads_~tmp___7~0); 432#L1231-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 486#L631true assume !(1 == ~t9_pc~0); 504#L631-2true is_transmit9_triggered_~__retres1~9 := 0; 53#L642true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 39#L643true activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 326#L1239true assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1023#L1239-2true assume !(1 == ~M_E~0); 659#L1047-1true assume !(1 == ~T1_E~0); 426#L1052-1true assume !(1 == ~T2_E~0); 19#L1057-1true assume !(1 == ~T3_E~0); 154#L1062-1true assume !(1 == ~T4_E~0); 752#L1067-1true assume !(1 == ~T5_E~0); 336#L1072-1true assume !(1 == ~T6_E~0); 598#L1077-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 101#L1082-1true assume !(1 == ~T8_E~0); 408#L1087-1true assume !(1 == ~T9_E~0); 6#L1092-1true assume !(1 == ~E_M~0); 20#L1097-1true assume !(1 == ~E_1~0); 918#L1102-1true assume !(1 == ~E_2~0); 482#L1107-1true assume !(1 == ~E_3~0); 428#L1112-1true assume !(1 == ~E_4~0); 462#L1117-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1126#L1122-1true assume !(1 == ~E_6~0); 373#L1127-1true assume !(1 == ~E_7~0); 215#L1132-1true assume !(1 == ~E_8~0); 922#L1137-1true assume !(1 == ~E_9~0); 376#L1428-1true [2021-11-07 07:26:07,458 INFO L793 eck$LassoCheckResult]: Loop: 376#L1428-1true assume !false; 425#L1429true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 947#L914true assume !true; 207#L929true start_simulation_~kernel_st~0 := 2; 481#L651-1true start_simulation_~kernel_st~0 := 3; 519#L939-2true assume 0 == ~M_E~0;~M_E~0 := 1; 402#L939-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 138#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 5#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 700#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 349#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 41#L964-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 258#L969-3true assume !(0 == ~T7_E~0); 137#L974-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1028#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 403#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1115#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 167#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 945#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 526#L1004-3true assume 0 == ~E_4~0;~E_4~0 := 1; 80#L1009-3true assume !(0 == ~E_5~0); 604#L1014-3true assume 0 == ~E_6~0;~E_6~0 := 1; 390#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1086#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 381#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 351#L1034-3true havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 898#L460-33true assume !(1 == ~m_pc~0); 559#L460-35true is_master_triggered_~__retres1~0 := 0; 538#L471-11true is_master_triggered_#res := is_master_triggered_~__retres1~0; 217#L472-11true activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9#L1167-33true assume !(0 != activate_threads_~tmp~1); 489#L1167-35true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 183#L479-33true assume 1 == ~t1_pc~0; 910#L480-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 165#L490-11true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 592#L491-11true activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 847#L1175-33true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 967#L1175-35true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 187#L498-33true assume !(1 == ~t2_pc~0); 60#L498-35true is_transmit2_triggered_~__retres1~2 := 0; 311#L509-11true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 125#L510-11true activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 417#L1183-33true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 113#L1183-35true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 975#L517-33true assume 1 == ~t3_pc~0; 1009#L518-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 718#L528-11true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1064#L529-11true activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 513#L1191-33true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 648#L1191-35true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 240#L536-33true assume 1 == ~t4_pc~0; 585#L537-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 279#L547-11true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 407#L548-11true activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 690#L1199-33true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 791#L1199-35true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30#L555-33true assume !(1 == ~t5_pc~0); 778#L555-35true is_transmit5_triggered_~__retres1~5 := 0; 457#L566-11true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 159#L567-11true activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 477#L1207-33true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1008#L1207-35true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18#L574-33true assume !(1 == ~t6_pc~0); 906#L574-35true is_transmit6_triggered_~__retres1~6 := 0; 824#L585-11true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 168#L586-11true activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 560#L1215-33true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 321#L1215-35true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50#L593-33true assume 1 == ~t7_pc~0; 389#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 930#L604-11true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 100#L605-11true activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 537#L1223-33true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 677#L1223-35true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1092#L612-33true assume !(1 == ~t8_pc~0); 1080#L612-35true is_transmit8_triggered_~__retres1~8 := 0; 831#L623-11true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1061#L624-11true activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 597#L1231-33true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 99#L1231-35true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1135#L631-33true assume 1 == ~t9_pc~0; 749#L632-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 72#L642-11true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 393#L643-11true activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 199#L1239-33true assume !(0 != activate_threads_~tmp___8~0); 126#L1239-35true assume 1 == ~M_E~0;~M_E~0 := 2; 218#L1047-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1145#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 660#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1139#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 77#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 999#L1072-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 285#L1077-3true assume !(1 == ~T7_E~0); 192#L1082-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 238#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 422#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1150#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 371#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 928#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 709#L1112-3true assume 1 == ~E_4~0;~E_4~0 := 2; 189#L1117-3true assume !(1 == ~E_5~0); 716#L1122-3true assume 1 == ~E_6~0;~E_6~0 := 2; 219#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 497#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1053#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 473#L1142-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 128#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 479#L768-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 474#L769-1true start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 297#L1447true assume !(0 == start_simulation_~tmp~3); 488#L1447-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 1113#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 713#L768-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 499#L769-2true stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 204#L1402true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 83#L1409true stop_simulation_#res := stop_simulation_~__retres2~0; 521#L1410true start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 337#L1460true assume !(0 != start_simulation_~tmp___0~1); 376#L1428-1true [2021-11-07 07:26:07,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:07,464 INFO L85 PathProgramCache]: Analyzing trace with hash -168145620, now seen corresponding path program 1 times [2021-11-07 07:26:07,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:07,479 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010915425] [2021-11-07 07:26:07,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:07,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:07,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:07,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:07,750 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:07,750 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010915425] [2021-11-07 07:26:07,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010915425] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:07,752 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:07,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:07,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447922319] [2021-11-07 07:26:07,766 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:07,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:07,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1652114992, now seen corresponding path program 1 times [2021-11-07 07:26:07,770 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:07,770 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085996064] [2021-11-07 07:26:07,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:07,771 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:07,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:07,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:07,845 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:07,846 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085996064] [2021-11-07 07:26:07,847 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085996064] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:07,847 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:07,847 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:26:07,847 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527915961] [2021-11-07 07:26:07,853 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:07,856 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:07,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:07,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:07,877 INFO L87 Difference]: Start difference. First operand has 1148 states, 1147 states have (on average 1.5222319093286836) internal successors, (1746), 1147 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:07,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:07,987 INFO L93 Difference]: Finished difference Result 1148 states and 1720 transitions. [2021-11-07 07:26:07,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:07,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1148 states and 1720 transitions. [2021-11-07 07:26:08,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1148 states to 1143 states and 1715 transitions. [2021-11-07 07:26:08,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:08,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:08,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1715 transitions. [2021-11-07 07:26:08,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:08,047 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-07 07:26:08,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1715 transitions. [2021-11-07 07:26:08,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:08,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.500437445319335) internal successors, (1715), 1142 states have internal predecessors, (1715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:08,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1715 transitions. [2021-11-07 07:26:08,152 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-07 07:26:08,152 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1715 transitions. [2021-11-07 07:26:08,153 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 07:26:08,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1715 transitions. [2021-11-07 07:26:08,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:08,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:08,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,172 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,174 INFO L791 eck$LassoCheckResult]: Stem: 3157#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3158#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3109#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3110#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 3378#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3334#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3299#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2806#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2807#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3230#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3231#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2321#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2322#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2520#L703-1 assume !(0 == ~M_E~0); 2837#L939-1 assume !(0 == ~T1_E~0); 2838#L944-1 assume !(0 == ~T2_E~0); 2928#L949-1 assume !(0 == ~T3_E~0); 2926#L954-1 assume !(0 == ~T4_E~0); 2927#L959-1 assume !(0 == ~T5_E~0); 3335#L964-1 assume !(0 == ~T6_E~0); 2661#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2662#L974-1 assume !(0 == ~T8_E~0); 3287#L979-1 assume !(0 == ~T9_E~0); 3288#L984-1 assume !(0 == ~E_M~0); 2818#L989-1 assume !(0 == ~E_1~0); 2819#L994-1 assume !(0 == ~E_2~0); 2708#L999-1 assume !(0 == ~E_3~0); 2709#L1004-1 assume !(0 == ~E_4~0); 2389#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2390#L1014-1 assume !(0 == ~E_6~0); 2702#L1019-1 assume !(0 == ~E_7~0); 3235#L1024-1 assume !(0 == ~E_8~0); 2634#L1029-1 assume !(0 == ~E_9~0); 2635#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2722#L460 assume !(1 == ~m_pc~0); 2307#L460-2 is_master_triggered_~__retres1~0 := 0; 2306#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3201#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3434#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2914#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2915#L479 assume 1 == ~t1_pc~0; 2898#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2899#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3393#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2646#L1175 assume !(0 != activate_threads_~tmp___0~0); 2647#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2502#L498 assume !(1 == ~t2_pc~0); 2503#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 2896#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2897#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3265#L1183 assume !(0 != activate_threads_~tmp___1~0); 3192#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3193#L517 assume 1 == ~t3_pc~0; 3397#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3398#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2971#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2679#L1191 assume !(0 != activate_threads_~tmp___2~0); 2680#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3244#L536 assume !(1 == ~t4_pc~0); 2960#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 2961#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3326#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2953#L1199 assume !(0 != activate_threads_~tmp___3~0); 2954#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3167#L555 assume 1 == ~t5_pc~0; 3168#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3236#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2418#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2419#L1207 assume !(0 != activate_threads_~tmp___4~0); 2521#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2426#L574 assume !(1 == ~t6_pc~0); 2427#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 3046#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2526#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2527#L1215 assume !(0 != activate_threads_~tmp___5~0); 3259#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3418#L593 assume 1 == ~t7_pc~0; 3419#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2653#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3338#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3439#L1223 assume !(0 != activate_threads_~tmp___6~0); 3401#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2813#L612 assume 1 == ~t8_pc~0; 2814#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3218#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3080#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3081#L1231 assume !(0 != activate_threads_~tmp___7~0); 3048#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3049#L631 assume !(1 == ~t9_pc~0); 3066#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 2417#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2387#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2388#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 2901#L1239-2 assume !(1 == ~M_E~0); 3267#L1047-1 assume !(1 == ~T1_E~0); 3041#L1052-1 assume !(1 == ~T2_E~0); 2342#L1057-1 assume !(1 == ~T3_E~0); 2343#L1062-1 assume !(1 == ~T4_E~0); 2618#L1067-1 assume !(1 == ~T5_E~0); 2917#L1072-1 assume !(1 == ~T6_E~0); 2918#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2516#L1082-1 assume !(1 == ~T8_E~0); 2517#L1087-1 assume !(1 == ~T9_E~0); 2315#L1092-1 assume !(1 == ~E_M~0); 2316#L1097-1 assume !(1 == ~E_1~0); 2344#L1102-1 assume !(1 == ~E_2~0); 3105#L1107-1 assume !(1 == ~E_3~0); 3044#L1112-1 assume !(1 == ~E_4~0); 3045#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3082#L1122-1 assume !(1 == ~E_6~0); 2972#L1127-1 assume !(1 == ~E_7~0); 2725#L1132-1 assume !(1 == ~E_8~0); 2726#L1137-1 assume !(1 == ~E_9~0); 2920#L1428-1 [2021-11-07 07:26:08,175 INFO L793 eck$LassoCheckResult]: Loop: 2920#L1428-1 assume !false; 2977#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 2555#L914 assume !false; 3039#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 3040#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2328#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 2329#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3262#L783 assume !(0 != eval_~tmp~0); 2711#L929 start_simulation_~kernel_st~0 := 2; 2712#L651-1 start_simulation_~kernel_st~0 := 3; 3104#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3013#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2588#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2311#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2312#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2934#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2391#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2392#L969-3 assume !(0 == ~T7_E~0); 2586#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2587#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3014#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3015#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2640#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2641#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3143#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2472#L1009-3 assume !(0 == ~E_5~0); 2473#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3000#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3001#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2984#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2935#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2936#L460-33 assume 1 == ~m_pc~0; 2973#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2974#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2729#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2319#L1167-33 assume !(0 != activate_threads_~tmp~1); 2320#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2669#L479-33 assume 1 == ~t1_pc~0; 2670#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2636#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2637#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3212#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3381#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2677#L498-33 assume !(1 == ~t2_pc~0); 2432#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 2433#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2561#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2562#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2538#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2539#L517-33 assume 1 == ~t3_pc~0; 3427#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3313#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3314#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3132#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3133#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2761#L536-33 assume !(1 == ~t4_pc~0); 2762#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 2829#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2830#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3022#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3292#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2366#L555-33 assume !(1 == ~t5_pc~0); 2368#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 3076#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2627#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2628#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3101#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2339#L574-33 assume !(1 == ~t6_pc~0); 2340#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 3304#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2642#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 2643#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2893#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2406#L593-33 assume 1 == ~t7_pc~0; 2407#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2849#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2514#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 2515#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3159#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3283#L612-33 assume !(1 == ~t8_pc~0); 3408#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 3372#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3373#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3219#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2507#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 2508#L631-33 assume !(1 == ~t9_pc~0); 3108#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 2455#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 2456#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 2697#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 2559#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 2560#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2730#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3268#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3269#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2467#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2468#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2836#L1077-3 assume !(1 == ~T7_E~0); 2686#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2687#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2757#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3038#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2969#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2970#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3305#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2681#L1117-3 assume !(1 == ~E_5~0); 2682#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2731#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2732#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3118#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3095#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 2563#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2449#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 3096#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 2856#L1447 assume !(0 == start_simulation_~tmp~3); 2858#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 3111#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 2601#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 3119#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 2707#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2476#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 2477#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 2919#L1460 assume !(0 != start_simulation_~tmp___0~1); 2920#L1428-1 [2021-11-07 07:26:08,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1963205102, now seen corresponding path program 1 times [2021-11-07 07:26:08,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,178 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816587960] [2021-11-07 07:26:08,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,298 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816587960] [2021-11-07 07:26:08,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816587960] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,299 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:08,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920514878] [2021-11-07 07:26:08,300 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:08,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1645751262, now seen corresponding path program 1 times [2021-11-07 07:26:08,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,301 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267429082] [2021-11-07 07:26:08,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,425 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,431 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267429082] [2021-11-07 07:26:08,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267429082] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,432 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,432 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:08,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240183596] [2021-11-07 07:26:08,433 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:08,434 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:08,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:08,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:08,436 INFO L87 Difference]: Start difference. First operand 1143 states and 1715 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:08,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:08,462 INFO L93 Difference]: Finished difference Result 1143 states and 1714 transitions. [2021-11-07 07:26:08,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:08,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1714 transitions. [2021-11-07 07:26:08,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1714 transitions. [2021-11-07 07:26:08,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:08,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:08,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1714 transitions. [2021-11-07 07:26:08,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:08,487 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-07 07:26:08,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1714 transitions. [2021-11-07 07:26:08,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:08,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.499562554680665) internal successors, (1714), 1142 states have internal predecessors, (1714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:08,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1714 transitions. [2021-11-07 07:26:08,543 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-07 07:26:08,544 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1714 transitions. [2021-11-07 07:26:08,544 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 07:26:08,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1714 transitions. [2021-11-07 07:26:08,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:08,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:08,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,561 INFO L791 eck$LassoCheckResult]: Stem: 5452#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5453#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5404#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5405#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 5673#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5629#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5594#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5101#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5102#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5525#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5526#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4616#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4617#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4815#L703-1 assume !(0 == ~M_E~0); 5132#L939-1 assume !(0 == ~T1_E~0); 5133#L944-1 assume !(0 == ~T2_E~0); 5223#L949-1 assume !(0 == ~T3_E~0); 5221#L954-1 assume !(0 == ~T4_E~0); 5222#L959-1 assume !(0 == ~T5_E~0); 5630#L964-1 assume !(0 == ~T6_E~0); 4956#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4957#L974-1 assume !(0 == ~T8_E~0); 5584#L979-1 assume !(0 == ~T9_E~0); 5585#L984-1 assume !(0 == ~E_M~0); 5113#L989-1 assume !(0 == ~E_1~0); 5114#L994-1 assume !(0 == ~E_2~0); 5003#L999-1 assume !(0 == ~E_3~0); 5004#L1004-1 assume !(0 == ~E_4~0); 4684#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4685#L1014-1 assume !(0 == ~E_6~0); 4999#L1019-1 assume !(0 == ~E_7~0); 5530#L1024-1 assume !(0 == ~E_8~0); 4929#L1029-1 assume !(0 == ~E_9~0); 4930#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5017#L460 assume !(1 == ~m_pc~0); 4605#L460-2 is_master_triggered_~__retres1~0 := 0; 4604#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5496#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5729#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5209#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5210#L479 assume 1 == ~t1_pc~0; 5193#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5194#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5688#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4941#L1175 assume !(0 != activate_threads_~tmp___0~0); 4942#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4797#L498 assume !(1 == ~t2_pc~0); 4798#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 5191#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5192#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5560#L1183 assume !(0 != activate_threads_~tmp___1~0); 5487#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5488#L517 assume 1 == ~t3_pc~0; 5692#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5693#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5266#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4974#L1191 assume !(0 != activate_threads_~tmp___2~0); 4975#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5541#L536 assume !(1 == ~t4_pc~0); 5255#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 5256#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5621#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5248#L1199 assume !(0 != activate_threads_~tmp___3~0); 5249#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5462#L555 assume 1 == ~t5_pc~0; 5463#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5531#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4713#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4714#L1207 assume !(0 != activate_threads_~tmp___4~0); 4816#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4721#L574 assume !(1 == ~t6_pc~0); 4722#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 5341#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4821#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4822#L1215 assume !(0 != activate_threads_~tmp___5~0); 5556#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5713#L593 assume 1 == ~t7_pc~0; 5714#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4948#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5633#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5734#L1223 assume !(0 != activate_threads_~tmp___6~0); 5696#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5108#L612 assume 1 == ~t8_pc~0; 5109#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5513#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5375#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5376#L1231 assume !(0 != activate_threads_~tmp___7~0); 5345#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5346#L631 assume !(1 == ~t9_pc~0); 5361#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 4712#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4682#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4683#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 5196#L1239-2 assume !(1 == ~M_E~0); 5562#L1047-1 assume !(1 == ~T1_E~0); 5336#L1052-1 assume !(1 == ~T2_E~0); 4637#L1057-1 assume !(1 == ~T3_E~0); 4638#L1062-1 assume !(1 == ~T4_E~0); 4913#L1067-1 assume !(1 == ~T5_E~0); 5212#L1072-1 assume !(1 == ~T6_E~0); 5213#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4811#L1082-1 assume !(1 == ~T8_E~0); 4812#L1087-1 assume !(1 == ~T9_E~0); 4612#L1092-1 assume !(1 == ~E_M~0); 4613#L1097-1 assume !(1 == ~E_1~0); 4639#L1102-1 assume !(1 == ~E_2~0); 5400#L1107-1 assume !(1 == ~E_3~0); 5339#L1112-1 assume !(1 == ~E_4~0); 5340#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5377#L1122-1 assume !(1 == ~E_6~0); 5267#L1127-1 assume !(1 == ~E_7~0); 5022#L1132-1 assume !(1 == ~E_8~0); 5023#L1137-1 assume !(1 == ~E_9~0); 5215#L1428-1 [2021-11-07 07:26:08,562 INFO L793 eck$LassoCheckResult]: Loop: 5215#L1428-1 assume !false; 5272#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 4850#L914 assume !false; 5334#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 5335#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4623#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 4624#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5557#L783 assume !(0 != eval_~tmp~0); 5006#L929 start_simulation_~kernel_st~0 := 2; 5007#L651-1 start_simulation_~kernel_st~0 := 3; 5399#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5308#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4885#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4606#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4607#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5229#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4686#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4687#L969-3 assume !(0 == ~T7_E~0); 4881#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4882#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5309#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5310#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4935#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4936#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5438#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4767#L1009-3 assume !(0 == ~E_5~0); 4768#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5295#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5296#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5279#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5230#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5231#L460-33 assume 1 == ~m_pc~0; 5269#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5270#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5024#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4614#L1167-33 assume !(0 != activate_threads_~tmp~1); 4615#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4964#L479-33 assume 1 == ~t1_pc~0; 4965#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4931#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4932#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5507#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5676#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4972#L498-33 assume !(1 == ~t2_pc~0); 4727#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 4728#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4856#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4857#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4833#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4834#L517-33 assume 1 == ~t3_pc~0; 5722#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5608#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5609#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5427#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5428#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5053#L536-33 assume !(1 == ~t4_pc~0); 5054#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 5124#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5125#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5317#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5587#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4658#L555-33 assume 1 == ~t5_pc~0; 4659#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5371#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4922#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4923#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5396#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4632#L574-33 assume !(1 == ~t6_pc~0); 4633#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 5599#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4937#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4938#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5188#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4704#L593-33 assume 1 == ~t7_pc~0; 4705#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5145#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4809#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4810#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5454#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5578#L612-33 assume 1 == ~t8_pc~0; 5702#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5667#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5668#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5514#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4805#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4806#L631-33 assume !(1 == ~t9_pc~0); 5403#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 4752#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4753#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4992#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 4854#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 4855#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5025#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5563#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5564#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4762#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4763#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5131#L1077-3 assume !(1 == ~T7_E~0); 4981#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4982#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5052#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5333#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5264#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5265#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5600#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4976#L1117-3 assume !(1 == ~E_5~0); 4977#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5026#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5027#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5413#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5390#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 4858#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4744#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 5391#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 5151#L1447 assume !(0 == start_simulation_~tmp~3); 5153#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 5406#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 4896#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 5414#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 5002#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4771#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 4772#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 5214#L1460 assume !(0 != start_simulation_~tmp___0~1); 5215#L1428-1 [2021-11-07 07:26:08,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,563 INFO L85 PathProgramCache]: Analyzing trace with hash -358596816, now seen corresponding path program 1 times [2021-11-07 07:26:08,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,564 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725847505] [2021-11-07 07:26:08,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725847505] [2021-11-07 07:26:08,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725847505] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,648 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,648 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:08,648 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832771538] [2021-11-07 07:26:08,649 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:08,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1101128032, now seen corresponding path program 1 times [2021-11-07 07:26:08,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,651 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949547235] [2021-11-07 07:26:08,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,736 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949547235] [2021-11-07 07:26:08,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949547235] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,737 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,737 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:08,739 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243136983] [2021-11-07 07:26:08,739 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:08,740 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:08,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:08,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:08,741 INFO L87 Difference]: Start difference. First operand 1143 states and 1714 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:08,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:08,767 INFO L93 Difference]: Finished difference Result 1143 states and 1713 transitions. [2021-11-07 07:26:08,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:08,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1713 transitions. [2021-11-07 07:26:08,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1713 transitions. [2021-11-07 07:26:08,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:08,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:08,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1713 transitions. [2021-11-07 07:26:08,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:08,792 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-07 07:26:08,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1713 transitions. [2021-11-07 07:26:08,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:08,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4986876640419948) internal successors, (1713), 1142 states have internal predecessors, (1713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:08,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1713 transitions. [2021-11-07 07:26:08,819 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-07 07:26:08,819 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1713 transitions. [2021-11-07 07:26:08,819 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 07:26:08,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1713 transitions. [2021-11-07 07:26:08,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:08,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:08,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:08,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:08,829 INFO L791 eck$LassoCheckResult]: Stem: 7745#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7746#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7697#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7698#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 7967#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7922#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7887#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7394#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7395#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7818#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7819#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6909#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6910#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7108#L703-1 assume !(0 == ~M_E~0); 7425#L939-1 assume !(0 == ~T1_E~0); 7426#L944-1 assume !(0 == ~T2_E~0); 7516#L949-1 assume !(0 == ~T3_E~0); 7514#L954-1 assume !(0 == ~T4_E~0); 7515#L959-1 assume !(0 == ~T5_E~0); 7923#L964-1 assume !(0 == ~T6_E~0); 7249#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7250#L974-1 assume !(0 == ~T8_E~0); 7877#L979-1 assume !(0 == ~T9_E~0); 7878#L984-1 assume !(0 == ~E_M~0); 7408#L989-1 assume !(0 == ~E_1~0); 7409#L994-1 assume !(0 == ~E_2~0); 7296#L999-1 assume !(0 == ~E_3~0); 7297#L1004-1 assume !(0 == ~E_4~0); 6977#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6978#L1014-1 assume !(0 == ~E_6~0); 7292#L1019-1 assume !(0 == ~E_7~0); 7823#L1024-1 assume !(0 == ~E_8~0); 7222#L1029-1 assume !(0 == ~E_9~0); 7223#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7312#L460 assume !(1 == ~m_pc~0); 6898#L460-2 is_master_triggered_~__retres1~0 := 0; 6897#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7789#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8022#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7502#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7503#L479 assume 1 == ~t1_pc~0; 7486#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7487#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7981#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7235#L1175 assume !(0 != activate_threads_~tmp___0~0); 7236#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7090#L498 assume !(1 == ~t2_pc~0); 7091#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 7484#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7485#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7853#L1183 assume !(0 != activate_threads_~tmp___1~0); 7780#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7781#L517 assume 1 == ~t3_pc~0; 7985#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7986#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7559#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7267#L1191 assume !(0 != activate_threads_~tmp___2~0); 7268#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7834#L536 assume !(1 == ~t4_pc~0); 7548#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 7549#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7914#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7541#L1199 assume !(0 != activate_threads_~tmp___3~0); 7542#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7755#L555 assume 1 == ~t5_pc~0; 7756#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7824#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7008#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7009#L1207 assume !(0 != activate_threads_~tmp___4~0); 7109#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7014#L574 assume !(1 == ~t6_pc~0); 7015#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 7634#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7114#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 7115#L1215 assume !(0 != activate_threads_~tmp___5~0); 7849#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8006#L593 assume 1 == ~t7_pc~0; 8007#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7241#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7926#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8027#L1223 assume !(0 != activate_threads_~tmp___6~0); 7989#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7401#L612 assume 1 == ~t8_pc~0; 7402#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7806#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7669#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7670#L1231 assume !(0 != activate_threads_~tmp___7~0); 7638#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7639#L631 assume !(1 == ~t9_pc~0); 7654#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 7005#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 6975#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 6976#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 7489#L1239-2 assume !(1 == ~M_E~0); 7855#L1047-1 assume !(1 == ~T1_E~0); 7629#L1052-1 assume !(1 == ~T2_E~0); 6930#L1057-1 assume !(1 == ~T3_E~0); 6931#L1062-1 assume !(1 == ~T4_E~0); 7206#L1067-1 assume !(1 == ~T5_E~0); 7505#L1072-1 assume !(1 == ~T6_E~0); 7506#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7104#L1082-1 assume !(1 == ~T8_E~0); 7105#L1087-1 assume !(1 == ~T9_E~0); 6905#L1092-1 assume !(1 == ~E_M~0); 6906#L1097-1 assume !(1 == ~E_1~0); 6932#L1102-1 assume !(1 == ~E_2~0); 7693#L1107-1 assume !(1 == ~E_3~0); 7632#L1112-1 assume !(1 == ~E_4~0); 7633#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7671#L1122-1 assume !(1 == ~E_6~0); 7560#L1127-1 assume !(1 == ~E_7~0); 7315#L1132-1 assume !(1 == ~E_8~0); 7316#L1137-1 assume !(1 == ~E_9~0); 7508#L1428-1 [2021-11-07 07:26:08,829 INFO L793 eck$LassoCheckResult]: Loop: 7508#L1428-1 assume !false; 7565#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 7143#L914 assume !false; 7627#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7628#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 6916#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 6917#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7850#L783 assume !(0 != eval_~tmp~0); 7299#L929 start_simulation_~kernel_st~0 := 2; 7300#L651-1 start_simulation_~kernel_st~0 := 3; 7692#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7601#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7178#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6899#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6900#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7522#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6981#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6982#L969-3 assume !(0 == ~T7_E~0); 7174#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7175#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7602#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7603#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7228#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7229#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7731#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7060#L1009-3 assume !(0 == ~E_5~0); 7061#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7588#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7589#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7572#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7526#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7527#L460-33 assume 1 == ~m_pc~0; 7561#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7562#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7317#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6907#L1167-33 assume !(0 != activate_threads_~tmp~1); 6908#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7253#L479-33 assume 1 == ~t1_pc~0; 7254#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7224#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7225#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7798#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7969#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7262#L498-33 assume !(1 == ~t2_pc~0); 7017#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 7018#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7147#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7148#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7126#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7127#L517-33 assume !(1 == ~t3_pc~0); 8016#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 7901#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7902#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7720#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7721#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7349#L536-33 assume !(1 == ~t4_pc~0); 7350#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 7417#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7418#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7610#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7880#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6954#L555-33 assume 1 == ~t5_pc~0; 6955#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7664#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7215#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7216#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7689#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6925#L574-33 assume !(1 == ~t6_pc~0); 6926#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 7892#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7230#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 7231#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7481#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6999#L593-33 assume 1 == ~t7_pc~0; 7000#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7441#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7102#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7103#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7747#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7871#L612-33 assume 1 == ~t8_pc~0; 7995#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7960#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7961#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 7807#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 7098#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7099#L631-33 assume !(1 == ~t9_pc~0); 7696#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 7045#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7046#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7285#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 7149#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 7150#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7318#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7856#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7857#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7055#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7056#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7424#L1077-3 assume !(1 == ~T7_E~0); 7274#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7275#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7345#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7626#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7557#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7558#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7893#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7269#L1117-3 assume !(1 == ~E_5~0); 7270#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7319#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7320#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7706#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7683#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7154#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 7037#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 7684#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 7444#L1447 assume !(0 == start_simulation_~tmp~3); 7446#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 7699#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 7189#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 7707#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 7295#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7064#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 7065#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 7507#L1460 assume !(0 != start_simulation_~tmp___0~1); 7508#L1428-1 [2021-11-07 07:26:08,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1783263662, now seen corresponding path program 1 times [2021-11-07 07:26:08,830 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,831 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038723509] [2021-11-07 07:26:08,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,831 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,888 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038723509] [2021-11-07 07:26:08,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038723509] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,888 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:08,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372161560] [2021-11-07 07:26:08,890 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:08,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:08,891 INFO L85 PathProgramCache]: Analyzing trace with hash -1526719681, now seen corresponding path program 1 times [2021-11-07 07:26:08,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:08,892 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509702561] [2021-11-07 07:26:08,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:08,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:08,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:08,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:08,946 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:08,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509702561] [2021-11-07 07:26:08,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509702561] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:08,951 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:08,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:08,952 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014207331] [2021-11-07 07:26:08,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:08,953 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:08,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:08,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:08,955 INFO L87 Difference]: Start difference. First operand 1143 states and 1713 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,015 INFO L93 Difference]: Finished difference Result 1143 states and 1712 transitions. [2021-11-07 07:26:09,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1712 transitions. [2021-11-07 07:26:09,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1712 transitions. [2021-11-07 07:26:09,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:09,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:09,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1712 transitions. [2021-11-07 07:26:09,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:09,039 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-07 07:26:09,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1712 transitions. [2021-11-07 07:26:09,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:09,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4978127734033246) internal successors, (1712), 1142 states have internal predecessors, (1712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1712 transitions. [2021-11-07 07:26:09,066 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-07 07:26:09,066 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1712 transitions. [2021-11-07 07:26:09,066 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 07:26:09,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1712 transitions. [2021-11-07 07:26:09,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:09,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:09,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,079 INFO L791 eck$LassoCheckResult]: Stem: 10038#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10039#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9990#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9991#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 10260#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10215#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10180#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9689#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9690#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10111#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10112#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9202#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9203#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9401#L703-1 assume !(0 == ~M_E~0); 9718#L939-1 assume !(0 == ~T1_E~0); 9719#L944-1 assume !(0 == ~T2_E~0); 9809#L949-1 assume !(0 == ~T3_E~0); 9807#L954-1 assume !(0 == ~T4_E~0); 9808#L959-1 assume !(0 == ~T5_E~0); 10216#L964-1 assume !(0 == ~T6_E~0); 9542#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9543#L974-1 assume !(0 == ~T8_E~0); 10170#L979-1 assume !(0 == ~T9_E~0); 10171#L984-1 assume !(0 == ~E_M~0); 9701#L989-1 assume !(0 == ~E_1~0); 9702#L994-1 assume !(0 == ~E_2~0); 9589#L999-1 assume !(0 == ~E_3~0); 9590#L1004-1 assume !(0 == ~E_4~0); 9270#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 9271#L1014-1 assume !(0 == ~E_6~0); 9585#L1019-1 assume !(0 == ~E_7~0); 10116#L1024-1 assume !(0 == ~E_8~0); 9515#L1029-1 assume !(0 == ~E_9~0); 9516#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9605#L460 assume !(1 == ~m_pc~0); 9191#L460-2 is_master_triggered_~__retres1~0 := 0; 9190#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10082#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10315#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9795#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9796#L479 assume 1 == ~t1_pc~0; 9779#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9780#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10274#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9528#L1175 assume !(0 != activate_threads_~tmp___0~0); 9529#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9383#L498 assume !(1 == ~t2_pc~0); 9384#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 9777#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9778#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10146#L1183 assume !(0 != activate_threads_~tmp___1~0); 10073#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10074#L517 assume 1 == ~t3_pc~0; 10279#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10280#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9852#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9560#L1191 assume !(0 != activate_threads_~tmp___2~0); 9561#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10127#L536 assume !(1 == ~t4_pc~0); 9841#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 9842#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10207#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9834#L1199 assume !(0 != activate_threads_~tmp___3~0); 9835#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10050#L555 assume 1 == ~t5_pc~0; 10051#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10117#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9301#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9302#L1207 assume !(0 != activate_threads_~tmp___4~0); 9404#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9307#L574 assume !(1 == ~t6_pc~0); 9308#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 9927#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9407#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9408#L1215 assume !(0 != activate_threads_~tmp___5~0); 10142#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10299#L593 assume 1 == ~t7_pc~0; 10300#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9534#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10221#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10320#L1223 assume !(0 != activate_threads_~tmp___6~0); 10282#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9694#L612 assume 1 == ~t8_pc~0; 9695#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10099#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9962#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9963#L1231 assume !(0 != activate_threads_~tmp___7~0); 9931#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9932#L631 assume !(1 == ~t9_pc~0); 9947#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 9298#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 9268#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9269#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 9782#L1239-2 assume !(1 == ~M_E~0); 10148#L1047-1 assume !(1 == ~T1_E~0); 9922#L1052-1 assume !(1 == ~T2_E~0); 9223#L1057-1 assume !(1 == ~T3_E~0); 9224#L1062-1 assume !(1 == ~T4_E~0); 9499#L1067-1 assume !(1 == ~T5_E~0); 9798#L1072-1 assume !(1 == ~T6_E~0); 9799#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9397#L1082-1 assume !(1 == ~T8_E~0); 9398#L1087-1 assume !(1 == ~T9_E~0); 9198#L1092-1 assume !(1 == ~E_M~0); 9199#L1097-1 assume !(1 == ~E_1~0); 9225#L1102-1 assume !(1 == ~E_2~0); 9986#L1107-1 assume !(1 == ~E_3~0); 9925#L1112-1 assume !(1 == ~E_4~0); 9926#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9964#L1122-1 assume !(1 == ~E_6~0); 9853#L1127-1 assume !(1 == ~E_7~0); 9608#L1132-1 assume !(1 == ~E_8~0); 9609#L1137-1 assume !(1 == ~E_9~0); 9801#L1428-1 [2021-11-07 07:26:09,079 INFO L793 eck$LassoCheckResult]: Loop: 9801#L1428-1 assume !false; 9858#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 9436#L914 assume !false; 9920#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 9921#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9211#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 9212#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10143#L783 assume !(0 != eval_~tmp~0); 9592#L929 start_simulation_~kernel_st~0 := 2; 9593#L651-1 start_simulation_~kernel_st~0 := 3; 9985#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9894#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9469#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9192#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9193#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9815#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9272#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9273#L969-3 assume !(0 == ~T7_E~0); 9467#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9468#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9895#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9896#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9521#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9522#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10024#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9353#L1009-3 assume !(0 == ~E_5~0); 9354#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9881#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9882#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9865#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9816#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9817#L460-33 assume !(1 == ~m_pc~0); 9856#L460-35 is_master_triggered_~__retres1~0 := 0; 9855#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9610#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9200#L1167-33 assume !(0 != activate_threads_~tmp~1); 9201#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9549#L479-33 assume 1 == ~t1_pc~0; 9550#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9517#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9518#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10093#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10262#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9558#L498-33 assume !(1 == ~t2_pc~0); 9313#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 9314#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9440#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9441#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9419#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9420#L517-33 assume 1 == ~t3_pc~0; 10308#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10194#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10195#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10013#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10014#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9642#L536-33 assume !(1 == ~t4_pc~0); 9643#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 9710#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9711#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9903#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10173#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9247#L555-33 assume 1 == ~t5_pc~0; 9248#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9957#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9508#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9509#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9982#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9220#L574-33 assume !(1 == ~t6_pc~0); 9221#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 10185#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9523#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9524#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9774#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9292#L593-33 assume 1 == ~t7_pc~0; 9293#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9735#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9395#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9396#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10040#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10164#L612-33 assume 1 == ~t8_pc~0; 10288#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10253#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10254#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 10100#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9393#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9394#L631-33 assume !(1 == ~t9_pc~0); 9989#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 9338#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 9339#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9580#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 9442#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 9443#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9611#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10149#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10150#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9348#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9349#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9717#L1077-3 assume !(1 == ~T7_E~0); 9567#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9568#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9638#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9919#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9850#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9851#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10186#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9562#L1117-3 assume !(1 == ~E_5~0); 9563#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9612#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9613#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9999#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9976#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 9447#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9333#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 9977#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 9737#L1447 assume !(0 == start_simulation_~tmp~3); 9739#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 9992#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 9482#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 10000#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 9588#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9357#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 9358#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 9800#L1460 assume !(0 != start_simulation_~tmp___0~1); 9801#L1428-1 [2021-11-07 07:26:09,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1888422032, now seen corresponding path program 1 times [2021-11-07 07:26:09,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,081 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730695945] [2021-11-07 07:26:09,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,121 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,121 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [730695945] [2021-11-07 07:26:09,121 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [730695945] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,122 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,122 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,122 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504622648] [2021-11-07 07:26:09,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:09,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,123 INFO L85 PathProgramCache]: Analyzing trace with hash -525401729, now seen corresponding path program 1 times [2021-11-07 07:26:09,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,124 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126812246] [2021-11-07 07:26:09,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,166 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,166 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126812246] [2021-11-07 07:26:09,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126812246] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,167 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,167 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,167 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059362447] [2021-11-07 07:26:09,168 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:09,168 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:09,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:09,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:09,169 INFO L87 Difference]: Start difference. First operand 1143 states and 1712 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,194 INFO L93 Difference]: Finished difference Result 1143 states and 1711 transitions. [2021-11-07 07:26:09,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1711 transitions. [2021-11-07 07:26:09,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1711 transitions. [2021-11-07 07:26:09,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:09,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:09,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1711 transitions. [2021-11-07 07:26:09,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:09,219 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-07 07:26:09,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1711 transitions. [2021-11-07 07:26:09,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:09,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4969378827646544) internal successors, (1711), 1142 states have internal predecessors, (1711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1711 transitions. [2021-11-07 07:26:09,247 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-07 07:26:09,247 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1711 transitions. [2021-11-07 07:26:09,247 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 07:26:09,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1711 transitions. [2021-11-07 07:26:09,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:09,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:09,257 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,257 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,257 INFO L791 eck$LassoCheckResult]: Stem: 12331#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12332#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12283#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12284#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 12552#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12508#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12473#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11980#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11981#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12402#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12403#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11495#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11496#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11694#L703-1 assume !(0 == ~M_E~0); 12010#L939-1 assume !(0 == ~T1_E~0); 12011#L944-1 assume !(0 == ~T2_E~0); 12102#L949-1 assume !(0 == ~T3_E~0); 12099#L954-1 assume !(0 == ~T4_E~0); 12100#L959-1 assume !(0 == ~T5_E~0); 12509#L964-1 assume !(0 == ~T6_E~0); 11835#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11836#L974-1 assume !(0 == ~T8_E~0); 12461#L979-1 assume !(0 == ~T9_E~0); 12462#L984-1 assume !(0 == ~E_M~0); 11992#L989-1 assume !(0 == ~E_1~0); 11993#L994-1 assume !(0 == ~E_2~0); 11882#L999-1 assume !(0 == ~E_3~0); 11883#L1004-1 assume !(0 == ~E_4~0); 11563#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 11564#L1014-1 assume !(0 == ~E_6~0); 11874#L1019-1 assume !(0 == ~E_7~0); 12409#L1024-1 assume !(0 == ~E_8~0); 11808#L1029-1 assume !(0 == ~E_9~0); 11809#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11896#L460 assume !(1 == ~m_pc~0); 11481#L460-2 is_master_triggered_~__retres1~0 := 0; 11480#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12375#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12608#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12088#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12089#L479 assume 1 == ~t1_pc~0; 12072#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12073#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12567#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11820#L1175 assume !(0 != activate_threads_~tmp___0~0); 11821#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11676#L498 assume !(1 == ~t2_pc~0); 11677#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 12070#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12071#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12439#L1183 assume !(0 != activate_threads_~tmp___1~0); 12365#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12366#L517 assume 1 == ~t3_pc~0; 12569#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12570#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12145#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 11853#L1191 assume !(0 != activate_threads_~tmp___2~0); 11854#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12418#L536 assume !(1 == ~t4_pc~0); 12134#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 12135#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12500#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12127#L1199 assume !(0 != activate_threads_~tmp___3~0); 12128#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12339#L555 assume 1 == ~t5_pc~0; 12340#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12410#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11592#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11593#L1207 assume !(0 != activate_threads_~tmp___4~0); 11695#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11600#L574 assume !(1 == ~t6_pc~0); 11601#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 12220#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11700#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 11701#L1215 assume !(0 != activate_threads_~tmp___5~0); 12433#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12592#L593 assume 1 == ~t7_pc~0; 12593#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11827#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12512#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12613#L1223 assume !(0 != activate_threads_~tmp___6~0); 12575#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11987#L612 assume 1 == ~t8_pc~0; 11988#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12392#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12254#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12255#L1231 assume !(0 != activate_threads_~tmp___7~0); 12222#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12223#L631 assume !(1 == ~t9_pc~0); 12240#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 11591#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11561#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 11562#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 12075#L1239-2 assume !(1 == ~M_E~0); 12441#L1047-1 assume !(1 == ~T1_E~0); 12215#L1052-1 assume !(1 == ~T2_E~0); 11516#L1057-1 assume !(1 == ~T3_E~0); 11517#L1062-1 assume !(1 == ~T4_E~0); 11792#L1067-1 assume !(1 == ~T5_E~0); 12091#L1072-1 assume !(1 == ~T6_E~0); 12092#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11690#L1082-1 assume !(1 == ~T8_E~0); 11691#L1087-1 assume !(1 == ~T9_E~0); 11487#L1092-1 assume !(1 == ~E_M~0); 11488#L1097-1 assume !(1 == ~E_1~0); 11518#L1102-1 assume !(1 == ~E_2~0); 12279#L1107-1 assume !(1 == ~E_3~0); 12218#L1112-1 assume !(1 == ~E_4~0); 12219#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12256#L1122-1 assume !(1 == ~E_6~0); 12146#L1127-1 assume !(1 == ~E_7~0); 11899#L1132-1 assume !(1 == ~E_8~0); 11900#L1137-1 assume !(1 == ~E_9~0); 12094#L1428-1 [2021-11-07 07:26:09,258 INFO L793 eck$LassoCheckResult]: Loop: 12094#L1428-1 assume !false; 12151#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 11729#L914 assume !false; 12213#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 12214#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11502#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 11503#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12436#L783 assume !(0 != eval_~tmp~0); 11885#L929 start_simulation_~kernel_st~0 := 2; 11886#L651-1 start_simulation_~kernel_st~0 := 3; 12278#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12187#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11762#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11485#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11486#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12108#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11565#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11566#L969-3 assume !(0 == ~T7_E~0); 11760#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11761#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12188#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12189#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11814#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11815#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12317#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11646#L1009-3 assume !(0 == ~E_5~0); 11647#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12174#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12175#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12158#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12109#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12110#L460-33 assume 1 == ~m_pc~0; 12147#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12148#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11903#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11493#L1167-33 assume !(0 != activate_threads_~tmp~1); 11494#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11842#L479-33 assume 1 == ~t1_pc~0; 11843#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11810#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11811#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12386#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12555#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11851#L498-33 assume !(1 == ~t2_pc~0); 11606#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 11607#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11733#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11734#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11712#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11713#L517-33 assume 1 == ~t3_pc~0; 12601#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12487#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12488#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12306#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12307#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11935#L536-33 assume !(1 == ~t4_pc~0); 11936#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 12003#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12004#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12196#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12466#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11540#L555-33 assume 1 == ~t5_pc~0; 11541#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12250#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11801#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11802#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12275#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11513#L574-33 assume !(1 == ~t6_pc~0); 11514#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 12478#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11816#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 11817#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12067#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11585#L593-33 assume 1 == ~t7_pc~0; 11586#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12028#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11688#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 11689#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12333#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12457#L612-33 assume 1 == ~t8_pc~0; 12581#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12546#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12547#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12393#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11686#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 11687#L631-33 assume !(1 == ~t9_pc~0); 12282#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 11631#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11632#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 11873#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 11735#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 11736#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11904#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12442#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12443#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11641#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11642#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12012#L1077-3 assume !(1 == ~T7_E~0); 11860#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11861#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11931#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12212#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12143#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12144#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12479#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11855#L1117-3 assume !(1 == ~E_5~0); 11856#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11905#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11906#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12292#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12269#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 11740#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11626#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 12270#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 12030#L1447 assume !(0 == start_simulation_~tmp~3); 12032#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 12285#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 11775#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 12293#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 11881#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11650#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 11651#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 12093#L1460 assume !(0 != start_simulation_~tmp___0~1); 12094#L1428-1 [2021-11-07 07:26:09,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,259 INFO L85 PathProgramCache]: Analyzing trace with hash -2006863506, now seen corresponding path program 1 times [2021-11-07 07:26:09,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,259 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072708570] [2021-11-07 07:26:09,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,320 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,321 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072708570] [2021-11-07 07:26:09,321 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2072708570] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,321 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,321 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,321 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199197787] [2021-11-07 07:26:09,322 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:09,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,323 INFO L85 PathProgramCache]: Analyzing trace with hash 1101128032, now seen corresponding path program 2 times [2021-11-07 07:26:09,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,324 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669174981] [2021-11-07 07:26:09,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,324 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,371 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669174981] [2021-11-07 07:26:09,371 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669174981] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,371 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096221184] [2021-11-07 07:26:09,373 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:09,375 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:09,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:09,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:09,376 INFO L87 Difference]: Start difference. First operand 1143 states and 1711 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,401 INFO L93 Difference]: Finished difference Result 1143 states and 1710 transitions. [2021-11-07 07:26:09,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1710 transitions. [2021-11-07 07:26:09,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1710 transitions. [2021-11-07 07:26:09,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:09,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:09,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1710 transitions. [2021-11-07 07:26:09,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:09,423 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-07 07:26:09,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1710 transitions. [2021-11-07 07:26:09,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:09,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4960629921259843) internal successors, (1710), 1142 states have internal predecessors, (1710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1710 transitions. [2021-11-07 07:26:09,449 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-07 07:26:09,449 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1710 transitions. [2021-11-07 07:26:09,449 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 07:26:09,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1710 transitions. [2021-11-07 07:26:09,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:09,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:09,458 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,458 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,459 INFO L791 eck$LassoCheckResult]: Stem: 14624#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14625#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14576#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14577#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 14845#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14801#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14766#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14273#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14274#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14695#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14696#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13788#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13789#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13987#L703-1 assume !(0 == ~M_E~0); 14303#L939-1 assume !(0 == ~T1_E~0); 14304#L944-1 assume !(0 == ~T2_E~0); 14395#L949-1 assume !(0 == ~T3_E~0); 14392#L954-1 assume !(0 == ~T4_E~0); 14393#L959-1 assume !(0 == ~T5_E~0); 14802#L964-1 assume !(0 == ~T6_E~0); 14128#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14129#L974-1 assume !(0 == ~T8_E~0); 14754#L979-1 assume !(0 == ~T9_E~0); 14755#L984-1 assume !(0 == ~E_M~0); 14285#L989-1 assume !(0 == ~E_1~0); 14286#L994-1 assume !(0 == ~E_2~0); 14175#L999-1 assume !(0 == ~E_3~0); 14176#L1004-1 assume !(0 == ~E_4~0); 13856#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13857#L1014-1 assume !(0 == ~E_6~0); 14167#L1019-1 assume !(0 == ~E_7~0); 14702#L1024-1 assume !(0 == ~E_8~0); 14101#L1029-1 assume !(0 == ~E_9~0); 14102#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14189#L460 assume !(1 == ~m_pc~0); 13774#L460-2 is_master_triggered_~__retres1~0 := 0; 13773#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14668#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14901#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14381#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14382#L479 assume 1 == ~t1_pc~0; 14365#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14366#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14860#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14113#L1175 assume !(0 != activate_threads_~tmp___0~0); 14114#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13969#L498 assume !(1 == ~t2_pc~0); 13970#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 14363#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14364#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14732#L1183 assume !(0 != activate_threads_~tmp___1~0); 14658#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14659#L517 assume 1 == ~t3_pc~0; 14862#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14863#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14438#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14146#L1191 assume !(0 != activate_threads_~tmp___2~0); 14147#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14711#L536 assume !(1 == ~t4_pc~0); 14427#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 14428#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14793#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14420#L1199 assume !(0 != activate_threads_~tmp___3~0); 14421#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14632#L555 assume 1 == ~t5_pc~0; 14633#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14703#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13885#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13886#L1207 assume !(0 != activate_threads_~tmp___4~0); 13988#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13893#L574 assume !(1 == ~t6_pc~0); 13894#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 14513#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13993#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 13994#L1215 assume !(0 != activate_threads_~tmp___5~0); 14726#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14885#L593 assume 1 == ~t7_pc~0; 14886#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14120#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14805#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14906#L1223 assume !(0 != activate_threads_~tmp___6~0); 14868#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14280#L612 assume 1 == ~t8_pc~0; 14281#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14685#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14547#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14548#L1231 assume !(0 != activate_threads_~tmp___7~0); 14515#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 14516#L631 assume !(1 == ~t9_pc~0); 14533#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 13884#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 13854#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 13855#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 14368#L1239-2 assume !(1 == ~M_E~0); 14734#L1047-1 assume !(1 == ~T1_E~0); 14508#L1052-1 assume !(1 == ~T2_E~0); 13809#L1057-1 assume !(1 == ~T3_E~0); 13810#L1062-1 assume !(1 == ~T4_E~0); 14085#L1067-1 assume !(1 == ~T5_E~0); 14384#L1072-1 assume !(1 == ~T6_E~0); 14385#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13983#L1082-1 assume !(1 == ~T8_E~0); 13984#L1087-1 assume !(1 == ~T9_E~0); 13780#L1092-1 assume !(1 == ~E_M~0); 13781#L1097-1 assume !(1 == ~E_1~0); 13811#L1102-1 assume !(1 == ~E_2~0); 14572#L1107-1 assume !(1 == ~E_3~0); 14511#L1112-1 assume !(1 == ~E_4~0); 14512#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14549#L1122-1 assume !(1 == ~E_6~0); 14439#L1127-1 assume !(1 == ~E_7~0); 14192#L1132-1 assume !(1 == ~E_8~0); 14193#L1137-1 assume !(1 == ~E_9~0); 14387#L1428-1 [2021-11-07 07:26:09,459 INFO L793 eck$LassoCheckResult]: Loop: 14387#L1428-1 assume !false; 14444#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 14022#L914 assume !false; 14506#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14507#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 13795#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 13796#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 14729#L783 assume !(0 != eval_~tmp~0); 14178#L929 start_simulation_~kernel_st~0 := 2; 14179#L651-1 start_simulation_~kernel_st~0 := 3; 14571#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14480#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14055#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13778#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13779#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14401#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13858#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13859#L969-3 assume !(0 == ~T7_E~0); 14053#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14054#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14481#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14482#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14107#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14108#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14610#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13939#L1009-3 assume !(0 == ~E_5~0); 13940#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14467#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14468#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14451#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14402#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14403#L460-33 assume 1 == ~m_pc~0; 14440#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 14441#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14196#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13786#L1167-33 assume !(0 != activate_threads_~tmp~1); 13787#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14135#L479-33 assume 1 == ~t1_pc~0; 14136#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14103#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14104#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14679#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14848#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14144#L498-33 assume 1 == ~t2_pc~0; 14145#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13900#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14026#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14027#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14005#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14006#L517-33 assume 1 == ~t3_pc~0; 14894#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14780#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14781#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 14599#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14600#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14228#L536-33 assume !(1 == ~t4_pc~0); 14229#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 14296#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14297#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 14489#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14759#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13833#L555-33 assume 1 == ~t5_pc~0; 13834#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14543#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14094#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 14095#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14568#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13806#L574-33 assume 1 == ~t6_pc~0; 13808#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14771#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14109#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 14110#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14360#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13878#L593-33 assume 1 == ~t7_pc~0; 13879#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 14321#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13981#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13982#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14626#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14750#L612-33 assume 1 == ~t8_pc~0; 14874#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14839#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14840#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14686#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13979#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13980#L631-33 assume 1 == ~t9_pc~0; 14800#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 13924#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 13925#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 14166#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 14028#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 14029#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14197#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14735#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14736#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13934#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13935#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14305#L1077-3 assume !(1 == ~T7_E~0); 14153#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14154#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14224#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14505#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14436#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14437#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14772#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14148#L1117-3 assume !(1 == ~E_5~0); 14149#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14198#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14199#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14585#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14562#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14033#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 13919#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 14563#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 14323#L1447 assume !(0 == start_simulation_~tmp~3); 14325#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 14578#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 14068#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 14586#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 14174#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13943#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 13944#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 14386#L1460 assume !(0 != start_simulation_~tmp___0~1); 14387#L1428-1 [2021-11-07 07:26:09,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,460 INFO L85 PathProgramCache]: Analyzing trace with hash 898809776, now seen corresponding path program 1 times [2021-11-07 07:26:09,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,461 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260866611] [2021-11-07 07:26:09,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,461 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,495 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,496 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260866611] [2021-11-07 07:26:09,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260866611] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,496 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,496 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,496 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930745135] [2021-11-07 07:26:09,497 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:09,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,497 INFO L85 PathProgramCache]: Analyzing trace with hash -446871101, now seen corresponding path program 1 times [2021-11-07 07:26:09,497 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571674342] [2021-11-07 07:26:09,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,498 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,551 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571674342] [2021-11-07 07:26:09,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571674342] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,551 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276344639] [2021-11-07 07:26:09,552 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:09,552 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:09,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:09,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:09,553 INFO L87 Difference]: Start difference. First operand 1143 states and 1710 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,578 INFO L93 Difference]: Finished difference Result 1143 states and 1709 transitions. [2021-11-07 07:26:09,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1709 transitions. [2021-11-07 07:26:09,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1709 transitions. [2021-11-07 07:26:09,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:09,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:09,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1709 transitions. [2021-11-07 07:26:09,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:09,627 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-07 07:26:09,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1709 transitions. [2021-11-07 07:26:09,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:09,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.495188101487314) internal successors, (1709), 1142 states have internal predecessors, (1709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1709 transitions. [2021-11-07 07:26:09,661 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-07 07:26:09,661 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1709 transitions. [2021-11-07 07:26:09,662 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 07:26:09,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1709 transitions. [2021-11-07 07:26:09,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:09,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:09,674 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,674 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,675 INFO L791 eck$LassoCheckResult]: Stem: 16917#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16918#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 16869#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16870#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 17138#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17094#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17059#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16566#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16567#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16988#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16989#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16081#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16082#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16280#L703-1 assume !(0 == ~M_E~0); 16596#L939-1 assume !(0 == ~T1_E~0); 16597#L944-1 assume !(0 == ~T2_E~0); 16688#L949-1 assume !(0 == ~T3_E~0); 16685#L954-1 assume !(0 == ~T4_E~0); 16686#L959-1 assume !(0 == ~T5_E~0); 17095#L964-1 assume !(0 == ~T6_E~0); 16421#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16422#L974-1 assume !(0 == ~T8_E~0); 17047#L979-1 assume !(0 == ~T9_E~0); 17048#L984-1 assume !(0 == ~E_M~0); 16578#L989-1 assume !(0 == ~E_1~0); 16579#L994-1 assume !(0 == ~E_2~0); 16468#L999-1 assume !(0 == ~E_3~0); 16469#L1004-1 assume !(0 == ~E_4~0); 16149#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 16150#L1014-1 assume !(0 == ~E_6~0); 16460#L1019-1 assume !(0 == ~E_7~0); 16995#L1024-1 assume !(0 == ~E_8~0); 16394#L1029-1 assume !(0 == ~E_9~0); 16395#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16482#L460 assume !(1 == ~m_pc~0); 16067#L460-2 is_master_triggered_~__retres1~0 := 0; 16066#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16961#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 17194#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16674#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16675#L479 assume 1 == ~t1_pc~0; 16658#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16659#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17153#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16406#L1175 assume !(0 != activate_threads_~tmp___0~0); 16407#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16262#L498 assume !(1 == ~t2_pc~0); 16263#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 16656#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16657#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17025#L1183 assume !(0 != activate_threads_~tmp___1~0); 16951#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16952#L517 assume 1 == ~t3_pc~0; 17155#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17156#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16731#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16439#L1191 assume !(0 != activate_threads_~tmp___2~0); 16440#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17004#L536 assume !(1 == ~t4_pc~0); 16720#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 16721#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17086#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16713#L1199 assume !(0 != activate_threads_~tmp___3~0); 16714#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16925#L555 assume 1 == ~t5_pc~0; 16926#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16996#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16178#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16179#L1207 assume !(0 != activate_threads_~tmp___4~0); 16281#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16186#L574 assume !(1 == ~t6_pc~0); 16187#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 16806#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16286#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16287#L1215 assume !(0 != activate_threads_~tmp___5~0); 17019#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17178#L593 assume 1 == ~t7_pc~0; 17179#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16413#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17098#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 17199#L1223 assume !(0 != activate_threads_~tmp___6~0); 17161#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16573#L612 assume 1 == ~t8_pc~0; 16574#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16978#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16840#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16841#L1231 assume !(0 != activate_threads_~tmp___7~0); 16808#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 16809#L631 assume !(1 == ~t9_pc~0); 16826#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 16177#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16147#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16148#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 16661#L1239-2 assume !(1 == ~M_E~0); 17027#L1047-1 assume !(1 == ~T1_E~0); 16801#L1052-1 assume !(1 == ~T2_E~0); 16102#L1057-1 assume !(1 == ~T3_E~0); 16103#L1062-1 assume !(1 == ~T4_E~0); 16378#L1067-1 assume !(1 == ~T5_E~0); 16677#L1072-1 assume !(1 == ~T6_E~0); 16678#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16276#L1082-1 assume !(1 == ~T8_E~0); 16277#L1087-1 assume !(1 == ~T9_E~0); 16073#L1092-1 assume !(1 == ~E_M~0); 16074#L1097-1 assume !(1 == ~E_1~0); 16104#L1102-1 assume !(1 == ~E_2~0); 16865#L1107-1 assume !(1 == ~E_3~0); 16804#L1112-1 assume !(1 == ~E_4~0); 16805#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 16842#L1122-1 assume !(1 == ~E_6~0); 16732#L1127-1 assume !(1 == ~E_7~0); 16485#L1132-1 assume !(1 == ~E_8~0); 16486#L1137-1 assume !(1 == ~E_9~0); 16680#L1428-1 [2021-11-07 07:26:09,675 INFO L793 eck$LassoCheckResult]: Loop: 16680#L1428-1 assume !false; 16737#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 16315#L914 assume !false; 16799#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16800#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16088#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 16089#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 17022#L783 assume !(0 != eval_~tmp~0); 16471#L929 start_simulation_~kernel_st~0 := 2; 16472#L651-1 start_simulation_~kernel_st~0 := 3; 16864#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16773#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16348#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16071#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16072#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16694#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16151#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16152#L969-3 assume !(0 == ~T7_E~0); 16346#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16347#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16774#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16775#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16400#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16401#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16903#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16232#L1009-3 assume !(0 == ~E_5~0); 16233#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16760#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16761#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16744#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16695#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16696#L460-33 assume 1 == ~m_pc~0; 16733#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16734#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16489#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16079#L1167-33 assume !(0 != activate_threads_~tmp~1); 16080#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16428#L479-33 assume 1 == ~t1_pc~0; 16429#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16396#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16397#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16972#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17141#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16437#L498-33 assume !(1 == ~t2_pc~0); 16192#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 16193#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16319#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16320#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16298#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16299#L517-33 assume 1 == ~t3_pc~0; 17187#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17073#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17074#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16892#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16893#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16521#L536-33 assume !(1 == ~t4_pc~0); 16522#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 16589#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16590#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16782#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17052#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16126#L555-33 assume !(1 == ~t5_pc~0); 16128#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 16836#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16387#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16388#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16861#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16099#L574-33 assume !(1 == ~t6_pc~0); 16100#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 17064#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16402#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16403#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16653#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16171#L593-33 assume 1 == ~t7_pc~0; 16172#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16614#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16274#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16275#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16919#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17043#L612-33 assume !(1 == ~t8_pc~0); 17168#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 17132#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17133#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16979#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 16272#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 16273#L631-33 assume !(1 == ~t9_pc~0); 16868#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 16217#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16218#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16459#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 16321#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 16322#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16490#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17028#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17029#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16227#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16228#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16598#L1077-3 assume !(1 == ~T7_E~0); 16446#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16447#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16517#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16798#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16729#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16730#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17065#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16441#L1117-3 assume !(1 == ~E_5~0); 16442#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16491#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16492#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16878#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16855#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16326#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16212#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 16856#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 16616#L1447 assume !(0 == start_simulation_~tmp~3); 16618#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 16871#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 16361#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 16879#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 16467#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16236#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 16237#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 16679#L1460 assume !(0 != start_simulation_~tmp___0~1); 16680#L1428-1 [2021-11-07 07:26:09,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1362763474, now seen corresponding path program 1 times [2021-11-07 07:26:09,677 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,677 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083140223] [2021-11-07 07:26:09,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,677 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,712 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083140223] [2021-11-07 07:26:09,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083140223] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,713 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542952717] [2021-11-07 07:26:09,714 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:09,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1645751262, now seen corresponding path program 2 times [2021-11-07 07:26:09,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,719 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123191465] [2021-11-07 07:26:09,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,771 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,772 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123191465] [2021-11-07 07:26:09,774 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123191465] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,774 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,775 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:09,775 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037281124] [2021-11-07 07:26:09,775 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:09,776 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:09,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:09,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:09,777 INFO L87 Difference]: Start difference. First operand 1143 states and 1709 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,806 INFO L93 Difference]: Finished difference Result 1143 states and 1708 transitions. [2021-11-07 07:26:09,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1708 transitions. [2021-11-07 07:26:09,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1708 transitions. [2021-11-07 07:26:09,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:09,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:09,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1708 transitions. [2021-11-07 07:26:09,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:09,828 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-07 07:26:09,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1708 transitions. [2021-11-07 07:26:09,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:09,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4943132108486439) internal successors, (1708), 1142 states have internal predecessors, (1708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1708 transitions. [2021-11-07 07:26:09,859 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-07 07:26:09,859 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1708 transitions. [2021-11-07 07:26:09,859 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 07:26:09,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1708 transitions. [2021-11-07 07:26:09,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:09,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:09,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:09,867 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,868 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:09,868 INFO L791 eck$LassoCheckResult]: Stem: 19212#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19213#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19164#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19165#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 19433#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19389#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19354#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18861#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18862#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19283#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19284#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18376#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18377#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18575#L703-1 assume !(0 == ~M_E~0); 18891#L939-1 assume !(0 == ~T1_E~0); 18892#L944-1 assume !(0 == ~T2_E~0); 18983#L949-1 assume !(0 == ~T3_E~0); 18980#L954-1 assume !(0 == ~T4_E~0); 18981#L959-1 assume !(0 == ~T5_E~0); 19390#L964-1 assume !(0 == ~T6_E~0); 18716#L969-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18717#L974-1 assume !(0 == ~T8_E~0); 19342#L979-1 assume !(0 == ~T9_E~0); 19343#L984-1 assume !(0 == ~E_M~0); 18873#L989-1 assume !(0 == ~E_1~0); 18874#L994-1 assume !(0 == ~E_2~0); 18763#L999-1 assume !(0 == ~E_3~0); 18764#L1004-1 assume !(0 == ~E_4~0); 18444#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 18445#L1014-1 assume !(0 == ~E_6~0); 18755#L1019-1 assume !(0 == ~E_7~0); 19290#L1024-1 assume !(0 == ~E_8~0); 18689#L1029-1 assume !(0 == ~E_9~0); 18690#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18777#L460 assume !(1 == ~m_pc~0); 18362#L460-2 is_master_triggered_~__retres1~0 := 0; 18361#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19256#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 19489#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18969#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18970#L479 assume 1 == ~t1_pc~0; 18953#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18954#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19448#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18701#L1175 assume !(0 != activate_threads_~tmp___0~0); 18702#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18557#L498 assume !(1 == ~t2_pc~0); 18558#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 18951#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18952#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 19320#L1183 assume !(0 != activate_threads_~tmp___1~0); 19246#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19247#L517 assume 1 == ~t3_pc~0; 19450#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 19451#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19026#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 18734#L1191 assume !(0 != activate_threads_~tmp___2~0); 18735#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19299#L536 assume !(1 == ~t4_pc~0); 19015#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 19016#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19381#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19008#L1199 assume !(0 != activate_threads_~tmp___3~0); 19009#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19220#L555 assume 1 == ~t5_pc~0; 19221#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19291#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18473#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18474#L1207 assume !(0 != activate_threads_~tmp___4~0); 18576#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18481#L574 assume !(1 == ~t6_pc~0); 18482#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 19101#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18581#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18582#L1215 assume !(0 != activate_threads_~tmp___5~0); 19314#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19473#L593 assume 1 == ~t7_pc~0; 19474#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18708#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19393#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 19494#L1223 assume !(0 != activate_threads_~tmp___6~0); 19456#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18868#L612 assume 1 == ~t8_pc~0; 18869#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19273#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19135#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 19136#L1231 assume !(0 != activate_threads_~tmp___7~0); 19103#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 19104#L631 assume !(1 == ~t9_pc~0); 19121#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 18472#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18442#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 18443#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 18956#L1239-2 assume !(1 == ~M_E~0); 19322#L1047-1 assume !(1 == ~T1_E~0); 19096#L1052-1 assume !(1 == ~T2_E~0); 18397#L1057-1 assume !(1 == ~T3_E~0); 18398#L1062-1 assume !(1 == ~T4_E~0); 18673#L1067-1 assume !(1 == ~T5_E~0); 18972#L1072-1 assume !(1 == ~T6_E~0); 18973#L1077-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18571#L1082-1 assume !(1 == ~T8_E~0); 18572#L1087-1 assume !(1 == ~T9_E~0); 18368#L1092-1 assume !(1 == ~E_M~0); 18369#L1097-1 assume !(1 == ~E_1~0); 18399#L1102-1 assume !(1 == ~E_2~0); 19160#L1107-1 assume !(1 == ~E_3~0); 19099#L1112-1 assume !(1 == ~E_4~0); 19100#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19137#L1122-1 assume !(1 == ~E_6~0); 19027#L1127-1 assume !(1 == ~E_7~0); 18780#L1132-1 assume !(1 == ~E_8~0); 18781#L1137-1 assume !(1 == ~E_9~0); 18975#L1428-1 [2021-11-07 07:26:09,869 INFO L793 eck$LassoCheckResult]: Loop: 18975#L1428-1 assume !false; 19032#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 18610#L914 assume !false; 19094#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 19095#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18383#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 18384#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 19317#L783 assume !(0 != eval_~tmp~0); 18766#L929 start_simulation_~kernel_st~0 := 2; 18767#L651-1 start_simulation_~kernel_st~0 := 3; 19159#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 19068#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18643#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18366#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18367#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18989#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18446#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18447#L969-3 assume !(0 == ~T7_E~0); 18641#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18642#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19069#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19070#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18695#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18696#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19198#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18527#L1009-3 assume !(0 == ~E_5~0); 18528#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19055#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19056#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19039#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18990#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18991#L460-33 assume 1 == ~m_pc~0; 19028#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 19029#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18784#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18374#L1167-33 assume !(0 != activate_threads_~tmp~1); 18375#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18723#L479-33 assume 1 == ~t1_pc~0; 18724#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18691#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18692#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 19267#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19436#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18732#L498-33 assume !(1 == ~t2_pc~0); 18487#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 18488#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18614#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 18615#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18593#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18594#L517-33 assume 1 == ~t3_pc~0; 19482#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 19368#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19369#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19187#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19188#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18816#L536-33 assume !(1 == ~t4_pc~0); 18817#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 18884#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18885#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19077#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19347#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18421#L555-33 assume 1 == ~t5_pc~0; 18422#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19131#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18682#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18683#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19156#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18394#L574-33 assume !(1 == ~t6_pc~0); 18395#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 19359#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18697#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18698#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 18948#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18466#L593-33 assume 1 == ~t7_pc~0; 18467#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18909#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18569#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18570#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19214#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19338#L612-33 assume 1 == ~t8_pc~0; 19462#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19427#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19428#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 19274#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18567#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 18568#L631-33 assume !(1 == ~t9_pc~0); 19163#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 18512#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18513#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 18754#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 18616#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 18617#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18785#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19323#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19324#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18522#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18523#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18893#L1077-3 assume !(1 == ~T7_E~0); 18741#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18742#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18812#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19093#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19024#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19025#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19360#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18736#L1117-3 assume !(1 == ~E_5~0); 18737#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18786#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18787#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19173#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19150#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 18621#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18507#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 19151#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 18911#L1447 assume !(0 == start_simulation_~tmp~3); 18913#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 19166#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 18656#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 19174#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 18762#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18531#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 18532#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 18974#L1460 assume !(0 != start_simulation_~tmp___0~1); 18975#L1428-1 [2021-11-07 07:26:09,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,870 INFO L85 PathProgramCache]: Analyzing trace with hash 503945200, now seen corresponding path program 1 times [2021-11-07 07:26:09,870 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,870 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454038354] [2021-11-07 07:26:09,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,871 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,921 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454038354] [2021-11-07 07:26:09,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454038354] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,921 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:26:09,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914498580] [2021-11-07 07:26:09,922 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:09,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:09,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1101128032, now seen corresponding path program 3 times [2021-11-07 07:26:09,923 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:09,923 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126452665] [2021-11-07 07:26:09,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:09,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:09,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:09,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:09,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:09,963 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126452665] [2021-11-07 07:26:09,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126452665] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:09,963 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:09,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:09,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820985863] [2021-11-07 07:26:09,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:09,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:09,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:09,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:09,965 INFO L87 Difference]: Start difference. First operand 1143 states and 1708 transitions. cyclomatic complexity: 566 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 2 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:09,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:09,996 INFO L93 Difference]: Finished difference Result 1143 states and 1703 transitions. [2021-11-07 07:26:09,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:09,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1703 transitions. [2021-11-07 07:26:10,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:10,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1703 transitions. [2021-11-07 07:26:10,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:10,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:10,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1703 transitions. [2021-11-07 07:26:10,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:10,019 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-07 07:26:10,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1703 transitions. [2021-11-07 07:26:10,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:10,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4899387576552932) internal successors, (1703), 1142 states have internal predecessors, (1703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:10,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1703 transitions. [2021-11-07 07:26:10,046 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-07 07:26:10,046 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1703 transitions. [2021-11-07 07:26:10,046 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 07:26:10,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1703 transitions. [2021-11-07 07:26:10,051 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:10,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:10,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:10,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,054 INFO L791 eck$LassoCheckResult]: Stem: 21505#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 21506#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21457#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21458#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 21726#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21682#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21647#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21154#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21155#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21578#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21579#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20669#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20670#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20868#L703-1 assume !(0 == ~M_E~0); 21185#L939-1 assume !(0 == ~T1_E~0); 21186#L944-1 assume !(0 == ~T2_E~0); 21276#L949-1 assume !(0 == ~T3_E~0); 21274#L954-1 assume !(0 == ~T4_E~0); 21275#L959-1 assume !(0 == ~T5_E~0); 21683#L964-1 assume !(0 == ~T6_E~0); 21009#L969-1 assume !(0 == ~T7_E~0); 21010#L974-1 assume !(0 == ~T8_E~0); 21635#L979-1 assume !(0 == ~T9_E~0); 21636#L984-1 assume !(0 == ~E_M~0); 21166#L989-1 assume !(0 == ~E_1~0); 21167#L994-1 assume !(0 == ~E_2~0); 21056#L999-1 assume !(0 == ~E_3~0); 21057#L1004-1 assume !(0 == ~E_4~0); 20737#L1009-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20738#L1014-1 assume !(0 == ~E_6~0); 21048#L1019-1 assume !(0 == ~E_7~0); 21583#L1024-1 assume !(0 == ~E_8~0); 20982#L1029-1 assume !(0 == ~E_9~0); 20983#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21070#L460 assume !(1 == ~m_pc~0); 20655#L460-2 is_master_triggered_~__retres1~0 := 0; 20654#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21549#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21782#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21262#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21263#L479 assume 1 == ~t1_pc~0; 21246#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21247#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21741#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20994#L1175 assume !(0 != activate_threads_~tmp___0~0); 20995#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20850#L498 assume !(1 == ~t2_pc~0); 20851#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 21244#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21245#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21613#L1183 assume !(0 != activate_threads_~tmp___1~0); 21540#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21541#L517 assume 1 == ~t3_pc~0; 21745#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 21746#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21319#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21027#L1191 assume !(0 != activate_threads_~tmp___2~0); 21028#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21592#L536 assume !(1 == ~t4_pc~0); 21308#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 21309#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21674#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21301#L1199 assume !(0 != activate_threads_~tmp___3~0); 21302#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21515#L555 assume 1 == ~t5_pc~0; 21516#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21584#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20766#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 20767#L1207 assume !(0 != activate_threads_~tmp___4~0); 20869#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20774#L574 assume !(1 == ~t6_pc~0); 20775#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 21394#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20874#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20875#L1215 assume !(0 != activate_threads_~tmp___5~0); 21607#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21766#L593 assume 1 == ~t7_pc~0; 21767#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21001#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21686#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21787#L1223 assume !(0 != activate_threads_~tmp___6~0); 21749#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21161#L612 assume 1 == ~t8_pc~0; 21162#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21566#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21428#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21429#L1231 assume !(0 != activate_threads_~tmp___7~0); 21396#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21397#L631 assume !(1 == ~t9_pc~0); 21414#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 20765#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20735#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20736#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 21249#L1239-2 assume !(1 == ~M_E~0); 21615#L1047-1 assume !(1 == ~T1_E~0); 21389#L1052-1 assume !(1 == ~T2_E~0); 20690#L1057-1 assume !(1 == ~T3_E~0); 20691#L1062-1 assume !(1 == ~T4_E~0); 20966#L1067-1 assume !(1 == ~T5_E~0); 21265#L1072-1 assume !(1 == ~T6_E~0); 21266#L1077-1 assume !(1 == ~T7_E~0); 20864#L1082-1 assume !(1 == ~T8_E~0); 20865#L1087-1 assume !(1 == ~T9_E~0); 20661#L1092-1 assume !(1 == ~E_M~0); 20662#L1097-1 assume !(1 == ~E_1~0); 20692#L1102-1 assume !(1 == ~E_2~0); 21453#L1107-1 assume !(1 == ~E_3~0); 21392#L1112-1 assume !(1 == ~E_4~0); 21393#L1117-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21430#L1122-1 assume !(1 == ~E_6~0); 21320#L1127-1 assume !(1 == ~E_7~0); 21073#L1132-1 assume !(1 == ~E_8~0); 21074#L1137-1 assume !(1 == ~E_9~0); 21268#L1428-1 [2021-11-07 07:26:10,054 INFO L793 eck$LassoCheckResult]: Loop: 21268#L1428-1 assume !false; 21325#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 20903#L914 assume !false; 21387#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 21388#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20676#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 20677#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 21610#L783 assume !(0 != eval_~tmp~0); 21059#L929 start_simulation_~kernel_st~0 := 2; 21060#L651-1 start_simulation_~kernel_st~0 := 3; 21452#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21361#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20936#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20659#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20660#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21282#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20739#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20740#L969-3 assume !(0 == ~T7_E~0); 20934#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20935#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21362#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21363#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20988#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20989#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21491#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20820#L1009-3 assume !(0 == ~E_5~0); 20821#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21348#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21349#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21332#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21283#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21284#L460-33 assume 1 == ~m_pc~0; 21321#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 21322#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21077#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20667#L1167-33 assume !(0 != activate_threads_~tmp~1); 20668#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21017#L479-33 assume 1 == ~t1_pc~0; 21018#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 20984#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20985#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21560#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21729#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21025#L498-33 assume 1 == ~t2_pc~0; 21026#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20781#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20909#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 20910#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20886#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20887#L517-33 assume !(1 == ~t3_pc~0); 21776#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 21661#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21662#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21480#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21481#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21109#L536-33 assume !(1 == ~t4_pc~0); 21110#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 21177#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21178#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21370#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21640#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20714#L555-33 assume 1 == ~t5_pc~0; 20715#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21424#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20975#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 20976#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21449#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20687#L574-33 assume !(1 == ~t6_pc~0); 20688#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 21652#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20990#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20991#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21241#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20759#L593-33 assume 1 == ~t7_pc~0; 20760#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21203#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20862#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20863#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21507#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21631#L612-33 assume 1 == ~t8_pc~0; 21755#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21720#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21721#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21567#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 20855#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 20856#L631-33 assume 1 == ~t9_pc~0; 21681#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 20803#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20804#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21045#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 20907#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 20908#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21078#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21616#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21617#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20815#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20816#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21184#L1077-3 assume !(1 == ~T7_E~0); 21034#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21035#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21105#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21386#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21317#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21318#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21653#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21029#L1117-3 assume !(1 == ~E_5~0); 21030#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21079#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21080#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21466#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21443#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 20911#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20797#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 21444#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 21204#L1447 assume !(0 == start_simulation_~tmp~3); 21206#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 21459#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 20949#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 21467#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 21055#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20824#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 20825#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 21267#L1460 assume !(0 != start_simulation_~tmp___0~1); 21268#L1428-1 [2021-11-07 07:26:10,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,055 INFO L85 PathProgramCache]: Analyzing trace with hash -966369804, now seen corresponding path program 1 times [2021-11-07 07:26:10,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,055 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642525142] [2021-11-07 07:26:10,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,113 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,114 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642525142] [2021-11-07 07:26:10,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642525142] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,114 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,114 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:26:10,114 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653243685] [2021-11-07 07:26:10,115 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:10,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,115 INFO L85 PathProgramCache]: Analyzing trace with hash 1227999041, now seen corresponding path program 1 times [2021-11-07 07:26:10,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885068644] [2021-11-07 07:26:10,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,116 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,155 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885068644] [2021-11-07 07:26:10,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885068644] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,155 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:10,156 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616109008] [2021-11-07 07:26:10,156 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:10,156 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:10,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:10,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:10,157 INFO L87 Difference]: Start difference. First operand 1143 states and 1703 transitions. cyclomatic complexity: 561 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 2 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:10,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:10,220 INFO L93 Difference]: Finished difference Result 1143 states and 1686 transitions. [2021-11-07 07:26:10,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:10,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1143 states and 1686 transitions. [2021-11-07 07:26:10,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:10,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1143 states to 1143 states and 1686 transitions. [2021-11-07 07:26:10,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1143 [2021-11-07 07:26:10,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1143 [2021-11-07 07:26:10,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1143 states and 1686 transitions. [2021-11-07 07:26:10,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:10,243 INFO L681 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-07 07:26:10,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states and 1686 transitions. [2021-11-07 07:26:10,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1143. [2021-11-07 07:26:10,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1143 states, 1143 states have (on average 1.4750656167979002) internal successors, (1686), 1142 states have internal predecessors, (1686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:10,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1143 states to 1143 states and 1686 transitions. [2021-11-07 07:26:10,269 INFO L704 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-07 07:26:10,269 INFO L587 BuchiCegarLoop]: Abstraction has 1143 states and 1686 transitions. [2021-11-07 07:26:10,269 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 07:26:10,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1143 states and 1686 transitions. [2021-11-07 07:26:10,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1020 [2021-11-07 07:26:10,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:10,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:10,276 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,276 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,277 INFO L791 eck$LassoCheckResult]: Stem: 23798#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23799#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23750#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23751#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 24019#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23975#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23940#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23444#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23445#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23871#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23872#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22962#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22963#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23160#L703-1 assume !(0 == ~M_E~0); 23476#L939-1 assume !(0 == ~T1_E~0); 23477#L944-1 assume !(0 == ~T2_E~0); 23567#L949-1 assume !(0 == ~T3_E~0); 23565#L954-1 assume !(0 == ~T4_E~0); 23566#L959-1 assume !(0 == ~T5_E~0); 23976#L964-1 assume !(0 == ~T6_E~0); 23299#L969-1 assume !(0 == ~T7_E~0); 23300#L974-1 assume !(0 == ~T8_E~0); 23928#L979-1 assume !(0 == ~T9_E~0); 23929#L984-1 assume !(0 == ~E_M~0); 23456#L989-1 assume !(0 == ~E_1~0); 23457#L994-1 assume !(0 == ~E_2~0); 23345#L999-1 assume !(0 == ~E_3~0); 23346#L1004-1 assume !(0 == ~E_4~0); 23028#L1009-1 assume !(0 == ~E_5~0); 23029#L1014-1 assume !(0 == ~E_6~0); 23341#L1019-1 assume !(0 == ~E_7~0); 23876#L1024-1 assume !(0 == ~E_8~0); 23273#L1029-1 assume !(0 == ~E_9~0); 23274#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23359#L460 assume !(1 == ~m_pc~0); 22951#L460-2 is_master_triggered_~__retres1~0 := 0; 22950#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23842#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 24075#L1167 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23553#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23554#L479 assume 1 == ~t1_pc~0; 23537#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23538#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24034#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23285#L1175 assume !(0 != activate_threads_~tmp___0~0); 23286#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23142#L498 assume !(1 == ~t2_pc~0); 23143#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 23535#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23536#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23906#L1183 assume !(0 != activate_threads_~tmp___1~0); 23833#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23834#L517 assume 1 == ~t3_pc~0; 24038#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 24039#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23610#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23317#L1191 assume !(0 != activate_threads_~tmp___2~0); 23318#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23887#L536 assume !(1 == ~t4_pc~0); 23599#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 23600#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23967#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23592#L1199 assume !(0 != activate_threads_~tmp___3~0); 23593#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23808#L555 assume !(1 == ~t5_pc~0); 23810#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 23877#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23057#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23058#L1207 assume !(0 != activate_threads_~tmp___4~0); 23161#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23066#L574 assume !(1 == ~t6_pc~0); 23067#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 23687#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23166#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23167#L1215 assume !(0 != activate_threads_~tmp___5~0); 23902#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24059#L593 assume 1 == ~t7_pc~0; 24060#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23292#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23979#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24080#L1223 assume !(0 != activate_threads_~tmp___6~0); 24042#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23451#L612 assume 1 == ~t8_pc~0; 23452#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 23859#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23721#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 23722#L1231 assume !(0 != activate_threads_~tmp___7~0); 23691#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 23692#L631 assume !(1 == ~t9_pc~0); 23707#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 23056#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23026#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23027#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 23540#L1239-2 assume !(1 == ~M_E~0); 23908#L1047-1 assume !(1 == ~T1_E~0); 23682#L1052-1 assume !(1 == ~T2_E~0); 22983#L1057-1 assume !(1 == ~T3_E~0); 22984#L1062-1 assume !(1 == ~T4_E~0); 23258#L1067-1 assume !(1 == ~T5_E~0); 23556#L1072-1 assume !(1 == ~T6_E~0); 23557#L1077-1 assume !(1 == ~T7_E~0); 23156#L1082-1 assume !(1 == ~T8_E~0); 23157#L1087-1 assume !(1 == ~T9_E~0); 22958#L1092-1 assume !(1 == ~E_M~0); 22959#L1097-1 assume !(1 == ~E_1~0); 22985#L1102-1 assume !(1 == ~E_2~0); 23746#L1107-1 assume !(1 == ~E_3~0); 23685#L1112-1 assume !(1 == ~E_4~0); 23686#L1117-1 assume !(1 == ~E_5~0); 23723#L1122-1 assume !(1 == ~E_6~0); 23611#L1127-1 assume !(1 == ~E_7~0); 23364#L1132-1 assume !(1 == ~E_8~0); 23365#L1137-1 assume !(1 == ~E_9~0); 23559#L1428-1 [2021-11-07 07:26:10,277 INFO L793 eck$LassoCheckResult]: Loop: 23559#L1428-1 assume !false; 23616#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 23195#L914 assume !false; 23680#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23681#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 22969#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 22970#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 23903#L783 assume !(0 != eval_~tmp~0); 23348#L929 start_simulation_~kernel_st~0 := 2; 23349#L651-1 start_simulation_~kernel_st~0 := 3; 23745#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23654#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23228#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22952#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22953#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23573#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23030#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23031#L969-3 assume !(0 == ~T7_E~0); 23226#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23227#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23655#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23656#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23279#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23280#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23784#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23112#L1009-3 assume !(0 == ~E_5~0); 23113#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23640#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23641#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23623#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23574#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23575#L460-33 assume 1 == ~m_pc~0; 23613#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 23614#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23366#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22960#L1167-33 assume !(0 != activate_threads_~tmp~1); 22961#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23307#L479-33 assume 1 == ~t1_pc~0; 23308#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23275#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23276#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23853#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24022#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23315#L498-33 assume !(1 == ~t2_pc~0); 23072#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 23073#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23201#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23202#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23178#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23179#L517-33 assume 1 == ~t3_pc~0; 24068#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23954#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23955#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23773#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23774#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23399#L536-33 assume !(1 == ~t4_pc~0); 23400#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 23468#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23469#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23663#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23933#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23003#L555-33 assume !(1 == ~t5_pc~0); 23005#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 23717#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23266#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23267#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23742#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22975#L574-33 assume !(1 == ~t6_pc~0); 22976#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 23945#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23281#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23282#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23532#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23048#L593-33 assume 1 == ~t7_pc~0; 23049#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23489#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23154#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23155#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23800#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23924#L612-33 assume 1 == ~t8_pc~0; 24048#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 24013#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24014#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 23860#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 23150#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 23151#L631-33 assume !(1 == ~t9_pc~0); 23749#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 23097#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23098#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23334#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 23199#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 23200#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23367#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23909#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23910#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23107#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23108#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23475#L1077-3 assume !(1 == ~T7_E~0); 23323#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23324#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23395#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23679#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23608#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23609#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23946#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23319#L1117-3 assume !(1 == ~E_5~0); 23320#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23368#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23369#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23759#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23736#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23203#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 23089#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 23737#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 23495#L1447 assume !(0 == start_simulation_~tmp~3); 23497#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 23752#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 23241#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 23760#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 23344#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23116#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 23117#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 23558#L1460 assume !(0 != start_simulation_~tmp___0~1); 23559#L1428-1 [2021-11-07 07:26:10,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1914803911, now seen corresponding path program 1 times [2021-11-07 07:26:10,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,278 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352332684] [2021-11-07 07:26:10,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,340 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,340 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352332684] [2021-11-07 07:26:10,340 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352332684] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,340 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,340 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:10,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257743342] [2021-11-07 07:26:10,341 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:10,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1374113345, now seen corresponding path program 1 times [2021-11-07 07:26:10,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,342 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727129193] [2021-11-07 07:26:10,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,384 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,384 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727129193] [2021-11-07 07:26:10,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727129193] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,384 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,385 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:10,385 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813068625] [2021-11-07 07:26:10,385 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:10,385 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:10,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:26:10,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:26:10,386 INFO L87 Difference]: Start difference. First operand 1143 states and 1686 transitions. cyclomatic complexity: 544 Second operand has 5 states, 5 states have (on average 22.6) internal successors, (113), 5 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:10,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:10,690 INFO L93 Difference]: Finished difference Result 3244 states and 4755 transitions. [2021-11-07 07:26:10,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:26:10,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3244 states and 4755 transitions. [2021-11-07 07:26:10,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2952 [2021-11-07 07:26:10,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3244 states to 3244 states and 4755 transitions. [2021-11-07 07:26:10,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3244 [2021-11-07 07:26:10,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3244 [2021-11-07 07:26:10,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3244 states and 4755 transitions. [2021-11-07 07:26:10,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:10,747 INFO L681 BuchiCegarLoop]: Abstraction has 3244 states and 4755 transitions. [2021-11-07 07:26:10,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3244 states and 4755 transitions. [2021-11-07 07:26:10,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3244 to 1182. [2021-11-07 07:26:10,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1182 states, 1182 states have (on average 1.4593908629441625) internal successors, (1725), 1181 states have internal predecessors, (1725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:10,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1182 states to 1182 states and 1725 transitions. [2021-11-07 07:26:10,788 INFO L704 BuchiCegarLoop]: Abstraction has 1182 states and 1725 transitions. [2021-11-07 07:26:10,788 INFO L587 BuchiCegarLoop]: Abstraction has 1182 states and 1725 transitions. [2021-11-07 07:26:10,788 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 07:26:10,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1182 states and 1725 transitions. [2021-11-07 07:26:10,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2021-11-07 07:26:10,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:10,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:10,796 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,796 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:10,796 INFO L791 eck$LassoCheckResult]: Stem: 28207#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 28208#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28158#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28159#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 28441#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28394#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28358#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27851#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27852#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28285#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28286#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27364#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27365#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27562#L703-1 assume !(0 == ~M_E~0); 27881#L939-1 assume !(0 == ~T1_E~0); 27882#L944-1 assume !(0 == ~T2_E~0); 27973#L949-1 assume !(0 == ~T3_E~0); 27971#L954-1 assume !(0 == ~T4_E~0); 27972#L959-1 assume !(0 == ~T5_E~0); 28395#L964-1 assume !(0 == ~T6_E~0); 27703#L969-1 assume !(0 == ~T7_E~0); 27704#L974-1 assume !(0 == ~T8_E~0); 28348#L979-1 assume !(0 == ~T9_E~0); 28349#L984-1 assume !(0 == ~E_M~0); 27863#L989-1 assume !(0 == ~E_1~0); 27864#L994-1 assume !(0 == ~E_2~0); 27749#L999-1 assume !(0 == ~E_3~0); 27750#L1004-1 assume !(0 == ~E_4~0); 27430#L1009-1 assume !(0 == ~E_5~0); 27431#L1014-1 assume !(0 == ~E_6~0); 27745#L1019-1 assume !(0 == ~E_7~0); 28290#L1024-1 assume !(0 == ~E_8~0); 27675#L1029-1 assume !(0 == ~E_9~0); 27676#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27765#L460 assume !(1 == ~m_pc~0); 27353#L460-2 is_master_triggered_~__retres1~0 := 0; 28255#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28256#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 28504#L1167 assume !(0 != activate_threads_~tmp~1); 27959#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27960#L479 assume 1 == ~t1_pc~0; 27943#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27944#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28456#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27688#L1175 assume !(0 != activate_threads_~tmp___0~0); 27689#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27544#L498 assume !(1 == ~t2_pc~0); 27545#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 27941#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27942#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 28322#L1183 assume !(0 != activate_threads_~tmp___1~0); 28246#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28247#L517 assume 1 == ~t3_pc~0; 28463#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 28464#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28016#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 27721#L1191 assume !(0 != activate_threads_~tmp___2~0); 27722#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28301#L536 assume !(1 == ~t4_pc~0); 28005#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 28006#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28386#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27998#L1199 assume !(0 != activate_threads_~tmp___3~0); 27999#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28221#L555 assume !(1 == ~t5_pc~0); 28223#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 28291#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27461#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27462#L1207 assume !(0 != activate_threads_~tmp___4~0); 27565#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 27468#L574 assume !(1 == ~t6_pc~0); 27469#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 28094#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27568#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27569#L1215 assume !(0 != activate_threads_~tmp___5~0); 28318#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28487#L593 assume 1 == ~t7_pc~0; 28488#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 27696#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28400#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28512#L1223 assume !(0 != activate_threads_~tmp___6~0); 28466#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 27856#L612 assume 1 == ~t8_pc~0; 27857#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 28273#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28130#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28131#L1231 assume !(0 != activate_threads_~tmp___7~0); 28098#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28099#L631 assume !(1 == ~t9_pc~0); 28114#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 27458#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 27428#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 27429#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 27946#L1239-2 assume !(1 == ~M_E~0); 28324#L1047-1 assume !(1 == ~T1_E~0); 28089#L1052-1 assume !(1 == ~T2_E~0); 27385#L1057-1 assume !(1 == ~T3_E~0); 27386#L1062-1 assume !(1 == ~T4_E~0); 27660#L1067-1 assume !(1 == ~T5_E~0); 27962#L1072-1 assume !(1 == ~T6_E~0); 27963#L1077-1 assume !(1 == ~T7_E~0); 27558#L1082-1 assume !(1 == ~T8_E~0); 27559#L1087-1 assume !(1 == ~T9_E~0); 27360#L1092-1 assume !(1 == ~E_M~0); 27361#L1097-1 assume !(1 == ~E_1~0); 27387#L1102-1 assume !(1 == ~E_2~0); 28154#L1107-1 assume !(1 == ~E_3~0); 28092#L1112-1 assume !(1 == ~E_4~0); 28093#L1117-1 assume !(1 == ~E_5~0); 28132#L1122-1 assume !(1 == ~E_6~0); 28017#L1127-1 assume !(1 == ~E_7~0); 27768#L1132-1 assume !(1 == ~E_8~0); 27769#L1137-1 assume !(1 == ~E_9~0); 27965#L1428-1 [2021-11-07 07:26:10,797 INFO L793 eck$LassoCheckResult]: Loop: 27965#L1428-1 assume !false; 28022#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 27597#L914 assume !false; 28087#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 28088#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27373#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 27374#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 28319#L783 assume !(0 != eval_~tmp~0); 27752#L929 start_simulation_~kernel_st~0 := 2; 27753#L651-1 start_simulation_~kernel_st~0 := 3; 28153#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28060#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27633#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27354#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27355#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27979#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27432#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27433#L969-3 assume !(0 == ~T7_E~0); 27628#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27629#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28061#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28062#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27681#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27682#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28193#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27514#L1009-3 assume !(0 == ~E_5~0); 27515#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28046#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28047#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28029#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27980#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27981#L460-33 assume 1 == ~m_pc~0; 28018#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 28019#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27770#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27771#L1167-33 assume !(0 != activate_threads_~tmp~1); 27363#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27710#L479-33 assume !(1 == ~t1_pc~0); 27712#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 27677#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27678#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 28267#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28443#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27719#L498-33 assume !(1 == ~t2_pc~0); 27474#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 27475#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27601#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 27602#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27580#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27581#L517-33 assume 1 == ~t3_pc~0; 28496#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 28372#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28373#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 28182#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28183#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27804#L536-33 assume !(1 == ~t4_pc~0); 27805#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 27873#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27874#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 28069#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28351#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27407#L555-33 assume !(1 == ~t5_pc~0); 27409#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 28125#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27668#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27669#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 28150#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 27382#L574-33 assume !(1 == ~t6_pc~0); 27383#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 28363#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27683#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27684#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 27938#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27452#L593-33 assume 1 == ~t7_pc~0; 27453#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 27898#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27556#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 27557#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 28209#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28341#L612-33 assume 1 == ~t8_pc~0; 28473#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 28434#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28435#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28274#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 27554#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 27555#L631-33 assume 1 == ~t9_pc~0; 28393#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 27499#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 27500#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 27740#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 27603#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 27604#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27772#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28325#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28326#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27509#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27510#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27880#L1077-3 assume !(1 == ~T7_E~0); 27727#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27728#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27800#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28086#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28014#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28015#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28364#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27723#L1117-3 assume !(1 == ~E_5~0); 27724#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27773#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27774#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28167#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28144#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 27608#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27494#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 28145#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 27900#L1447 assume !(0 == start_simulation_~tmp~3); 27902#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 28160#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 27643#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 28168#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 27748#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27518#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 27519#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 27964#L1460 assume !(0 != start_simulation_~tmp___0~1); 27965#L1428-1 [2021-11-07 07:26:10,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,798 INFO L85 PathProgramCache]: Analyzing trace with hash -180699461, now seen corresponding path program 1 times [2021-11-07 07:26:10,798 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,798 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135573092] [2021-11-07 07:26:10,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,857 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,857 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135573092] [2021-11-07 07:26:10,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135573092] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,857 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:10,859 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649949319] [2021-11-07 07:26:10,859 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:10,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:10,861 INFO L85 PathProgramCache]: Analyzing trace with hash -975513665, now seen corresponding path program 1 times [2021-11-07 07:26:10,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:10,862 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299616396] [2021-11-07 07:26:10,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:10,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:10,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:10,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:10,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:10,898 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299616396] [2021-11-07 07:26:10,899 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299616396] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:10,899 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:10,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:10,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489258673] [2021-11-07 07:26:10,900 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:10,900 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:10,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:26:10,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:26:10,901 INFO L87 Difference]: Start difference. First operand 1182 states and 1725 transitions. cyclomatic complexity: 544 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:11,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:11,168 INFO L93 Difference]: Finished difference Result 3135 states and 4511 transitions. [2021-11-07 07:26:11,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:26:11,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3135 states and 4511 transitions. [2021-11-07 07:26:11,188 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2938 [2021-11-07 07:26:11,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3135 states to 3135 states and 4511 transitions. [2021-11-07 07:26:11,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3135 [2021-11-07 07:26:11,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3135 [2021-11-07 07:26:11,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3135 states and 4511 transitions. [2021-11-07 07:26:11,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:11,222 INFO L681 BuchiCegarLoop]: Abstraction has 3135 states and 4511 transitions. [2021-11-07 07:26:11,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3135 states and 4511 transitions. [2021-11-07 07:26:11,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3135 to 3001. [2021-11-07 07:26:11,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3001 states, 3001 states have (on average 1.4421859380206599) internal successors, (4328), 3000 states have internal predecessors, (4328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:11,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3001 states to 3001 states and 4328 transitions. [2021-11-07 07:26:11,295 INFO L704 BuchiCegarLoop]: Abstraction has 3001 states and 4328 transitions. [2021-11-07 07:26:11,295 INFO L587 BuchiCegarLoop]: Abstraction has 3001 states and 4328 transitions. [2021-11-07 07:26:11,295 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 07:26:11,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3001 states and 4328 transitions. [2021-11-07 07:26:11,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2875 [2021-11-07 07:26:11,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:11,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:11,310 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:11,310 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:11,311 INFO L791 eck$LassoCheckResult]: Stem: 32545#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 32546#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 32489#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32490#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 32805#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32741#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32704#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32174#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32175#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32627#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32628#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31690#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31691#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31887#L703-1 assume !(0 == ~M_E~0); 32205#L939-1 assume !(0 == ~T1_E~0); 32206#L944-1 assume !(0 == ~T2_E~0); 32295#L949-1 assume !(0 == ~T3_E~0); 32292#L954-1 assume !(0 == ~T4_E~0); 32293#L959-1 assume !(0 == ~T5_E~0); 32742#L964-1 assume !(0 == ~T6_E~0); 32029#L969-1 assume !(0 == ~T7_E~0); 32030#L974-1 assume !(0 == ~T8_E~0); 32690#L979-1 assume !(0 == ~T9_E~0); 32691#L984-1 assume !(0 == ~E_M~0); 32186#L989-1 assume !(0 == ~E_1~0); 32187#L994-1 assume !(0 == ~E_2~0); 32074#L999-1 assume !(0 == ~E_3~0); 32075#L1004-1 assume !(0 == ~E_4~0); 31756#L1009-1 assume !(0 == ~E_5~0); 31757#L1014-1 assume !(0 == ~E_6~0); 32066#L1019-1 assume !(0 == ~E_7~0); 32634#L1024-1 assume !(0 == ~E_8~0); 32001#L1029-1 assume !(0 == ~E_9~0); 32002#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32089#L460 assume !(1 == ~m_pc~0); 32868#L460-2 is_master_triggered_~__retres1~0 := 0; 32598#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32599#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 32902#L1167 assume !(0 != activate_threads_~tmp~1); 32280#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32281#L479 assume !(1 == ~t1_pc~0); 32437#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 32438#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32829#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32013#L1175 assume !(0 != activate_threads_~tmp___0~0); 32014#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31869#L498 assume !(1 == ~t2_pc~0); 31870#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 32265#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32266#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32667#L1183 assume !(0 != activate_threads_~tmp___1~0); 32587#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32588#L517 assume 1 == ~t3_pc~0; 32835#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32836#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32340#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32046#L1191 assume !(0 != activate_threads_~tmp___2~0); 32047#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32643#L536 assume !(1 == ~t4_pc~0); 32329#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 32330#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32733#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32322#L1199 assume !(0 != activate_threads_~tmp___3~0); 32323#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32556#L555 assume !(1 == ~t5_pc~0); 32558#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 32635#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31785#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 31786#L1207 assume !(0 != activate_threads_~tmp___4~0); 31888#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31794#L574 assume !(1 == ~t6_pc~0); 31795#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 32416#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31893#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 31894#L1215 assume !(0 != activate_threads_~tmp___5~0); 32660#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32875#L593 assume 1 == ~t7_pc~0; 32876#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32020#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32745#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32914#L1223 assume !(0 != activate_threads_~tmp___6~0); 32841#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32181#L612 assume 1 == ~t8_pc~0; 32182#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32617#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32458#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32459#L1231 assume !(0 != activate_threads_~tmp___7~0); 32418#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32419#L631 assume !(1 == ~t9_pc~0); 32436#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 31784#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 31754#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 31755#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 32267#L1239-2 assume !(1 == ~M_E~0); 32669#L1047-1 assume !(1 == ~T1_E~0); 32411#L1052-1 assume !(1 == ~T2_E~0); 31711#L1057-1 assume !(1 == ~T3_E~0); 31712#L1062-1 assume !(1 == ~T4_E~0); 31986#L1067-1 assume !(1 == ~T5_E~0); 32284#L1072-1 assume !(1 == ~T6_E~0); 32285#L1077-1 assume !(1 == ~T7_E~0); 31883#L1082-1 assume !(1 == ~T8_E~0); 31884#L1087-1 assume !(1 == ~T9_E~0); 31682#L1092-1 assume !(1 == ~E_M~0); 31683#L1097-1 assume !(1 == ~E_1~0); 31713#L1102-1 assume !(1 == ~E_2~0); 32485#L1107-1 assume !(1 == ~E_3~0); 32414#L1112-1 assume !(1 == ~E_4~0); 32415#L1117-1 assume !(1 == ~E_5~0); 32460#L1122-1 assume !(1 == ~E_6~0); 32341#L1127-1 assume !(1 == ~E_7~0); 32092#L1132-1 assume !(1 == ~E_8~0); 32093#L1137-1 assume !(1 == ~E_9~0); 32287#L1428-1 [2021-11-07 07:26:11,311 INFO L793 eck$LassoCheckResult]: Loop: 32287#L1428-1 assume !false; 32346#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 31922#L914 assume !false; 32409#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 32410#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 31697#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 31698#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 33979#L783 assume !(0 != eval_~tmp~0); 32078#L929 start_simulation_~kernel_st~0 := 2; 32079#L651-1 start_simulation_~kernel_st~0 := 3; 32484#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32382#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31955#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31680#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31681#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32301#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31758#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31759#L969-3 assume !(0 == ~T7_E~0); 31953#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31954#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32383#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32384#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32007#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32008#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32529#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31839#L1009-3 assume !(0 == ~E_5~0); 31840#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32368#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32369#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32353#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32302#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32303#L460-33 assume !(1 == ~m_pc~0); 32574#L460-35 is_master_triggered_~__retres1~0 := 0; 32548#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32096#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 31688#L1167-33 assume !(0 != activate_threads_~tmp~1); 31689#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32033#L479-33 assume !(1 == ~t1_pc~0); 32034#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 32003#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32004#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32611#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32808#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32041#L498-33 assume !(1 == ~t2_pc~0); 31800#L498-35 is_transmit2_triggered_~__retres1~2 := 0; 31801#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31926#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 31927#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 31905#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31906#L517-33 assume 1 == ~t3_pc~0; 32887#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32718#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32719#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32516#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32517#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32126#L536-33 assume 1 == ~t4_pc~0; 32128#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32198#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32199#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32391#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32697#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31731#L555-33 assume !(1 == ~t5_pc~0); 31733#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 32453#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31994#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 31995#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32481#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31705#L574-33 assume !(1 == ~t6_pc~0); 31706#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 32709#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32009#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32010#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32262#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31775#L593-33 assume 1 == ~t7_pc~0; 31776#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32223#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31881#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 31882#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32547#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32685#L612-33 assume 1 == ~t8_pc~0; 32848#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32797#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32798#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32618#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 31879#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 31880#L631-33 assume 1 == ~t9_pc~0; 32740#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 31824#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 31825#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32065#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 31928#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 31929#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32097#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32670#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32671#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31834#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31835#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32207#L1077-3 assume !(1 == ~T7_E~0); 32052#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32053#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32125#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32408#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32338#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32339#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32710#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32048#L1117-3 assume !(1 == ~E_5~0); 32049#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32098#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32099#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32499#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32475#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 31933#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 31819#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 32476#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 32225#L1447 assume !(0 == start_simulation_~tmp~3); 32227#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 34074#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 34064#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 34062#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 34060#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34058#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 32524#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 32286#L1460 assume !(0 != start_simulation_~tmp___0~1); 32287#L1428-1 [2021-11-07 07:26:11,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:11,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1951288572, now seen corresponding path program 1 times [2021-11-07 07:26:11,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:11,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707110822] [2021-11-07 07:26:11,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:11,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:11,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:11,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:11,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:11,366 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707110822] [2021-11-07 07:26:11,366 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707110822] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:11,366 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:11,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:11,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320037223] [2021-11-07 07:26:11,368 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:11,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:11,369 INFO L85 PathProgramCache]: Analyzing trace with hash -144889153, now seen corresponding path program 1 times [2021-11-07 07:26:11,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:11,369 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530517952] [2021-11-07 07:26:11,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:11,369 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:11,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:11,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:11,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:11,409 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530517952] [2021-11-07 07:26:11,409 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530517952] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:11,410 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:11,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:11,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442422682] [2021-11-07 07:26:11,411 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:11,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:11,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:26:11,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:26:11,412 INFO L87 Difference]: Start difference. First operand 3001 states and 4328 transitions. cyclomatic complexity: 1329 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:11,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:11,699 INFO L93 Difference]: Finished difference Result 8323 states and 11881 transitions. [2021-11-07 07:26:11,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:26:11,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8323 states and 11881 transitions. [2021-11-07 07:26:11,746 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8033 [2021-11-07 07:26:11,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8323 states to 8323 states and 11881 transitions. [2021-11-07 07:26:11,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8323 [2021-11-07 07:26:11,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8323 [2021-11-07 07:26:11,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8323 states and 11881 transitions. [2021-11-07 07:26:11,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:11,838 INFO L681 BuchiCegarLoop]: Abstraction has 8323 states and 11881 transitions. [2021-11-07 07:26:11,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8323 states and 11881 transitions. [2021-11-07 07:26:11,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8323 to 8021. [2021-11-07 07:26:12,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8021 states, 8021 states have (on average 1.4304949507542701) internal successors, (11474), 8020 states have internal predecessors, (11474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:12,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8021 states to 8021 states and 11474 transitions. [2021-11-07 07:26:12,036 INFO L704 BuchiCegarLoop]: Abstraction has 8021 states and 11474 transitions. [2021-11-07 07:26:12,036 INFO L587 BuchiCegarLoop]: Abstraction has 8021 states and 11474 transitions. [2021-11-07 07:26:12,036 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 07:26:12,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8021 states and 11474 transitions. [2021-11-07 07:26:12,109 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7886 [2021-11-07 07:26:12,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:12,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:12,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:12,112 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:12,112 INFO L791 eck$LassoCheckResult]: Stem: 43876#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 43877#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 43822#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43823#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 44125#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44071#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44032#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43507#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43508#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43955#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43956#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43026#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43027#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43225#L703-1 assume !(0 == ~M_E~0); 43538#L939-1 assume !(0 == ~T1_E~0); 43539#L944-1 assume !(0 == ~T2_E~0); 43629#L949-1 assume !(0 == ~T3_E~0); 43626#L954-1 assume !(0 == ~T4_E~0); 43627#L959-1 assume !(0 == ~T5_E~0); 44072#L964-1 assume !(0 == ~T6_E~0); 43367#L969-1 assume !(0 == ~T7_E~0); 43368#L974-1 assume !(0 == ~T8_E~0); 44017#L979-1 assume !(0 == ~T9_E~0); 44018#L984-1 assume !(0 == ~E_M~0); 43519#L989-1 assume !(0 == ~E_1~0); 43520#L994-1 assume !(0 == ~E_2~0); 43410#L999-1 assume !(0 == ~E_3~0); 43411#L1004-1 assume !(0 == ~E_4~0); 43092#L1009-1 assume !(0 == ~E_5~0); 43093#L1014-1 assume !(0 == ~E_6~0); 43402#L1019-1 assume !(0 == ~E_7~0); 43962#L1024-1 assume !(0 == ~E_8~0); 43339#L1029-1 assume !(0 == ~E_9~0); 43340#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43424#L460 assume !(1 == ~m_pc~0); 44180#L460-2 is_master_triggered_~__retres1~0 := 0; 43926#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43927#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 44210#L1167 assume !(0 != activate_threads_~tmp~1); 43614#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43615#L479 assume !(1 == ~t1_pc~0); 43768#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 43769#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44146#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 43351#L1175 assume !(0 != activate_threads_~tmp___0~0); 43352#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43207#L498 assume !(1 == ~t2_pc~0); 43208#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 43598#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43599#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 43994#L1183 assume !(0 != activate_threads_~tmp___1~0); 43915#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43916#L517 assume !(1 == ~t3_pc~0); 44229#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 44230#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43672#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 43384#L1191 assume !(0 != activate_threads_~tmp___2~0); 43385#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43971#L536 assume !(1 == ~t4_pc~0); 43661#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 43662#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44064#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 43654#L1199 assume !(0 != activate_threads_~tmp___3~0); 43655#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43885#L555 assume !(1 == ~t5_pc~0); 43887#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 43963#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43121#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 43122#L1207 assume !(0 != activate_threads_~tmp___4~0); 43228#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 43130#L574 assume !(1 == ~t6_pc~0); 43131#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 43747#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43233#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43234#L1215 assume !(0 != activate_threads_~tmp___5~0); 43987#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 44187#L593 assume 1 == ~t7_pc~0; 44188#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 43358#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44075#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44232#L1223 assume !(0 != activate_threads_~tmp___6~0); 44154#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 43514#L612 assume 1 == ~t8_pc~0; 43515#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 43944#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 43788#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43789#L1231 assume !(0 != activate_threads_~tmp___7~0); 43749#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 43750#L631 assume !(1 == ~t9_pc~0); 43767#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 43120#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 43090#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 43091#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 43600#L1239-2 assume !(1 == ~M_E~0); 43997#L1047-1 assume !(1 == ~T1_E~0); 43743#L1052-1 assume !(1 == ~T2_E~0); 43047#L1057-1 assume !(1 == ~T3_E~0); 43048#L1062-1 assume !(1 == ~T4_E~0); 43324#L1067-1 assume !(1 == ~T5_E~0); 43618#L1072-1 assume !(1 == ~T6_E~0); 43619#L1077-1 assume !(1 == ~T7_E~0); 43221#L1082-1 assume !(1 == ~T8_E~0); 43222#L1087-1 assume !(1 == ~T9_E~0); 43018#L1092-1 assume !(1 == ~E_M~0); 43019#L1097-1 assume !(1 == ~E_1~0); 43049#L1102-1 assume !(1 == ~E_2~0); 43814#L1107-1 assume !(1 == ~E_3~0); 43745#L1112-1 assume !(1 == ~E_4~0); 43746#L1117-1 assume !(1 == ~E_5~0); 43790#L1122-1 assume !(1 == ~E_6~0); 43673#L1127-1 assume !(1 == ~E_7~0); 43427#L1132-1 assume !(1 == ~E_8~0); 43428#L1137-1 assume !(1 == ~E_9~0); 44175#L1428-1 [2021-11-07 07:26:12,113 INFO L793 eck$LassoCheckResult]: Loop: 44175#L1428-1 assume !false; 50295#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 50294#L914 assume !false; 50293#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 43948#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 43033#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 43034#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 43990#L783 assume !(0 != eval_~tmp~0); 43992#L929 start_simulation_~kernel_st~0 := 2; 50809#L651-1 start_simulation_~kernel_st~0 := 3; 50808#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 50807#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50806#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50805#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50804#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50803#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50802#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50801#L969-3 assume !(0 == ~T7_E~0); 50800#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50799#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50798#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50797#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50796#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50795#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50794#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50793#L1009-3 assume !(0 == ~E_5~0); 50792#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50791#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50790#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50789#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50788#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50787#L460-33 assume !(1 == ~m_pc~0); 50786#L460-35 is_master_triggered_~__retres1~0 := 0; 50785#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50784#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 50783#L1167-33 assume !(0 != activate_threads_~tmp~1); 50782#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50781#L479-33 assume !(1 == ~t1_pc~0); 50780#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 50779#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50778#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 50777#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 50776#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50775#L498-33 assume 1 == ~t2_pc~0; 50773#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 50772#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50771#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 50770#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 50769#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50768#L517-33 assume !(1 == ~t3_pc~0); 50767#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 50766#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50765#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 50764#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 50763#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50762#L536-33 assume !(1 == ~t4_pc~0); 50760#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 50759#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50758#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 50757#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 50756#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50755#L555-33 assume !(1 == ~t5_pc~0); 50753#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 50752#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50751#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 50750#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 50749#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50748#L574-33 assume !(1 == ~t6_pc~0); 50746#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 50745#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 50744#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50743#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 50742#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50741#L593-33 assume 1 == ~t7_pc~0; 50739#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 50738#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 50737#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50736#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 50735#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 50734#L612-33 assume !(1 == ~t8_pc~0); 50732#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 50731#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 50730#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50729#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 50728#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 50727#L631-33 assume 1 == ~t9_pc~0; 50725#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 50724#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 50723#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 50722#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 50721#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 50720#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50719#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50718#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50717#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50716#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50715#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50714#L1077-3 assume !(1 == ~T7_E~0); 50713#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50712#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50711#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50710#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50709#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50708#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50707#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50706#L1117-3 assume !(1 == ~E_5~0); 50705#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50704#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50703#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50702#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50701#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 50700#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 50690#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 50689#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 50687#L1447 assume !(0 == start_simulation_~tmp~3); 50685#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 50684#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 50674#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 50673#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 50672#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 50671#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 50670#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 50669#L1460 assume !(0 != start_simulation_~tmp___0~1); 44175#L1428-1 [2021-11-07 07:26:12,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:12,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1315146563, now seen corresponding path program 1 times [2021-11-07 07:26:12,114 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:12,114 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926826510] [2021-11-07 07:26:12,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:12,115 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:12,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:12,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:12,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:12,157 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926826510] [2021-11-07 07:26:12,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926826510] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:12,157 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:12,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:12,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456257217] [2021-11-07 07:26:12,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:12,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:12,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1068012861, now seen corresponding path program 1 times [2021-11-07 07:26:12,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:12,159 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616818351] [2021-11-07 07:26:12,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:12,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:12,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:12,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:12,198 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:12,198 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616818351] [2021-11-07 07:26:12,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616818351] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:12,198 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:12,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:12,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329511360] [2021-11-07 07:26:12,199 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:12,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:12,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:26:12,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:26:12,201 INFO L87 Difference]: Start difference. First operand 8021 states and 11474 transitions. cyclomatic complexity: 3457 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:12,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:12,543 INFO L93 Difference]: Finished difference Result 22397 states and 31783 transitions. [2021-11-07 07:26:12,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:26:12,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22397 states and 31783 transitions. [2021-11-07 07:26:12,664 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21913 [2021-11-07 07:26:12,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22397 states to 22397 states and 31783 transitions. [2021-11-07 07:26:12,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22397 [2021-11-07 07:26:12,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22397 [2021-11-07 07:26:12,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22397 states and 31783 transitions. [2021-11-07 07:26:12,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:12,868 INFO L681 BuchiCegarLoop]: Abstraction has 22397 states and 31783 transitions. [2021-11-07 07:26:12,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22397 states and 31783 transitions. [2021-11-07 07:26:13,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22397 to 21878. [2021-11-07 07:26:13,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21878 states, 21878 states have (on average 1.4214279184568974) internal successors, (31098), 21877 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:13,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21878 states to 21878 states and 31098 transitions. [2021-11-07 07:26:13,448 INFO L704 BuchiCegarLoop]: Abstraction has 21878 states and 31098 transitions. [2021-11-07 07:26:13,448 INFO L587 BuchiCegarLoop]: Abstraction has 21878 states and 31098 transitions. [2021-11-07 07:26:13,448 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 07:26:13,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21878 states and 31098 transitions. [2021-11-07 07:26:13,602 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21724 [2021-11-07 07:26:13,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:13,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:13,605 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:13,605 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:13,605 INFO L791 eck$LassoCheckResult]: Stem: 74320#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 74321#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 74263#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 74264#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 74604#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74537#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74495#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73939#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73940#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74414#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74415#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73455#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73456#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73652#L703-1 assume !(0 == ~M_E~0); 73970#L939-1 assume !(0 == ~T1_E~0); 73971#L944-1 assume !(0 == ~T2_E~0); 74068#L949-1 assume !(0 == ~T3_E~0); 74066#L954-1 assume !(0 == ~T4_E~0); 74067#L959-1 assume !(0 == ~T5_E~0); 74538#L964-1 assume !(0 == ~T6_E~0); 73794#L969-1 assume !(0 == ~T7_E~0); 73795#L974-1 assume !(0 == ~T8_E~0); 74480#L979-1 assume !(0 == ~T9_E~0); 74481#L984-1 assume !(0 == ~E_M~0); 73951#L989-1 assume !(0 == ~E_1~0); 73952#L994-1 assume !(0 == ~E_2~0); 73837#L999-1 assume !(0 == ~E_3~0); 73838#L1004-1 assume !(0 == ~E_4~0); 73521#L1009-1 assume !(0 == ~E_5~0); 73522#L1014-1 assume !(0 == ~E_6~0); 73831#L1019-1 assume !(0 == ~E_7~0); 74419#L1024-1 assume !(0 == ~E_8~0); 73766#L1029-1 assume !(0 == ~E_9~0); 73767#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 73855#L460 assume !(1 == ~m_pc~0); 74669#L460-2 is_master_triggered_~__retres1~0 := 0; 74378#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 74379#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 74704#L1167 assume !(0 != activate_threads_~tmp~1); 74051#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74052#L479 assume !(1 == ~t1_pc~0); 74216#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 74217#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 74626#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 73779#L1175 assume !(0 != activate_threads_~tmp___0~0); 73780#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 73634#L498 assume !(1 == ~t2_pc~0); 73635#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 74035#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74036#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 74454#L1183 assume !(0 != activate_threads_~tmp___1~0); 74367#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 74368#L517 assume !(1 == ~t3_pc~0); 74726#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 74727#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 74116#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 73811#L1191 assume !(0 != activate_threads_~tmp___2~0); 73812#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 74432#L536 assume !(1 == ~t4_pc~0); 74105#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 74106#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 74530#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 74095#L1199 assume !(0 != activate_threads_~tmp___3~0); 74096#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 74338#L555 assume !(1 == ~t5_pc~0); 74340#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 74420#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 73551#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 73552#L1207 assume !(0 != activate_threads_~tmp___4~0); 73657#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 73558#L574 assume !(1 == ~t6_pc~0); 73559#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 74195#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 73660#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 73661#L1215 assume !(0 != activate_threads_~tmp___5~0); 74448#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 74679#L593 assume !(1 == ~t7_pc~0); 73784#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 73785#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 74544#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 74733#L1223 assume !(0 != activate_threads_~tmp___6~0); 74635#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 73944#L612 assume 1 == ~t8_pc~0; 73945#L613 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 74398#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 74235#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 74236#L1231 assume !(0 != activate_threads_~tmp___7~0); 74197#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 74198#L631 assume !(1 == ~t9_pc~0); 74215#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 73548#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 73519#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 73520#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 74037#L1239-2 assume !(1 == ~M_E~0); 74458#L1047-1 assume !(1 == ~T1_E~0); 74191#L1052-1 assume !(1 == ~T2_E~0); 73476#L1057-1 assume !(1 == ~T3_E~0); 73477#L1062-1 assume !(1 == ~T4_E~0); 73751#L1067-1 assume !(1 == ~T5_E~0); 74055#L1072-1 assume !(1 == ~T6_E~0); 74056#L1077-1 assume !(1 == ~T7_E~0); 73648#L1082-1 assume !(1 == ~T8_E~0); 73649#L1087-1 assume !(1 == ~T9_E~0); 73449#L1092-1 assume !(1 == ~E_M~0); 73450#L1097-1 assume !(1 == ~E_1~0); 73478#L1102-1 assume !(1 == ~E_2~0); 74259#L1107-1 assume !(1 == ~E_3~0); 74193#L1112-1 assume !(1 == ~E_4~0); 74194#L1117-1 assume !(1 == ~E_5~0); 74237#L1122-1 assume !(1 == ~E_6~0); 74117#L1127-1 assume !(1 == ~E_7~0); 73856#L1132-1 assume !(1 == ~E_8~0); 73857#L1137-1 assume !(1 == ~E_9~0); 74058#L1428-1 [2021-11-07 07:26:13,606 INFO L793 eck$LassoCheckResult]: Loop: 74058#L1428-1 assume !false; 74123#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 73689#L914 assume !false; 74189#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 74190#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 73464#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 73465#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 74451#L783 assume !(0 != eval_~tmp~0); 73841#L929 start_simulation_~kernel_st~0 := 2; 73842#L651-1 start_simulation_~kernel_st~0 := 3; 74258#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 74163#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73724#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73445#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73446#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74074#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73525#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73526#L969-3 assume !(0 == ~T7_E~0); 73720#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 73721#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 74164#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 74165#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73772#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73773#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74304#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 73603#L1009-3 assume !(0 == ~E_5~0); 73604#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74148#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74149#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 74128#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 74078#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 74079#L460-33 assume !(1 == ~m_pc~0); 74347#L460-35 is_master_triggered_~__retres1~0 := 0; 74323#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 73860#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 73453#L1167-33 assume !(0 != activate_threads_~tmp~1); 73454#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 73801#L479-33 assume !(1 == ~t1_pc~0); 73802#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 73768#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 73769#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 74391#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 74605#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 73809#L498-33 assume 1 == ~t2_pc~0; 73810#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 73565#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 73695#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 73696#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 73672#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 73673#L517-33 assume !(1 == ~t3_pc~0); 74696#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 74509#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 74510#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 74289#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 74290#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 73893#L536-33 assume 1 == ~t4_pc~0; 73895#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 73962#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 73963#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 74172#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 74488#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 74571#L555-33 assume !(1 == ~t5_pc~0); 93274#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 93272#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93270#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 93268#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 93265#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 93263#L574-33 assume 1 == ~t6_pc~0; 93261#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 93258#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 93255#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 93252#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 93250#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 93248#L593-33 assume !(1 == ~t7_pc~0); 93246#L593-35 is_transmit7_triggered_~__retres1~7 := 0; 93244#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 93242#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 93240#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 93237#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 93235#L612-33 assume 1 == ~t8_pc~0; 93233#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 74595#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 74596#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 74399#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 73639#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 73640#L631-33 assume !(1 == ~t9_pc~0); 74260#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 73586#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 73587#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 73828#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 73693#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 73694#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73861#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74459#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74460#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73598#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73599#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73969#L1077-3 assume !(1 == ~T7_E~0); 73817#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 73818#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 73888#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 74188#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74114#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74115#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74501#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73813#L1117-3 assume !(1 == ~E_5~0); 73814#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73862#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73863#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 74272#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74249#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 73697#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 73581#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 74250#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 73992#L1447 assume !(0 == start_simulation_~tmp~3); 73994#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 74265#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 73734#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 74273#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 73836#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 73609#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 73610#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 74057#L1460 assume !(0 != start_simulation_~tmp___0~1); 74058#L1428-1 [2021-11-07 07:26:13,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:13,607 INFO L85 PathProgramCache]: Analyzing trace with hash -189886594, now seen corresponding path program 1 times [2021-11-07 07:26:13,607 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:13,607 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385943014] [2021-11-07 07:26:13,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:13,608 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:13,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:13,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:13,687 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:13,687 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385943014] [2021-11-07 07:26:13,687 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385943014] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:13,687 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:13,687 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:13,688 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975552471] [2021-11-07 07:26:13,688 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:13,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:13,688 INFO L85 PathProgramCache]: Analyzing trace with hash -709464418, now seen corresponding path program 1 times [2021-11-07 07:26:13,689 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:13,689 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797063106] [2021-11-07 07:26:13,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:13,689 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:13,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:13,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:13,758 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:13,758 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797063106] [2021-11-07 07:26:13,759 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797063106] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:13,759 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:13,759 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:13,759 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379858902] [2021-11-07 07:26:13,759 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:13,760 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:13,760 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:26:13,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:26:13,760 INFO L87 Difference]: Start difference. First operand 21878 states and 31098 transitions. cyclomatic complexity: 9228 Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:14,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:14,553 INFO L93 Difference]: Finished difference Result 61223 states and 86451 transitions. [2021-11-07 07:26:14,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:26:14,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61223 states and 86451 transitions. [2021-11-07 07:26:15,004 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60328 [2021-11-07 07:26:15,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61223 states to 61223 states and 86451 transitions. [2021-11-07 07:26:15,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61223 [2021-11-07 07:26:15,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61223 [2021-11-07 07:26:15,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61223 states and 86451 transitions. [2021-11-07 07:26:15,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:15,479 INFO L681 BuchiCegarLoop]: Abstraction has 61223 states and 86451 transitions. [2021-11-07 07:26:15,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61223 states and 86451 transitions. [2021-11-07 07:26:16,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61223 to 60143. [2021-11-07 07:26:16,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60143 states, 60143 states have (on average 1.4141961658048319) internal successors, (85054), 60142 states have internal predecessors, (85054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:16,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60143 states to 60143 states and 85054 transitions. [2021-11-07 07:26:16,952 INFO L704 BuchiCegarLoop]: Abstraction has 60143 states and 85054 transitions. [2021-11-07 07:26:16,952 INFO L587 BuchiCegarLoop]: Abstraction has 60143 states and 85054 transitions. [2021-11-07 07:26:16,953 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 07:26:16,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60143 states and 85054 transitions. [2021-11-07 07:26:17,336 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59950 [2021-11-07 07:26:17,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:17,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:17,339 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:17,339 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:17,339 INFO L791 eck$LassoCheckResult]: Stem: 157462#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 157463#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 157403#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 157404#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 157754#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157681#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157637#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157061#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157062#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157552#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157553#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 156568#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 156569#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 156766#L703-1 assume !(0 == ~M_E~0); 157097#L939-1 assume !(0 == ~T1_E~0); 157098#L944-1 assume !(0 == ~T2_E~0); 157197#L949-1 assume !(0 == ~T3_E~0); 157195#L954-1 assume !(0 == ~T4_E~0); 157196#L959-1 assume !(0 == ~T5_E~0); 157682#L964-1 assume !(0 == ~T6_E~0); 156913#L969-1 assume !(0 == ~T7_E~0); 156914#L974-1 assume !(0 == ~T8_E~0); 157623#L979-1 assume !(0 == ~T9_E~0); 157624#L984-1 assume !(0 == ~E_M~0); 157074#L989-1 assume !(0 == ~E_1~0); 157075#L994-1 assume !(0 == ~E_2~0); 156957#L999-1 assume !(0 == ~E_3~0); 156958#L1004-1 assume !(0 == ~E_4~0); 156634#L1009-1 assume !(0 == ~E_5~0); 156635#L1014-1 assume !(0 == ~E_6~0); 156951#L1019-1 assume !(0 == ~E_7~0); 157557#L1024-1 assume !(0 == ~E_8~0); 156885#L1029-1 assume !(0 == ~E_9~0); 156886#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156974#L460 assume !(1 == ~m_pc~0); 157824#L460-2 is_master_triggered_~__retres1~0 := 0; 157520#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 157521#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 157865#L1167 assume !(0 != activate_threads_~tmp~1); 157179#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 157180#L479 assume !(1 == ~t1_pc~0); 157350#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 157351#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157777#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 156898#L1175 assume !(0 != activate_threads_~tmp___0~0); 156899#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156747#L498 assume !(1 == ~t2_pc~0); 156748#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 157161#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157162#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 157590#L1183 assume !(0 != activate_threads_~tmp___1~0); 157509#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157510#L517 assume !(1 == ~t3_pc~0); 157886#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 157887#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157242#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 156930#L1191 assume !(0 != activate_threads_~tmp___2~0); 156931#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 157569#L536 assume !(1 == ~t4_pc~0); 157231#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 157232#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157673#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 157224#L1199 assume !(0 != activate_threads_~tmp___3~0); 157225#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157477#L555 assume !(1 == ~t5_pc~0); 157479#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 157558#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156664#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 156665#L1207 assume !(0 != activate_threads_~tmp___4~0); 156769#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 156671#L574 assume !(1 == ~t6_pc~0); 156672#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 157327#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 156774#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 156775#L1215 assume !(0 != activate_threads_~tmp___5~0); 157583#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 157834#L593 assume !(1 == ~t7_pc~0); 156903#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 156904#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 157687#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 157893#L1223 assume !(0 != activate_threads_~tmp___6~0); 157789#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 157068#L612 assume !(1 == ~t8_pc~0); 157069#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 157778#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 157372#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 157373#L1231 assume !(0 != activate_threads_~tmp___7~0); 157332#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 157333#L631 assume !(1 == ~t9_pc~0); 157349#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 156661#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 156632#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 156633#L1239 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 157163#L1239-2 assume !(1 == ~M_E~0); 157597#L1047-1 assume !(1 == ~T1_E~0); 157322#L1052-1 assume !(1 == ~T2_E~0); 156589#L1057-1 assume !(1 == ~T3_E~0); 156590#L1062-1 assume !(1 == ~T4_E~0); 156868#L1067-1 assume !(1 == ~T5_E~0); 157183#L1072-1 assume !(1 == ~T6_E~0); 157184#L1077-1 assume !(1 == ~T7_E~0); 156761#L1082-1 assume !(1 == ~T8_E~0); 156762#L1087-1 assume !(1 == ~T9_E~0); 156562#L1092-1 assume !(1 == ~E_M~0); 156563#L1097-1 assume !(1 == ~E_1~0); 156591#L1102-1 assume !(1 == ~E_2~0); 157399#L1107-1 assume !(1 == ~E_3~0); 157325#L1112-1 assume !(1 == ~E_4~0); 157326#L1117-1 assume !(1 == ~E_5~0); 157374#L1122-1 assume !(1 == ~E_6~0); 157243#L1127-1 assume !(1 == ~E_7~0); 156977#L1132-1 assume !(1 == ~E_8~0); 156978#L1137-1 assume !(1 == ~E_9~0); 157186#L1428-1 [2021-11-07 07:26:17,340 INFO L793 eck$LassoCheckResult]: Loop: 157186#L1428-1 assume !false; 209454#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 157836#L914 assume !false; 157320#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 157321#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 209133#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 209131#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 209127#L783 assume !(0 != eval_~tmp~0); 209128#L929 start_simulation_~kernel_st~0 := 2; 214823#L651-1 start_simulation_~kernel_st~0 := 3; 214820#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 214818#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 214816#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 214814#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 214812#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 214810#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 214808#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 214805#L969-3 assume !(0 == ~T7_E~0); 214803#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 214801#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 214799#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 214797#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 214795#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 214793#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 214791#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 214789#L1009-3 assume !(0 == ~E_5~0); 214787#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 214785#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 214783#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 214780#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 214778#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 214776#L460-33 assume !(1 == ~m_pc~0); 214774#L460-35 is_master_triggered_~__retres1~0 := 0; 214772#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 214770#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 214767#L1167-33 assume !(0 != activate_threads_~tmp~1); 214765#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 214764#L479-33 assume !(1 == ~t1_pc~0); 214762#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 214760#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 214759#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 214758#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 157847#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156928#L498-33 assume 1 == ~t2_pc~0; 156929#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 156678#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156810#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 156811#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 214512#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 214511#L517-33 assume !(1 == ~t3_pc~0); 214510#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 214509#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 214508#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 214506#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 214504#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 214502#L536-33 assume !(1 == ~t4_pc~0); 214499#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 214497#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 214495#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 214493#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 214491#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 214489#L555-33 assume !(1 == ~t5_pc~0); 214486#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 214484#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 214482#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 214480#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 214478#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 214477#L574-33 assume !(1 == ~t6_pc~0); 214475#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 214474#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 214473#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 214472#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 211619#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 156656#L593-33 assume !(1 == ~t7_pc~0); 156657#L593-35 is_transmit7_triggered_~__retres1~7 := 0; 157113#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 156759#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 156760#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 157464#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 157617#L612-33 assume !(1 == ~t8_pc~0); 157906#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 157741#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 157742#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 157539#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 156754#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 156755#L631-33 assume 1 == ~t9_pc~0; 157680#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 156699#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 156700#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 156947#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 156808#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 156809#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 156980#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 157598#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157599#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156711#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 156712#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 157096#L1077-3 assume !(1 == ~T7_E~0); 156936#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 156937#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 157007#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 157319#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 157240#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 157241#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 157648#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 156932#L1117-3 assume !(1 == ~E_5~0); 156933#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 156981#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 156982#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 157412#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 157386#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 156815#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 156694#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 211674#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 157116#L1447 assume !(0 == start_simulation_~tmp~3); 157118#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 157405#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 156851#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 157413#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 156956#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 156722#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 156723#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 157185#L1460 assume !(0 != start_simulation_~tmp___0~1); 157186#L1428-1 [2021-11-07 07:26:17,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:17,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1961357569, now seen corresponding path program 1 times [2021-11-07 07:26:17,341 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:17,341 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733151147] [2021-11-07 07:26:17,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:17,342 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:17,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:17,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:17,385 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:17,385 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733151147] [2021-11-07 07:26:17,385 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733151147] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:17,385 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:17,385 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:17,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334891268] [2021-11-07 07:26:17,386 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:17,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:17,387 INFO L85 PathProgramCache]: Analyzing trace with hash -662324196, now seen corresponding path program 1 times [2021-11-07 07:26:17,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:17,387 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963312469] [2021-11-07 07:26:17,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:17,388 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:17,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:17,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:17,425 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:17,425 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963312469] [2021-11-07 07:26:17,426 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963312469] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:17,426 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:17,426 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:17,426 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047266993] [2021-11-07 07:26:17,427 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:17,427 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:17,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:26:17,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:26:17,428 INFO L87 Difference]: Start difference. First operand 60143 states and 85054 transitions. cyclomatic complexity: 24927 Second operand has 5 states, 5 states have (on average 22.6) internal successors, (113), 5 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:18,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:18,588 INFO L93 Difference]: Finished difference Result 132280 states and 189857 transitions. [2021-11-07 07:26:18,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:26:18,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132280 states and 189857 transitions. [2021-11-07 07:26:19,561 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 131909 [2021-11-07 07:26:20,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132280 states to 132280 states and 189857 transitions. [2021-11-07 07:26:20,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132280 [2021-11-07 07:26:20,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132280 [2021-11-07 07:26:20,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132280 states and 189857 transitions. [2021-11-07 07:26:20,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:20,632 INFO L681 BuchiCegarLoop]: Abstraction has 132280 states and 189857 transitions. [2021-11-07 07:26:20,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132280 states and 189857 transitions. [2021-11-07 07:26:21,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132280 to 62219. [2021-11-07 07:26:21,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62219 states, 62219 states have (on average 1.4003760909047076) internal successors, (87130), 62218 states have internal predecessors, (87130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:22,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62219 states to 62219 states and 87130 transitions. [2021-11-07 07:26:22,288 INFO L704 BuchiCegarLoop]: Abstraction has 62219 states and 87130 transitions. [2021-11-07 07:26:22,288 INFO L587 BuchiCegarLoop]: Abstraction has 62219 states and 87130 transitions. [2021-11-07 07:26:22,288 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 07:26:22,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62219 states and 87130 transitions. [2021-11-07 07:26:22,493 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62023 [2021-11-07 07:26:22,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:22,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:22,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:22,496 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:22,497 INFO L791 eck$LassoCheckResult]: Stem: 349885#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 349886#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 349826#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 349827#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 350175#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 350106#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350056#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 349493#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 349494#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 349971#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 349972#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 349006#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 349007#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 349204#L703-1 assume !(0 == ~M_E~0); 349524#L939-1 assume !(0 == ~T1_E~0); 349525#L944-1 assume !(0 == ~T2_E~0); 349620#L949-1 assume !(0 == ~T3_E~0); 349617#L954-1 assume !(0 == ~T4_E~0); 349618#L959-1 assume !(0 == ~T5_E~0); 350107#L964-1 assume !(0 == ~T6_E~0); 349344#L969-1 assume !(0 == ~T7_E~0); 349345#L974-1 assume !(0 == ~T8_E~0); 350043#L979-1 assume !(0 == ~T9_E~0); 350044#L984-1 assume !(0 == ~E_M~0); 349504#L989-1 assume !(0 == ~E_1~0); 349505#L994-1 assume !(0 == ~E_2~0); 349389#L999-1 assume !(0 == ~E_3~0); 349390#L1004-1 assume !(0 == ~E_4~0); 349072#L1009-1 assume !(0 == ~E_5~0); 349073#L1014-1 assume !(0 == ~E_6~0); 349385#L1019-1 assume !(0 == ~E_7~0); 349976#L1024-1 assume !(0 == ~E_8~0); 349316#L1029-1 assume !(0 == ~E_9~0); 349317#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 349406#L460 assume !(1 == ~m_pc~0); 350245#L460-2 is_master_triggered_~__retres1~0 := 0; 349941#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 349942#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 350294#L1167 assume !(0 != activate_threads_~tmp~1); 349603#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 349604#L479 assume !(1 == ~t1_pc~0); 349774#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 349775#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 350199#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 349330#L1175 assume !(0 != activate_threads_~tmp___0~0); 349331#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 349186#L498 assume !(1 == ~t2_pc~0); 349187#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 349586#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 349587#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 350010#L1183 assume !(0 != activate_threads_~tmp___1~0); 349931#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 349932#L517 assume !(1 == ~t3_pc~0); 350313#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 350314#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 349667#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 349362#L1191 assume !(0 != activate_threads_~tmp___2~0); 349363#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 349989#L536 assume !(1 == ~t4_pc~0); 349656#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 349657#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 350097#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 349649#L1199 assume !(0 != activate_threads_~tmp___3~0); 349650#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 349902#L555 assume !(1 == ~t5_pc~0); 349904#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 349977#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 349103#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 349104#L1207 assume !(0 != activate_threads_~tmp___4~0); 349209#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 349110#L574 assume !(1 == ~t6_pc~0); 349111#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 349751#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 349212#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 349213#L1215 assume !(0 != activate_threads_~tmp___5~0); 350005#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 350255#L593 assume !(1 == ~t7_pc~0); 349334#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 349335#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 350113#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 350319#L1223 assume !(0 != activate_threads_~tmp___6~0); 350208#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 349498#L612 assume !(1 == ~t8_pc~0); 349499#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 350200#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 349794#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 349795#L1231 assume !(0 != activate_threads_~tmp___7~0); 349755#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 349756#L631 assume !(1 == ~t9_pc~0); 349772#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 349099#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 349100#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 349588#L1239 assume !(0 != activate_threads_~tmp___8~0); 349589#L1239-2 assume !(1 == ~M_E~0); 350016#L1047-1 assume !(1 == ~T1_E~0); 349747#L1052-1 assume !(1 == ~T2_E~0); 349027#L1057-1 assume !(1 == ~T3_E~0); 349028#L1062-1 assume !(1 == ~T4_E~0); 349301#L1067-1 assume !(1 == ~T5_E~0); 349607#L1072-1 assume !(1 == ~T6_E~0); 349608#L1077-1 assume !(1 == ~T7_E~0); 349200#L1082-1 assume !(1 == ~T8_E~0); 349201#L1087-1 assume !(1 == ~T9_E~0); 349002#L1092-1 assume !(1 == ~E_M~0); 349003#L1097-1 assume !(1 == ~E_1~0); 349029#L1102-1 assume !(1 == ~E_2~0); 349819#L1107-1 assume !(1 == ~E_3~0); 349749#L1112-1 assume !(1 == ~E_4~0); 349750#L1117-1 assume !(1 == ~E_5~0); 349796#L1122-1 assume !(1 == ~E_6~0); 349668#L1127-1 assume !(1 == ~E_7~0); 349409#L1132-1 assume !(1 == ~E_8~0); 349410#L1137-1 assume !(1 == ~E_9~0); 350239#L1428-1 [2021-11-07 07:26:22,497 INFO L793 eck$LassoCheckResult]: Loop: 350239#L1428-1 assume !false; 408179#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 408174#L914 assume !false; 408171#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 408013#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 408000#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 407994#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 407988#L783 assume !(0 != eval_~tmp~0); 407989#L929 start_simulation_~kernel_st~0 := 2; 409979#L651-1 start_simulation_~kernel_st~0 := 3; 409977#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 409975#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 409973#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 409971#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 409969#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 409967#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 409965#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 409963#L969-3 assume !(0 == ~T7_E~0); 409961#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 409957#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 409953#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 409848#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 409804#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 409797#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 409729#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 409727#L1009-3 assume !(0 == ~E_5~0); 409725#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 409617#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 409551#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 409550#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 409549#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 409548#L460-33 assume !(1 == ~m_pc~0); 409547#L460-35 is_master_triggered_~__retres1~0 := 0; 409546#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 409545#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 409544#L1167-33 assume !(0 != activate_threads_~tmp~1); 409543#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 409542#L479-33 assume !(1 == ~t1_pc~0); 409541#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 409540#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 409539#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 409538#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 409537#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 409536#L498-33 assume 1 == ~t2_pc~0; 409534#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 409533#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 409532#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 409531#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 409530#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 409529#L517-33 assume !(1 == ~t3_pc~0); 409528#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 409527#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 409526#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 409525#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 409524#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 409523#L536-33 assume 1 == ~t4_pc~0; 409522#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 409520#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 409519#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 409518#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 409517#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 409516#L555-33 assume !(1 == ~t5_pc~0); 409514#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 409513#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 409512#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 409511#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 409510#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 409509#L574-33 assume 1 == ~t6_pc~0; 409508#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 409506#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 409505#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 409504#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 409503#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 409502#L593-33 assume !(1 == ~t7_pc~0); 409501#L593-35 is_transmit7_triggered_~__retres1~7 := 0; 409500#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 409499#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 409498#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 409497#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 409496#L612-33 assume !(1 == ~t8_pc~0); 409495#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 409494#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 409493#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 409492#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 409491#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 409490#L631-33 assume !(1 == ~t9_pc~0); 409488#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 409486#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 409484#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 409482#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 409387#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 409382#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 409381#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 409380#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 409379#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409378#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 409377#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 409376#L1077-3 assume !(1 == ~T7_E~0); 409375#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 409374#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 409373#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 409372#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 409371#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 409370#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 409369#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 409130#L1117-3 assume !(1 == ~E_5~0); 409129#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 409128#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 409127#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 409121#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 409119#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 409037#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 409021#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 409017#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 408884#L1447 assume !(0 == start_simulation_~tmp~3); 408877#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 408836#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 408814#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 408748#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 408740#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 408733#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 408589#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 408588#L1460 assume !(0 != start_simulation_~tmp___0~1); 350239#L1428-1 [2021-11-07 07:26:22,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:22,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1538655743, now seen corresponding path program 1 times [2021-11-07 07:26:22,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:22,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766947983] [2021-11-07 07:26:22,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:22,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:22,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:22,518 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:22,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:22,626 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:22,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:22,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1984567107, now seen corresponding path program 1 times [2021-11-07 07:26:22,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:22,628 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14741496] [2021-11-07 07:26:22,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:22,629 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:22,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:22,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:22,666 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:22,666 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14741496] [2021-11-07 07:26:22,666 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14741496] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:22,667 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:22,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:26:22,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717556742] [2021-11-07 07:26:22,667 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:22,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:22,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:26:22,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:26:22,669 INFO L87 Difference]: Start difference. First operand 62219 states and 87130 transitions. cyclomatic complexity: 24927 Second operand has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:23,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:23,192 INFO L93 Difference]: Finished difference Result 114020 states and 157447 transitions. [2021-11-07 07:26:23,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-07 07:26:23,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114020 states and 157447 transitions. [2021-11-07 07:26:24,176 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 113749 [2021-11-07 07:26:24,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114020 states to 114020 states and 157447 transitions. [2021-11-07 07:26:24,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114020 [2021-11-07 07:26:24,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114020 [2021-11-07 07:26:24,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114020 states and 157447 transitions. [2021-11-07 07:26:24,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:24,804 INFO L681 BuchiCegarLoop]: Abstraction has 114020 states and 157447 transitions. [2021-11-07 07:26:24,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114020 states and 157447 transitions. [2021-11-07 07:26:25,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114020 to 62462. [2021-11-07 07:26:25,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62462 states, 62462 states have (on average 1.3988184816368352) internal successors, (87373), 62461 states have internal predecessors, (87373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:26,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62462 states to 62462 states and 87373 transitions. [2021-11-07 07:26:26,009 INFO L704 BuchiCegarLoop]: Abstraction has 62462 states and 87373 transitions. [2021-11-07 07:26:26,009 INFO L587 BuchiCegarLoop]: Abstraction has 62462 states and 87373 transitions. [2021-11-07 07:26:26,010 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 07:26:26,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62462 states and 87373 transitions. [2021-11-07 07:26:26,178 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62266 [2021-11-07 07:26:26,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:26,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:26,180 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:26,180 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:26,181 INFO L791 eck$LassoCheckResult]: Stem: 526168#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 526169#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 526104#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 526105#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 526492#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 526416#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 526361#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 525755#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 525756#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 526268#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 526269#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 525261#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 525262#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 525460#L703-1 assume !(0 == ~M_E~0); 525788#L939-1 assume !(0 == ~T1_E~0); 525789#L944-1 assume !(0 == ~T2_E~0); 525894#L949-1 assume !(0 == ~T3_E~0); 525890#L954-1 assume !(0 == ~T4_E~0); 525891#L959-1 assume !(0 == ~T5_E~0); 526417#L964-1 assume !(0 == ~T6_E~0); 525603#L969-1 assume !(0 == ~T7_E~0); 525604#L974-1 assume !(0 == ~T8_E~0); 526344#L979-1 assume !(0 == ~T9_E~0); 526345#L984-1 assume !(0 == ~E_M~0); 525766#L989-1 assume !(0 == ~E_1~0); 525767#L994-1 assume !(0 == ~E_2~0); 525648#L999-1 assume !(0 == ~E_3~0); 525649#L1004-1 assume !(0 == ~E_4~0); 525328#L1009-1 assume !(0 == ~E_5~0); 525329#L1014-1 assume !(0 == ~E_6~0); 525640#L1019-1 assume !(0 == ~E_7~0); 526275#L1024-1 assume !(0 == ~E_8~0); 525575#L1029-1 assume !(0 == ~E_9~0); 525576#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 525663#L460 assume !(1 == ~m_pc~0); 526565#L460-2 is_master_triggered_~__retres1~0 := 0; 526230#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 526231#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 526607#L1167 assume !(0 != activate_threads_~tmp~1); 525877#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 525878#L479 assume !(1 == ~t1_pc~0); 526046#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 526047#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 526517#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 525587#L1175 assume !(0 != activate_threads_~tmp___0~0); 525588#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 525442#L498 assume !(1 == ~t2_pc~0); 525443#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 525860#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 525861#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 526311#L1183 assume !(0 != activate_threads_~tmp___1~0); 526219#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 526220#L517 assume !(1 == ~t3_pc~0); 526632#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 526633#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 525939#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 525621#L1191 assume !(0 != activate_threads_~tmp___2~0); 525622#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 526287#L536 assume !(1 == ~t4_pc~0); 525928#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 525929#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 526407#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 525920#L1199 assume !(0 != activate_threads_~tmp___3~0); 525921#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 526183#L555 assume !(1 == ~t5_pc~0); 526185#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 526276#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 525357#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 525358#L1207 assume !(0 != activate_threads_~tmp___4~0); 525463#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 525366#L574 assume !(1 == ~t6_pc~0); 525367#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 526025#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 525468#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 525469#L1215 assume !(0 != activate_threads_~tmp___5~0); 526303#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 526574#L593 assume !(1 == ~t7_pc~0); 525593#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 525594#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 526421#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 526638#L1223 assume !(0 != activate_threads_~tmp___6~0); 526528#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 525762#L612 assume !(1 == ~t8_pc~0); 525763#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 526518#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 526068#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 526069#L1231 assume !(0 != activate_threads_~tmp___7~0); 526027#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 526028#L631 assume !(1 == ~t9_pc~0); 526045#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 526124#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 525326#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 525327#L1239 assume !(0 != activate_threads_~tmp___8~0); 525862#L1239-2 assume !(1 == ~M_E~0); 526318#L1047-1 assume !(1 == ~T1_E~0); 526021#L1052-1 assume !(1 == ~T2_E~0); 525282#L1057-1 assume !(1 == ~T3_E~0); 525283#L1062-1 assume !(1 == ~T4_E~0); 525560#L1067-1 assume !(1 == ~T5_E~0); 525881#L1072-1 assume !(1 == ~T6_E~0); 525882#L1077-1 assume !(1 == ~T7_E~0); 525456#L1082-1 assume !(1 == ~T8_E~0); 525457#L1087-1 assume !(1 == ~T9_E~0); 525253#L1092-1 assume !(1 == ~E_M~0); 525254#L1097-1 assume !(1 == ~E_1~0); 525284#L1102-1 assume !(1 == ~E_2~0); 526098#L1107-1 assume !(1 == ~E_3~0); 526023#L1112-1 assume !(1 == ~E_4~0); 526024#L1117-1 assume !(1 == ~E_5~0); 526070#L1122-1 assume !(1 == ~E_6~0); 525940#L1127-1 assume !(1 == ~E_7~0); 525666#L1132-1 assume !(1 == ~E_8~0); 525667#L1137-1 assume !(1 == ~E_9~0); 526560#L1428-1 [2021-11-07 07:26:26,182 INFO L793 eck$LassoCheckResult]: Loop: 526560#L1428-1 assume !false; 570677#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 570676#L914 assume !false; 570675#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 570670#L716 assume !(0 == ~m_st~0); 570671#L720 assume !(0 == ~t1_st~0); 570674#L724 assume !(0 == ~t2_st~0); 570668#L728 assume !(0 == ~t3_st~0); 570669#L732 assume !(0 == ~t4_st~0); 570673#L736 assume !(0 == ~t5_st~0); 570666#L740 assume !(0 == ~t6_st~0); 570667#L744 assume !(0 == ~t7_st~0); 570672#L748 assume !(0 == ~t8_st~0); 570664#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10 := 0; 570665#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 566709#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 566710#L783 assume !(0 != eval_~tmp~0); 570845#L929 start_simulation_~kernel_st~0 := 2; 570844#L651-1 start_simulation_~kernel_st~0 := 3; 570843#L939-2 assume 0 == ~M_E~0;~M_E~0 := 1; 570842#L939-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 570841#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 570840#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 570839#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 570838#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 570837#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 570836#L969-3 assume !(0 == ~T7_E~0); 570835#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 570834#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 570833#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 570832#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 570831#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 570830#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 570829#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 570828#L1009-3 assume !(0 == ~E_5~0); 570827#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 570826#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 570825#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 570824#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 570823#L1034-3 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 570822#L460-33 assume !(1 == ~m_pc~0); 570821#L460-35 is_master_triggered_~__retres1~0 := 0; 570820#L471-11 is_master_triggered_#res := is_master_triggered_~__retres1~0; 570819#L472-11 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 570818#L1167-33 assume !(0 != activate_threads_~tmp~1); 570817#L1167-35 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 570816#L479-33 assume !(1 == ~t1_pc~0); 570815#L479-35 is_transmit1_triggered_~__retres1~1 := 0; 570814#L490-11 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 570813#L491-11 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 570812#L1175-33 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 570811#L1175-35 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 570810#L498-33 assume 1 == ~t2_pc~0; 570808#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 570807#L509-11 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 570806#L510-11 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 570805#L1183-33 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 570804#L1183-35 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 570803#L517-33 assume !(1 == ~t3_pc~0); 570802#L517-35 is_transmit3_triggered_~__retres1~3 := 0; 570801#L528-11 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 570800#L529-11 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 570799#L1191-33 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 570798#L1191-35 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 570797#L536-33 assume !(1 == ~t4_pc~0); 570795#L536-35 is_transmit4_triggered_~__retres1~4 := 0; 570794#L547-11 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 570793#L548-11 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 570792#L1199-33 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 570791#L1199-35 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 570790#L555-33 assume !(1 == ~t5_pc~0); 570788#L555-35 is_transmit5_triggered_~__retres1~5 := 0; 570787#L566-11 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 570786#L567-11 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 570785#L1207-33 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 570784#L1207-35 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 570783#L574-33 assume !(1 == ~t6_pc~0); 570781#L574-35 is_transmit6_triggered_~__retres1~6 := 0; 570780#L585-11 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 570779#L586-11 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 570778#L1215-33 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 570777#L1215-35 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 570776#L593-33 assume !(1 == ~t7_pc~0); 570775#L593-35 is_transmit7_triggered_~__retres1~7 := 0; 570774#L604-11 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 570773#L605-11 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 570772#L1223-33 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 570771#L1223-35 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 570770#L612-33 assume !(1 == ~t8_pc~0); 570769#L612-35 is_transmit8_triggered_~__retres1~8 := 0; 570768#L623-11 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 570767#L624-11 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 570766#L1231-33 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 570765#L1231-35 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 570764#L631-33 assume !(1 == ~t9_pc~0); 570762#L631-35 is_transmit9_triggered_~__retres1~9 := 0; 570760#L642-11 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 570758#L643-11 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 570754#L1239-33 assume !(0 != activate_threads_~tmp___8~0); 570753#L1239-35 assume 1 == ~M_E~0;~M_E~0 := 2; 570752#L1047-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 570751#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 570750#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 570749#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 570748#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 570747#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 570746#L1077-3 assume !(1 == ~T7_E~0); 570745#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 570744#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 570743#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 570742#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 570741#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 570740#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 570739#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 570738#L1117-3 assume !(1 == ~E_5~0); 570737#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 570736#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 570735#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 570734#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 570733#L1142-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 570732#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 570720#L768-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 570717#L769-1 start_simulation_#t~ret30 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret30;havoc start_simulation_#t~ret30; 570713#L1447 assume !(0 == start_simulation_~tmp~3); 570710#L1447-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret29, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 570709#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 570698#L768-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 570695#L769-2 stop_simulation_#t~ret29 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret29;havoc stop_simulation_#t~ret29; 570692#L1402 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 570689#L1409 stop_simulation_#res := stop_simulation_~__retres2~0; 570686#L1410 start_simulation_#t~ret31 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret31;havoc start_simulation_#t~ret31; 570682#L1460 assume !(0 != start_simulation_~tmp___0~1); 526560#L1428-1 [2021-11-07 07:26:26,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:26,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1538655743, now seen corresponding path program 2 times [2021-11-07 07:26:26,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:26,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143673846] [2021-11-07 07:26:26,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:26,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:26,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:26,197 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:26,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:26,255 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:26,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:26,255 INFO L85 PathProgramCache]: Analyzing trace with hash 121295818, now seen corresponding path program 1 times [2021-11-07 07:26:26,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:26,256 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656787865] [2021-11-07 07:26:26,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:26,256 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:26,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:26,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:26,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:26,291 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656787865] [2021-11-07 07:26:26,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1656787865] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:26,291 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:26,291 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:26,292 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197717931] [2021-11-07 07:26:26,292 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:26:26,292 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:26,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:26,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:26,293 INFO L87 Difference]: Start difference. First operand 62462 states and 87373 transitions. cyclomatic complexity: 24927 Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 3 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:27,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:27,140 INFO L93 Difference]: Finished difference Result 107486 states and 147734 transitions. [2021-11-07 07:26:27,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:27,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107486 states and 147734 transitions. [2021-11-07 07:26:27,635 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 107288 [2021-11-07 07:26:28,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107486 states to 107486 states and 147734 transitions. [2021-11-07 07:26:28,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107486 [2021-11-07 07:26:28,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107486 [2021-11-07 07:26:28,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107486 states and 147734 transitions. [2021-11-07 07:26:28,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:28,148 INFO L681 BuchiCegarLoop]: Abstraction has 107486 states and 147734 transitions. [2021-11-07 07:26:28,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107486 states and 147734 transitions. [2021-11-07 07:26:29,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107486 to 106446. [2021-11-07 07:26:29,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106446 states, 106446 states have (on average 1.3748003682618417) internal successors, (146342), 106445 states have internal predecessors, (146342), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:30,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106446 states to 106446 states and 146342 transitions. [2021-11-07 07:26:30,053 INFO L704 BuchiCegarLoop]: Abstraction has 106446 states and 146342 transitions. [2021-11-07 07:26:30,053 INFO L587 BuchiCegarLoop]: Abstraction has 106446 states and 146342 transitions. [2021-11-07 07:26:30,053 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 07:26:30,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106446 states and 146342 transitions. [2021-11-07 07:26:30,953 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 106248 [2021-11-07 07:26:30,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:30,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:30,979 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:30,979 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:30,982 INFO L791 eck$LassoCheckResult]: Stem: 696097#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 696098#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 696035#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 696036#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 696401#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 696330#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 696276#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 695701#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 695702#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 696187#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 696188#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 695215#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 695216#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 695414#L703-1 assume !(0 == ~M_E~0); 695734#L939-1 assume !(0 == ~T1_E~0); 695735#L944-1 assume !(0 == ~T2_E~0); 695830#L949-1 assume !(0 == ~T3_E~0); 695826#L954-1 assume !(0 == ~T4_E~0); 695827#L959-1 assume !(0 == ~T5_E~0); 696331#L964-1 assume !(0 == ~T6_E~0); 695556#L969-1 assume !(0 == ~T7_E~0); 695557#L974-1 assume !(0 == ~T8_E~0); 696261#L979-1 assume !(0 == ~T9_E~0); 696262#L984-1 assume !(0 == ~E_M~0); 695712#L989-1 assume !(0 == ~E_1~0); 695713#L994-1 assume !(0 == ~E_2~0); 695599#L999-1 assume !(0 == ~E_3~0); 695600#L1004-1 assume !(0 == ~E_4~0); 695281#L1009-1 assume !(0 == ~E_5~0); 695282#L1014-1 assume !(0 == ~E_6~0); 695591#L1019-1 assume !(0 == ~E_7~0); 696196#L1024-1 assume !(0 == ~E_8~0); 695528#L1029-1 assume !(0 == ~E_9~0); 695529#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 695615#L460 assume !(1 == ~m_pc~0); 696477#L460-2 is_master_triggered_~__retres1~0 := 0; 696157#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 696158#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 696521#L1167 assume !(0 != activate_threads_~tmp~1); 695813#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 695814#L479 assume !(1 == ~t1_pc~0); 695982#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 695983#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 696426#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 695540#L1175 assume !(0 != activate_threads_~tmp___0~0); 695541#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 695396#L498 assume !(1 == ~t2_pc~0); 695397#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 695799#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 695800#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 696232#L1183 assume !(0 != activate_threads_~tmp___1~0); 696146#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 696147#L517 assume !(1 == ~t3_pc~0); 696543#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 696544#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 695876#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 695573#L1191 assume !(0 != activate_threads_~tmp___2~0); 695574#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 696207#L536 assume !(1 == ~t4_pc~0); 695865#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 695866#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 696322#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 695857#L1199 assume !(0 != activate_threads_~tmp___3~0); 695858#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 696110#L555 assume !(1 == ~t5_pc~0); 696112#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 696197#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 695310#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 695311#L1207 assume !(0 != activate_threads_~tmp___4~0); 695417#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 695319#L574 assume !(1 == ~t6_pc~0); 695320#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 695961#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 695422#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 695423#L1215 assume !(0 != activate_threads_~tmp___5~0); 696226#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 696485#L593 assume !(1 == ~t7_pc~0); 695546#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 695547#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 696335#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 696549#L1223 assume !(0 != activate_threads_~tmp___6~0); 696437#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 695708#L612 assume !(1 == ~t8_pc~0); 695709#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 696427#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 696001#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 696002#L1231 assume !(0 != activate_threads_~tmp___7~0); 695963#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 695964#L631 assume !(1 == ~t9_pc~0); 695981#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 696056#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 695279#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 695280#L1239 assume !(0 != activate_threads_~tmp___8~0); 695801#L1239-2 assume !(1 == ~M_E~0); 696237#L1047-1 assume !(1 == ~T1_E~0); 695955#L1052-1 assume !(1 == ~T2_E~0); 695236#L1057-1 assume !(1 == ~T3_E~0); 695237#L1062-1 assume !(1 == ~T4_E~0); 695513#L1067-1 assume !(1 == ~T5_E~0); 695817#L1072-1 assume !(1 == ~T6_E~0); 695818#L1077-1 assume !(1 == ~T7_E~0); 695410#L1082-1 assume !(1 == ~T8_E~0); 695411#L1087-1 assume !(1 == ~T9_E~0); 695207#L1092-1 assume !(1 == ~E_M~0); 695208#L1097-1 assume !(1 == ~E_1~0); 695238#L1102-1 assume !(1 == ~E_2~0); 696027#L1107-1 assume !(1 == ~E_3~0); 695958#L1112-1 assume !(1 == ~E_4~0); 695959#L1117-1 assume !(1 == ~E_5~0); 696003#L1122-1 assume !(1 == ~E_6~0); 695877#L1127-1 assume !(1 == ~E_7~0); 695618#L1132-1 assume !(1 == ~E_8~0); 695619#L1137-1 assume !(1 == ~E_9~0); 696472#L1428-1 assume !false; 748761#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 748758#L914 [2021-11-07 07:26:30,996 INFO L793 eck$LassoCheckResult]: Loop: 748758#L914 assume !false; 748756#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 748753#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 748750#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 748749#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 748748#L783 assume 0 != eval_~tmp~0; 748746#L783-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 748745#L791 assume !(0 != eval_~tmp_ndt_1~0); 748744#L788 assume !(0 == ~t1_st~0); 748743#L802 assume !(0 == ~t2_st~0); 748788#L816 assume !(0 == ~t3_st~0); 748786#L830 assume !(0 == ~t4_st~0); 748781#L844 assume !(0 == ~t5_st~0); 748776#L858 assume !(0 == ~t6_st~0); 748771#L872 assume !(0 == ~t7_st~0); 748768#L886 assume !(0 == ~t8_st~0); 748765#L900 assume !(0 == ~t9_st~0); 748758#L914 [2021-11-07 07:26:30,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:30,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1179401661, now seen corresponding path program 1 times [2021-11-07 07:26:30,997 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:30,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392070544] [2021-11-07 07:26:30,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:30,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:31,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:31,027 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:31,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:31,152 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:31,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:31,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1564251751, now seen corresponding path program 1 times [2021-11-07 07:26:31,154 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:31,154 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556343554] [2021-11-07 07:26:31,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:31,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:31,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:31,159 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:31,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:31,167 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:31,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:31,169 INFO L85 PathProgramCache]: Analyzing trace with hash 450977893, now seen corresponding path program 1 times [2021-11-07 07:26:31,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:31,169 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451773070] [2021-11-07 07:26:31,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:31,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:31,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:31,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:31,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:31,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451773070] [2021-11-07 07:26:31,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451773070] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:31,228 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:31,228 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:31,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386949076] [2021-11-07 07:26:31,420 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:31,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:31,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:31,421 INFO L87 Difference]: Start difference. First operand 106446 states and 146342 transitions. cyclomatic complexity: 39927 Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 3 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:32,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:32,130 INFO L93 Difference]: Finished difference Result 206607 states and 281761 transitions. [2021-11-07 07:26:32,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:32,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 206607 states and 281761 transitions. [2021-11-07 07:26:33,603 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 201275 [2021-11-07 07:26:34,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 206607 states to 206607 states and 281761 transitions. [2021-11-07 07:26:34,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 206607 [2021-11-07 07:26:34,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 206607 [2021-11-07 07:26:34,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 206607 states and 281761 transitions. [2021-11-07 07:26:34,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:34,275 INFO L681 BuchiCegarLoop]: Abstraction has 206607 states and 281761 transitions. [2021-11-07 07:26:34,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206607 states and 281761 transitions. [2021-11-07 07:26:36,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206607 to 203367. [2021-11-07 07:26:37,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203367 states, 203367 states have (on average 1.3645035821937679) internal successors, (277495), 203366 states have internal predecessors, (277495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:37,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203367 states to 203367 states and 277495 transitions. [2021-11-07 07:26:37,615 INFO L704 BuchiCegarLoop]: Abstraction has 203367 states and 277495 transitions. [2021-11-07 07:26:37,615 INFO L587 BuchiCegarLoop]: Abstraction has 203367 states and 277495 transitions. [2021-11-07 07:26:37,615 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 07:26:37,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203367 states and 277495 transitions. [2021-11-07 07:26:38,180 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 198035 [2021-11-07 07:26:38,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:38,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:38,182 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:38,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:38,182 INFO L791 eck$LassoCheckResult]: Stem: 1009162#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1009163#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1009101#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1009102#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 1009463#L658-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1009385#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1009340#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1008762#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1008763#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1009253#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1009254#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1008276#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1008277#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1008473#L703-1 assume !(0 == ~M_E~0); 1008796#L939-1 assume !(0 == ~T1_E~0); 1008797#L944-1 assume !(0 == ~T2_E~0); 1008898#L949-1 assume !(0 == ~T3_E~0); 1008894#L954-1 assume !(0 == ~T4_E~0); 1008895#L959-1 assume !(0 == ~T5_E~0); 1009386#L964-1 assume !(0 == ~T6_E~0); 1008616#L969-1 assume !(0 == ~T7_E~0); 1008617#L974-1 assume !(0 == ~T8_E~0); 1009324#L979-1 assume !(0 == ~T9_E~0); 1009325#L984-1 assume !(0 == ~E_M~0); 1008774#L989-1 assume !(0 == ~E_1~0); 1008775#L994-1 assume !(0 == ~E_2~0); 1008660#L999-1 assume !(0 == ~E_3~0); 1008661#L1004-1 assume !(0 == ~E_4~0); 1008343#L1009-1 assume !(0 == ~E_5~0); 1008344#L1014-1 assume !(0 == ~E_6~0); 1008651#L1019-1 assume !(0 == ~E_7~0); 1009260#L1024-1 assume !(0 == ~E_8~0); 1008586#L1029-1 assume !(0 == ~E_9~0); 1008587#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1008675#L460 assume !(1 == ~m_pc~0); 1009540#L460-2 is_master_triggered_~__retres1~0 := 0; 1009223#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1009224#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1009585#L1167 assume !(0 != activate_threads_~tmp~1); 1008882#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1008883#L479 assume !(1 == ~t1_pc~0); 1009049#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 1009050#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1106327#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1008598#L1175 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1008599#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1106322#L498 assume !(1 == ~t2_pc~0); 1106319#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 1106317#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1106316#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1106315#L1183 assume !(0 != activate_threads_~tmp___1~0); 1106314#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1106313#L517 assume !(1 == ~t3_pc~0); 1106312#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 1106311#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1106310#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1106309#L1191 assume !(0 != activate_threads_~tmp___2~0); 1106308#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1106307#L536 assume !(1 == ~t4_pc~0); 1106305#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 1106304#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1106303#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1106302#L1199 assume !(0 != activate_threads_~tmp___3~0); 1106301#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1106300#L555 assume !(1 == ~t5_pc~0); 1106298#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 1106297#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1106296#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1106295#L1207 assume !(0 != activate_threads_~tmp___4~0); 1106294#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1106293#L574 assume !(1 == ~t6_pc~0); 1106287#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 1106286#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1106285#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1106284#L1215 assume !(0 != activate_threads_~tmp___5~0); 1106283#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1106282#L593 assume !(1 == ~t7_pc~0); 1106281#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 1106280#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1106279#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1106278#L1223 assume !(0 != activate_threads_~tmp___6~0); 1106277#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1106276#L612 assume !(1 == ~t8_pc~0); 1106275#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 1106274#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1106273#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1106272#L1231 assume !(0 != activate_threads_~tmp___7~0); 1106271#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1106270#L631 assume !(1 == ~t9_pc~0); 1106259#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 1009660#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1009659#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1008866#L1239 assume !(0 != activate_threads_~tmp___8~0); 1008867#L1239-2 assume !(1 == ~M_E~0); 1009298#L1047-1 assume !(1 == ~T1_E~0); 1009022#L1052-1 assume !(1 == ~T2_E~0); 1008297#L1057-1 assume !(1 == ~T3_E~0); 1008298#L1062-1 assume !(1 == ~T4_E~0); 1008570#L1067-1 assume !(1 == ~T5_E~0); 1009387#L1072-1 assume !(1 == ~T6_E~0); 1106246#L1077-1 assume !(1 == ~T7_E~0); 1106244#L1082-1 assume !(1 == ~T8_E~0); 1009002#L1087-1 assume !(1 == ~T9_E~0); 1008268#L1092-1 assume !(1 == ~E_M~0); 1008269#L1097-1 assume !(1 == ~E_1~0); 1008299#L1102-1 assume !(1 == ~E_2~0); 1009096#L1107-1 assume !(1 == ~E_3~0); 1009024#L1112-1 assume !(1 == ~E_4~0); 1009025#L1117-1 assume !(1 == ~E_5~0); 1009069#L1122-1 assume !(1 == ~E_6~0); 1008945#L1127-1 assume !(1 == ~E_7~0); 1008678#L1132-1 assume !(1 == ~E_8~0); 1008679#L1137-1 assume !(1 == ~E_9~0); 1009535#L1428-1 assume !false; 1138636#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 1138634#L914 [2021-11-07 07:26:38,182 INFO L793 eck$LassoCheckResult]: Loop: 1138634#L914 assume !false; 1138632#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 1138629#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 1138628#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 1138627#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1138625#L783 assume 0 != eval_~tmp~0; 1138623#L783-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1138621#L791 assume !(0 != eval_~tmp_ndt_1~0); 1039629#L788 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1036849#L805 assume !(0 != eval_~tmp_ndt_2~0); 1036850#L802 assume !(0 == ~t2_st~0); 1138666#L816 assume !(0 == ~t3_st~0); 1138662#L830 assume !(0 == ~t4_st~0); 1138657#L844 assume !(0 == ~t5_st~0); 1138653#L858 assume !(0 == ~t6_st~0); 1138649#L872 assume !(0 == ~t7_st~0); 1138647#L886 assume !(0 == ~t8_st~0); 1138640#L900 assume !(0 == ~t9_st~0); 1138634#L914 [2021-11-07 07:26:38,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:38,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1859413949, now seen corresponding path program 1 times [2021-11-07 07:26:38,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:38,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659083942] [2021-11-07 07:26:38,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:38,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:38,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:38,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:38,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:38,214 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659083942] [2021-11-07 07:26:38,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659083942] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:38,214 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:38,215 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:38,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599099206] [2021-11-07 07:26:38,215 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:26:38,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:38,216 INFO L85 PathProgramCache]: Analyzing trace with hash -74726741, now seen corresponding path program 1 times [2021-11-07 07:26:38,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:38,216 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201094456] [2021-11-07 07:26:38,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:38,217 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:38,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:38,221 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:38,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:38,227 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:38,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:38,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:38,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:38,370 INFO L87 Difference]: Start difference. First operand 203367 states and 277495 transitions. cyclomatic complexity: 74175 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:39,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:39,692 INFO L93 Difference]: Finished difference Result 166245 states and 226582 transitions. [2021-11-07 07:26:39,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:39,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166245 states and 226582 transitions. [2021-11-07 07:26:40,275 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 165977 [2021-11-07 07:26:40,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166245 states to 166245 states and 226582 transitions. [2021-11-07 07:26:40,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 166245 [2021-11-07 07:26:40,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 166245 [2021-11-07 07:26:40,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166245 states and 226582 transitions. [2021-11-07 07:26:41,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:41,522 INFO L681 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-07 07:26:41,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166245 states and 226582 transitions. [2021-11-07 07:26:43,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166245 to 166245. [2021-11-07 07:26:43,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166245 states, 166245 states have (on average 1.3629402388041745) internal successors, (226582), 166244 states have internal predecessors, (226582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:43,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166245 states to 166245 states and 226582 transitions. [2021-11-07 07:26:43,747 INFO L704 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-07 07:26:43,747 INFO L587 BuchiCegarLoop]: Abstraction has 166245 states and 226582 transitions. [2021-11-07 07:26:43,747 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 07:26:43,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 166245 states and 226582 transitions. [2021-11-07 07:26:44,267 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 165977 [2021-11-07 07:26:44,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:26:44,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:26:44,268 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:44,268 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:26:44,269 INFO L791 eck$LassoCheckResult]: Stem: 1378801#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1378802#L-1 havoc main_#res;havoc main_~__retres1~11;havoc main_~__retres1~11;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1378734#L1391 havoc start_simulation_#t~ret30, start_simulation_#t~ret31, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1378735#L651 assume 1 == ~m_i~0;~m_st~0 := 0; 1379134#L658-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1379046#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1378990#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1378387#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1378388#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1378894#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1378895#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1377894#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1377895#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1378094#L703-1 assume !(0 == ~M_E~0); 1378424#L939-1 assume !(0 == ~T1_E~0); 1378425#L944-1 assume !(0 == ~T2_E~0); 1378526#L949-1 assume !(0 == ~T3_E~0); 1378523#L954-1 assume !(0 == ~T4_E~0); 1378524#L959-1 assume !(0 == ~T5_E~0); 1379047#L964-1 assume !(0 == ~T6_E~0); 1378239#L969-1 assume !(0 == ~T7_E~0); 1378240#L974-1 assume !(0 == ~T8_E~0); 1378976#L979-1 assume !(0 == ~T9_E~0); 1378977#L984-1 assume !(0 == ~E_M~0); 1378401#L989-1 assume !(0 == ~E_1~0); 1378402#L994-1 assume !(0 == ~E_2~0); 1378282#L999-1 assume !(0 == ~E_3~0); 1378283#L1004-1 assume !(0 == ~E_4~0); 1377961#L1009-1 assume !(0 == ~E_5~0); 1377962#L1014-1 assume !(0 == ~E_6~0); 1378276#L1019-1 assume !(0 == ~E_7~0); 1378900#L1024-1 assume !(0 == ~E_8~0); 1378210#L1029-1 assume !(0 == ~E_9~0); 1378211#L1034-1 havoc activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1378300#L460 assume !(1 == ~m_pc~0); 1379212#L460-2 is_master_triggered_~__retres1~0 := 0; 1378863#L471 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1378864#L472 activate_threads_#t~ret19 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1379261#L1167 assume !(0 != activate_threads_~tmp~1); 1378509#L1167-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1378510#L479 assume !(1 == ~t1_pc~0); 1378680#L479-2 is_transmit1_triggered_~__retres1~1 := 0; 1378681#L490 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1379159#L491 activate_threads_#t~ret20 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1378223#L1175 assume !(0 != activate_threads_~tmp___0~0); 1378224#L1175-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1378076#L498 assume !(1 == ~t2_pc~0); 1378077#L498-2 is_transmit2_triggered_~__retres1~2 := 0; 1378491#L509 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1378492#L510 activate_threads_#t~ret21 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1378937#L1183 assume !(0 != activate_threads_~tmp___1~0); 1378851#L1183-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1378852#L517 assume !(1 == ~t3_pc~0); 1379283#L517-2 is_transmit3_triggered_~__retres1~3 := 0; 1379284#L528 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1378576#L529 activate_threads_#t~ret22 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1378256#L1191 assume !(0 != activate_threads_~tmp___2~0); 1378257#L1191-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1378914#L536 assume !(1 == ~t4_pc~0); 1378565#L536-2 is_transmit4_triggered_~__retres1~4 := 0; 1378566#L547 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1379038#L548 activate_threads_#t~ret23 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1378556#L1199 assume !(0 != activate_threads_~tmp___3~0); 1378557#L1199-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1378822#L555 assume !(1 == ~t5_pc~0); 1378824#L555-2 is_transmit5_triggered_~__retres1~5 := 0; 1378901#L566 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1377992#L567 activate_threads_#t~ret24 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1377993#L1207 assume !(0 != activate_threads_~tmp___4~0); 1378099#L1207-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1377999#L574 assume !(1 == ~t6_pc~0); 1378000#L574-2 is_transmit6_triggered_~__retres1~6 := 0; 1378657#L585 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1378102#L586 activate_threads_#t~ret25 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1378103#L1215 assume !(0 != activate_threads_~tmp___5~0); 1378931#L1215-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1379224#L593 assume !(1 == ~t7_pc~0); 1378229#L593-2 is_transmit7_triggered_~__retres1~7 := 0; 1378230#L604 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1379053#L605 activate_threads_#t~ret26 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1379291#L1223 assume !(0 != activate_threads_~tmp___6~0); 1379172#L1223-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1378395#L612 assume !(1 == ~t8_pc~0); 1378396#L612-2 is_transmit8_triggered_~__retres1~8 := 0; 1379160#L623 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1378701#L624 activate_threads_#t~ret27 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1378702#L1231 assume !(0 != activate_threads_~tmp___7~0); 1378661#L1231-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1378662#L631 assume !(1 == ~t9_pc~0); 1378678#L631-2 is_transmit9_triggered_~__retres1~9 := 0; 1378757#L642 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1377959#L643 activate_threads_#t~ret28 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1377960#L1239 assume !(0 != activate_threads_~tmp___8~0); 1378493#L1239-2 assume !(1 == ~M_E~0); 1378944#L1047-1 assume !(1 == ~T1_E~0); 1378653#L1052-1 assume !(1 == ~T2_E~0); 1377915#L1057-1 assume !(1 == ~T3_E~0); 1377916#L1062-1 assume !(1 == ~T4_E~0); 1378194#L1067-1 assume !(1 == ~T5_E~0); 1378513#L1072-1 assume !(1 == ~T6_E~0); 1378514#L1077-1 assume !(1 == ~T7_E~0); 1378090#L1082-1 assume !(1 == ~T8_E~0); 1378091#L1087-1 assume !(1 == ~T9_E~0); 1377888#L1092-1 assume !(1 == ~E_M~0); 1377889#L1097-1 assume !(1 == ~E_1~0); 1377917#L1102-1 assume !(1 == ~E_2~0); 1378727#L1107-1 assume !(1 == ~E_3~0); 1378655#L1112-1 assume !(1 == ~E_4~0); 1378656#L1117-1 assume !(1 == ~E_5~0); 1378703#L1122-1 assume !(1 == ~E_6~0); 1378577#L1127-1 assume !(1 == ~E_7~0); 1378303#L1132-1 assume !(1 == ~E_8~0); 1378304#L1137-1 assume !(1 == ~E_9~0); 1379207#L1428-1 assume !false; 1456833#L1429 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_#t~nondet17, eval_~tmp_ndt_9~0, eval_#t~nondet18, eval_~tmp_ndt_10~0, eval_~tmp~0;havoc eval_~tmp~0; 1456831#L914 [2021-11-07 07:26:44,269 INFO L793 eck$LassoCheckResult]: Loop: 1456831#L914 assume !false; 1456829#L779 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~10;havoc exists_runnable_thread_~__retres1~10; 1456824#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10 := 1; 1456822#L768 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~10; 1456820#L769 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1456818#L783 assume 0 != eval_~tmp~0; 1456814#L783-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1456813#L791 assume !(0 != eval_~tmp_ndt_1~0); 1456809#L788 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1456807#L805 assume !(0 != eval_~tmp_ndt_2~0); 1456778#L802 assume !(0 == ~t2_st~0); 1456773#L816 assume !(0 == ~t3_st~0); 1456772#L830 assume !(0 == ~t4_st~0); 1456767#L844 assume !(0 == ~t5_st~0); 1456762#L858 assume !(0 == ~t6_st~0); 1456757#L872 assume !(0 == ~t7_st~0); 1456756#L886 assume !(0 == ~t8_st~0); 1456837#L900 assume !(0 == ~t9_st~0); 1456831#L914 [2021-11-07 07:26:44,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:44,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1179401661, now seen corresponding path program 2 times [2021-11-07 07:26:44,270 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:44,270 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441901356] [2021-11-07 07:26:44,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:44,271 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:44,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:44,286 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:44,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:44,352 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:44,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:44,353 INFO L85 PathProgramCache]: Analyzing trace with hash -74726741, now seen corresponding path program 2 times [2021-11-07 07:26:44,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:44,353 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550335955] [2021-11-07 07:26:44,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:44,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:44,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:44,358 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:26:44,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:26:44,364 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:26:44,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:26:44,365 INFO L85 PathProgramCache]: Analyzing trace with hash -226477971, now seen corresponding path program 1 times [2021-11-07 07:26:44,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:26:44,365 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174211576] [2021-11-07 07:26:44,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:26:44,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:26:44,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:26:44,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:26:44,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:26:44,407 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174211576] [2021-11-07 07:26:44,407 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174211576] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:26:44,408 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:26:44,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:26:44,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072265724] [2021-11-07 07:26:44,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:26:44,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:26:44,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:26:44,568 INFO L87 Difference]: Start difference. First operand 166245 states and 226582 transitions. cyclomatic complexity: 60368 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:26:46,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:26:46,371 INFO L93 Difference]: Finished difference Result 321756 states and 436877 transitions. [2021-11-07 07:26:46,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:26:46,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 321756 states and 436877 transitions. [2021-11-07 07:26:48,410 INFO L131 ngComponentsAnalysis]: Automaton has 31 accepting balls. 321343 [2021-11-07 07:26:48,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 321756 states to 321756 states and 436877 transitions. [2021-11-07 07:26:48,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 321756 [2021-11-07 07:26:49,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 321756 [2021-11-07 07:26:49,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 321756 states and 436877 transitions. [2021-11-07 07:26:49,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:26:49,187 INFO L681 BuchiCegarLoop]: Abstraction has 321756 states and 436877 transitions. [2021-11-07 07:26:49,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321756 states and 436877 transitions.